include/configs/MHPC.h

   1 /*
   2  * (C) Copyright 2001
   3  * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
   4  *
   5  * (C) Copyright 2001
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * Configuation settings for the miniHiPerCam.
   9  *
  10  * -----------------------------------------------------------------
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * board/config.h - configuration options, board specific
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  42 #define CONFIG_MHPC             1       /* on a miniHiPerCam            */
  43 #define CONFIG_BOARD_EARLY_INIT_F 1     /* do special hardware init.    */
  44 #define CONFIG_MISC_INIT_R      1
  45
  46 #define CONFIG_SYS_TEXT_BASE    0xfe000000
  47
  48 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_SPEED
  49 #undef  CONFIG_8xx_CONS_SMC1
  50 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  51 #undef  CONFIG_8xx_CONS_NONE
  52 #define CONFIG_BAUDRATE         9600
  53 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  54
  55 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  56
  57 #define CONFIG_ENV_OVERWRITE    1
  58 #define CONFIG_ETHADDR          00:00:5b:ee:de:ad
  59
  60 #undef  CONFIG_BOOTARGS
  61 #define CONFIG_BOOTCOMMAND      \
  62         "bootp;"                                                                \
  63         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  64         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  65         "bootm"
  66
  67 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  68 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  69
  70 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  71 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  72
  73 #undef  CONFIG_UCODE_PATCH
  74
  75 /* enable I2C and select the hardware/software driver */
  76 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  77 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  78 /*
  79  * Software (bit-bang) I2C driver configuration
  80  */
  81 #define PB_SCL          0x00000020      /* PB 26 */
  82 #define PB_SDA          0x00000010      /* PB 27 */
  83
  84 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
  85 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
  86 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  87 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  88 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
  89                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
  90 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
  91                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
  92 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  93
  94 #define CONFIG_SYS_I2C_SPEED                    50000
  95 #define CONFIG_SYS_I2C_SLAVE                    0xFE
  96 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* EEPROM X24C04                */
  97 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1       /* bytes of address             */
  98 /* mask of address bits that overflow into the "EEPROM chip address"    */
  99 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 100 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 101 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 102
 103 #define LCD_VIDEO_ADDR          (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
 104 #define LCD_VIDEO_SIZE          SDRAM_RES_SIZE  /* 2MB */
 105 #define LCD_VIDEO_COLS          640
 106 #define LCD_VIDEO_ROWS          480
 107 #define LCD_VIDEO_FG            255
 108 #define LCD_VIDEO_BG            0
 109
 110 #undef  CONFIG_VIDEO                            /* test only ! s.a devices.c and 8xx */
 111 #define CONFIG_CFB_CONSOLE                      /* framebuffer console with std input */
 112 #define CONFIG_VIDEO_LOGO
 113
 114 #define VIDEO_KBD_INIT_FCT      0               /* no KBD dev on MHPC - use serial */
 115 #define VIDEO_TSTC_FCT          serial_tstc
 116 #define VIDEO_GETC_FCT          serial_getc
 117
 118 #define CONFIG_BR0_WORKAROUND   1
 119
 120
 121 /*
 122  * Command line configuration.
 123  */
 124 #include <config_cmd_default.h>
 125
 126 #define CONFIG_CMD_DATE
 127 #define CONFIG_CMD_EEPROM
 128 #define CONFIG_CMD_ELF
 129 #define CONFIG_CMD_I2C
 130 #define CONFIG_CMD_JFFS2
 131 #define CONFIG_CMD_REGINFO
 132
 133
 134 /*
 135  * BOOTP options
 136  */
 137 #define CONFIG_BOOTP_SUBNETMASK
 138 #define CONFIG_BOOTP_GATEWAY
 139 #define CONFIG_BOOTP_HOSTNAME
 140 #define CONFIG_BOOTP_BOOTPATH
 141 #define CONFIG_BOOTP_BOOTFILESIZE
 142
 143
 144 /*
 145  * Miscellaneous configurable options
 146  */
 147 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 148 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 149 #if defined(CONFIG_CMD_KGDB)
 150 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 151 #else
 152 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 153 #endif
 154 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 155 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 156 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 157
 158 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 159 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 160
 161 #define CONFIG_SYS_LOAD_ADDR            0x300000        /* default load address */
 162
 163 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 164
 165 /*
 166  * Low Level Configuration Settings
 167  * (address mappings, register initial values, etc.)
 168  * You should know what you are doing if you make changes here.
 169  */
 170
 171 /*-----------------------------------------------------------------------
 172  * Physical memory map
 173  */
 174 #define CONFIG_SYS_IMMR         0xFFF00000 /* Internal Memory Mapped Register*/
 175
 176 /*-----------------------------------------------------------------------
 177  * Definitions for initial stack pointer and data area (in DPRAM)
 178  */
 179 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 180 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 181 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 182 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 183
 184 /*-----------------------------------------------------------------------
 185  * Start addresses for the final memory configuration
 186  * (Set up by the startup code)
 187  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 188  */
 189 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 190 #define CONFIG_SYS_FLASH_BASE           0xfe000000
 191
 192 #define CONFIG_SYS_MONITOR_LEN          0x40000         /* Reserve 256 kB for Monitor   */
 193 #undef  CONFIG_SYS_MONITOR_BASE             /* to run U-Boot from RAM */
 194 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 195 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 196
 197 /*
 198  * JFFS2 partitions
 199  *
 200  */
 201 /* No command line, one static partition, whole device */
 202 #undef CONFIG_CMD_MTDPARTS
 203 #define CONFIG_JFFS2_DEV                "nor0"
 204 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 205 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 206
 207 /* mtdparts command line support */
 208 /* Note: fake mtd_id used, no linux mtd map file */
 209 /*
 210 #define CONFIG_CMD_MTDPARTS
 211 #define MTDIDS_DEFAULT          "nor0=mhpc-0"
 212 #define MTDPARTS_DEFAULT        "mtdparts=mhpc-0:-(jffs2)"
 213 */
 214
 215 /*
 216  * For booting Linux, the board info and command line data
 217  * have to be in the first 8 MB of memory, since this is
 218  * the maximum mapped by the Linux kernel during initialization.
 219  */
 220 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map- for Linux        */
 221
 222 /*-----------------------------------------------------------------------
 223  * FLASH organization
 224  */
 225 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 226 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max number of sectors on one chip    */
 227
 228 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 229 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 230 #define CONFIG_ENV_IS_IN_FLASH  1
 231 #define CONFIG_ENV_OFFSET               CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
 232 #define CONFIG_ENV_SIZE         0x20000 /* Total Size of Environment    */
 233
 234 /*-----------------------------------------------------------------------
 235  * Cache Configuration
 236  */
 237 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 238 #if defined(CONFIG_CMD_KGDB)
 239 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 240 #endif
 241
 242 /*-----------------------------------------------------------------------
 243  * SYPCR - System Protection Control                            11-9
 244  * SYPCR can only be written once after reset!
 245  *-----------------------------------------------------------------------
 246  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 247  */
 248 #if defined(CONFIG_WATCHDOG)
 249 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 250                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 251 #else
 252 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 253                          SYPCR_SWP)
 254 #endif
 255
 256 /*-----------------------------------------------------------------------
 257  * SIUMCR - SIU Module Configuration                            11-6
 258  *-----------------------------------------------------------------------
 259  * PCMCIA config., multi-function pin tri-state
 260  */
 261 #define CONFIG_SYS_SIUMCR       (SIUMCR_SEME)
 262
 263 /*-----------------------------------------------------------------------
 264  * TBSCR - Time Base Status and Control                         11-26
 265  *-----------------------------------------------------------------------
 266  * Clear Reference Interrupt Status, Timebase freezing enabled
 267  */
 268 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 269
 270 /*-----------------------------------------------------------------------
 271  * PISCR - Periodic Interrupt Status and Control                11-31
 272  *-----------------------------------------------------------------------
 273  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 274  */
 275 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF | PISCR_PTE)
 276
 277 /*-----------------------------------------------------------------------
 278  * RTCSC - Real-Time Clock Status and Control Register          12-18
 279  *-----------------------------------------------------------------------
 280  */
 281 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 282
 283 /*-----------------------------------------------------------------------
 284  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 285  *-----------------------------------------------------------------------
 286  * Reset PLL lock status sticky bit, timer expired status bit and timer
 287  * interrupt status bit - leave PLL multiplication factor unchanged !
 288  */
 289 #define MPC8XX_SPEED    50000000L
 290 #define MPC8XX_XIN      5000000L      /* ref clk */
 291 #define MPC8XX_FACT     (MPC8XX_SPEED/MPC8XX_XIN)
 292 #define CONFIG_SYS_PLPRCR       (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 293                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 294
 295 /*-----------------------------------------------------------------------
 296  * SCCR - System Clock and reset Control Register               15-27
 297  *-----------------------------------------------------------------------
 298  * Set clock output, timebase and RTC source and divider,
 299  * power management and some other internal clocks
 300  */
 301
 302 #define SCCR_MASK       (SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
 303 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001)
 304
 305
 306 /*-----------------------------------------------------------------------
 307  * MAMR settings for SDRAM      - 16-14
 308  * => 0xC080200F
 309  *-----------------------------------------------------------------------
 310  * periodic timer for refresh
 311  */
 312 #define CONFIG_SYS_MAMR_PTA     0xC0
 313 #define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
 314
 315 /*
 316  * BR0 and OR0 (FLASH) used to re-map FLASH
 317  */
 318
 319 /* allow for max 8 MB of Flash */
 320 #define FLASH_BASE              0xFE000000      /* FLASH bank #0*/
 321 #define FLASH_BASE0_PRELIM      0xFE000000      /* FLASH bank #0*/
 322 #define CONFIG_SYS_REMAP_OR_AM          0xFF800000      /* OR addr mask */
 323 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000      /* OR addr mask */
 324
 325 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
 326
 327 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 328 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 329 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
 330
 331 /*
 332  * BR1 and OR1 (SDRAM)
 333  */
 334 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 335 #define SDRAM_MAX_SIZE          0x01000000      /* max 16 MB            */
 336 #define SDRAM_RES_SIZE          0x00200000      /* 2 MB for framebuffer */
 337
 338 /* SDRAM timing: drive GPL5 high on first cycle */
 339 #define CONFIG_SYS_OR_TIMING_SDRAM      (OR_G5LS)
 340
 341 #define CONFIG_SYS_OR1_PRELIM   ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
 342 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 343
 344 /*
 345  * BR2/OR2 - DIMM
 346  */
 347 #define CONFIG_SYS_OR2          (OR_ACS_DIV4)
 348 #define CONFIG_SYS_BR2          (BR_MS_UPMA)
 349
 350 /*
 351  * BR3/OR3 - DIMM
 352  */
 353 #define CONFIG_SYS_OR3          (OR_ACS_DIV4)
 354 #define CONFIG_SYS_BR3          (BR_MS_UPMA)
 355
 356 /*
 357  * BR4/OR4
 358  */
 359 #define CONFIG_SYS_OR4          0
 360 #define CONFIG_SYS_BR4          0
 361
 362 /*
 363  * BR5/OR5
 364  */
 365 #define CONFIG_SYS_OR5          0
 366 #define CONFIG_SYS_BR5          0
 367
 368 /*
 369  * BR6/OR6
 370  */
 371 #define CONFIG_SYS_OR6          0
 372 #define CONFIG_SYS_BR6          0
 373
 374 /*
 375  * BR7/OR7
 376  */
 377 #define CONFIG_SYS_OR7          0
 378 #define CONFIG_SYS_BR7          0
 379
 380
 381 /*-----------------------------------------------------------------------
 382  * Debug Entry Mode
 383  *-----------------------------------------------------------------------
 384  *
 385  */
 386 #define CONFIG_SYS_DER 0
 387
 388 #endif  /* __CONFIG_H */