include/configs/MUSENKI.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  *
  10  * Configuration settings for the MUSENKI board.
  11  *
  12  */
  13
  14 /* ------------------------------------------------------------------------- */
  15
  16 /*
  17  * board/config.h - configuration options, board specific
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  * (easy to change)
  26  */
  27
  28 #define CONFIG_MPC824X          1
  29 #define CONFIG_MPC8245          1
  30 #define CONFIG_MUSENKI          1
  31
  32 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  33
  34 #define CONFIG_CONS_INDEX       1
  35 #define CONFIG_BAUDRATE         9600
  36
  37 #define CONFIG_BOOTDELAY        5
  38
  39
  40 /*
  41  * BOOTP options
  42  */
  43 #define CONFIG_BOOTP_BOOTFILESIZE
  44 #define CONFIG_BOOTP_BOOTPATH
  45 #define CONFIG_BOOTP_GATEWAY
  46 #define CONFIG_BOOTP_HOSTNAME
  47
  48
  49 /*
  50  * Command line configuration.
  51  */
  52 #include <config_cmd_default.h>
  53
  54
  55 /*
  56  * Miscellaneous configurable options
  57  */
  58 #undef CONFIG_SYS_LONGHELP                      /* undef to save memory         */
  59 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  60 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  61
  62 /* Print Buffer Size
  63  */
  64 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  65 #define CONFIG_SYS_MAXARGS      8               /* Max number of command args   */
  66 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  67 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
  68
  69 /*-----------------------------------------------------------------------
  70  * PCI stuff
  71  *-----------------------------------------------------------------------
  72  */
  73 #define CONFIG_PCI                      /* include pci support          */
  74 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  75 #undef CONFIG_PCI_PNP
  76
  77
  78 #define CONFIG_TULIP
  79
  80 #define PCI_ENET0_IOADDR                0x80000000
  81 #define PCI_ENET0_MEMADDR               0x80000000
  82 #define PCI_ENET1_IOADDR                0x81000000
  83 #define PCI_ENET1_MEMADDR               0x81000000
  84
  85
  86 /*-----------------------------------------------------------------------
  87  * Start addresses for the final memory configuration
  88  * (Set up by the startup code)
  89  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  90  */
  91 #define CONFIG_SYS_SDRAM_BASE       0x00000000
  92
  93 #define CONFIG_SYS_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
  94 #define CONFIG_SYS_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
  95 #define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_FLASH_BASE0_PRELIM
  96
  97 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
  98  * reset vector is actually located at FFB00100, but the 8245
  99  * takes care of us.
 100  */
 101 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 102
 103 #define CONFIG_SYS_EUMB_ADDR        0xFC000000
 104
 105 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 106 #define CONFIG_SYS_MONITOR_LEN      (256 << 10) /* Reserve 256 kB for Monitor   */
 107 #define CONFIG_SYS_MALLOC_LEN       (128 << 10) /* Reserve 128 kB for malloc()  */
 108
 109 #define CONFIG_SYS_MEMTEST_START   0x00004000   /* memtest works on             */
 110 #define CONFIG_SYS_MEMTEST_END      0x02000000  /* 0 ... 32 MB in DRAM          */
 111
 112         /* Maximum amount of RAM.
 113          */
 114 #define CONFIG_SYS_MAX_RAM_SIZE    0x08000000   /* 0 .. 128 MB of (S)DRAM */
 115
 116
 117 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 118 #undef CONFIG_SYS_RAMBOOT
 119 #else
 120 #define CONFIG_SYS_RAMBOOT
 121 #endif
 122
 123 /*
 124  * NS16550 Configuration
 125  */
 126 #define CONFIG_SYS_NS16550
 127 #define CONFIG_SYS_NS16550_SERIAL
 128
 129 #define CONFIG_SYS_NS16550_REG_SIZE     1
 130
 131 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 132
 133 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 134 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
 135
 136 /*-----------------------------------------------------------------------
 137  * Definitions for initial stack pointer and data area
 138  */
 139
 140 /* #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE */
 141 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 142 #define CONFIG_SYS_INIT_RAM_SIZE      0x1000
 143 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 144
 145
 146 /*
 147  * Low Level Configuration Settings
 148  * (address mappings, register initial values, etc.)
 149  * You should know what you are doing if you make changes here.
 150  * For the detail description refer to the MPC8240 user's manual.
 151  */
 152
 153 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 154 #define CONFIG_SYS_HZ                1000
 155
 156         /* Bit-field values for MCCR1.
 157          */
 158 #define CONFIG_SYS_ROMNAL           7
 159 #define CONFIG_SYS_ROMFAL           11
 160 #define CONFIG_SYS_DBUS_SIZE       0x3
 161
 162         /* Bit-field values for MCCR2.
 163          */
 164 #define CONFIG_SYS_TSWAIT           0x5             /* Transaction Start Wait States timer */
 165 #define CONFIG_SYS_REFINT           0x400           /* Refresh interval FIXME: was 0t430                */
 166
 167         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 168          */
 169 #define CONFIG_SYS_BSTOPRE          121
 170
 171         /* Bit-field values for MCCR3.
 172          */
 173 #define CONFIG_SYS_REFREC           8       /* Refresh to activate interval */
 174
 175         /* Bit-field values for MCCR4.
 176          */
 177 #define CONFIG_SYS_PRETOACT         3       /* Precharge to activate interval FIXME: was 2      */
 178 #define CONFIG_SYS_ACTTOPRE         5       /* Activate to Precharge interval FIXME: was 5      */
 179 #define CONFIG_SYS_ACTORW           3           /* FIXME was 2 */
 180 #define CONFIG_SYS_SDMODE_CAS_LAT  3        /* SDMODE CAS latancy */
 181 #define CONFIG_SYS_SDMODE_WRAP      0       /* SDMODE wrap type */
 182 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 183 #define CONFIG_SYS_EXTROM           1
 184 #define CONFIG_SYS_REGDIMM          0
 185
 186 #define CONFIG_SYS_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
 187
 188 #define CONFIG_SYS_SDRAM_DSCD   0x20    /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
 189
 190 /* Memory bank settings.
 191  * Only bits 20-29 are actually used from these vales to set the
 192  * start/end addresses. The upper two bits will always be 0, and the lower
 193  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 194  * address. Refer to the MPC8240 book.
 195  */
 196
 197 #define CONFIG_SYS_BANK0_START      0x00000000
 198 #define CONFIG_SYS_BANK0_END        (CONFIG_SYS_MAX_RAM_SIZE - 1)
 199 #define CONFIG_SYS_BANK0_ENABLE    1
 200 #define CONFIG_SYS_BANK1_START      0x3ff00000
 201 #define CONFIG_SYS_BANK1_END        0x3fffffff
 202 #define CONFIG_SYS_BANK1_ENABLE    0
 203 #define CONFIG_SYS_BANK2_START      0x3ff00000
 204 #define CONFIG_SYS_BANK2_END        0x3fffffff
 205 #define CONFIG_SYS_BANK2_ENABLE    0
 206 #define CONFIG_SYS_BANK3_START      0x3ff00000
 207 #define CONFIG_SYS_BANK3_END        0x3fffffff
 208 #define CONFIG_SYS_BANK3_ENABLE    0
 209 #define CONFIG_SYS_BANK4_START      0x3ff00000
 210 #define CONFIG_SYS_BANK4_END        0x3fffffff
 211 #define CONFIG_SYS_BANK4_ENABLE    0
 212 #define CONFIG_SYS_BANK5_START      0x3ff00000
 213 #define CONFIG_SYS_BANK5_END        0x3fffffff
 214 #define CONFIG_SYS_BANK5_ENABLE    0
 215 #define CONFIG_SYS_BANK6_START      0x3ff00000
 216 #define CONFIG_SYS_BANK6_END        0x3fffffff
 217 #define CONFIG_SYS_BANK6_ENABLE    0
 218 #define CONFIG_SYS_BANK7_START      0x3ff00000
 219 #define CONFIG_SYS_BANK7_END        0x3fffffff
 220 #define CONFIG_SYS_BANK7_ENABLE    0
 221
 222 #define CONFIG_SYS_ODCR     0xff
 223
 224 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 225 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 226
 227 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 228 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 229
 230 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 231 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 232
 233 #define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 234 #define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 235
 236 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 237 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 238 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 239 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 240 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 241 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 242 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 243 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 244
 245 /*
 246  * For booting Linux, the board info and command line data
 247  * have to be in the first 8 MB of memory, since this is
 248  * the maximum mapped by the Linux kernel during initialization.
 249  */
 250 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)   /* Initial Memory map for Linux */
 251
 252 /*-----------------------------------------------------------------------
 253  * FLASH organization
 254  */
 255 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* Max number of flash banks            */
 256 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* Max number of sectors per flash      */
 257
 258 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 259 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 260
 261
 262         /* Warining: environment is not EMBEDDED in the U-Boot code.
 263          * It's stored in flash separately.
 264          */
 265 #define CONFIG_ENV_IS_IN_FLASH      1
 266 #define CONFIG_ENV_ADDR         0xFFFF0000
 267 #define CONFIG_ENV_SIZE         0x00010000 /* Size of the Environment           */
 268 #define CONFIG_ENV_SECT_SIZE    0x20000 /* Size of the Environment Sector       */
 269
 270 /*-----------------------------------------------------------------------
 271  * Cache Configuration
 272  */
 273 #define CONFIG_SYS_CACHELINE_SIZE       32
 274 #if defined(CONFIG_CMD_KGDB)
 275 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 276 #endif
 277
 278 #endif  /* __CONFIG_H */