include/configs/PM826.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #undef CONFIG_SYS_RAMBOOT
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU        */
  39 #define CONFIG_PM826            1       /* ...on a PM8260 module        */
  40 #define CONFIG_CPM2             1       /* Has a CPM2 */
  41
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0xFF000000      /* Standard: boot 64-bit flash */
  44 #endif
  45
  46 #undef CONFIG_DB_CR826_J30x_ON          /* J30x jumpers on D.B. carrier */
  47
  48 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  49
  50 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  51
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_BOOTCOMMAND                                                      \
  54         "bootp; "                                                               \
  55         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  56         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  57         "bootm"
  58
  59 /* enable I2C and select the hardware/software driver */
  60 #undef  CONFIG_HARD_I2C
  61 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  62 # define CONFIG_SYS_I2C_SPEED           50000
  63 # define CONFIG_SYS_I2C_SLAVE           0xFE
  64 /*
  65  * Software (bit-bang) I2C driver configuration
  66  */
  67 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
  68 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
  69 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
  70 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
  71 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
  72                         else    iop->pdat &= ~0x00010000
  73 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
  74                         else    iop->pdat &= ~0x00020000
  75 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  76
  77
  78 #define CONFIG_RTC_PCF8563
  79 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  80
  81 /*
  82  * select serial console configuration
  83  *
  84  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  85  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  86  * for SCC).
  87  *
  88  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  89  * defined elsewhere (for example, on the cogent platform, there are serial
  90  * ports on the motherboard which are used for the serial console - see
  91  * cogent/cma101/serial.[ch]).
  92  */
  93 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
  94 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
  95 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  96 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
  97
  98 /*
  99  * select ethernet configuration
 100  *
 101  * if CONFIG_ETHER_ON_SCC is selected, then
 102  *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
 103  *
 104  * if CONFIG_ETHER_ON_FCC is selected, then
 105  *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
 106  *
 107  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 108  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 109  */
 110 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 111
 112 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 113 #define CONFIG_ETHER_INDEX    1         /* which SCC channel for ethernet */
 114
 115 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 116 /*
 117  * - Rx-CLK is CLK11
 118  * - Tx-CLK is CLK10
 119  */
 120 #define CONFIG_ETHER_ON_FCC1
 121 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
 122 #ifndef CONFIG_DB_CR826_J30x_ON
 123 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
 124 #else
 125 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
 126 #endif
 127 /*
 128  * - Rx-CLK is CLK15
 129  * - Tx-CLK is CLK14
 130  */
 131 #define CONFIG_ETHER_ON_FCC2
 132 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 133 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 134 /*
 135  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 136  * - Enable Full Duplex in FSMR
 137  */
 138 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 139 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 140
 141 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 142 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
 143
 144 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
 145 #define CONFIG_BAUDRATE         230400
 146 #else
 147 #define CONFIG_BAUDRATE         9600
 148 #endif
 149
 150 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 151 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 152
 153 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 154
 155 /*
 156  * BOOTP options
 157  */
 158 #define CONFIG_BOOTP_SUBNETMASK
 159 #define CONFIG_BOOTP_GATEWAY
 160 #define CONFIG_BOOTP_HOSTNAME
 161 #define CONFIG_BOOTP_BOOTPATH
 162 #define CONFIG_BOOTP_BOOTFILESIZE
 163
 164
 165 /*
 166  * Command line configuration.
 167  */
 168 #include <config_cmd_default.h>
 169
 170 #define CONFIG_CMD_BEDBUG
 171 #define CONFIG_CMD_DATE
 172 #define CONFIG_CMD_DHCP
 173 #define CONFIG_CMD_EEPROM
 174 #define CONFIG_CMD_I2C
 175 #define CONFIG_CMD_NFS
 176 #define CONFIG_CMD_SNTP
 177
 178 #ifdef CONFIG_PCI
 179 #define CONFIG_PCI_INDIRECT_BRIDGE
 180 #define CONFIG_CMD_PCI
 181 #endif
 182
 183 /*
 184  * Miscellaneous configurable options
 185  */
 186 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 187 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 188 #if defined(CONFIG_CMD_KGDB)
 189 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 190 #else
 191 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 192 #endif
 193 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 194 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 195 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 196
 197 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 198 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 199
 200 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 201
 202 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 203
 204 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address                */
 205
 206 /*
 207  * For booting Linux, the board info and command line data
 208  * have to be in the first 8 MB of memory, since this is
 209  * the maximum mapped by the Linux kernel during initialization.
 210  */
 211 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 212
 213 /*-----------------------------------------------------------------------
 214  * Flash and Boot ROM mapping
 215  */
 216 #ifdef CONFIG_FLASH_32MB
 217 #define CONFIG_SYS_FLASH0_BASE          0x40000000
 218 #define CONFIG_SYS_FLASH0_SIZE          0x02000000
 219 #else
 220 #define CONFIG_SYS_FLASH0_BASE          0xFF000000
 221 #define CONFIG_SYS_FLASH0_SIZE          0x00800000
 222 #endif
 223 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 224 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 225 #define CONFIG_SYS_DOC_BASE             0xFF800000
 226 #define CONFIG_SYS_DOC_SIZE             0x00100000
 227
 228 /* Flash bank size (for preliminary settings)
 229  */
 230 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 231
 232 /*-----------------------------------------------------------------------
 233  * FLASH organization
 234  */
 235 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 236 #ifdef CONFIG_FLASH_32MB
 237 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
 238 #else
 239 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 240 #endif
 241 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 242 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 243
 244 #if 0
 245 /* Start port with environment in flash; switch to EEPROM later */
 246 #define CONFIG_ENV_IS_IN_FLASH  1
 247 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+0x40000)
 248 #define CONFIG_ENV_SIZE         0x40000
 249 #define CONFIG_ENV_SECT_SIZE    0x40000
 250 #else
 251 /* Final version: environment in EEPROM */
 252 #define CONFIG_ENV_IS_IN_EEPROM 1
 253 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58
 254 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 256 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 257 #define CONFIG_ENV_OFFSET               512
 258 #define CONFIG_ENV_SIZE         (2048 - 512)
 259 #endif
 260
 261 /*-----------------------------------------------------------------------
 262  * Hard Reset Configuration Words
 263  *
 264  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 265  * defines for the various registers affected by the HRCW e.g. changing
 266  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 267  */
 268 #if defined(CONFIG_BOOT_ROM)
 269 #define CONFIG_SYS_HRCW_MASTER          (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 270 #else
 271 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 272 #endif
 273
 274 /* no slaves so just fill with zeros */
 275 #define CONFIG_SYS_HRCW_SLAVE1          0
 276 #define CONFIG_SYS_HRCW_SLAVE2          0
 277 #define CONFIG_SYS_HRCW_SLAVE3          0
 278 #define CONFIG_SYS_HRCW_SLAVE4          0
 279 #define CONFIG_SYS_HRCW_SLAVE5          0
 280 #define CONFIG_SYS_HRCW_SLAVE6          0
 281 #define CONFIG_SYS_HRCW_SLAVE7          0
 282
 283 /*-----------------------------------------------------------------------
 284  * Internal Memory Mapped Register
 285  */
 286 #define CONFIG_SYS_IMMR         0xF0000000
 287
 288 /*-----------------------------------------------------------------------
 289  * Definitions for initial stack pointer and data area (in DPRAM)
 290  */
 291 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 292 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 293 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 294 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 295
 296 /*-----------------------------------------------------------------------
 297  * Start addresses for the final memory configuration
 298  * (Set up by the startup code)
 299  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 300  *
 301  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
 302  * is mapped at SDRAM_BASE2_PRELIM.
 303  */
 304 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 305 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 306 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 307 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 308 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 309
 310 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 311 # define CONFIG_SYS_RAMBOOT
 312 #endif
 313
 314 #ifdef  CONFIG_PCI
 315 #define CONFIG_PCI_PNP
 316 #define CONFIG_EEPRO100
 317 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 318 #endif
 319
 320 /*-----------------------------------------------------------------------
 321  * Cache Configuration
 322  */
 323 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 324 #if defined(CONFIG_CMD_KGDB)
 325 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 326 #endif
 327
 328 /*-----------------------------------------------------------------------
 329  * HIDx - Hardware Implementation-dependent Registers                    2-11
 330  *-----------------------------------------------------------------------
 331  * HID0 also contains cache control - initially enable both caches and
 332  * invalidate contents, then the final state leaves only the instruction
 333  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 334  * but Soft reset does not.
 335  *
 336  * HID1 has only read-only information - nothing to set.
 337  */
 338 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 339                                 HID0_IFEM|HID0_ABE)
 340 #define CONFIG_SYS_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
 341 #define CONFIG_SYS_HID2        0
 342
 343 /*-----------------------------------------------------------------------
 344  * RMR - Reset Mode Register                                     5-5
 345  *-----------------------------------------------------------------------
 346  * turn on Checkstop Reset Enable
 347  */
 348 #define CONFIG_SYS_RMR         RMR_CSRE
 349
 350 /*-----------------------------------------------------------------------
 351  * BCR - Bus Configuration                                       4-25
 352  *-----------------------------------------------------------------------
 353  */
 354
 355 #define BCR_APD01       0x10000000
 356 #define CONFIG_SYS_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 357
 358 /*-----------------------------------------------------------------------
 359  * SIUMCR - SIU Module Configuration                             4-31
 360  *-----------------------------------------------------------------------
 361  */
 362 #if 0
 363 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
 364 #else
 365 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC10|SIUMCR_APPC10)
 366 #endif
 367
 368
 369 /*-----------------------------------------------------------------------
 370  * SYPCR - System Protection Control                             4-35
 371  * SYPCR can only be written once after reset!
 372  *-----------------------------------------------------------------------
 373  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 374  */
 375 #if defined(CONFIG_WATCHDOG)
 376 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 377                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 378 #else
 379 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 380                          SYPCR_SWRI|SYPCR_SWP)
 381 #endif /* CONFIG_WATCHDOG */
 382
 383 /*-----------------------------------------------------------------------
 384  * TMCNTSC - Time Counter Status and Control                     4-40
 385  *-----------------------------------------------------------------------
 386  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 387  * and enable Time Counter
 388  */
 389 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 390
 391 /*-----------------------------------------------------------------------
 392  * PISCR - Periodic Interrupt Status and Control                 4-42
 393  *-----------------------------------------------------------------------
 394  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 395  * Periodic timer
 396  */
 397 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 398
 399 /*-----------------------------------------------------------------------
 400  * SCCR - System Clock Control                                   9-8
 401  *-----------------------------------------------------------------------
 402  */
 403 #define CONFIG_SYS_SCCR        (SCCR_DFBRG00)
 404
 405 /*-----------------------------------------------------------------------
 406  * RCCR - RISC Controller Configuration                         13-7
 407  *-----------------------------------------------------------------------
 408  */
 409 #define CONFIG_SYS_RCCR        0
 410
 411 /*
 412  * Init Memory Controller:
 413  *
 414  * Bank Bus     Machine PortSz  Device
 415  * ---- ---     ------- ------  ------
 416  *  0   60x     GPCM    64 bit  FLASH
 417  *  1   60x     SDRAM   64 bit  SDRAM
 418  *
 419  */
 420
 421         /* Initialize SDRAM on local bus
 422          */
 423 #define CONFIG_SYS_INIT_LOCAL_SDRAM
 424
 425
 426 /* Minimum mask to separate preliminary
 427  * address ranges for CS[0:2]
 428  */
 429 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
 430
 431 /*
 432  * we use the same values for 32 MB and 128 MB SDRAM
 433  * refresh rate = 7.73 uS (64 MHz Bus Clock)
 434  */
 435 #define CONFIG_SYS_MPTPR       0x2000
 436 #define CONFIG_SYS_PSRT        0x0E
 437
 438 #define CONFIG_SYS_MRS_OFFS     0x00000000
 439
 440
 441 #if defined(CONFIG_BOOT_ROM)
 442 /*
 443  * Bank 0 - Boot ROM (8 bit wide)
 444  */
 445 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 446                          BRx_PS_8                       |\
 447                          BRx_MS_GPCM_P                  |\
 448                          BRx_V)
 449
 450 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 451                          ORxG_CSNT                      |\
 452                          ORxG_ACS_DIV1                  |\
 453                          ORxG_SCY_3_CLK                 |\
 454                          ORxG_EHTR                      |\
 455                          ORxG_TRLX)
 456
 457 /*
 458  * Bank 1 - Flash (64 bit wide)
 459  */
 460 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 461                          BRx_PS_64                      |\
 462                          BRx_MS_GPCM_P                  |\
 463                          BRx_V)
 464
 465 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 466                          ORxG_CSNT                      |\
 467                          ORxG_ACS_DIV1                  |\
 468                          ORxG_SCY_3_CLK                 |\
 469                          ORxG_EHTR                      |\
 470                          ORxG_TRLX)
 471
 472 #else   /* ! CONFIG_BOOT_ROM */
 473
 474 /*
 475  * Bank 0 - Flash (64 bit wide)
 476  */
 477 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 478                          BRx_PS_64                      |\
 479                          BRx_MS_GPCM_P                  |\
 480                          BRx_V)
 481
 482 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)       |\
 483                          ORxG_CSNT                      |\
 484                          ORxG_ACS_DIV1                  |\
 485                          ORxG_SCY_3_CLK                 |\
 486                          ORxG_EHTR                      |\
 487                          ORxG_TRLX)
 488
 489 /*
 490  * Bank 1 - Disk-On-Chip
 491  */
 492 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
 493                          BRx_PS_8                       |\
 494                          BRx_MS_GPCM_P                  |\
 495                          BRx_V)
 496
 497 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
 498                          ORxG_CSNT                      |\
 499                          ORxG_ACS_DIV1                  |\
 500                          ORxG_SCY_3_CLK                 |\
 501                          ORxG_EHTR                      |\
 502                          ORxG_TRLX)
 503
 504 #endif /* CONFIG_BOOT_ROM */
 505
 506 /* Bank 2 - SDRAM
 507  */
 508
 509 #ifndef CONFIG_SYS_RAMBOOT
 510 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 511                          BRx_PS_64                      |\
 512                          BRx_MS_SDRAM_P                 |\
 513                          BRx_V)
 514
 515         /* SDRAM initialization values for 8-column chips
 516          */
 517 #define CONFIG_SYS_OR2_8COL    (CONFIG_SYS_MIN_AM_MASK          |\
 518                          ORxS_BPD_4                     |\
 519                          ORxS_ROWST_PBI0_A9             |\
 520                          ORxS_NUMR_12)
 521
 522 #define CONFIG_SYS_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
 523                          PSDMR_BSMA_A14_A16             |\
 524                          PSDMR_SDA10_PBI0_A10           |\
 525                          PSDMR_RFRC_7_CLK               |\
 526                          PSDMR_PRETOACT_2W              |\
 527                          PSDMR_ACTTORW_1W               |\
 528                          PSDMR_LDOTOPRE_1C              |\
 529                          PSDMR_WRC_1C                   |\
 530                          PSDMR_CL_2)
 531
 532         /* SDRAM initialization values for 9-column chips
 533          */
 534 #define CONFIG_SYS_OR2_9COL    (CONFIG_SYS_MIN_AM_MASK                |\
 535                          ORxS_BPD_4                     |\
 536                          ORxS_ROWST_PBI0_A7             |\
 537                          ORxS_NUMR_13)
 538
 539 #define CONFIG_SYS_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
 540                          PSDMR_BSMA_A13_A15             |\
 541                          PSDMR_SDA10_PBI0_A9            |\
 542                          PSDMR_RFRC_7_CLK               |\
 543                          PSDMR_PRETOACT_2W              |\
 544                          PSDMR_ACTTORW_1W               |\
 545                          PSDMR_LDOTOPRE_1C              |\
 546                          PSDMR_WRC_1C                   |\
 547                          PSDMR_CL_2)
 548
 549 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR2_9COL
 550 #define CONFIG_SYS_PSDMR        CONFIG_SYS_PSDMR_9COL
 551
 552 #endif /* CONFIG_SYS_RAMBOOT */
 553
 554 #endif  /* __CONFIG_H */