include/configs/T102xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_MP                       /* support multiple processors */
  17 #define CONFIG_ENABLE_36BIT_PHYS
  18
  19 #ifdef CONFIG_PHYS_64BIT
  20 #define CONFIG_ADDR_MAP         1
  21 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  22 #endif
  23
  24 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  25 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  26 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  27
  28 #define CONFIG_ENV_OVERWRITE
  29
  30 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  31
  32 /* support deep sleep */
  33 #ifdef CONFIG_ARCH_T1024
  34 #define CONFIG_DEEP_SLEEP
  35 #endif
  36 #if defined(CONFIG_DEEP_SLEEP)
  37 #define CONFIG_BOARD_EARLY_INIT_F
  38 #endif
  39
  40 #ifdef CONFIG_RAMBOOT_PBL
  41 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  42 #define CONFIG_SPL_FLUSH_IMAGE
  43 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  44 #define CONFIG_SYS_TEXT_BASE            0x30001000
  45 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  46 #define CONFIG_SPL_PAD_TO               0x40000
  47 #define CONFIG_SPL_MAX_SIZE             0x28000
  48 #define RESET_VECTOR_OFFSET             0x27FFC
  49 #define BOOT_PAGE_OFFSET                0x27000
  50 #ifdef CONFIG_SPL_BUILD
  51 #define CONFIG_SPL_SKIP_RELOCATE
  52 #define CONFIG_SPL_COMMON_INIT_DDR
  53 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  54 #define CONFIG_SYS_NO_FLASH
  55 #endif
  56
  57 #ifdef CONFIG_NAND
  58 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  59 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  60 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  61 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  62 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  63 #if defined(CONFIG_TARGET_T1024RDB)
  64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  65 #elif defined(CONFIG_TARGET_T1023RDB)
  66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  67 #endif
  68 #define CONFIG_SPL_NAND_BOOT
  69 #endif
  70
  71 #ifdef CONFIG_SPIFLASH
  72 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  73 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  78 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  79 #ifndef CONFIG_SPL_BUILD
  80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  81 #endif
  82 #if defined(CONFIG_TARGET_T1024RDB)
  83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  84 #elif defined(CONFIG_TARGET_T1023RDB)
  85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  86 #endif
  87 #define CONFIG_SPL_SPI_BOOT
  88 #endif
  89
  90 #ifdef CONFIG_SDCARD
  91 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  92 #define CONFIG_SPL_MMC_MINIMAL
  93 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  94 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  95 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  96 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  97 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  98 #ifndef CONFIG_SPL_BUILD
  99 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 100 #endif
 101 #if defined(CONFIG_TARGET_T1024RDB)
 102 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
 103 #elif defined(CONFIG_TARGET_T1023RDB)
 104 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
 105 #endif
 106 #define CONFIG_SPL_MMC_BOOT
 107 #endif
 108
 109 #endif /* CONFIG_RAMBOOT_PBL */
 110
 111 #ifndef CONFIG_SYS_TEXT_BASE
 112 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 113 #endif
 114
 115 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 116 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 117 #endif
 118
 119 #ifndef CONFIG_SYS_NO_FLASH
 120 #define CONFIG_FLASH_CFI_DRIVER
 121 #define CONFIG_SYS_FLASH_CFI
 122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 123 #endif
 124
 125 /* PCIe Boot - Master */
 126 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 127 /*
 128  * for slave u-boot IMAGE instored in master memory space,
 129  * PHYS must be aligned based on the SIZE
 130  */
 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 133 #ifdef CONFIG_PHYS_64BIT
 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 136 #else
 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 138 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 139 #endif
 140 /*
 141  * for slave UCODE and ENV instored in master memory space,
 142  * PHYS must be aligned based on the SIZE
 143  */
 144 #ifdef CONFIG_PHYS_64BIT
 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 147 #else
 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 149 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 150 #endif
 151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 152 /* slave core release by master*/
 153 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 154 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 155
 156 /* PCIe Boot - Slave */
 157 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 159 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 160                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 161 /* Set 1M boot space for PCIe boot */
 162 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 163 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 164                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 165 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 166 #define CONFIG_SYS_NO_FLASH
 167 #endif
 168
 169 #if defined(CONFIG_SPIFLASH)
 170 #define CONFIG_SYS_EXTRA_ENV_RELOC
 171 #define CONFIG_ENV_IS_IN_SPI_FLASH
 172 #define CONFIG_ENV_SPI_BUS              0
 173 #define CONFIG_ENV_SPI_CS               0
 174 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 175 #define CONFIG_ENV_SPI_MODE             0
 176 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 177 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 178 #if defined(CONFIG_TARGET_T1024RDB)
 179 #define CONFIG_ENV_SECT_SIZE            0x10000
 180 #elif defined(CONFIG_TARGET_T1023RDB)
 181 #define CONFIG_ENV_SECT_SIZE            0x40000
 182 #endif
 183 #elif defined(CONFIG_SDCARD)
 184 #define CONFIG_SYS_EXTRA_ENV_RELOC
 185 #define CONFIG_ENV_IS_IN_MMC
 186 #define CONFIG_SYS_MMC_ENV_DEV          0
 187 #define CONFIG_ENV_SIZE                 0x2000
 188 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 189 #elif defined(CONFIG_NAND)
 190 #define CONFIG_SYS_EXTRA_ENV_RELOC
 191 #define CONFIG_ENV_IS_IN_NAND
 192 #define CONFIG_ENV_SIZE                 0x2000
 193 #if defined(CONFIG_TARGET_T1024RDB)
 194 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 195 #elif defined(CONFIG_TARGET_T1023RDB)
 196 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 197 #endif
 198 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 199 #define CONFIG_ENV_IS_IN_REMOTE
 200 #define CONFIG_ENV_ADDR         0xffe20000
 201 #define CONFIG_ENV_SIZE         0x2000
 202 #elif defined(CONFIG_ENV_IS_NOWHERE)
 203 #define CONFIG_ENV_SIZE         0x2000
 204 #else
 205 #define CONFIG_ENV_IS_IN_FLASH
 206 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 207 #define CONFIG_ENV_SIZE         0x2000
 208 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 209 #endif
 210
 211 #ifndef __ASSEMBLY__
 212 unsigned long get_board_sys_clk(void);
 213 unsigned long get_board_ddr_clk(void);
 214 #endif
 215
 216 #define CONFIG_SYS_CLK_FREQ     100000000
 217 #define CONFIG_DDR_CLK_FREQ     100000000
 218
 219 /*
 220  * These can be toggled for performance analysis, otherwise use default.
 221  */
 222 #define CONFIG_SYS_CACHE_STASHING
 223 #define CONFIG_BACKSIDE_L2_CACHE
 224 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 225 #define CONFIG_BTB                      /* toggle branch predition */
 226 #define CONFIG_DDR_ECC
 227 #ifdef CONFIG_DDR_ECC
 228 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 229 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 230 #endif
 231
 232 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 233 #define CONFIG_SYS_MEMTEST_END          0x00400000
 234 #define CONFIG_SYS_ALT_MEMTEST
 235 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 236
 237 /*
 238  *  Config the L3 Cache as L3 SRAM
 239  */
 240 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 241 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 242 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 243 #ifdef CONFIG_RAMBOOT_PBL
 244 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 245 #endif
 246 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 247 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 248 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 249 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 250
 251 #ifdef CONFIG_PHYS_64BIT
 252 #define CONFIG_SYS_DCSRBAR              0xf0000000
 253 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 254 #endif
 255
 256 /* EEPROM */
 257 #define CONFIG_ID_EEPROM
 258 #define CONFIG_SYS_I2C_EEPROM_NXID
 259 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 260 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 261 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 263 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 264
 265 /*
 266  * DDR Setup
 267  */
 268 #define CONFIG_VERY_BIG_RAM
 269 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 270 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 271 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 272 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 273 #define CONFIG_FSL_DDR_INTERACTIVE
 274 #if defined(CONFIG_TARGET_T1024RDB)
 275 #define CONFIG_DDR_SPD
 276 #define CONFIG_SYS_FSL_DDR3
 277 #define CONFIG_SYS_SPD_BUS_NUM  0
 278 #define SPD_EEPROM_ADDRESS      0x51
 279 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 280 #elif defined(CONFIG_TARGET_T1023RDB)
 281 #define CONFIG_SYS_FSL_DDR4
 282 #define CONFIG_SYS_DDR_RAW_TIMING
 283 #define CONFIG_SYS_SDRAM_SIZE   2048
 284 #endif
 285
 286 /*
 287  * IFC Definitions
 288  */
 289 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 290 #ifdef CONFIG_PHYS_64BIT
 291 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 292 #else
 293 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 294 #endif
 295
 296 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 297 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 298                                 CSPR_PORT_SIZE_16 | \
 299                                 CSPR_MSEL_NOR | \
 300                                 CSPR_V)
 301 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 302
 303 /* NOR Flash Timing Params */
 304 #if defined(CONFIG_TARGET_T1024RDB)
 305 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 306 #elif defined(CONFIG_TARGET_T1023RDB)
 307 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 308                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 309 #endif
 310 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 311                                 FTIM0_NOR_TEADC(0x5) | \
 312                                 FTIM0_NOR_TEAHC(0x5))
 313 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 314                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 315                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 316 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 317                                 FTIM2_NOR_TCH(0x4) | \
 318                                 FTIM2_NOR_TWPH(0x0E) | \
 319                                 FTIM2_NOR_TWP(0x1c))
 320 #define CONFIG_SYS_NOR_FTIM3    0x0
 321
 322 #define CONFIG_SYS_FLASH_QUIET_TEST
 323 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 324
 325 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 326 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 327 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 328 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 329
 330 #define CONFIG_SYS_FLASH_EMPTY_INFO
 331 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 332
 333 #ifdef CONFIG_TARGET_T1024RDB
 334 /* CPLD on IFC */
 335 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 336 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 337 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 338 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 339                                                 | CSPR_PORT_SIZE_8 \
 340                                                 | CSPR_MSEL_GPCM \
 341                                                 | CSPR_V)
 342 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 343 #define CONFIG_SYS_CSOR2                0x0
 344
 345 /* CPLD Timing parameters for IFC CS2 */
 346 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 347                                                 FTIM0_GPCM_TEADC(0x0e) | \
 348                                                 FTIM0_GPCM_TEAHC(0x0e))
 349 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 350                                                 FTIM1_GPCM_TRAD(0x1f))
 351 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 352                                                 FTIM2_GPCM_TCH(0x8) | \
 353                                                 FTIM2_GPCM_TWP(0x1f))
 354 #define CONFIG_SYS_CS2_FTIM3            0x0
 355 #endif
 356
 357 /* NAND Flash on IFC */
 358 #define CONFIG_NAND_FSL_IFC
 359 #define CONFIG_SYS_NAND_BASE            0xff800000
 360 #ifdef CONFIG_PHYS_64BIT
 361 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 362 #else
 363 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 364 #endif
 365 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 366 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 367                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 368                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 369                                 | CSPR_V)
 370 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 371
 372 #if defined(CONFIG_TARGET_T1024RDB)
 373 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 374                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 375                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 376                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 377                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 378                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 379                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 380 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 381 #elif defined(CONFIG_TARGET_T1023RDB)
 382 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 383                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 384                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 385                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 386                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 387                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 388                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 389 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 390 #endif
 391
 392 #define CONFIG_SYS_NAND_ONFI_DETECTION
 393 /* ONFI NAND Flash mode0 Timing Params */
 394 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 395                                         FTIM0_NAND_TWP(0x18)   | \
 396                                         FTIM0_NAND_TWCHT(0x07) | \
 397                                         FTIM0_NAND_TWH(0x0a))
 398 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 399                                         FTIM1_NAND_TWBE(0x39)  | \
 400                                         FTIM1_NAND_TRR(0x0e)   | \
 401                                         FTIM1_NAND_TRP(0x18))
 402 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 403                                         FTIM2_NAND_TREH(0x0a) | \
 404                                         FTIM2_NAND_TWHRE(0x1e))
 405 #define CONFIG_SYS_NAND_FTIM3           0x0
 406
 407 #define CONFIG_SYS_NAND_DDR_LAW         11
 408 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 409 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 410 #define CONFIG_CMD_NAND
 411
 412 #if defined(CONFIG_NAND)
 413 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 414 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 415 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 416 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 417 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 418 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 419 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 420 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 421 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 422 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 423 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 424 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 425 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 426 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 427 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 428 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 429 #else
 430 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 431 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 432 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 433 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 434 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 435 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 436 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 437 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 438 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 439 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 440 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 441 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 442 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 443 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 444 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 445 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 446 #endif
 447
 448 #ifdef CONFIG_SPL_BUILD
 449 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 450 #else
 451 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 452 #endif
 453
 454 #if defined(CONFIG_RAMBOOT_PBL)
 455 #define CONFIG_SYS_RAMBOOT
 456 #endif
 457
 458 #define CONFIG_BOARD_EARLY_INIT_R
 459 #define CONFIG_MISC_INIT_R
 460
 461 #define CONFIG_HWCONFIG
 462
 463 /* define to use L1 as initial stack */
 464 #define CONFIG_L1_INIT_RAM
 465 #define CONFIG_SYS_INIT_RAM_LOCK
 466 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 467 #ifdef CONFIG_PHYS_64BIT
 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 470 /* The assembler doesn't like typecast */
 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 472         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 473           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 474 #else
 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 478 #endif
 479 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 480
 481 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 482                                         GENERATED_GBL_DATA_SIZE)
 483 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 484
 485 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 486 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 487
 488 /* Serial Port */
 489 #define CONFIG_CONS_INDEX       1
 490 #define CONFIG_SYS_NS16550_SERIAL
 491 #define CONFIG_SYS_NS16550_REG_SIZE     1
 492 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 493
 494 #define CONFIG_SYS_BAUDRATE_TABLE       \
 495         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 496
 497 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 498 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 499 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 500 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 501
 502 /* Video */
 503 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 504 #ifdef CONFIG_FSL_DIU_FB
 505 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 506 #define CONFIG_CMD_BMP
 507 #define CONFIG_VIDEO_LOGO
 508 #define CONFIG_VIDEO_BMP_LOGO
 509 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 510 /*
 511  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 512  * disable empty flash sector detection, which is I/O-intensive.
 513  */
 514 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 515 #endif
 516
 517 /* I2C */
 518 #define CONFIG_SYS_I2C
 519 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 520 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 521 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 522 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 523 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 524 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 525 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 526
 527 #define I2C_PCA6408_BUS_NUM             1
 528 #define I2C_PCA6408_ADDR                0x20
 529
 530 /* I2C bus multiplexer */
 531 #define I2C_MUX_CH_DEFAULT      0x8
 532
 533 /*
 534  * RTC configuration
 535  */
 536 #define RTC
 537 #define CONFIG_RTC_DS1337       1
 538 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 539
 540 /*
 541  * eSPI - Enhanced SPI
 542  */
 543 #define CONFIG_SPI_FLASH_BAR
 544 #define CONFIG_SF_DEFAULT_SPEED 10000000
 545 #define CONFIG_SF_DEFAULT_MODE  0
 546
 547 /*
 548  * General PCIe
 549  * Memory space is mapped 1-1, but I/O space must start from 0.
 550  */
 551 #define CONFIG_PCIE1            /* PCIE controller 1 */
 552 #define CONFIG_PCIE2            /* PCIE controller 2 */
 553 #define CONFIG_PCIE3            /* PCIE controller 3 */
 554 #ifdef CONFIG_ARCH_T1040
 555 #define CONFIG_PCIE4            /* PCIE controller 4 */
 556 #endif
 557 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 558 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 559 #define CONFIG_PCI_INDIRECT_BRIDGE
 560
 561 #ifdef CONFIG_PCI
 562 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 563 #ifdef CONFIG_PCIE1
 564 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 565 #ifdef CONFIG_PHYS_64BIT
 566 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 567 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 568 #else
 569 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 570 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 571 #endif
 572 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 573 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 574 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 575 #ifdef CONFIG_PHYS_64BIT
 576 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 577 #else
 578 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 579 #endif
 580 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 581 #endif
 582
 583 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 584 #ifdef CONFIG_PCIE2
 585 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 586 #ifdef CONFIG_PHYS_64BIT
 587 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 588 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 589 #else
 590 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 591 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 592 #endif
 593 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 594 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 595 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 596 #ifdef CONFIG_PHYS_64BIT
 597 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 598 #else
 599 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 600 #endif
 601 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 602 #endif
 603
 604 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 605 #ifdef CONFIG_PCIE3
 606 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 607 #ifdef CONFIG_PHYS_64BIT
 608 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 609 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 610 #else
 611 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 612 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 613 #endif
 614 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 615 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 616 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 617 #ifdef CONFIG_PHYS_64BIT
 618 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 619 #else
 620 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 621 #endif
 622 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 623 #endif
 624
 625 /* controller 4, Base address 203000, to be removed */
 626 #ifdef CONFIG_PCIE4
 627 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 628 #ifdef CONFIG_PHYS_64BIT
 629 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 630 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 631 #else
 632 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 633 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 634 #endif
 635 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 636 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 637 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 638 #ifdef CONFIG_PHYS_64BIT
 639 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 640 #else
 641 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 642 #endif
 643 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 644 #endif
 645
 646 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 647 #define CONFIG_DOS_PARTITION
 648 #endif  /* CONFIG_PCI */
 649
 650 /*
 651  * USB
 652  */
 653 #define CONFIG_HAS_FSL_DR_USB
 654
 655 #ifdef CONFIG_HAS_FSL_DR_USB
 656 #define CONFIG_USB_EHCI
 657 #define CONFIG_USB_EHCI_FSL
 658 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 659 #endif
 660
 661 /*
 662  * SDHC
 663  */
 664 #ifdef CONFIG_MMC
 665 #define CONFIG_FSL_ESDHC
 666 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 667 #define CONFIG_GENERIC_MMC
 668 #define CONFIG_DOS_PARTITION
 669 #endif
 670
 671 /* Qman/Bman */
 672 #ifndef CONFIG_NOBQFMAN
 673 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 674 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 675 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 676 #ifdef CONFIG_PHYS_64BIT
 677 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 678 #else
 679 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 680 #endif
 681 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 682 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 683 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 684 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 685 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 686 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 687                                         CONFIG_SYS_BMAN_CENA_SIZE)
 688 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 689 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 690 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 691 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 692 #ifdef CONFIG_PHYS_64BIT
 693 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 694 #else
 695 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 696 #endif
 697 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 698 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 699 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 700 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 701 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 702 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 703                                         CONFIG_SYS_QMAN_CENA_SIZE)
 704 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 705 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 706
 707 #define CONFIG_SYS_DPAA_FMAN
 708
 709 #ifdef CONFIG_TARGET_T1024RDB
 710 #define CONFIG_QE
 711 #define CONFIG_U_QE
 712 #endif
 713 /* Default address of microcode for the Linux FMan driver */
 714 #if defined(CONFIG_SPIFLASH)
 715 /*
 716  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 717  * env, so we got 0x110000.
 718  */
 719 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 720 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 721 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 722 #elif defined(CONFIG_SDCARD)
 723 /*
 724  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 725  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 726  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 727  */
 728 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 729 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 730 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 731 #elif defined(CONFIG_NAND)
 732 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 733 #if defined(CONFIG_TARGET_T1024RDB)
 734 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 735 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 736 #elif defined(CONFIG_TARGET_T1023RDB)
 737 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 738 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 739 #endif
 740 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 741 /*
 742  * Slave has no ucode locally, it can fetch this from remote. When implementing
 743  * in two corenet boards, slave's ucode could be stored in master's memory
 744  * space, the address can be mapped from slave TLB->slave LAW->
 745  * slave SRIO or PCIE outbound window->master inbound window->
 746  * master LAW->the ucode address in master's memory space.
 747  */
 748 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 749 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 750 #else
 751 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 752 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 753 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 754 #endif
 755 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 756 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 757 #endif /* CONFIG_NOBQFMAN */
 758
 759 #ifdef CONFIG_SYS_DPAA_FMAN
 760 #define CONFIG_FMAN_ENET
 761 #define CONFIG_PHYLIB_10G
 762 #define CONFIG_PHY_REALTEK
 763 #define CONFIG_PHY_AQUANTIA
 764 #if defined(CONFIG_TARGET_T1024RDB)
 765 #define RGMII_PHY1_ADDR         0x2
 766 #define RGMII_PHY2_ADDR         0x6
 767 #define SGMII_AQR_PHY_ADDR      0x2
 768 #define FM1_10GEC1_PHY_ADDR     0x1
 769 #elif defined(CONFIG_TARGET_T1023RDB)
 770 #define RGMII_PHY1_ADDR         0x1
 771 #define SGMII_RTK_PHY_ADDR      0x3
 772 #define SGMII_AQR_PHY_ADDR      0x2
 773 #endif
 774 #endif
 775
 776 #ifdef CONFIG_FMAN_ENET
 777 #define CONFIG_MII              /* MII PHY management */
 778 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 779 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 780 #endif
 781
 782 /*
 783  * Dynamic MTD Partition support with mtdparts
 784  */
 785 #ifndef CONFIG_SYS_NO_FLASH
 786 #define CONFIG_MTD_DEVICE
 787 #define CONFIG_MTD_PARTITIONS
 788 #define CONFIG_CMD_MTDPARTS
 789 #define CONFIG_FLASH_CFI_MTD
 790 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 791                         "spi0=spife110000.1"
 792 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 793                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 794                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
 795                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 796 #endif
 797
 798 /*
 799  * Environment
 800  */
 801 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 802 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 803
 804 /*
 805  * Command line configuration.
 806  */
 807 #define CONFIG_CMD_DATE
 808 #define CONFIG_CMD_EEPROM
 809 #define CONFIG_CMD_ERRATA
 810 #define CONFIG_CMD_IRQ
 811 #define CONFIG_CMD_REGINFO
 812
 813 #ifdef CONFIG_PCI
 814 #define CONFIG_CMD_PCI
 815 #endif
 816
 817 /*
 818  * Miscellaneous configurable options
 819  */
 820 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 821 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 822 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 823 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 824 #ifdef CONFIG_CMD_KGDB
 825 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 826 #else
 827 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 828 #endif
 829 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 830 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 831 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 832
 833 /*
 834  * For booting Linux, the board info and command line data
 835  * have to be in the first 64 MB of memory, since this is
 836  * the maximum mapped by the Linux kernel during initialization.
 837  */
 838 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 839 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 840
 841 #ifdef CONFIG_CMD_KGDB
 842 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 843 #endif
 844
 845 /*
 846  * Environment Configuration
 847  */
 848 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 849 #define CONFIG_BOOTFILE         "uImage"
 850 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 851 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 852 #define CONFIG_BAUDRATE         115200
 853 #define __USB_PHY_TYPE          utmi
 854
 855 #ifdef CONFIG_ARCH_T1024
 856 #define CONFIG_BOARDNAME t1024rdb
 857 #define BANK_INTLV cs0_cs1
 858 #else
 859 #define CONFIG_BOARDNAME t1023rdb
 860 #define BANK_INTLV  null
 861 #endif
 862
 863 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 864         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 865         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 866         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 867         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 868         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 869         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 870         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 871         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 872         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 873         "netdev=eth0\0"                                         \
 874         "tftpflash=tftpboot $loadaddr $uboot && "               \
 875         "protect off $ubootaddr +$filesize && "                 \
 876         "erase $ubootaddr +$filesize && "                       \
 877         "cp.b $loadaddr $ubootaddr $filesize && "               \
 878         "protect on $ubootaddr +$filesize && "                  \
 879         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 880         "consoledev=ttyS0\0"                                    \
 881         "ramdiskaddr=2000000\0"                                 \
 882         "fdtaddr=1e00000\0"                                     \
 883         "bdev=sda3\0"
 884
 885 #define CONFIG_LINUX                                    \
 886         "setenv bootargs root=/dev/ram rw "             \
 887         "console=$consoledev,$baudrate $othbootargs;"   \
 888         "setenv ramdiskaddr 0x02000000;"                \
 889         "setenv fdtaddr 0x00c00000;"                    \
 890         "setenv loadaddr 0x1000000;"                    \
 891         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 892
 893 #define CONFIG_NFSBOOTCOMMAND                   \
 894         "setenv bootargs root=/dev/nfs rw "     \
 895         "nfsroot=$serverip:$rootpath "          \
 896         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 897         "console=$consoledev,$baudrate $othbootargs;"   \
 898         "tftp $loadaddr $bootfile;"             \
 899         "tftp $fdtaddr $fdtfile;"               \
 900         "bootm $loadaddr - $fdtaddr"
 901
 902 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 903
 904 /* Hash command with SHA acceleration supported in hardware */
 905 #ifdef CONFIG_FSL_CAAM
 906 #define CONFIG_CMD_HASH
 907 #define CONFIG_SHA_HW_ACCEL
 908 #endif
 909
 910 #include <asm/fsl_secure_boot.h>
 911
 912 #endif  /* __T1024RDB_H */