include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_E500                     /* BOOKE e500 family */
  14 #include <asm/config_mpc85xx.h>
  15
  16 #ifdef CONFIG_RAMBOOT_PBL
  17
  18 #ifndef CONFIG_SECURE_BOOT
  19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  20 #else
  21 #define CONFIG_SYS_FSL_PBL_PBI \
  22                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  23 #endif
  24
  25 #define CONFIG_SPL_FLUSH_IMAGE
  26 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  27 #define CONFIG_SYS_TEXT_BASE            0x30001000
  28 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  29 #define CONFIG_SPL_PAD_TO               0x40000
  30 #define CONFIG_SPL_MAX_SIZE             0x28000
  31 #ifdef CONFIG_SPL_BUILD
  32 #define CONFIG_SPL_SKIP_RELOCATE
  33 #define CONFIG_SPL_COMMON_INIT_DDR
  34 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  35 #define CONFIG_SYS_NO_FLASH
  36 #endif
  37 #define RESET_VECTOR_OFFSET             0x27FFC
  38 #define BOOT_PAGE_OFFSET                0x27000
  39
  40 #ifdef CONFIG_NAND
  41 #ifdef CONFIG_SECURE_BOOT
  42 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  43 /*
  44  * HDR would be appended at end of image and copied to DDR along
  45  * with U-Boot image.
  46  */
  47 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  48                                          CONFIG_U_BOOT_HDR_SIZE)
  49 #else
  50 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  51 #endif
  52 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  53 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  54 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  56 #ifdef CONFIG_TARGET_T1040RDB
  57 #define CONFIG_SYS_FSL_PBL_RCW \
  58 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  59 #endif
  60 #ifdef CONFIG_TARGET_T1042RDB_PI
  61 #define CONFIG_SYS_FSL_PBL_RCW \
  62 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  63 #endif
  64 #ifdef CONFIG_TARGET_T1042RDB
  65 #define CONFIG_SYS_FSL_PBL_RCW \
  66 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  67 #endif
  68 #ifdef CONFIG_TARGET_T1040D4RDB
  69 #define CONFIG_SYS_FSL_PBL_RCW \
  70 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  71 #endif
  72 #ifdef CONFIG_TARGET_T1042D4RDB
  73 #define CONFIG_SYS_FSL_PBL_RCW \
  74 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  75 #endif
  76 #define CONFIG_SPL_NAND_BOOT
  77 #endif
  78
  79 #ifdef CONFIG_SPIFLASH
  80 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  81 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  86 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  87 #ifndef CONFIG_SPL_BUILD
  88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  89 #endif
  90 #ifdef CONFIG_TARGET_T1040RDB
  91 #define CONFIG_SYS_FSL_PBL_RCW \
  92 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  93 #endif
  94 #ifdef CONFIG_TARGET_T1042RDB_PI
  95 #define CONFIG_SYS_FSL_PBL_RCW \
  96 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  97 #endif
  98 #ifdef CONFIG_TARGET_T1042RDB
  99 #define CONFIG_SYS_FSL_PBL_RCW \
 100 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
 101 #endif
 102 #ifdef CONFIG_TARGET_T1040D4RDB
 103 #define CONFIG_SYS_FSL_PBL_RCW \
 104 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
 105 #endif
 106 #ifdef CONFIG_TARGET_T1042D4RDB
 107 #define CONFIG_SYS_FSL_PBL_RCW \
 108 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 109 #endif
 110 #define CONFIG_SPL_SPI_BOOT
 111 #endif
 112
 113 #ifdef CONFIG_SDCARD
 114 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 115 #define CONFIG_SPL_MMC_MINIMAL
 116 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 117 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 118 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 119 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 120 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 121 #ifndef CONFIG_SPL_BUILD
 122 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 123 #endif
 124 #ifdef CONFIG_TARGET_T1040RDB
 125 #define CONFIG_SYS_FSL_PBL_RCW \
 126 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 127 #endif
 128 #ifdef CONFIG_TARGET_T1042RDB_PI
 129 #define CONFIG_SYS_FSL_PBL_RCW \
 130 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 131 #endif
 132 #ifdef CONFIG_TARGET_T1042RDB
 133 #define CONFIG_SYS_FSL_PBL_RCW \
 134 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 135 #endif
 136 #ifdef CONFIG_TARGET_T1040D4RDB
 137 #define CONFIG_SYS_FSL_PBL_RCW \
 138 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 139 #endif
 140 #ifdef CONFIG_TARGET_T1042D4RDB
 141 #define CONFIG_SYS_FSL_PBL_RCW \
 142 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 143 #endif
 144 #define CONFIG_SPL_MMC_BOOT
 145 #endif
 146
 147 #endif
 148
 149 /* High Level Configuration Options */
 150 #define CONFIG_BOOKE
 151 #define CONFIG_E500MC                   /* BOOKE e500mc family */
 152 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 153 #define CONFIG_MP                       /* support multiple processors */
 154
 155 /* support deep sleep */
 156 #define CONFIG_DEEP_SLEEP
 157 #if defined(CONFIG_DEEP_SLEEP)
 158 #define CONFIG_BOARD_EARLY_INIT_F
 159 #endif
 160
 161 #ifndef CONFIG_SYS_TEXT_BASE
 162 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 163 #endif
 164
 165 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 166 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 167 #endif
 168
 169 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 170 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
 171 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 172 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 173 #define CONFIG_PCI_INDIRECT_BRIDGE
 174 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 175 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 176 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 177 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 178
 179 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 180 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 181
 182 #define CONFIG_ENV_OVERWRITE
 183
 184 #ifndef CONFIG_SYS_NO_FLASH
 185 #define CONFIG_FLASH_CFI_DRIVER
 186 #define CONFIG_SYS_FLASH_CFI
 187 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 188 #endif
 189
 190 #if defined(CONFIG_SPIFLASH)
 191 #define CONFIG_SYS_EXTRA_ENV_RELOC
 192 #define CONFIG_ENV_IS_IN_SPI_FLASH
 193 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 194 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 195 #define CONFIG_ENV_SECT_SIZE            0x10000
 196 #elif defined(CONFIG_SDCARD)
 197 #define CONFIG_SYS_EXTRA_ENV_RELOC
 198 #define CONFIG_ENV_IS_IN_MMC
 199 #define CONFIG_SYS_MMC_ENV_DEV          0
 200 #define CONFIG_ENV_SIZE                 0x2000
 201 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 202 #elif defined(CONFIG_NAND)
 203 #ifdef CONFIG_SECURE_BOOT
 204 #define CONFIG_RAMBOOT_NAND
 205 #define CONFIG_BOOTSCRIPT_COPY_RAM
 206 #endif
 207 #define CONFIG_SYS_EXTRA_ENV_RELOC
 208 #define CONFIG_ENV_IS_IN_NAND
 209 #define CONFIG_ENV_SIZE                 0x2000
 210 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 211 #else
 212 #define CONFIG_ENV_IS_IN_FLASH
 213 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 214 #define CONFIG_ENV_SIZE         0x2000
 215 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 216 #endif
 217
 218 #define CONFIG_SYS_CLK_FREQ     100000000
 219 #define CONFIG_DDR_CLK_FREQ     66666666
 220
 221 /*
 222  * These can be toggled for performance analysis, otherwise use default.
 223  */
 224 #define CONFIG_SYS_CACHE_STASHING
 225 #define CONFIG_BACKSIDE_L2_CACHE
 226 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 227 #define CONFIG_BTB                      /* toggle branch predition */
 228 #define CONFIG_DDR_ECC
 229 #ifdef CONFIG_DDR_ECC
 230 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 231 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 232 #endif
 233
 234 #define CONFIG_ENABLE_36BIT_PHYS
 235
 236 #define CONFIG_ADDR_MAP
 237 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 238
 239 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 240 #define CONFIG_SYS_MEMTEST_END          0x00400000
 241 #define CONFIG_SYS_ALT_MEMTEST
 242 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 243
 244 /*
 245  *  Config the L3 Cache as L3 SRAM
 246  */
 247 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 248 /*
 249  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 250  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 251  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 252  */
 253 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 254 #define CONFIG_SYS_L3_SIZE              256 << 10
 255 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 256 #ifdef CONFIG_RAMBOOT_PBL
 257 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 258 #endif
 259 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 260 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 261 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 262 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 263
 264 #define CONFIG_SYS_DCSRBAR              0xf0000000
 265 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 266
 267 /*
 268  * DDR Setup
 269  */
 270 #define CONFIG_VERY_BIG_RAM
 271 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 272 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 273
 274 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 275 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 276 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 277
 278 #define CONFIG_DDR_SPD
 279 #ifndef CONFIG_SYS_FSL_DDR4
 280 #define CONFIG_SYS_FSL_DDR3
 281 #endif
 282
 283 #define CONFIG_SYS_SPD_BUS_NUM  0
 284 #define SPD_EEPROM_ADDRESS      0x51
 285
 286 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 287
 288 /*
 289  * IFC Definitions
 290  */
 291 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 292 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 293
 294 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 295 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 296                                 CSPR_PORT_SIZE_16 | \
 297                                 CSPR_MSEL_NOR | \
 298                                 CSPR_V)
 299 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 300
 301 /*
 302  * TDM Definition
 303  */
 304 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 305
 306 /* NOR Flash Timing Params */
 307 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 308 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 309                                 FTIM0_NOR_TEADC(0x5) | \
 310                                 FTIM0_NOR_TEAHC(0x5))
 311 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 312                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 313                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 314 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 315                                 FTIM2_NOR_TCH(0x4) | \
 316                                 FTIM2_NOR_TWPH(0x0E) | \
 317                                 FTIM2_NOR_TWP(0x1c))
 318 #define CONFIG_SYS_NOR_FTIM3    0x0
 319
 320 #define CONFIG_SYS_FLASH_QUIET_TEST
 321 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 322
 323 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 324 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 325 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 326 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 327
 328 #define CONFIG_SYS_FLASH_EMPTY_INFO
 329 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 330
 331 /* CPLD on IFC */
 332 #define CPLD_LBMAP_MASK                 0x3F
 333 #define CPLD_BANK_SEL_MASK              0x07
 334 #define CPLD_BANK_OVERRIDE              0x40
 335 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 336 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 337 #define CPLD_LBMAP_RESET                0xFF
 338 #define CPLD_LBMAP_SHIFT                0x03
 339
 340 #if defined(CONFIG_TARGET_T1042RDB_PI)
 341 #define CPLD_DIU_SEL_DFP                0x80
 342 #elif defined(CONFIG_TARGET_T1042D4RDB)
 343 #define CPLD_DIU_SEL_DFP                0xc0
 344 #endif
 345
 346 #if defined(CONFIG_TARGET_T1040D4RDB)
 347 #define CPLD_INT_MASK_ALL               0xFF
 348 #define CPLD_INT_MASK_THERM             0x80
 349 #define CPLD_INT_MASK_DVI_DFP           0x40
 350 #define CPLD_INT_MASK_QSGMII1           0x20
 351 #define CPLD_INT_MASK_QSGMII2           0x10
 352 #define CPLD_INT_MASK_SGMI1             0x08
 353 #define CPLD_INT_MASK_SGMI2             0x04
 354 #define CPLD_INT_MASK_TDMR1             0x02
 355 #define CPLD_INT_MASK_TDMR2             0x01
 356 #endif
 357
 358 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 359 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 360 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 361 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 362                                 | CSPR_PORT_SIZE_8 \
 363                                 | CSPR_MSEL_GPCM \
 364                                 | CSPR_V)
 365 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 366 #define CONFIG_SYS_CSOR2        0x0
 367 /* CPLD Timing parameters for IFC CS2 */
 368 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 369                                         FTIM0_GPCM_TEADC(0x0e) | \
 370                                         FTIM0_GPCM_TEAHC(0x0e))
 371 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 372                                         FTIM1_GPCM_TRAD(0x1f))
 373 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 374                                         FTIM2_GPCM_TCH(0x8) | \
 375                                         FTIM2_GPCM_TWP(0x1f))
 376 #define CONFIG_SYS_CS2_FTIM3            0x0
 377
 378 /* NAND Flash on IFC */
 379 #define CONFIG_NAND_FSL_IFC
 380 #define CONFIG_SYS_NAND_BASE            0xff800000
 381 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 382
 383 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 384 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 385                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 386                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 387                                 | CSPR_V)
 388 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 389
 390 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 391                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 392                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 393                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 394                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 395                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 396                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 397
 398 #define CONFIG_SYS_NAND_ONFI_DETECTION
 399
 400 /* ONFI NAND Flash mode0 Timing Params */
 401 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 402                                         FTIM0_NAND_TWP(0x18)   | \
 403                                         FTIM0_NAND_TWCHT(0x07) | \
 404                                         FTIM0_NAND_TWH(0x0a))
 405 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 406                                         FTIM1_NAND_TWBE(0x39)  | \
 407                                         FTIM1_NAND_TRR(0x0e)   | \
 408                                         FTIM1_NAND_TRP(0x18))
 409 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 410                                         FTIM2_NAND_TREH(0x0a) | \
 411                                         FTIM2_NAND_TWHRE(0x1e))
 412 #define CONFIG_SYS_NAND_FTIM3           0x0
 413
 414 #define CONFIG_SYS_NAND_DDR_LAW         11
 415 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 416 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 417 #define CONFIG_CMD_NAND
 418
 419 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 420
 421 #if defined(CONFIG_NAND)
 422 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 423 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 424 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 425 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 426 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 427 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 428 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 429 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 430 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 431 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 432 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 433 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 434 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 435 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 436 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 437 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 438 #else
 439 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 440 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 441 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 442 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 443 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 444 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 445 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 446 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 447 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 448 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 449 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 450 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 451 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 452 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 453 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 454 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 455 #endif
 456
 457 #ifdef CONFIG_SPL_BUILD
 458 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 459 #else
 460 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 461 #endif
 462
 463 #if defined(CONFIG_RAMBOOT_PBL)
 464 #define CONFIG_SYS_RAMBOOT
 465 #endif
 466
 467 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 468 #if defined(CONFIG_NAND)
 469 #define CONFIG_A008044_WORKAROUND
 470 #endif
 471 #endif
 472
 473 #define CONFIG_BOARD_EARLY_INIT_R
 474 #define CONFIG_MISC_INIT_R
 475
 476 #define CONFIG_HWCONFIG
 477
 478 /* define to use L1 as initial stack */
 479 #define CONFIG_L1_INIT_RAM
 480 #define CONFIG_SYS_INIT_RAM_LOCK
 481 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 484 /* The assembler doesn't like typecast */
 485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 486         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 487           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 488 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 489
 490 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 491                                         GENERATED_GBL_DATA_SIZE)
 492 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 493
 494 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 495 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 496
 497 /* Serial Port - controlled on board with jumper J8
 498  * open - index 2
 499  * shorted - index 1
 500  */
 501 #define CONFIG_CONS_INDEX       1
 502 #define CONFIG_SYS_NS16550_SERIAL
 503 #define CONFIG_SYS_NS16550_REG_SIZE     1
 504 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 505
 506 #define CONFIG_SYS_BAUDRATE_TABLE       \
 507         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 508
 509 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 510 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 511 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 512 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 513
 514 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 515 /* Video */
 516 #define CONFIG_FSL_DIU_FB
 517
 518 #ifdef CONFIG_FSL_DIU_FB
 519 #define CONFIG_FSL_DIU_CH7301
 520 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 521 #define CONFIG_CMD_BMP
 522 #define CONFIG_VIDEO_LOGO
 523 #define CONFIG_VIDEO_BMP_LOGO
 524 #endif
 525 #endif
 526
 527 /* I2C */
 528 #define CONFIG_SYS_I2C
 529 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 530 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 531 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 532 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 533 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 534 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 535 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 536 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 537 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 538 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 539 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 540 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 541 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 542
 543 /* I2C bus multiplexer */
 544 #define I2C_MUX_PCA_ADDR                0x70
 545 #define I2C_MUX_CH_DEFAULT      0x8
 546
 547 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 548         defined(CONFIG_TARGET_T1040D4RDB)       || \
 549         defined(CONFIG_TARGET_T1042D4RDB)
 550 /* LDI/DVI Encoder for display */
 551 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 552 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 553
 554 /*
 555  * RTC configuration
 556  */
 557 #define RTC
 558 #define CONFIG_RTC_DS1337               1
 559 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 560
 561 /*DVI encoder*/
 562 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 563 #endif
 564
 565 /*
 566  * eSPI - Enhanced SPI
 567  */
 568 #define CONFIG_SPI_FLASH_BAR
 569 #define CONFIG_SF_DEFAULT_SPEED         10000000
 570 #define CONFIG_SF_DEFAULT_MODE          0
 571 #define CONFIG_ENV_SPI_BUS              0
 572 #define CONFIG_ENV_SPI_CS               0
 573 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 574 #define CONFIG_ENV_SPI_MODE             0
 575
 576 /*
 577  * General PCI
 578  * Memory space is mapped 1-1, but I/O space must start from 0.
 579  */
 580
 581 #ifdef CONFIG_PCI
 582 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 583 #ifdef CONFIG_PCIE1
 584 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 585 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 586 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 587 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 588 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 589 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 590 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 591 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 592 #endif
 593
 594 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 595 #ifdef CONFIG_PCIE2
 596 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 597 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 598 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 599 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 600 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 601 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 602 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 603 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 604 #endif
 605
 606 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 607 #ifdef CONFIG_PCIE3
 608 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 609 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 610 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 611 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 612 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 613 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 614 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 615 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 616 #endif
 617
 618 /* controller 4, Base address 203000 */
 619 #ifdef CONFIG_PCIE4
 620 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 621 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 622 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 623 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 624 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 625 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 626 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 627 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 628 #endif
 629
 630 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 631 #define CONFIG_DOS_PARTITION
 632 #endif  /* CONFIG_PCI */
 633
 634 /* SATA */
 635 #define CONFIG_FSL_SATA_V2
 636 #ifdef CONFIG_FSL_SATA_V2
 637 #define CONFIG_LIBATA
 638 #define CONFIG_FSL_SATA
 639
 640 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 641 #define CONFIG_SATA1
 642 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 643 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 644
 645 #define CONFIG_LBA48
 646 #define CONFIG_CMD_SATA
 647 #define CONFIG_DOS_PARTITION
 648 #endif
 649
 650 /*
 651 * USB
 652 */
 653 #define CONFIG_HAS_FSL_DR_USB
 654
 655 #ifdef CONFIG_HAS_FSL_DR_USB
 656 #define CONFIG_USB_EHCI
 657
 658 #ifdef CONFIG_USB_EHCI
 659 #define CONFIG_USB_EHCI_FSL
 660 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 661 #endif
 662 #endif
 663
 664 #define CONFIG_MMC
 665
 666 #ifdef CONFIG_MMC
 667 #define CONFIG_FSL_ESDHC
 668 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 669 #define CONFIG_GENERIC_MMC
 670 #define CONFIG_DOS_PARTITION
 671 #endif
 672
 673 /* Qman/Bman */
 674 #ifndef CONFIG_NOBQFMAN
 675 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 676 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 677 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 678 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 679 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 680 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 681 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 682 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 683 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 684 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 685                                         CONFIG_SYS_BMAN_CENA_SIZE)
 686 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 687 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 688 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 689 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 690 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 691 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 692 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 693 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 694 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 695 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 696 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 697                                         CONFIG_SYS_QMAN_CENA_SIZE)
 698 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 699 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 700
 701 #define CONFIG_SYS_DPAA_FMAN
 702 #define CONFIG_SYS_DPAA_PME
 703
 704 #define CONFIG_QE
 705 #define CONFIG_U_QE
 706
 707 /* Default address of microcode for the Linux Fman driver */
 708 #if defined(CONFIG_SPIFLASH)
 709 /*
 710  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 711  * env, so we got 0x110000.
 712  */
 713 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 714 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 715 #elif defined(CONFIG_SDCARD)
 716 /*
 717  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 718  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 719  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 720  */
 721 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 722 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 723 #elif defined(CONFIG_NAND)
 724 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 725 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 726 #else
 727 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 728 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 729 #endif
 730
 731 #if defined(CONFIG_SPIFLASH)
 732 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 733 #elif defined(CONFIG_SDCARD)
 734 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 735 #elif defined(CONFIG_NAND)
 736 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 737 #else
 738 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 739 #endif
 740
 741 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 742 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 743 #endif /* CONFIG_NOBQFMAN */
 744
 745 #ifdef CONFIG_SYS_DPAA_FMAN
 746 #define CONFIG_FMAN_ENET
 747 #define CONFIG_PHY_VITESSE
 748 #define CONFIG_PHY_REALTEK
 749 #endif
 750
 751 #ifdef CONFIG_FMAN_ENET
 752 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 753 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 754 #elif defined(CONFIG_TARGET_T1040D4RDB)
 755 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 756 #elif defined(CONFIG_TARGET_T1042D4RDB)
 757 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 758 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 759 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 760 #endif
 761
 762 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 763 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 764 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 765 #else
 766 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 767 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 768 #endif
 769
 770 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 771 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 772 #define CONFIG_VSC9953
 773 #define CONFIG_CMD_ETHSW
 774 #ifdef CONFIG_TARGET_T1040RDB
 775 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 776 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 777 #else
 778 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 779 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 780 #endif
 781 #endif
 782
 783 #define CONFIG_MII              /* MII PHY management */
 784 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 785 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 786 #endif
 787
 788 /*
 789  * Environment
 790  */
 791 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 792 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 793
 794 /*
 795  * Command line configuration.
 796  */
 797 #ifdef CONFIG_TARGET_T1042RDB_PI
 798 #define CONFIG_CMD_DATE
 799 #endif
 800 #define CONFIG_CMD_ERRATA
 801 #define CONFIG_CMD_IRQ
 802 #define CONFIG_CMD_REGINFO
 803
 804 #ifdef CONFIG_PCI
 805 #define CONFIG_CMD_PCI
 806 #endif
 807
 808 /* Hash command with SHA acceleration supported in hardware */
 809 #ifdef CONFIG_FSL_CAAM
 810 #define CONFIG_CMD_HASH
 811 #define CONFIG_SHA_HW_ACCEL
 812 #endif
 813
 814 /*
 815  * Miscellaneous configurable options
 816  */
 817 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 818 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 819 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 820 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 821 #ifdef CONFIG_CMD_KGDB
 822 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 823 #else
 824 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 825 #endif
 826 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 827 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 828 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 829
 830 /*
 831  * For booting Linux, the board info and command line data
 832  * have to be in the first 64 MB of memory, since this is
 833  * the maximum mapped by the Linux kernel during initialization.
 834  */
 835 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 836 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 837
 838 #ifdef CONFIG_CMD_KGDB
 839 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 840 #endif
 841
 842 /*
 843  * Dynamic MTD Partition support with mtdparts
 844  */
 845 #ifndef CONFIG_SYS_NO_FLASH
 846 #define CONFIG_MTD_DEVICE
 847 #define CONFIG_MTD_PARTITIONS
 848 #define CONFIG_CMD_MTDPARTS
 849 #define CONFIG_FLASH_CFI_MTD
 850 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 851                         "spi0=spife110000.0"
 852 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 853                                 "128k(dtb),96m(fs),-(user);"\
 854                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 855                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 856                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 857 #endif
 858
 859 /*
 860  * Environment Configuration
 861  */
 862 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 863 #define CONFIG_BOOTFILE         "uImage"
 864 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 865
 866 /* default location for tftp and bootm */
 867 #define CONFIG_LOADADDR         1000000
 868
 869
 870 #define CONFIG_BAUDRATE 115200
 871
 872 #define __USB_PHY_TYPE  utmi
 873 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 874
 875 #ifdef CONFIG_TARGET_T1040RDB
 876 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 877 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 878 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 879 #elif defined(CONFIG_TARGET_T1042RDB)
 880 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 881 #elif defined(CONFIG_TARGET_T1040D4RDB)
 882 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 883 #elif defined(CONFIG_TARGET_T1042D4RDB)
 884 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 885 #endif
 886
 887 #ifdef CONFIG_FSL_DIU_FB
 888 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 889 #else
 890 #define DIU_ENVIRONMENT
 891 #endif
 892
 893 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 894         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 895         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 896         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 897         "netdev=eth0\0"                                         \
 898         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 899         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 900         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 901         "tftpflash=tftpboot $loadaddr $uboot && "               \
 902         "protect off $ubootaddr +$filesize && "                 \
 903         "erase $ubootaddr +$filesize && "                       \
 904         "cp.b $loadaddr $ubootaddr $filesize && "               \
 905         "protect on $ubootaddr +$filesize && "                  \
 906         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 907         "consoledev=ttyS0\0"                                    \
 908         "ramdiskaddr=2000000\0"                                 \
 909         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 910         "fdtaddr=1e00000\0"                                     \
 911         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 912         "bdev=sda3\0"
 913
 914 #define CONFIG_LINUX                       \
 915         "setenv bootargs root=/dev/ram rw "            \
 916         "console=$consoledev,$baudrate $othbootargs;"  \
 917         "setenv ramdiskaddr 0x02000000;"               \
 918         "setenv fdtaddr 0x00c00000;"                   \
 919         "setenv loadaddr 0x1000000;"                   \
 920         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 921
 922 #define CONFIG_HDBOOT                                   \
 923         "setenv bootargs root=/dev/$bdev rw "           \
 924         "console=$consoledev,$baudrate $othbootargs;"   \
 925         "tftp $loadaddr $bootfile;"                     \
 926         "tftp $fdtaddr $fdtfile;"                       \
 927         "bootm $loadaddr - $fdtaddr"
 928
 929 #define CONFIG_NFSBOOTCOMMAND                   \
 930         "setenv bootargs root=/dev/nfs rw "     \
 931         "nfsroot=$serverip:$rootpath "          \
 932         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 933         "console=$consoledev,$baudrate $othbootargs;"   \
 934         "tftp $loadaddr $bootfile;"             \
 935         "tftp $fdtaddr $fdtfile;"               \
 936         "bootm $loadaddr - $fdtaddr"
 937
 938 #define CONFIG_RAMBOOTCOMMAND                           \
 939         "setenv bootargs root=/dev/ram rw "             \
 940         "console=$consoledev,$baudrate $othbootargs;"   \
 941         "tftp $ramdiskaddr $ramdiskfile;"               \
 942         "tftp $loadaddr $bootfile;"                     \
 943         "tftp $fdtaddr $fdtfile;"                       \
 944         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 945
 946 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 947
 948 #include <asm/fsl_secure_boot.h>
 949
 950 #endif  /* __CONFIG_H */