include/configs/TQM8260.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * Imported from global configuration:
  33  *      CONFIG_MPC8255
  34  *      CONFIG_MPC8265
  35  *      CONFIG_200MHz
  36  *      CONFIG_266MHz
  37  *      CONFIG_300MHz
  38  *      CONFIG_L2_CACHE
  39  *      CONFIG_BUSMODE_60x
  40  */
  41
  42 /*
  43  * High Level Configuration Options
  44  * (easy to change)
  45  */
  46
  47 #define CONFIG_SYS_TEXT_BASE    0x40000000
  48
  49 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  50
  51 #if 0
  52 #define CONFIG_TQM8260          100     /* ...on a TQM8260 module Rev.100       */
  53 #else
  54 #define CONFIG_TQM8260          200     /* ...on a TQM8260 module Rev.200       */
  55 #endif
  56
  57 #define CONFIG_CPM2             1       /* Has a CPM2 */
  58
  59 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1                      */
  60
  61 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  62
  63 #define CONFIG_BOOTCOUNT_LIMIT
  64
  65 #define CONFIG_BAUDRATE         115200
  66
  67 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  68
  69 #undef  CONFIG_BOOTARGS
  70
  71 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  72         "netdev=eth0\0"                                                 \
  73         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  74                 "nfsroot=${serverip}:${rootpath}\0"                     \
  75         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  76         "addip=setenv bootargs ${bootargs} "                            \
  77                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  78                 ":${hostname}:${netdev}:off panic=1\0"                  \
  79         "flash_nfs=run nfsargs addip;"                                  \
  80                 "bootm ${kernel_addr}\0"                                \
  81         "flash_self=run ramargs addip;"                                 \
  82                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  83         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  84         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
  85         "bootfile=tqm8260/uImage\0"                             \
  86         "kernel_addr=400C0000\0"                                        \
  87         "ramdisk_addr=40240000\0"                                       \
  88         ""
  89 #define CONFIG_BOOTCOMMAND      "run flash_self"
  90
  91 /* enable I2C and select the hardware/software driver */
  92 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  93 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  94 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
  95 #define CONFIG_SYS_I2C_SLAVE            0x7F
  96
  97 /*
  98  * Software (bit-bang) I2C driver configuration
  99  */
 100
 101 /* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
 102 #if (CONFIG_TQM8260 <= 100)
 103
 104 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 105 #define I2C_ACTIVE      (iop->pdir |=  0x00020000)
 106 #define I2C_TRISTATE    (iop->pdir &= ~0x00020000)
 107 #define I2C_READ        ((iop->pdat & 0x00020000) != 0)
 108 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00020000; \
 109                         else    iop->pdat &= ~0x00020000
 110 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00010000; \
 111                         else    iop->pdat &= ~0x00010000
 112 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 113
 114 #else
 115
 116 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 117 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 118 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 119 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 120 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 121                         else    iop->pdat &= ~0x00010000
 122 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 123                         else    iop->pdat &= ~0x00020000
 124 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 125 #endif
 126
 127 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 128 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 129 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 130 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 131
 132 #define CONFIG_I2C_X
 133
 134 /*
 135  * select serial console configuration
 136  *
 137  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 138  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 139  * for SCC).
 140  *
 141  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 142  * defined elsewhere (for example, on the cogent platform, there are serial
 143  * ports on the motherboard which are used for the serial console - see
 144  * cogent/cma101/serial.[ch]).
 145  */
 146 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 147 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 148 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 149 #ifdef CONFIG_82xx_CONS_SMC1
 150 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 151 #endif
 152 #ifdef CONFIG_82xx_CONS_SMC2
 153 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 154 #endif
 155
 156 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 157 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 158 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 159
 160 /*
 161  * select ethernet configuration
 162  *
 163  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 164  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 165  * for FCC)
 166  *
 167  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 168  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 169  *
 170  * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 171  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 172  */
 173 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 174 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 175 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 176 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 177
 178 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 179
 180 /*
 181  *  - RX clk is CLK11
 182  *  - TX clk is CLK12
 183  */
 184 # define CONFIG_SYS_CMXSCR_VALUE1       (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 185
 186 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 187
 188 /*
 189  * - Rx-CLK is CLK13
 190  * - Tx-CLK is CLK14
 191  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 192  * - Enable Full Duplex in FSMR
 193  */
 194 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 195 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 196 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 197 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 198
 199 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 200
 201
 202 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 203 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
 204 #  define CONFIG_8260_CLKIN     66666666        /* in Hz */
 205 #else   /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
 206 # ifndef CONFIG_300MHz
 207 #  define CONFIG_8260_CLKIN     66666666        /* in Hz */
 208 # else
 209 #  define CONFIG_8260_CLKIN     83333000        /* in Hz */
 210 # endif
 211 #endif  /* CONFIG_MPC8255 */
 212
 213 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 214 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 215
 216 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 217
 218 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 219
 220
 221 /*
 222  * BOOTP options
 223  */
 224 #define CONFIG_BOOTP_SUBNETMASK
 225 #define CONFIG_BOOTP_GATEWAY
 226 #define CONFIG_BOOTP_HOSTNAME
 227 #define CONFIG_BOOTP_BOOTPATH
 228 #define CONFIG_BOOTP_BOOTFILESIZE
 229
 230
 231 /*
 232  * Command line configuration.
 233  */
 234 #include <config_cmd_default.h>
 235
 236 #define CONFIG_CMD_DHCP
 237 #define CONFIG_CMD_I2C
 238 #define CONFIG_CMD_EEPROM
 239 #define CONFIG_CMD_NFS
 240 #define CONFIG_CMD_SNTP
 241
 242
 243 /*
 244  * Miscellaneous configurable options
 245  */
 246 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 247 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 248
 249 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 250 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 251 #ifdef  CONFIG_SYS_HUSH_PARSER
 252 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 253 #endif
 254
 255 #if defined(CONFIG_CMD_KGDB)
 256 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 257 #else
 258 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 259 #endif
 260 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 261 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 262 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 263
 264 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 265 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 266
 267 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 268
 269 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 270
 271 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 272
 273 #define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC     /* "bad" address                */
 274
 275 /*
 276  * For booting Linux, the board info and command line data
 277  * have to be in the first 8 MB of memory, since this is
 278  * the maximum mapped by the Linux kernel during initialization.
 279  */
 280 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 281
 282
 283 /* What should the base address of the main FLASH be and how big is
 284  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
 285  * The main FLASH is whichever is connected to *CS0.
 286  */
 287 #define CONFIG_SYS_FLASH0_BASE 0x40000000
 288 #define CONFIG_SYS_FLASH1_BASE 0x60000000
 289 #define CONFIG_SYS_FLASH0_SIZE 32
 290 #define CONFIG_SYS_FLASH1_SIZE 32
 291
 292 /* Flash bank size (for preliminary settings)
 293  */
 294 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 295
 296 /*-----------------------------------------------------------------------
 297  * FLASH organization
 298  */
 299 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 300 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 301
 302 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 303 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 304
 305 /* use CFI flash driver */
 306 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 307 #define CONFIG_FLASH_CFI_DRIVER         1       /* Use the common driver */
 308 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 309 #define CONFIG_SYS_FLASH_EMPTY_INFO     1
 310 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
 311
 312 #define CONFIG_ENV_IS_IN_FLASH  1
 313 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x40000)
 314 #define CONFIG_ENV_SIZE         0x08000
 315 #define CONFIG_ENV_SECT_SIZE    0x40000
 316 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 317 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 318
 319 /*-----------------------------------------------------------------------
 320  * Hardware Information Block
 321  */
 322 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 323 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 324 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 325
 326 /*-----------------------------------------------------------------------
 327  * Hard Reset Configuration Words
 328  *
 329  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 330  * defines for the various registers affected by the HRCW e.g. changing
 331  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 332  */
 333 #define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 334
 335 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
 336 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0111)
 337 #else   /* ! MPC8255 && !MPC8265 */
 338 # if defined(CONFIG_266MHz)
 339 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0111)
 340 # elif defined(CONFIG_300MHz)
 341 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0110)
 342 # else
 343 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__)
 344 # endif
 345 #endif  /* CONFIG_MPC8255 */
 346
 347 /* no slaves so just fill with zeros */
 348 #define CONFIG_SYS_HRCW_SLAVE1          0
 349 #define CONFIG_SYS_HRCW_SLAVE2          0
 350 #define CONFIG_SYS_HRCW_SLAVE3          0
 351 #define CONFIG_SYS_HRCW_SLAVE4          0
 352 #define CONFIG_SYS_HRCW_SLAVE5          0
 353 #define CONFIG_SYS_HRCW_SLAVE6          0
 354 #define CONFIG_SYS_HRCW_SLAVE7          0
 355
 356 /*-----------------------------------------------------------------------
 357  * Internal Memory Mapped Register
 358  */
 359 #define CONFIG_SYS_IMMR         0xFFF00000
 360
 361 /*-----------------------------------------------------------------------
 362  * Definitions for initial stack pointer and data area (in DPRAM)
 363  */
 364 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 365 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 366 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 367 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 368
 369 /*-----------------------------------------------------------------------
 370  * Start addresses for the final memory configuration
 371  * (Set up by the startup code)
 372  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 373  *
 374  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
 375  * is mapped at SDRAM_BASE2_PRELIM.
 376  */
 377 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 378 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 379 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 380 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 381 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()*/
 382
 383 /*-----------------------------------------------------------------------
 384  * Cache Configuration
 385  */
 386 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 387 #if defined(CONFIG_CMD_KGDB)
 388 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 389 #endif
 390
 391 /*-----------------------------------------------------------------------
 392  * HIDx - Hardware Implementation-dependent Registers                    2-11
 393  *-----------------------------------------------------------------------
 394  * HID0 also contains cache control - initially enable both caches and
 395  * invalidate contents, then the final state leaves only the instruction
 396  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 397  * but Soft reset does not.
 398  *
 399  * HID1 has only read-only information - nothing to set.
 400  */
 401 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 402                                 HID0_IFEM|HID0_ABE)
 403 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 404 #define CONFIG_SYS_HID2        0
 405
 406 /*-----------------------------------------------------------------------
 407  * RMR - Reset Mode Register                                     5-5
 408  *-----------------------------------------------------------------------
 409  * turn on Checkstop Reset Enable
 410  */
 411 #define CONFIG_SYS_RMR         RMR_CSRE
 412
 413 /*-----------------------------------------------------------------------
 414  * BCR - Bus Configuration                                       4-25
 415  *-----------------------------------------------------------------------
 416  */
 417 #ifdef  CONFIG_BUSMODE_60x
 418 #define CONFIG_SYS_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
 419                          BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode  */
 420 #else
 421 #define BCR_APD01       0x10000000
 422 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 423 #endif
 424
 425 /*-----------------------------------------------------------------------
 426  * SIUMCR - SIU Module Configuration                             4-31
 427  *-----------------------------------------------------------------------
 428  */
 429 #if 0
 430 #define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
 431 #else
 432 #define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
 433 #endif
 434
 435
 436 /*-----------------------------------------------------------------------
 437  * SYPCR - System Protection Control                             4-35
 438  * SYPCR can only be written once after reset!
 439  *-----------------------------------------------------------------------
 440  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 441  */
 442 #if defined(CONFIG_WATCHDOG)
 443 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 444                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 445 #else
 446 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 447                          SYPCR_SWRI|SYPCR_SWP)
 448 #endif /* CONFIG_WATCHDOG */
 449
 450 /*-----------------------------------------------------------------------
 451  * TMCNTSC - Time Counter Status and Control                     4-40
 452  *-----------------------------------------------------------------------
 453  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 454  * and enable Time Counter
 455  */
 456 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 457
 458 /*-----------------------------------------------------------------------
 459  * PISCR - Periodic Interrupt Status and Control                 4-42
 460  *-----------------------------------------------------------------------
 461  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 462  * Periodic timer
 463  */
 464 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 465
 466 /*-----------------------------------------------------------------------
 467  * SCCR - System Clock Control                                   9-8
 468  *-----------------------------------------------------------------------
 469  * Ensure DFBRG is Divide by 16
 470  */
 471 #define CONFIG_SYS_SCCR        0
 472
 473 /*-----------------------------------------------------------------------
 474  * RCCR - RISC Controller Configuration                         13-7
 475  *-----------------------------------------------------------------------
 476  */
 477 #define CONFIG_SYS_RCCR        0
 478
 479 /*
 480  * Init Memory Controller:
 481  *
 482  * Bank Bus     Machine PortSz  Device
 483  * ---- ---     ------- ------  ------
 484  *  0   60x     GPCM    64 bit  FLASH
 485  *  1   60x     SDRAM   64 bit  SDRAM
 486  *  2   Local   SDRAM   32 bit  SDRAM
 487  *
 488  */
 489
 490         /* Initialize SDRAM on local bus
 491          */
 492 #define CONFIG_SYS_INIT_LOCAL_SDRAM
 493
 494 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 495
 496 /* Minimum mask to separate preliminary
 497  * address ranges for CS[0:2]
 498  */
 499 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512<<20)       /* less than 512 MB */
 500 #define CONFIG_SYS_LOCAL_SDRAM_LIMIT    (128<<20)       /* less than 128 MB */
 501
 502 #define CONFIG_SYS_MPTPR       0x4000
 503
 504 /*-----------------------------------------------------------------------------
 505  * Address for Mode Register Set (MRS) command
 506  *-----------------------------------------------------------------------------
 507  * In fact, the address is rather configuration data presented to the SDRAM on
 508  * its address lines. Because the address lines may be mux'ed externally either
 509  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 510  * address:
 511  *
 512  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 513  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 514  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 515  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 516  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 517  *-----------------------------------------------------------------------------
 518  */
 519 #define CONFIG_SYS_MRS_OFFS     0x00000110
 520
 521
 522 /* Bank 0 - FLASH
 523  */
 524 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 525                          BRx_PS_64                      |\
 526                          BRx_MS_GPCM_P                  |\
 527                          BRx_V)
 528
 529 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 530                          ORxG_CSNT                      |\
 531                          ORxG_ACS_DIV1                  |\
 532                          ORxG_SCY_3_CLK                 |\
 533                          ORxG_EHTR                      |\
 534                          ORxG_TRLX)
 535
 536         /* SDRAM on TQM8260 can have either 8 or 9 columns.
 537          * The number affects configuration values.
 538          */
 539
 540 /* Bank 1 - 60x bus SDRAM
 541  */
 542 #define CONFIG_SYS_PSRT        0x20
 543 #define CONFIG_SYS_LSRT        0x20
 544 #ifndef CONFIG_SYS_RAMBOOT
 545 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 546                          BRx_PS_64                      |\
 547                          BRx_MS_SDRAM_P                 |\
 548                          BRx_V)
 549
 550 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1_8COL
 551
 552
 553         /* SDRAM initialization values for 8-column chips
 554          */
 555 #define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 556                          ORxS_BPD_4                     |\
 557                          ORxS_ROWST_PBI1_A7             |\
 558                          ORxS_NUMR_12)
 559
 560 #define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 561                          PSDMR_SDAM_A15_IS_A5           |\
 562                          PSDMR_BSMA_A12_A14             |\
 563                          PSDMR_SDA10_PBI1_A8            |\
 564                          PSDMR_RFRC_7_CLK               |\
 565                          PSDMR_PRETOACT_2W              |\
 566                          PSDMR_ACTTORW_2W               |\
 567                          PSDMR_LDOTOPRE_1C              |\
 568                          PSDMR_WRC_2C                   |\
 569                          PSDMR_EAMUX                    |\
 570                          PSDMR_CL_2)
 571
 572         /* SDRAM initialization values for 9-column chips
 573          */
 574 #define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 575                          ORxS_BPD_4                     |\
 576                          ORxS_ROWST_PBI1_A5             |\
 577                          ORxS_NUMR_13)
 578
 579 #define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 580                          PSDMR_SDAM_A16_IS_A5           |\
 581                          PSDMR_BSMA_A12_A14             |\
 582                          PSDMR_SDA10_PBI1_A7            |\
 583                          PSDMR_RFRC_7_CLK               |\
 584                          PSDMR_PRETOACT_2W              |\
 585                          PSDMR_ACTTORW_2W               |\
 586                          PSDMR_LDOTOPRE_1C              |\
 587                          PSDMR_WRC_2C                   |\
 588                          PSDMR_EAMUX                    |\
 589                          PSDMR_CL_2)
 590
 591 /* Bank 2 - Local bus SDRAM
 592  */
 593 #ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
 594 #define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
 595                          BRx_PS_32                      |\
 596                          BRx_MS_SDRAM_L                 |\
 597                          BRx_V)
 598
 599 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR2_8COL
 600
 601 #define SDRAM_BASE2_PRELIM      0x80000000
 602
 603         /* SDRAM initialization values for 8-column chips
 604          */
 605 #define CONFIG_SYS_OR2_8COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 606                          ORxS_BPD_4                     |\
 607                          ORxS_ROWST_PBI1_A8             |\
 608                          ORxS_NUMR_12)
 609
 610 #define CONFIG_SYS_LSDMR_8COL  (PSDMR_PBI                      |\
 611                          PSDMR_SDAM_A15_IS_A5           |\
 612                          PSDMR_BSMA_A13_A15             |\
 613                          PSDMR_SDA10_PBI1_A9            |\
 614                          PSDMR_RFRC_7_CLK               |\
 615                          PSDMR_PRETOACT_2W              |\
 616                          PSDMR_ACTTORW_2W               |\
 617                          PSDMR_BL                       |\
 618                          PSDMR_LDOTOPRE_1C              |\
 619                          PSDMR_WRC_2C                   |\
 620                          PSDMR_CL_2)
 621
 622         /* SDRAM initialization values for 9-column chips
 623          */
 624 #define CONFIG_SYS_OR2_9COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 625                          ORxS_BPD_4                     |\
 626                          ORxS_ROWST_PBI1_A6             |\
 627                          ORxS_NUMR_13)
 628
 629 #define CONFIG_SYS_LSDMR_9COL  (PSDMR_PBI                      |\
 630                          PSDMR_SDAM_A16_IS_A5           |\
 631                          PSDMR_BSMA_A13_A15             |\
 632                          PSDMR_SDA10_PBI1_A8            |\
 633                          PSDMR_RFRC_7_CLK               |\
 634                          PSDMR_PRETOACT_2W              |\
 635                          PSDMR_ACTTORW_2W               |\
 636                          PSDMR_BL                       |\
 637                          PSDMR_LDOTOPRE_1C              |\
 638                          PSDMR_WRC_2C                   |\
 639                          PSDMR_CL_2)
 640
 641 #endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
 642
 643 #endif /* CONFIG_SYS_RAMBOOT */
 644
 645 #endif  /* __CONFIG_H */