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mmc: complete unfinished move of CONFIG_MMC
[people/ms/u-boot.git] / include / configs / UCP1020.h
1 /*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #define CONFIG_FSL_ELBC
18 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
19 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
20 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
21 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
22 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
23 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
24
25 #if defined(CONFIG_TARTGET_UCP1020T1)
26
27 #define CONFIG_UCP1020_REV_1_3
28
29 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
30
31 #define CONFIG_TSEC_ENET
32 #define CONFIG_TSEC1
33 #define CONFIG_TSEC3
34 #define CONFIG_HAS_ETH0
35 #define CONFIG_HAS_ETH1
36 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
37 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
38 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
39 #define CONFIG_IPADDR 10.80.41.229
40 #define CONFIG_SERVERIP 10.80.41.227
41 #define CONFIG_NETMASK 255.255.252.0
42 #define CONFIG_ETHPRIME "eTSEC3"
43
44 #ifndef CONFIG_SPI_FLASH
45 #endif
46 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
47
48 #define CONFIG_SYS_L2_SIZE (256 << 10)
49
50 #define CONFIG_LAST_STAGE_INIT
51
52 #endif
53
54 #if defined(CONFIG_TARGET_UCP1020)
55
56 #define CONFIG_UCP1020
57 #define CONFIG_UCP1020_REV_1_3
58
59 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
60
61 #define CONFIG_TSEC_ENET
62 #define CONFIG_TSEC1
63 #define CONFIG_TSEC2
64 #define CONFIG_TSEC3
65 #define CONFIG_HAS_ETH0
66 #define CONFIG_HAS_ETH1
67 #define CONFIG_HAS_ETH2
68 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
69 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
70 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
71 #define CONFIG_IPADDR 192.168.1.81
72 #define CONFIG_IPADDR1 192.168.1.82
73 #define CONFIG_IPADDR2 192.168.1.83
74 #define CONFIG_SERVERIP 192.168.1.80
75 #define CONFIG_GATEWAYIP 102.168.1.1
76 #define CONFIG_NETMASK 255.255.255.0
77 #define CONFIG_ETHPRIME "eTSEC1"
78
79 #ifndef CONFIG_SPI_FLASH
80 #endif
81 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
82
83 #define CONFIG_SYS_L2_SIZE (256 << 10)
84
85 #define CONFIG_LAST_STAGE_INIT
86
87 #endif
88
89 #ifdef CONFIG_SDCARD
90 #define CONFIG_RAMBOOT_SDCARD
91 #define CONFIG_SYS_RAMBOOT
92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_SYS_TEXT_BASE 0x11000000
94 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
95 #endif
96
97 #ifdef CONFIG_SPIFLASH
98 #define CONFIG_RAMBOOT_SPIFLASH
99 #define CONFIG_SYS_RAMBOOT
100 #define CONFIG_SYS_EXTRA_ENV_RELOC
101 #define CONFIG_SYS_TEXT_BASE 0x11000000
102 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
103 #endif
104
105 #ifndef CONFIG_SYS_TEXT_BASE
106 #define CONFIG_SYS_TEXT_BASE 0xeff80000
107 #endif
108 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
109
110 #ifndef CONFIG_RESET_VECTOR_ADDRESS
111 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
112 #endif
113
114 #ifndef CONFIG_SYS_MONITOR_BASE
115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
116 #endif
117
118 /* High Level Configuration Options */
119 #define CONFIG_BOOKE
120 #define CONFIG_E500
121 /* #define CONFIG_MPC85xx */
122
123 #define CONFIG_MP
124
125 #define CONFIG_ENV_OVERWRITE
126
127 #define CONFIG_CMD_SATA
128 #define CONFIG_SATA_SIL
129 #define CONFIG_SYS_SATA_MAX_DEVICE 2
130 #define CONFIG_LIBATA
131 #define CONFIG_LBA48
132
133 #define CONFIG_SYS_CLK_FREQ 66666666
134 #define CONFIG_DDR_CLK_FREQ 66666666
135
136 #define CONFIG_HWCONFIG
137
138 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
139 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
140 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
141 /*
142 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
143 * there will be one entry in this array for each two (dummy) sensors in
144 * CONFIG_DTT_SENSORS.
145 *
146 * For uCP1020 module:
147 * - only one ADM1021/NCT72
148 * - i2c addr 0x41
149 * - conversion rate 0x02 = 0.25 conversions/second
150 * - ALERT output disabled
151 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
152 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
153 */
154 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
155 0x02, 0, 1, 0, 85, 1, 0, 85} }
156
157 #define CONFIG_CMD_DTT
158
159 /*
160 * These can be toggled for performance analysis, otherwise use default.
161 */
162 #define CONFIG_L2_CACHE
163 #define CONFIG_BTB
164
165 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
166
167 #define CONFIG_ENABLE_36BIT_PHYS
168
169 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
170 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
171 #define CONFIG_PANIC_HANG /* do not reset board on panic */
172
173 #define CONFIG_SYS_CCSRBAR 0xffe00000
174 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
175
176 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
177 SPL code*/
178 #ifdef CONFIG_SPL_BUILD
179 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
180 #endif
181
182 /* DDR Setup */
183 #define CONFIG_DDR_ECC_ENABLE
184 #define CONFIG_SYS_FSL_DDR3
185 #ifndef CONFIG_DDR_ECC_ENABLE
186 #define CONFIG_SYS_DDR_RAW_TIMING
187 #define CONFIG_DDR_SPD
188 #endif
189 #define CONFIG_SYS_SPD_BUS_NUM 1
190 #undef CONFIG_FSL_DDR_INTERACTIVE
191
192 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
193 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
194 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
195 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
196 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
197
198 #define CONFIG_NUM_DDR_CONTROLLERS 1
199 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
200
201 /* Default settings for DDR3 */
202 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
203 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
204 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
205 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
206 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
207 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
208
209 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
210 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
211 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
212 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
213
214 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
215 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
216 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
217 #define CONFIG_SYS_DDR_RCW_1 0x00000000
218 #define CONFIG_SYS_DDR_RCW_2 0x00000000
219 #ifdef CONFIG_DDR_ECC_ENABLE
220 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
221 #else
222 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
223 #endif
224 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
225 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
226 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
227
228 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
229 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
230 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
231 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
232 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
233 #define CONFIG_SYS_DDR_MODE_1 0x40461520
234 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
235 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
236
237 #undef CONFIG_CLOCKS_IN_MHZ
238
239 /*
240 * Memory map
241 *
242 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
243 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
244 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
245 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
246 * (early boot only)
247 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
248 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
249 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
250 */
251
252 /*
253 * Local Bus Definitions
254 */
255 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
256 #define CONFIG_SYS_FLASH_BASE 0xec000000
257
258 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
259
260 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
261 | BR_PS_16 | BR_V)
262
263 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
264
265 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
266 #define CONFIG_SYS_FLASH_QUIET_TEST
267 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
268
269 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
270
271 #undef CONFIG_SYS_FLASH_CHECKSUM
272 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
273 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
274
275 #define CONFIG_FLASH_CFI_DRIVER
276 #define CONFIG_SYS_FLASH_CFI
277 #define CONFIG_SYS_FLASH_EMPTY_INFO
278 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
279
280 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
281
282 #define CONFIG_SYS_INIT_RAM_LOCK
283 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
284 /* Initial L1 address */
285 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
288 /* Size of used area in RAM */
289 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
290
291 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
292 GENERATED_GBL_DATA_SIZE)
293 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
294
295 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
296 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
297
298 #define CONFIG_SYS_PMC_BASE 0xff980000
299 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
300 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
301 BR_PS_8 | BR_V)
302 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
303 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
304 OR_GPCM_EAD)
305
306 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
307 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
308 #ifdef CONFIG_NAND_FSL_ELBC
309 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
310 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
311 #endif
312
313 /* Serial Port - controlled on board with jumper J8
314 * open - index 2
315 * shorted - index 1
316 */
317 #define CONFIG_CONS_INDEX 1
318 #undef CONFIG_SERIAL_SOFTWARE_FIFO
319 #define CONFIG_SYS_NS16550_SERIAL
320 #define CONFIG_SYS_NS16550_REG_SIZE 1
321 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
322 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
323 #define CONFIG_NS16550_MIN_FUNCTIONS
324 #endif
325
326 #define CONFIG_SYS_BAUDRATE_TABLE \
327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
328
329 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
330 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
331
332 /* I2C */
333 #define CONFIG_SYS_I2C
334 #define CONFIG_SYS_I2C_FSL
335 #define CONFIG_SYS_FSL_I2C_SPEED 400000
336 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
337 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
338 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
339 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
340 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
341 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
342 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
343
344 #define CONFIG_RTC_DS1337
345 #define CONFIG_SYS_RTC_DS1337_NOOSC
346 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
347 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
348 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
349 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
350
351 /*
352 * eSPI - Enhanced SPI
353 */
354 #define CONFIG_HARD_SPI
355
356 #define CONFIG_SF_DEFAULT_SPEED 10000000
357 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
358
359 #if defined(CONFIG_PCI)
360 /*
361 * General PCI
362 * Memory space is mapped 1-1, but I/O space must start from 0.
363 */
364
365 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
366 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
367 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
368 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
369 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
370 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
371 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
372 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
373 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
374 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
375
376 /* controller 1, Slot 2, tgtid 1, Base address a000 */
377 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
378 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
379 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
380 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
381 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
382 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
383 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
384 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
385 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
386
387 #define CONFIG_CMD_PCI
388
389 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
390 #define CONFIG_DOS_PARTITION
391 #endif /* CONFIG_PCI */
392
393 /*
394 * Environment
395 */
396 #ifdef CONFIG_ENV_FIT_UCBOOT
397
398 #define CONFIG_ENV_IS_IN_FLASH
399 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
400 #define CONFIG_ENV_SIZE 0x20000
401 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
402
403 #else
404
405 #define CONFIG_ENV_SPI_BUS 0
406 #define CONFIG_ENV_SPI_CS 0
407 #define CONFIG_ENV_SPI_MAX_HZ 10000000
408 #define CONFIG_ENV_SPI_MODE 0
409
410 #ifdef CONFIG_RAMBOOT_SPIFLASH
411
412 #define CONFIG_ENV_IS_IN_SPI_FLASH
413 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
414 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
415 #define CONFIG_ENV_SECT_SIZE 0x1000
416
417 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
418 /* Address and size of Redundant Environment Sector */
419 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
420 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
421 #endif
422
423 #elif defined(CONFIG_RAMBOOT_SDCARD)
424 #define CONFIG_ENV_IS_IN_MMC
425 #define CONFIG_FSL_FIXED_MMC_LOCATION
426 #define CONFIG_ENV_SIZE 0x2000
427 #define CONFIG_SYS_MMC_ENV_DEV 0
428
429 #elif defined(CONFIG_SYS_RAMBOOT)
430 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
431 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
432 #define CONFIG_ENV_SIZE 0x2000
433
434 #else
435 #define CONFIG_ENV_IS_IN_FLASH
436 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
437 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
438 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
439 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
440 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
441 /* Address and size of Redundant Environment Sector */
442 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
443 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
444 #endif
445
446 #endif
447
448 #endif /* CONFIG_ENV_FIT_UCBOOT */
449
450 #define CONFIG_LOADS_ECHO /* echo on for serial download */
451 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
452
453 /*
454 * Command line configuration.
455 */
456 #define CONFIG_CMD_IRQ
457 #define CONFIG_CMD_DATE
458 #define CONFIG_CMD_IRQ
459 #define CONFIG_CMD_REGINFO
460 #define CONFIG_CMD_ERRATA
461 #define CONFIG_CMD_CRAMFS
462
463 /*
464 * USB
465 */
466 #define CONFIG_HAS_FSL_DR_USB
467
468 #if defined(CONFIG_HAS_FSL_DR_USB)
469 #define CONFIG_USB_EHCI
470
471 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
472
473 #ifdef CONFIG_USB_EHCI
474 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
475 #define CONFIG_USB_EHCI_FSL
476 #endif
477 #endif
478
479 #undef CONFIG_WATCHDOG /* watchdog disabled */
480
481 #ifdef CONFIG_MMC
482 #define CONFIG_FSL_ESDHC
483 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
484 #define CONFIG_MMC_SPI
485 #define CONFIG_CMD_MMC_SPI
486 #define CONFIG_GENERIC_MMC
487 #endif
488
489 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
490 #define CONFIG_DOS_PARTITION
491 #endif
492
493 /* Misc Extra Settings */
494 #undef CONFIG_WATCHDOG /* watchdog disabled */
495
496 /*
497 * Miscellaneous configurable options
498 */
499 #define CONFIG_SYS_LONGHELP /* undef to save memory */
500 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
501 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
502 #if defined(CONFIG_CMD_KGDB)
503 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
504 #else
505 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
506 #endif
507 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
508 /* Print Buffer Size */
509 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
510 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
511 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
512
513 /*
514 * For booting Linux, the board info and command line data
515 * have to be in the first 64 MB of memory, since this is
516 * the maximum mapped by the Linux kernel during initialization.
517 */
518 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
519 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
520
521 #if defined(CONFIG_CMD_KGDB)
522 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
523 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
524 #endif
525
526 /*
527 * Environment Configuration
528 */
529
530 #if defined(CONFIG_TSEC_ENET)
531
532 #if defined(CONFIG_UCP1020_REV_1_2)
533 #define CONFIG_PHY_MICREL_KSZ9021
534 #elif defined(CONFIG_UCP1020_REV_1_3)
535 #define CONFIG_PHY_MICREL_KSZ9031
536 #else
537 #error "UCP1020 module revision is not defined !!!"
538 #endif
539
540 #define CONFIG_BOOTP_SERVERIP
541
542 #define CONFIG_MII /* MII PHY management */
543 #define CONFIG_TSEC1_NAME "eTSEC1"
544 #define CONFIG_TSEC2_NAME "eTSEC2"
545 #define CONFIG_TSEC3_NAME "eTSEC3"
546
547 #define TSEC1_PHY_ADDR 4
548 #define TSEC2_PHY_ADDR 0
549 #define TSEC2_PHY_ADDR_SGMII 0x00
550 #define TSEC3_PHY_ADDR 6
551
552 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
553 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
554 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
555
556 #define TSEC1_PHYIDX 0
557 #define TSEC2_PHYIDX 0
558 #define TSEC3_PHYIDX 0
559
560 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
561
562 #endif
563
564 #define CONFIG_HOSTNAME UCP1020
565 #define CONFIG_ROOTPATH "/opt/nfsroot"
566 #define CONFIG_BOOTFILE "uImage"
567 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
568
569 /* default location for tftp and bootm */
570 #define CONFIG_LOADADDR 1000000
571
572 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
573
574 #define CONFIG_BAUDRATE 115200
575
576 #if defined(CONFIG_DONGLE)
577
578 #define CONFIG_EXTRA_ENV_SETTINGS \
579 "bootcmd=run prog_spi_mbrbootcramfs\0" \
580 "bootfile=uImage\0" \
581 "consoledev=ttyS0\0" \
582 "cramfsfile=image.cramfs\0" \
583 "dtbaddr=0x00c00000\0" \
584 "dtbfile=image.dtb\0" \
585 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
586 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
587 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
588 "fileaddr=0x01000000\0" \
589 "filesize=0x00080000\0" \
590 "flashmbr=sf probe 0; " \
591 "tftp $loadaddr $mbr; " \
592 "sf erase $mbr_offset +$filesize; " \
593 "sf write $loadaddr $mbr_offset $filesize\0" \
594 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
595 "protect off $nor_recoveryaddr +$filesize; " \
596 "erase $nor_recoveryaddr +$filesize; " \
597 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
598 "protect on $nor_recoveryaddr +$filesize\0 " \
599 "flashuboot=tftp $ubootaddr $ubootfile; " \
600 "protect off $nor_ubootaddr +$filesize; " \
601 "erase $nor_ubootaddr +$filesize; " \
602 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
603 "protect on $nor_ubootaddr +$filesize\0 " \
604 "flashworking=tftp $workingaddr $cramfsfile; " \
605 "protect off $nor_workingaddr +$filesize; " \
606 "erase $nor_workingaddr +$filesize; " \
607 "cp.b $workingaddr $nor_workingaddr $filesize; " \
608 "protect on $nor_workingaddr +$filesize\0 " \
609 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
610 "kerneladdr=0x01100000\0" \
611 "kernelfile=uImage\0" \
612 "loadaddr=0x01000000\0" \
613 "mbr=uCP1020d.mbr\0" \
614 "mbr_offset=0x00000000\0" \
615 "mmbr=uCP1020Quiet.mbr\0" \
616 "mmcpart=0:2\0" \
617 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
618 "mmc erase 1 1; " \
619 "mmc write $loadaddr 1 1\0" \
620 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
621 "mmc erase 0x40 0x400; " \
622 "mmc write $loadaddr 0x40 0x400\0" \
623 "netdev=eth0\0" \
624 "nor_recoveryaddr=0xEC0A0000\0" \
625 "nor_ubootaddr=0xEFF80000\0" \
626 "nor_workingaddr=0xECFA0000\0" \
627 "norbootrecovery=setenv bootargs $recoverybootargs" \
628 " console=$consoledev,$baudrate $othbootargs; " \
629 "run norloadrecovery; " \
630 "bootm $kerneladdr - $dtbaddr\0" \
631 "norbootworking=setenv bootargs $workingbootargs" \
632 " console=$consoledev,$baudrate $othbootargs; " \
633 "run norloadworking; " \
634 "bootm $kerneladdr - $dtbaddr\0" \
635 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
636 "setenv cramfsaddr $nor_recoveryaddr; " \
637 "cramfsload $dtbaddr $dtbfile; " \
638 "cramfsload $kerneladdr $kernelfile\0" \
639 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
640 "setenv cramfsaddr $nor_workingaddr; " \
641 "cramfsload $dtbaddr $dtbfile; " \
642 "cramfsload $kerneladdr $kernelfile\0" \
643 "prog_spi_mbr=run spi__mbr\0" \
644 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
645 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
646 "run spi__cramfs\0" \
647 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
648 " console=$consoledev,$baudrate $othbootargs; " \
649 "tftp $rootfsaddr $rootfsfile; " \
650 "tftp $loadaddr $kernelfile; " \
651 "tftp $dtbaddr $dtbfile; " \
652 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
653 "ramdisk_size=120000\0" \
654 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
655 "recoveryaddr=0x02F00000\0" \
656 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
657 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
658 "mw.l 0xffe0f008 0x00400000\0" \
659 "rootfsaddr=0x02F00000\0" \
660 "rootfsfile=rootfs.ext2.gz.uboot\0" \
661 "rootpath=/opt/nfsroot\0" \
662 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
663 "protect off 0xeC000000 +$filesize; " \
664 "erase 0xEC000000 +$filesize; " \
665 "cp.b $loadaddr 0xEC000000 $filesize; " \
666 "cmp.b $loadaddr 0xEC000000 $filesize; " \
667 "protect on 0xeC000000 +$filesize\0" \
668 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
669 "protect off 0xeFF80000 +$filesize; " \
670 "erase 0xEFF80000 +$filesize; " \
671 "cp.b $loadaddr 0xEFF80000 $filesize; " \
672 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
673 "protect on 0xeFF80000 +$filesize\0" \
674 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
675 "sf probe 0; sf erase 0x8000 +$filesize; " \
676 "sf write $loadaddr 0x8000 $filesize\0" \
677 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
678 "protect off 0xec0a0000 +$filesize; " \
679 "erase 0xeC0A0000 +$filesize; " \
680 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
681 "protect on 0xec0a0000 +$filesize\0" \
682 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
683 "sf probe 1; sf erase 0 +$filesize; " \
684 "sf write $loadaddr 0 $filesize\0" \
685 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
686 "sf probe 0; sf erase 0 +$filesize; " \
687 "sf write $loadaddr 0 $filesize\0" \
688 "tftpflash=tftpboot $loadaddr $uboot; " \
689 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
690 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
691 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
692 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
693 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
694 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
695 "ubootaddr=0x01000000\0" \
696 "ubootfile=u-boot.bin\0" \
697 "ubootd=u-boot4dongle.bin\0" \
698 "upgrade=run flashworking\0" \
699 "usb_phy_type=ulpi\0 " \
700 "workingaddr=0x02F00000\0" \
701 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
702
703 #else
704
705 #if defined(CONFIG_UCP1020T1)
706
707 #define CONFIG_EXTRA_ENV_SETTINGS \
708 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
709 "bootfile=uImage\0" \
710 "consoledev=ttyS0\0" \
711 "cramfsfile=image.cramfs\0" \
712 "dtbaddr=0x00c00000\0" \
713 "dtbfile=image.dtb\0" \
714 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
715 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
716 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
717 "fileaddr=0x01000000\0" \
718 "filesize=0x00080000\0" \
719 "flashmbr=sf probe 0; " \
720 "tftp $loadaddr $mbr; " \
721 "sf erase $mbr_offset +$filesize; " \
722 "sf write $loadaddr $mbr_offset $filesize\0" \
723 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
724 "protect off $nor_recoveryaddr +$filesize; " \
725 "erase $nor_recoveryaddr +$filesize; " \
726 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
727 "protect on $nor_recoveryaddr +$filesize\0 " \
728 "flashuboot=tftp $ubootaddr $ubootfile; " \
729 "protect off $nor_ubootaddr +$filesize; " \
730 "erase $nor_ubootaddr +$filesize; " \
731 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
732 "protect on $nor_ubootaddr +$filesize\0 " \
733 "flashworking=tftp $workingaddr $cramfsfile; " \
734 "protect off $nor_workingaddr +$filesize; " \
735 "erase $nor_workingaddr +$filesize; " \
736 "cp.b $workingaddr $nor_workingaddr $filesize; " \
737 "protect on $nor_workingaddr +$filesize\0 " \
738 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
739 "kerneladdr=0x01100000\0" \
740 "kernelfile=uImage\0" \
741 "loadaddr=0x01000000\0" \
742 "mbr=uCP1020.mbr\0" \
743 "mbr_offset=0x00000000\0" \
744 "netdev=eth0\0" \
745 "nor_recoveryaddr=0xEC0A0000\0" \
746 "nor_ubootaddr=0xEFF80000\0" \
747 "nor_workingaddr=0xECFA0000\0" \
748 "norbootrecovery=setenv bootargs $recoverybootargs" \
749 " console=$consoledev,$baudrate $othbootargs; " \
750 "run norloadrecovery; " \
751 "bootm $kerneladdr - $dtbaddr\0" \
752 "norbootworking=setenv bootargs $workingbootargs" \
753 " console=$consoledev,$baudrate $othbootargs; " \
754 "run norloadworking; " \
755 "bootm $kerneladdr - $dtbaddr\0" \
756 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
757 "setenv cramfsaddr $nor_recoveryaddr; " \
758 "cramfsload $dtbaddr $dtbfile; " \
759 "cramfsload $kerneladdr $kernelfile\0" \
760 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
761 "setenv cramfsaddr $nor_workingaddr; " \
762 "cramfsload $dtbaddr $dtbfile; " \
763 "cramfsload $kerneladdr $kernelfile\0" \
764 "othbootargs=quiet\0" \
765 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
766 " console=$consoledev,$baudrate $othbootargs; " \
767 "tftp $rootfsaddr $rootfsfile; " \
768 "tftp $loadaddr $kernelfile; " \
769 "tftp $dtbaddr $dtbfile; " \
770 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
771 "ramdisk_size=120000\0" \
772 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
773 "recoveryaddr=0x02F00000\0" \
774 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
775 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
776 "mw.l 0xffe0f008 0x00400000\0" \
777 "rootfsaddr=0x02F00000\0" \
778 "rootfsfile=rootfs.ext2.gz.uboot\0" \
779 "rootpath=/opt/nfsroot\0" \
780 "silent=1\0" \
781 "tftpflash=tftpboot $loadaddr $uboot; " \
782 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
783 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
784 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
785 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
786 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
787 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
788 "ubootaddr=0x01000000\0" \
789 "ubootfile=u-boot.bin\0" \
790 "upgrade=run flashworking\0" \
791 "workingaddr=0x02F00000\0" \
792 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
793
794 #else /* For Arcturus Modules */
795
796 #define CONFIG_EXTRA_ENV_SETTINGS \
797 "bootcmd=run norkernel\0" \
798 "bootfile=uImage\0" \
799 "consoledev=ttyS0\0" \
800 "dtbaddr=0x00c00000\0" \
801 "dtbfile=image.dtb\0" \
802 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
803 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
804 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
805 "fileaddr=0x01000000\0" \
806 "filesize=0x00080000\0" \
807 "flashmbr=sf probe 0; " \
808 "tftp $loadaddr $mbr; " \
809 "sf erase $mbr_offset +$filesize; " \
810 "sf write $loadaddr $mbr_offset $filesize\0" \
811 "flashuboot=tftp $loadaddr $ubootfile; " \
812 "protect off $nor_ubootaddr0 +$filesize; " \
813 "erase $nor_ubootaddr0 +$filesize; " \
814 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
815 "protect on $nor_ubootaddr0 +$filesize; " \
816 "protect off $nor_ubootaddr1 +$filesize; " \
817 "erase $nor_ubootaddr1 +$filesize; " \
818 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
819 "protect on $nor_ubootaddr1 +$filesize\0 " \
820 "format0=protect off $part0base +$part0size; " \
821 "erase $part0base +$part0size\0" \
822 "format1=protect off $part1base +$part1size; " \
823 "erase $part1base +$part1size\0" \
824 "format2=protect off $part2base +$part2size; " \
825 "erase $part2base +$part2size\0" \
826 "format3=protect off $part3base +$part3size; " \
827 "erase $part3base +$part3size\0" \
828 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
829 "kerneladdr=0x01100000\0" \
830 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
831 "kernelfile=uImage\0" \
832 "loadaddr=0x01000000\0" \
833 "mbr=uCP1020.mbr\0" \
834 "mbr_offset=0x00000000\0" \
835 "netdev=eth0\0" \
836 "nor_ubootaddr0=0xEC000000\0" \
837 "nor_ubootaddr1=0xEFF80000\0" \
838 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
839 "run norkernelload; " \
840 "bootm $kerneladdr - $dtbaddr\0" \
841 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
842 "setenv cramfsaddr $part0base; " \
843 "cramfsload $dtbaddr $dtbfile; " \
844 "cramfsload $kerneladdr $kernelfile\0" \
845 "part0base=0xEC100000\0" \
846 "part0size=0x00700000\0" \
847 "part1base=0xEC800000\0" \
848 "part1size=0x02000000\0" \
849 "part2base=0xEE800000\0" \
850 "part2size=0x00800000\0" \
851 "part3base=0xEF000000\0" \
852 "part3size=0x00F80000\0" \
853 "partENVbase=0xEC080000\0" \
854 "partENVsize=0x00080000\0" \
855 "program0=tftp part0-000000.bin; " \
856 "protect off $part0base +$filesize; " \
857 "erase $part0base +$filesize; " \
858 "cp.b $loadaddr $part0base $filesize; " \
859 "echo Verifying...; " \
860 "cmp.b $loadaddr $part0base $filesize\0" \
861 "program1=tftp part1-000000.bin; " \
862 "protect off $part1base +$filesize; " \
863 "erase $part1base +$filesize; " \
864 "cp.b $loadaddr $part1base $filesize; " \
865 "echo Verifying...; " \
866 "cmp.b $loadaddr $part1base $filesize\0" \
867 "program2=tftp part2-000000.bin; " \
868 "protect off $part2base +$filesize; " \
869 "erase $part2base +$filesize; " \
870 "cp.b $loadaddr $part2base $filesize; " \
871 "echo Verifying...; " \
872 "cmp.b $loadaddr $part2base $filesize\0" \
873 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
874 " console=$consoledev,$baudrate $othbootargs; " \
875 "tftp $rootfsaddr $rootfsfile; " \
876 "tftp $loadaddr $kernelfile; " \
877 "tftp $dtbaddr $dtbfile; " \
878 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
879 "ramdisk_size=120000\0" \
880 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
881 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
882 "mw.l 0xffe0f008 0x00400000\0" \
883 "rootfsaddr=0x02F00000\0" \
884 "rootfsfile=rootfs.ext2.gz.uboot\0" \
885 "rootpath=/opt/nfsroot\0" \
886 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
887 "sf probe 0; sf erase 0 +$filesize; " \
888 "sf write $loadaddr 0 $filesize\0" \
889 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
890 "protect off 0xeC000000 +$filesize; " \
891 "erase 0xEC000000 +$filesize; " \
892 "cp.b $loadaddr 0xEC000000 $filesize; " \
893 "cmp.b $loadaddr 0xEC000000 $filesize; " \
894 "protect on 0xeC000000 +$filesize\0" \
895 "tftpflash=tftpboot $loadaddr $uboot; " \
896 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
897 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
898 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
899 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
900 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
901 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
902 "ubootfile=u-boot.bin\0" \
903 "upgrade=run flashuboot\0" \
904 "usb_phy_type=ulpi\0 " \
905 "boot_nfs= " \
906 "setenv bootargs root=/dev/nfs rw " \
907 "nfsroot=$serverip:$rootpath " \
908 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
909 "console=$consoledev,$baudrate $othbootargs;" \
910 "tftp $loadaddr $bootfile;" \
911 "tftp $fdtaddr $fdtfile;" \
912 "bootm $loadaddr - $fdtaddr\0" \
913 "boot_hd = " \
914 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
915 "console=$consoledev,$baudrate $othbootargs;" \
916 "usb start;" \
917 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
918 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
919 "bootm $loadaddr - $fdtaddr\0" \
920 "boot_usb_fat = " \
921 "setenv bootargs root=/dev/ram rw " \
922 "console=$consoledev,$baudrate $othbootargs " \
923 "ramdisk_size=$ramdisk_size;" \
924 "usb start;" \
925 "fatload usb 0:2 $loadaddr $bootfile;" \
926 "fatload usb 0:2 $fdtaddr $fdtfile;" \
927 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
928 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
929 "boot_usb_ext2 = " \
930 "setenv bootargs root=/dev/ram rw " \
931 "console=$consoledev,$baudrate $othbootargs " \
932 "ramdisk_size=$ramdisk_size;" \
933 "usb start;" \
934 "ext2load usb 0:4 $loadaddr $bootfile;" \
935 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
936 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
937 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
938 "boot_nor = " \
939 "setenv bootargs root=/dev/$jffs2nor rw " \
940 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
941 "bootm $norbootaddr - $norfdtaddr\0 " \
942 "boot_ram = " \
943 "setenv bootargs root=/dev/ram rw " \
944 "console=$consoledev,$baudrate $othbootargs " \
945 "ramdisk_size=$ramdisk_size;" \
946 "tftp $ramdiskaddr $ramdiskfile;" \
947 "tftp $loadaddr $bootfile;" \
948 "tftp $fdtaddr $fdtfile;" \
949 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
950
951 #endif
952 #endif
953
954 #endif /* __CONFIG_H */
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