include/configs/cm_fx6.h

   1 /*
   2  * Config file for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_CM_FX6_H
  12 #define __CONFIG_CM_FX6_H
  13
  14 #include "mx6_common.h"
  15
  16 /* Machine config */
  17 #define CONFIG_SYS_LITTLE_ENDIAN
  18 #define CONFIG_MACH_TYPE                4273
  19
  20 /* MMC */
  21 #define CONFIG_SYS_FSL_USDHC_NUM        3
  22 #define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC2_BASE_ADDR
  23
  24 /* RAM */
  25 #define PHYS_SDRAM_1                    MMDC0_ARB_BASE_ADDR
  26 #define PHYS_SDRAM_2                    MMDC1_ARB_BASE_ADDR
  27 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  28 #define CONFIG_NR_DRAM_BANKS            2
  29 #define CONFIG_SYS_MEMTEST_START        0x10000000
  30 #define CONFIG_SYS_MEMTEST_END          0x10010000
  31 #define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
  32 #define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
  33 #define CONFIG_SYS_INIT_SP_OFFSET \
  34         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  35 #define CONFIG_SYS_INIT_SP_ADDR \
  36         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  37
  38 /* Serial console */
  39 #define CONFIG_MXC_UART
  40 #define CONFIG_MXC_UART_BASE            UART4_BASE
  41 #define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}
  42
  43 /* Shell */
  44 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
  45                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  46
  47 /* SPI flash */
  48 #define CONFIG_SF_DEFAULT_BUS           0
  49 #define CONFIG_SF_DEFAULT_CS            0
  50 #define CONFIG_SF_DEFAULT_SPEED         25000000
  51 #define CONFIG_SF_DEFAULT_MODE          (SPI_MODE_0)
  52
  53 /* MTD support */
  54 #ifndef CONFIG_SPL_BUILD
  55 #define CONFIG_MTD_DEVICE
  56 #define CONFIG_MTD_PARTITIONS
  57 #define CONFIG_SPI_FLASH_MTD
  58 #endif
  59
  60 #define MTDIDS_DEFAULT          "nor0=spi0.0"
  61 #define MTDPARTS_DEFAULT        "mtdparts=spi0.0:" \
  62                                 "768k(uboot)," \
  63                                 "256k(uboot-environment)," \
  64                                 "-(reserved)"
  65
  66 /* Environment */
  67 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
  68 #define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
  69 #define CONFIG_ENV_SPI_BUS              CONFIG_SF_DEFAULT_BUS
  70 #define CONFIG_ENV_SPI_CS               CONFIG_SF_DEFAULT_CS
  71 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
  72 #define CONFIG_ENV_SIZE                 (8 * 1024)
  73 #define CONFIG_ENV_OFFSET               (768 * 1024)
  74
  75 #define CONFIG_EXTRA_ENV_SETTINGS \
  76         "stdin=serial,usbkbd\0" \
  77         "stdout=serial,vga\0" \
  78         "stderr=serial,vga\0" \
  79         "panel=HDMI\0" \
  80         "autoload=no\0" \
  81         "uImage=uImage-cm-fx6\0" \
  82         "zImage=zImage-cm-fx6\0" \
  83         "kernel=uImage-cm-fx6\0" \
  84         "script=boot.scr\0" \
  85         "dtb=cm-fx6.dtb\0" \
  86         "bootm_low=18000000\0" \
  87         "loadaddr=0x10800000\0" \
  88         "fdtaddr=0x11000000\0" \
  89         "console=ttymxc3,115200\0" \
  90         "ethprime=FEC0\0" \
  91         "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
  92         "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
  93         "doboot=bootm ${loadaddr}\0" \
  94         "doloadfdt=false\0" \
  95         "mtdids=" MTDIDS_DEFAULT "\0" \
  96         "mtdparts=" MTDPARTS_DEFAULT "\0" \
  97         "setboottypez=setenv kernel ${zImage};" \
  98                 "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
  99                 "setenv doloadfdt true;\0" \
 100         "setboottypem=setenv kernel ${uImage};" \
 101                 "setenv doboot bootm ${loadaddr};" \
 102                 "setenv doloadfdt false;\0"\
 103         "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
 104         "sataroot=/dev/sda2 rw rootwait\0" \
 105         "nandroot=/dev/mtdblock4 rw\0" \
 106         "nandrootfstype=ubifs\0" \
 107         "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
 108                 "${video} ${extrabootargs}\0" \
 109         "sataargs=setenv bootargs console=${console} root=${sataroot} " \
 110                 "${video} ${extrabootargs}\0" \
 111         "nandargs=setenv bootargs console=${console} " \
 112                 "root=${nandroot} " \
 113                 "rootfstype=${nandrootfstype} " \
 114                 "${video} ${extrabootargs}\0" \
 115         "nandboot=if run nandloadkernel; then " \
 116                         "run nandloadfdt;" \
 117                         "run setboottypem;" \
 118                         "run storagebootcmd;" \
 119                         "run setboottypez;" \
 120                         "run storagebootcmd;" \
 121                 "fi;\0" \
 122         "run_eboot=echo Starting EBOOT ...; "\
 123                 "mmc dev 2 && " \
 124                 "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
 125         "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\
 126         "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\
 127         "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \
 128         "bootscript=echo Running bootscript from ${storagetype} ...;" \
 129                    "source ${loadaddr};\0" \
 130         "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \
 131         "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
 132         "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
 133         "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
 134         "setupnandboot=setenv storagetype nand;\0" \
 135         "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \
 136         "storagebootcmd=echo Booting from ${storagetype} ...;" \
 137                         "run ${storagetype}args; run doboot;\0" \
 138         "trybootk=if run loadkernel; then " \
 139                 "if ${doloadfdt}; then " \
 140                         "run loadfdt;" \
 141                 "fi;" \
 142                 "run storagebootcmd;" \
 143                 "fi;\0" \
 144         "trybootsmz=if run loadscript; then " \
 145                         "run bootscript;" \
 146                 "fi;" \
 147                 "run setboottypem;" \
 148                 "run trybootk;" \
 149                 "run setboottypez;" \
 150                 "run trybootk;\0"
 151
 152 #define CONFIG_BOOTCOMMAND \
 153         "run setupmmcboot;" \
 154         "mmc dev ${storagedev};" \
 155         "if mmc rescan; then " \
 156                 "run trybootsmz;" \
 157         "fi;" \
 158         "run setupusbboot;" \
 159         "if usb start; then "\
 160                 "if run loadscript; then " \
 161                         "run bootscript;" \
 162                 "fi;" \
 163         "fi;" \
 164         "run setupsataboot;" \
 165         "if sata init; then " \
 166                 "run trybootsmz;" \
 167         "fi;" \
 168         "run setupnandboot;" \
 169         "run nandboot;"
 170
 171 #define CONFIG_PREBOOT          "usb start;sf probe"
 172
 173 /* SPI */
 174 #define CONFIG_SPI
 175 #define CONFIG_MXC_SPI
 176
 177 /* NAND */
 178 #ifndef CONFIG_SPL_BUILD
 179 #define CONFIG_SYS_NAND_BASE            0x40000000
 180 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 181 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 182 #define CONFIG_NAND_MXS
 183 #define CONFIG_SYS_NAND_ONFI_DETECTION
 184 /* APBH DMA is required for NAND support */
 185 #define CONFIG_APBH_DMA
 186 #define CONFIG_APBH_DMA_BURST
 187 #define CONFIG_APBH_DMA_BURST8
 188 #endif
 189
 190 /* Ethernet */
 191 #define CONFIG_FEC_MXC
 192 #define CONFIG_FEC_MXC_PHYADDR          0
 193 #define CONFIG_FEC_XCV_TYPE             RGMII
 194 #define IMX_FEC_BASE                    ENET_BASE_ADDR
 195 #define CONFIG_PHY_ATHEROS
 196 #define CONFIG_MII
 197 #define CONFIG_ETHPRIME                 "FEC0"
 198 #define CONFIG_ARP_TIMEOUT              200UL
 199 #define CONFIG_NET_RETRY_COUNT          5
 200
 201 /* USB */
 202 #define CONFIG_MXC_USB_PORTSC           (PORT_PTS_UTMI | PORT_PTS_PTW)
 203 #define CONFIG_MXC_USB_FLAGS            0
 204 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 205 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET        /* For OTG port */
 206
 207 /* I2C */
 208 #define CONFIG_SYS_I2C
 209 #define CONFIG_SYS_I2C_MXC
 210 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 211 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 212 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 213 #define CONFIG_SYS_I2C_SPEED            100000
 214 #define CONFIG_SYS_MXC_I2C3_SPEED       400000
 215
 216 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 218 #define CONFIG_SYS_I2C_EEPROM_BUS       2
 219
 220 /* SATA */
 221 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 222 #define CONFIG_LIBATA
 223 #define CONFIG_LBA48
 224 #define CONFIG_DWC_AHSATA
 225 #define CONFIG_DWC_AHSATA_PORT_ID       0
 226 #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_ARB_BASE_ADDR
 227
 228 /* Boot */
 229 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 230 #define CONFIG_SERIAL_TAG
 231
 232 /* misc */
 233 #define CONFIG_SYS_MALLOC_LEN                   (10 * 1024 * 1024)
 234 #define CONFIG_MISC_INIT_R
 235
 236 /* SPL */
 237 #include "imx6_spl.h"
 238 #define CONFIG_SYS_SPI_U_BOOT_OFFS      (64 * 1024)
 239 #define CONFIG_SPL_SPI_LOAD
 240
 241 /* Display */
 242 #define CONFIG_VIDEO_IPUV3
 243 #define CONFIG_IPUV3_CLK          260000000
 244 #define CONFIG_IMX_HDMI
 245
 246 #define CONFIG_SPLASH_SCREEN
 247 #define CONFIG_SPLASH_SOURCE
 248 #define CONFIG_VIDEO_BMP_RLE8
 249
 250 #define CONFIG_VIDEO_LOGO
 251 #define CONFIG_VIDEO_BMP_LOGO
 252
 253 /* EEPROM */
 254 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 255 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 256 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 258 #define CONFIG_SYS_EEPROM_SIZE                  256
 259
 260 #endif  /* __CONFIG_CM_FX6_H */