include/configs/cm_t3517.h

   1 /*
   2  * (C) Copyright 2013 CompuLab, Ltd.
   3  * Author: Igor Grinberg <grinberg@compulab.co.il>
   4  *
   5  * Configuration settings for the CompuLab CM-T3517 board
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_OMAP     /* in a TI OMAP core */
  17 #define CONFIG_CM_T3517 /* working with CM-T3517 */
  18
  19 #define CONFIG_SYS_TEXT_BASE    0x80008000
  20
  21 /*
  22  * This is needed for the DMA stuff.
  23  * Although the default iss 64, we still define it
  24  * to be on the safe side once the default is changed.
  25  */
  26
  27 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
  28
  29 #include <asm/arch/cpu.h>               /* get chip and board defs */
  30 #include <asm/arch/omap.h>
  31
  32 #define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517
  33
  34 /* Clock Defines */
  35 #define V_OSCK                  26000000        /* Clock output from T2 */
  36 #define V_SCLK                  (V_OSCK >> 1)
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 /*
  41  * The early kernel mapping on ARM currently only maps from the base of DRAM
  42  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
  43  * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
  44  * so that leaves DRAM base to DRAM base + 0x4000 available.
  45  */
  46 #define CONFIG_SYS_BOOTMAPSZ            0x4000
  47
  48 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  49 #define CONFIG_SETUP_MEMORY_TAGS
  50 #define CONFIG_INITRD_TAG
  51 #define CONFIG_REVISION_TAG
  52 #define CONFIG_SERIAL_TAG
  53
  54 /*
  55  * Size of malloc() pool
  56  */
  57 #define CONFIG_ENV_SIZE         (128 << 10)     /* 128 KiB */
  58 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  59
  60 /*
  61  * Hardware drivers
  62  */
  63
  64 /*
  65  * NS16550 Configuration
  66  */
  67 #define CONFIG_SYS_NS16550_SERIAL
  68 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  69 #define CONFIG_SYS_NS16550_CLK          48000000        /* 48MHz (APLL96/2) */
  70
  71 /*
  72  * select serial console configuration
  73  */
  74 #define CONFIG_CONS_INDEX               3
  75 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  76 #define CONFIG_SERIAL3                  3       /* UART3 */
  77
  78 /* allow to overwrite serial and ethaddr */
  79 #define CONFIG_ENV_OVERWRITE
  80 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  81                                         115200}
  82
  83 #define CONFIG_OMAP_GPIO
  84
  85 /* USB */
  86 #define CONFIG_USB_MUSB_AM35X
  87
  88 #ifndef CONFIG_USB_MUSB_AM35X
  89 #define CONFIG_USB_OMAP3
  90 #define CONFIG_USB_EHCI
  91 #define CONFIG_USB_EHCI_OMAP
  92 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
  93 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
  94 #else /* !CONFIG_USB_MUSB_AM35X */
  95 #define CONFIG_USB_MUSB_PIO_ONLY
  96 #endif /* CONFIG_USB_MUSB_AM35X */
  97
  98 /* commands to include */
  99 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
 100 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 101 #define CONFIG_MTD_PARTITIONS
 102 #define MTDIDS_DEFAULT          "nand0=nand"
 103 #define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
 104                                 "1920k(u-boot),256k(u-boot-env),"\
 105                                 "4m(kernel),-(fs)"
 106
 107 #define CONFIG_CMD_NAND         /* NAND support                 */
 108
 109 #define CONFIG_SYS_I2C
 110 #define CONFIG_SYS_OMAP24_I2C_SPEED     400000
 111 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 112 #define CONFIG_SYS_I2C_OMAP34XX
 113 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 115 #define CONFIG_SYS_I2C_EEPROM_BUS       0
 116 #define CONFIG_I2C_MULTI_BUS
 117
 118 /*
 119  * Board NAND Info.
 120  */
 121 #define CONFIG_NAND_OMAP_GPMC
 122 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 123                                                         /* to access nand */
 124 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 125                                                         /* to access nand at */
 126                                                         /* CS0 */
 127 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 128                                                         /* devices */
 129
 130 /* Environment information */
 131 #define CONFIG_EXTRA_ENV_SETTINGS \
 132         "loadaddr=0x82000000\0" \
 133         "baudrate=115200\0" \
 134         "console=ttyO2,115200n8\0" \
 135         "netretry=yes\0" \
 136         "mpurate=auto\0" \
 137         "vram=12M\0" \
 138         "dvimode=1024x768MR-16@60\0" \
 139         "defaultdisplay=dvi\0" \
 140         "mmcdev=0\0" \
 141         "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
 142         "mmcrootfstype=ext4\0" \
 143         "nandroot=/dev/mtdblock4 rw\0" \
 144         "nandrootfstype=ubifs\0" \
 145         "mmcargs=setenv bootargs console=${console} " \
 146                 "mpurate=${mpurate} " \
 147                 "vram=${vram} " \
 148                 "omapfb.mode=dvi:${dvimode} " \
 149                 "omapdss.def_disp=${defaultdisplay} " \
 150                 "root=${mmcroot} " \
 151                 "rootfstype=${mmcrootfstype}\0" \
 152         "nandargs=setenv bootargs console=${console} " \
 153                 "mpurate=${mpurate} " \
 154                 "vram=${vram} " \
 155                 "omapfb.mode=dvi:${dvimode} " \
 156                 "omapdss.def_disp=${defaultdisplay} " \
 157                 "root=${nandroot} " \
 158                 "rootfstype=${nandrootfstype}\0" \
 159         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 160         "bootscript=echo Running bootscript from mmc ...; " \
 161                 "source ${loadaddr}\0" \
 162         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 163         "mmcboot=echo Booting from mmc ...; " \
 164                 "run mmcargs; " \
 165                 "bootm ${loadaddr}\0" \
 166         "nandboot=echo Booting from nand ...; " \
 167                 "run nandargs; " \
 168                 "nand read ${loadaddr} 2a0000 400000; " \
 169                 "bootm ${loadaddr}\0" \
 170
 171 #define CONFIG_BOOTCOMMAND \
 172         "mmc dev ${mmcdev}; if mmc rescan; then " \
 173                 "if run loadbootscript; then " \
 174                         "run bootscript; " \
 175                 "else " \
 176                         "if run loaduimage; then " \
 177                                 "run mmcboot; " \
 178                         "else run nandboot; " \
 179                         "fi; " \
 180                 "fi; " \
 181         "else run nandboot; fi"
 182
 183 /*
 184  * Miscellaneous configurable options
 185  */
 186 #define CONFIG_AUTO_COMPLETE
 187 #define CONFIG_CMDLINE_EDITING
 188 #define CONFIG_TIMESTAMP
 189 #define CONFIG_SYS_AUTOLOAD             "no"
 190 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 191 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 192 /* Print Buffer Size */
 193 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 194                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 195 #define CONFIG_SYS_MAXARGS              32      /* max number of command args */
 196 /* Boot Argument Buffer Size */
 197 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 198
 199 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 200
 201 /*
 202  * AM3517 has 12 GP timers, they can be driven by the system clock
 203  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 204  * This rate is divided by a local divisor.
 205  */
 206 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 207 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 208 #define CONFIG_SYS_HZ                   1000
 209
 210 /*-----------------------------------------------------------------------
 211  * Physical Memory Map
 212  */
 213 #define CONFIG_NR_DRAM_BANKS    1       /* CM-T3517 DRAM is only on CS0 */
 214 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 215 #define CONFIG_SYS_CS0_SIZE             (256 << 20)
 216
 217 /*-----------------------------------------------------------------------
 218  * FLASH and environment organization
 219  */
 220
 221 /* **** PISMO SUPPORT *** */
 222 /* Monitor at start of flash */
 223 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 224 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 225
 226 #define CONFIG_ENV_IS_IN_NAND
 227 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 228 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 229 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 230
 231 #if defined(CONFIG_CMD_NET)
 232 #define CONFIG_DRIVER_TI_EMAC
 233 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
 234 #define CONFIG_MII
 235 #define CONFIG_SMC911X
 236 #define CONFIG_SMC911X_32_BIT
 237 #define CONFIG_SMC911X_BASE     (0x2C000000 + (16 << 20))
 238 #define CONFIG_ARP_TIMEOUT              200UL
 239 #define CONFIG_NET_RETRY_COUNT          5
 240 #endif /* CONFIG_CMD_NET */
 241
 242 /* additions for new relocation code, must be added to all boards */
 243 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 244 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 245 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 246 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 247                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 248                                          GENERATED_GBL_DATA_SIZE)
 249
 250 /* Status LED */
 251 #define GREEN_LED_GPIO                  186 /* CM-T3517 Green LED is GPIO186 */
 252
 253 /* GPIO banks */
 254 #ifdef CONFIG_LED_STATUS
 255 #define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 256 #endif
 257
 258 /* Display Configuration */
 259 #define CONFIG_OMAP3_GPIO_2
 260 #define CONFIG_OMAP3_GPIO_5
 261 #define CONFIG_VIDEO_OMAP3
 262 #define LCD_BPP         LCD_COLOR16
 263
 264 #define CONFIG_SPLASH_SCREEN
 265 #define CONFIG_SPLASHIMAGE_GUARD
 266 #define CONFIG_CMD_BMP
 267 #define CONFIG_BMP_16BPP
 268 #define CONFIG_SCF0403_LCD
 269
 270 #define CONFIG_OMAP3_SPI
 271
 272 /* EEPROM */
 273 #define CONFIG_CMD_EEPROM
 274 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 275 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 276 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 277 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 278 #define CONFIG_SYS_EEPROM_SIZE                  256
 279
 280 #define CONFIG_CMD_EEPROM_LAYOUT
 281 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
 282
 283 #endif /* __CONFIG_H */