include/configs/cradle.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35 #define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
  36 #define CONFIG_HHP_CRADLE       1       /* on an Cradle Board       */
  37
  38 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  39
  40 /*
  41  * Size of malloc() pool
  42  */
  43 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128*1024)
  44 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
  45
  46 /*
  47  * Hardware drivers
  48  */
  49 #define CONFIG_DRIVER_SMC91111
  50 #define CONFIG_SMC91111_BASE 0x10000300
  51 #define CONFIG_SMC91111_EXT_PHY
  52 #define CONFIG_SMC_USE_32_BIT
  53
  54 /*
  55  * select serial console configuration
  56  */
  57 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
  58
  59 /* allow to overwrite serial and ethaddr */
  60 #define CONFIG_ENV_OVERWRITE
  61
  62 #define CONFIG_BAUDRATE         115200
  63
  64
  65 /*
  66  * BOOTP options
  67  */
  68 #define CONFIG_BOOTP_BOOTFILESIZE
  69 #define CONFIG_BOOTP_BOOTPATH
  70 #define CONFIG_BOOTP_GATEWAY
  71 #define CONFIG_BOOTP_HOSTNAME
  72
  73
  74 /*
  75  * Command line configuration.
  76  */
  77 #include <config_cmd_default.h>
  78
  79
  80 #define CONFIG_BOOTDELAY        3
  81 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 console=ttyS0,115200"
  82 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
  83 #define CONFIG_NETMASK          255.255.0.0
  84 #define CONFIG_IPADDR           192.168.0.21
  85 #define CONFIG_SERVERIP         192.168.0.250
  86 #define CONFIG_BOOTCOMMAND      "bootm 40000"
  87 #define CONFIG_CMDLINE_TAG
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
  93 #define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
  94 #define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
  95 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  96 #define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
  97 #define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */
  98
  99 #define CONFIG_SYS_MEMTEST_START       0xa0400000      /* memtest works on     */
 100 #define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 101
 102 #undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 103
 104 #define CONFIG_SYS_LOAD_ADDR           0xa2000000      /* default load address */
 105
 106 #define CONFIG_SYS_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 107 #define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 108
 109                                                 /* valid baudrates */
 110 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 111
 112 /*
 113  * Stack sizes
 114  *
 115  * The stack sizes are set up in start.S using the settings below
 116  */
 117 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 118 #ifdef CONFIG_USE_IRQ
 119 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 120 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 121 #endif
 122
 123 /*
 124  * Physical Memory Map
 125  */
 126 #define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
 127 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 128 #define PHYS_SDRAM_1_SIZE       0x01000000 /* 64 MB */
 129 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 130 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 131 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 132 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 133 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 134 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 135
 136 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 137 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
 138 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 139
 140 #define CONFIG_SYS_DRAM_BASE           0xa0000000
 141 #define CONFIG_SYS_DRAM_SIZE           0x04000000
 142
 143 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 144
 145 /*
 146  * FLASH and environment organization
 147  */
 148 #define CONFIG_SYS_MAX_FLASH_BANKS     1     /* max number of memory banks           */
 149 #define CONFIG_SYS_MAX_FLASH_SECT      32    /* max number of sectors on one chip    */
 150
 151 /* timeout values are in ticks */
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 154
 155 #define CONFIG_ENV_IS_IN_FLASH  1
 156 #define CONFIG_ENV_ADDR                         0x00020000      /* absolute address for now   */
 157 #define CONFIG_ENV_SIZE                         0x20000    /* 8K ouch, this may later be */
 158
 159 /******************************************************************************
 160  *
 161  * CPU specific defines
 162  *
 163  ******************************************************************************/
 164
 165 /*
 166  * GPIO settings
 167  *
 168  * GPIO pin assignments
 169  * GPIO     Name        Dir Out AF
 170  * 0        NC
 171  * 1        NC
 172  * 2        SIRQ1       I
 173  * 3        SIRQ2       I
 174  * 4        SIRQ3       I
 175  * 5        DMAACK1     O   0
 176  * 6        DMAACK2     O   0
 177  * 7        DMAACK3     O   0
 178  * 8        TC1         O   0
 179  * 9        TC2         O   0
 180  * 10       TC3         O   0
 181  * 11       nDMAEN      O   1
 182  * 12       AENCTRL     O   0
 183  * 13       PLDTC       O   0
 184  * 14       ETHIRQ      I
 185  * 15       NC
 186  * 16       NC
 187  * 17       NC
 188  * 18       RDY         I
 189  * 19       DMASIO      I
 190  * 20       ETHIRQ      NC
 191  * 21       NC
 192  * 22       PGMEN       O   1    FIXME for debug only enable flash
 193  * 23       NC
 194  * 24       NC
 195  * 25       NC
 196  * 26       NC
 197  * 27       NC
 198  * 28       NC
 199  * 29       NC
 200  * 30       NC
 201  * 31       NC
 202  * 32       NC
 203  * 33       NC
 204  * 34       FFRXD       I       01
 205  * 35       FFCTS       I       01
 206  * 36       FFDCD       I       01
 207  * 37       FFDSR       I       01
 208  * 38       FFRI        I       01
 209  * 39       FFTXD       O   1   10
 210  * 40       FFDTR       O   0   10
 211  * 41       FFRTS       O   0   10
 212  * 42       RS232FOFF   O   0   00
 213  * 43       NC
 214  * 44       NC
 215  * 45       IRSL0       O   0
 216  * 46       IRRX0       I       01
 217  * 47       IRTX0       O   0   10
 218  * 48       NC
 219  * 49       nIOWE       O   0
 220  * 50       NC
 221  * 51       NC
 222  * 52       NC
 223  * 53       NC
 224  * 54       NC
 225  * 55       NC
 226  * 56       NC
 227  * 57       NC
 228  * 58       DKDIRQ      I
 229  * 59       NC
 230  * 60       NC
 231  * 61       NC
 232  * 62       NC
 233  * 63       NC
 234  * 64       COMLED      O   0
 235  * 65       COMLED      O   0
 236  * 66       COMLED      O   0
 237  * 67       COMLED      O   0
 238  * 68       COMLED      O   0
 239  * 69       COMLED      O   0
 240  * 70       COMLED      O   0
 241  * 71       COMLED      O   0
 242  * 72       NC
 243  * 73       NC
 244  * 74       NC
 245  * 75       NC
 246  * 76       NC
 247  * 77       NC
 248  * 78       CSIO        O   1
 249  * 79       NC
 250  * 80       CSETH       O   1
 251  *
 252  * NOTE: All NC's are defined to be outputs
 253  *
 254  */
 255 /* Pin direction control */
 256 /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
 257 #define CONFIG_SYS_GPDR0_VAL       0xfff3bf02
 258 #define CONFIG_SYS_GPDR1_VAL       0xfbffbf83
 259 #define CONFIG_SYS_GPDR2_VAL       0x0001ffff
 260 /* Set and Clear registers */
 261 #define CONFIG_SYS_GPSR0_VAL       0x00400800
 262 #define CONFIG_SYS_GPSR1_VAL       0x00000480
 263 #define CONFIG_SYS_GPSR2_VAL       0x00014000
 264 #define CONFIG_SYS_GPCR0_VAL       0x00000000
 265 #define CONFIG_SYS_GPCR1_VAL       0x00000000
 266 #define CONFIG_SYS_GPCR2_VAL       0x00000000
 267 /* Edge detect registers (these are set by the kernel) */
 268 #define CONFIG_SYS_GRER0_VAL       0x00000000
 269 #define CONFIG_SYS_GRER1_VAL       0x00000000
 270 #define CONFIG_SYS_GRER2_VAL       0x00000000
 271 #define CONFIG_SYS_GFER0_VAL       0x00000000
 272 #define CONFIG_SYS_GFER1_VAL       0x00000000
 273 #define CONFIG_SYS_GFER2_VAL       0x00000000
 274 /* Alternate function registers */
 275 #define CONFIG_SYS_GAFR0_L_VAL     0x00000000
 276 #define CONFIG_SYS_GAFR0_U_VAL     0x00000010
 277 #define CONFIG_SYS_GAFR1_L_VAL     0x900a9550
 278 #define CONFIG_SYS_GAFR1_U_VAL     0x00000008
 279 #define CONFIG_SYS_GAFR2_L_VAL     0x20000000
 280 #define CONFIG_SYS_GAFR2_U_VAL     0x00000002
 281
 282 /*
 283  * Clocks, power control and interrupts
 284  */
 285 #define CONFIG_SYS_PSSR_VAL        0x00000020
 286 #define CONFIG_SYS_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
 287 #define CONFIG_SYS_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
 288 #define CONFIG_SYS_ICMR_VAL        0x00000000  /* No interrupts enabled        */
 289
 290 /* FIXME
 291  *
 292  * RTC settings
 293  * Watchdog
 294  *
 295  */
 296
 297 /*
 298  * Memory settings
 299  *
 300  * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
 301  *       Verify timings on all
 302  */
 303 #define CONFIG_SYS_MSC0_VAL        0x000023FA  /* flash bank    (cs0)   */
 304 /*#define CONFIG_SYS_MSC1_VAL        0x00003549  / * SuperIO bank  (cs2)   */
 305 #define CONFIG_SYS_MSC1_VAL        0x0000354c  /* SuperIO bank  (cs2)   */
 306 #define CONFIG_SYS_MSC2_VAL        0x00001224  /* Ethernet bank (cs4)   */
 307 #ifdef REDBOOT_WAY
 308 #define CONFIG_SYS_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
 309 #define CONFIG_SYS_MDMRS_VAL       0x00000000
 310 #define CONFIG_SYS_MDREFR_VAL      0x00018018
 311 #else
 312 #define CONFIG_SYS_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
 313 #define CONFIG_SYS_MDMRS_VAL       0x00000000
 314 #define CONFIG_SYS_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
 315 #endif
 316
 317 /*
 318  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
 319  */
 320 #define CONFIG_SYS_MECR_VAL          0x00000000
 321 #define CONFIG_SYS_MCMEM0_VAL        0x00010504
 322 #define CONFIG_SYS_MCMEM1_VAL        0x00010504
 323 #define CONFIG_SYS_MCATT0_VAL        0x00010504
 324 #define CONFIG_SYS_MCATT1_VAL        0x00010504
 325 #define CONFIG_SYS_MCIO0_VAL         0x00004715
 326 #define CONFIG_SYS_MCIO1_VAL         0x00004715
 327
 328 /* Board specific defines */
 329
 330 /* LED defines */
 331 #define YELLOW    0x03
 332 #define RED       0x02
 333 #define GREEN     0x01
 334 #define OFF       0x00
 335 #define LED_IRDA0 0
 336 #define LED_IRDA1 2
 337 #define LED_IRDA2 4
 338 #define LED_IRDA3 6
 339 #define CRADLE_LED_SET_REG GPSR2
 340 #define CRADLE_LED_CLR_REG GPCR2
 341
 342 /* SuperIO defines */
 343 #define CRADLE_SIO_INDEX      0x2e
 344 #define CRADLE_SIO_DATA       0x2f
 345
 346 /* IO defines */
 347 #define CRADLE_CPLD_PHYS      0x08000000
 348 #define CRADLE_SIO1_PHYS      0x08100000
 349 #define CRADLE_SIO2_PHYS      0x08200000
 350 #define CRADLE_SIO3_PHYS      0x08300000
 351 #define CRADLE_ETH_PHYS       0x10000000
 352
 353 #ifndef __ASSEMBLY__
 354
 355 /* global prototypes */
 356 void led_code(int code, int color);
 357
 358 #endif
 359
 360 #endif  /* __CONFIG_H */