include/configs/inka4x0.h

   1 /*
   2  * (C) Copyright 2009
   3  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4  *
   5  * (C) Copyright 2003-2005
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU       */
  20 #define CONFIG_INKA4X0          1       /* INKA4x0 board                */
  21 #define CONFIG_DISPLAY_BOARDINFO
  22
  23 /*
  24  * Valid values for CONFIG_SYS_TEXT_BASE are:
  25  * 0xFFE00000   boot low
  26  * 0x00100000   boot from RAM (for testing only)
  27  */
  28 #ifndef CONFIG_SYS_TEXT_BASE
  29 #define CONFIG_SYS_TEXT_BASE    0xFFE00000      /* Standard: boot low */
  30 #endif
  31 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
  32
  33 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  34
  35 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  36
  37 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  38
  39 /*
  40  * Serial console configuration
  41  */
  42 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  43 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  44 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  45
  46 /*
  47  * PCI Mapping:
  48  * 0x40000000 - 0x4fffffff - PCI Memory
  49  * 0x50000000 - 0x50ffffff - PCI IO Space
  50  */
  51 #define CONFIG_PCI              1
  52 #define CONFIG_PCI_PNP          1
  53 #define CONFIG_PCI_SCAN_SHOW    1
  54 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  55
  56 #define CONFIG_PCI_MEM_BUS      0x40000000
  57 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  58 #define CONFIG_PCI_MEM_SIZE     0x10000000
  59
  60 #define CONFIG_PCI_IO_BUS       0x50000000
  61 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  62 #define CONFIG_PCI_IO_SIZE      0x01000000
  63
  64 #define CONFIG_SYS_XLB_PIPELINING       1
  65
  66 /* Partitions */
  67 #define CONFIG_MAC_PARTITION
  68 #define CONFIG_DOS_PARTITION
  69 #define CONFIG_ISO_PARTITION
  70
  71
  72 /*
  73  * BOOTP options
  74  */
  75 #define CONFIG_BOOTP_BOOTFILESIZE
  76 #define CONFIG_BOOTP_BOOTPATH
  77 #define CONFIG_BOOTP_GATEWAY
  78 #define CONFIG_BOOTP_HOSTNAME
  79
  80
  81 /*
  82  * Command line configuration.
  83  */
  84 #define CONFIG_CMD_DATE
  85 #define CONFIG_CMD_DHCP
  86 #define CONFIG_CMD_EXT2
  87 #define CONFIG_CMD_FAT
  88 #define CONFIG_CMD_IDE
  89 #define CONFIG_CMD_PCI
  90 #define CONFIG_CMD_PING
  91 #define CONFIG_CMD_SNTP
  92 #define CONFIG_CMD_USB
  93
  94 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  95
  96 #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)                /* Boot low */
  97 #   define CONFIG_SYS_LOWBOOT           1
  98 #endif
  99
 100 /*
 101  * Autobooting
 102  */
 103 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 104
 105 #define CONFIG_PREBOOT  "echo;" \
 106         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 107         "echo"
 108
 109 #undef  CONFIG_BOOTARGS
 110
 111 #define CONFIG_IPADDR           192.168.100.2
 112 #define CONFIG_SERVERIP         192.168.100.1
 113 #define CONFIG_NETMASK          255.255.255.0
 114 #define HOSTNAME                inka4x0
 115 #define CONFIG_BOOTFILE         "/tftpboot/inka4x0/uImage"
 116 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 117
 118 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 119         "netdev=eth0\0"                                                 \
 120         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 121                 "nfsroot=${serverip}:${rootpath}\0"                     \
 122         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 123         "addip=setenv bootargs ${bootargs} "                            \
 124                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 125                 ":${hostname}:${netdev}:off panic=1\0"                  \
 126         "addcons=setenv bootargs ${bootargs} "                          \
 127                 "console=ttyS0,${baudrate}\0"                           \
 128         "flash_nfs=run nfsargs addip addcons;"                          \
 129                 "bootm ${kernel_addr}\0"                                \
 130         "net_nfs=tftp 200000 ${bootfile};"                              \
 131                 "run nfsargs addip addcons;bootm\0"                     \
 132         "enable_disp=mw.l 100000 04000000 1;"                           \
 133                 "cp.l 100000 f0000b20 1;"                               \
 134                 "cp.l 100000 f0000b28 1\0"                              \
 135         "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 136         "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 137                 "run ideargs addip addcons enable_disp;bootm\0"         \
 138         "brightness=255\0"                                              \
 139         ""
 140
 141 #define CONFIG_BOOTCOMMAND      "run ide_boot"
 142
 143 /*
 144  * IPB Bus clocking configuration.
 145  */
 146 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 147
 148 /*
 149  * Flash configuration
 150  */
 151 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 152 #define CONFIG_FLASH_CFI_DRIVER 1
 153 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 154 #define CONFIG_SYS_FLASH_SIZE           0x00200000
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 156 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 157 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 158 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 159
 160 /*
 161  * Environment settings
 162  */
 163 #define CONFIG_ENV_IS_IN_FLASH  1
 164 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #define CONFIG_ENV_SECT_SIZE    0x2000
 167 #define CONFIG_ENV_OVERWRITE    1
 168 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 169
 170 /*
 171  * Memory map
 172  */
 173 #define CONFIG_SYS_MBAR         0xF0000000
 174 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 175 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 176
 177 /*
 178  * SDRAM controller configuration
 179  */
 180 #undef CONFIG_SDR_MT48LC16M16A2
 181 #undef CONFIG_DDR_MT46V16M16
 182 #undef CONFIG_DDR_MT46V32M16
 183 #undef CONFIG_DDR_HYB25D512160BF
 184 #define CONFIG_DDR_K4H511638C
 185
 186 /* Use ON-Chip SRAM until RAM will be available */
 187 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 188
 189 /* preserve space for the post_word at end of on-chip SRAM */
 190 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 191
 192 #ifdef CONFIG_POST
 193 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 194 #else
 195 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 196 #endif
 197
 198 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 199 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 200
 201 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 202 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 203 #   define CONFIG_SYS_RAMBOOT           1
 204 #endif
 205
 206 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 207 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 208 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 209
 210 /*
 211  * Ethernet configuration
 212  */
 213 #define CONFIG_MPC5xxx_FEC      1
 214 #define CONFIG_MPC5xxx_FEC_MII100
 215 /*
 216  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 217  */
 218 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 219 #define CONFIG_PHY_ADDR         0x00
 220 #define CONFIG_MII
 221
 222 /*
 223  * GPIO configuration
 224  *
 225  * use CS1 as gpio_wkup_6 output
 226  *      Bit 0 (mask: 0x80000000): 0
 227  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 228  *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 229  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 230  *            EEPROM
 231  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 232  * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 233  * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 234  * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 235  */
 236 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 237
 238 /*
 239  * RTC configuration
 240  */
 241 #define CONFIG_RTC_RTC4543      1       /* use external RTC */
 242
 243 /*
 244  * Software (bit-bang) three wire serial configuration
 245  *
 246  * Note that we need the ifdefs because otherwise compilation of
 247  * mkimage.c fails.
 248  */
 249 #define CONFIG_SOFT_TWS         1
 250
 251 #ifdef TWS_IMPLEMENTATION
 252 #include <mpc5xxx.h>
 253 #include <asm/io.h>
 254
 255 #define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 256 #define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 257 #define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 258 #define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 259
 260 static inline void tws_ce(unsigned bit)
 261 {
 262         struct mpc5xxx_wu_gpio *wu_gpio =
 263                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 264         if (bit)
 265                 setbits_8(&wu_gpio->dvo, TWS_CE);
 266         else
 267                 clrbits_8(&wu_gpio->dvo, TWS_CE);
 268 }
 269
 270 static inline void tws_wr(unsigned bit)
 271 {
 272         struct mpc5xxx_wu_gpio *wu_gpio =
 273                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 274         if (bit)
 275                 setbits_8(&wu_gpio->dvo, TWS_WR);
 276         else
 277                 clrbits_8(&wu_gpio->dvo, TWS_WR);
 278 }
 279
 280 static inline void tws_clk(unsigned bit)
 281 {
 282         struct mpc5xxx_gpio *gpio =
 283                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 284         if (bit)
 285                 setbits_8(&gpio->sint_dvo, TWS_CLK);
 286         else
 287                 clrbits_8(&gpio->sint_dvo, TWS_CLK);
 288 }
 289
 290 static inline void tws_data(unsigned bit)
 291 {
 292         struct mpc5xxx_gpio *gpio =
 293                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 294         if (bit)
 295                 setbits_8(&gpio->sint_dvo, TWS_DATA);
 296         else
 297                 clrbits_8(&gpio->sint_dvo, TWS_DATA);
 298 }
 299
 300 static inline unsigned tws_data_read(void)
 301 {
 302         struct mpc5xxx_gpio *gpio =
 303                         (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 304         return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 305 }
 306
 307 static inline void tws_data_config_output(unsigned output)
 308 {
 309         struct mpc5xxx_gpio *gpio =
 310                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 311         if (output)
 312                 setbits_8(&gpio->sint_ddr, TWS_DATA);
 313         else
 314                 clrbits_8(&gpio->sint_ddr, TWS_DATA);
 315 }
 316 #endif /* TWS_IMPLEMENTATION */
 317
 318 /*
 319  * Miscellaneous configurable options
 320  */
 321 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 322 #if defined(CONFIG_CMD_KGDB)
 323 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 324 #else
 325 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 326 #endif
 327 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 328 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 329 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 330
 331 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 332 #if defined(CONFIG_CMD_KGDB)
 333 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 334 #endif
 335
 336 /* Enable an alternate, more extensive memory test */
 337 #define CONFIG_SYS_ALT_MEMTEST
 338
 339 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 340 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 341
 342 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 343
 344 /*
 345  * Enable loopw command.
 346  */
 347 #define CONFIG_LOOPW
 348
 349 /*
 350  * Various low-level settings
 351  */
 352 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 353 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 354
 355 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 356 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 357 #define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 358 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 359 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 360
 361 /* 32Mbit SRAM @0x30000000 */
 362 #define CONFIG_SYS_CS1_START            0x30000000
 363 #define CONFIG_SYS_CS1_SIZE             0x00400000
 364 #define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 365
 366 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 367 #define CONFIG_SYS_CS2_START            0x80000000
 368 #define CONFIG_SYS_CS2_SIZE             0x0001000
 369 #define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 370
 371 /* GPIO in @0x30400000 */
 372 #define CONFIG_SYS_CS3_START            0x30400000
 373 #define CONFIG_SYS_CS3_SIZE             0x00100000
 374 #define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 375
 376 #define CONFIG_SYS_CS_BURST             0x00000000
 377 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 378
 379 /*-----------------------------------------------------------------------
 380  * USB stuff
 381  *-----------------------------------------------------------------------
 382  */
 383 #define CONFIG_USB_OHCI
 384 #define CONFIG_USB_CLOCK        0x00015555
 385 #define CONFIG_USB_CONFIG       0x00001000
 386 #define CONFIG_USB_STORAGE
 387
 388 /*-----------------------------------------------------------------------
 389  * IDE/ATA stuff Supports IDE harddisk
 390  *-----------------------------------------------------------------------
 391  */
 392
 393 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 394
 395 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 396 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 397
 398 #define CONFIG_IDE_PREINIT
 399
 400 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 401 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 402
 403 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 404 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 405 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 406 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 407 #define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 408 #define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 409
 410 #define CONFIG_ATAPI            1
 411
 412 #define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 413
 414 #endif /* __CONFIG_H */