include/configs/ls1043aqds.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043AQDS_H__
   8 #define __LS1043AQDS_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
  13 #define CONFIG_SYS_TEXT_BASE            0x82000000
  14 #elif defined(CONFIG_QSPI_BOOT)
  15 #define CONFIG_SYS_TEXT_BASE            0x40100000
  16 #else
  17 #define CONFIG_SYS_TEXT_BASE            0x60100000
  18 #endif
  19
  20 #ifndef __ASSEMBLY__
  21 unsigned long get_board_sys_clk(void);
  22 unsigned long get_board_ddr_clk(void);
  23 #endif
  24
  25 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  26 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  27
  28 #define CONFIG_SKIP_LOWLEVEL_INIT
  29
  30 #define CONFIG_LAYERSCAPE_NS_ACCESS
  31
  32 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  33 /* Physical Memory Map */
  34 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  35 #define CONFIG_NR_DRAM_BANKS            2
  36
  37 #define CONFIG_DDR_SPD
  38 #define SPD_EEPROM_ADDRESS              0x51
  39 #define CONFIG_SYS_SPD_BUS_NUM          0
  40
  41 #ifndef CONFIG_SPL
  42 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  43 #endif
  44
  45 #define CONFIG_DDR_ECC
  46 #ifdef CONFIG_DDR_ECC
  47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  48 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  49 #endif
  50
  51 #ifdef CONFIG_SYS_DPAA_FMAN
  52 #define CONFIG_FMAN_ENET
  53 #define CONFIG_PHYLIB
  54 #define CONFIG_PHY_VITESSE
  55 #define CONFIG_PHY_REALTEK
  56 #define CONFIG_PHYLIB_10G
  57 #define RGMII_PHY1_ADDR         0x1
  58 #define RGMII_PHY2_ADDR         0x2
  59 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  60 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  61 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  62 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  63 /* PHY address on QSGMII riser card on slot 1 */
  64 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  65 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  66 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  67 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  68 /* PHY address on QSGMII riser card on slot 2 */
  69 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  70 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  71 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  72 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  73 #endif
  74
  75 #ifdef CONFIG_RAMBOOT_PBL
  76 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
  77 #endif
  78
  79 #ifdef CONFIG_NAND_BOOT
  80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
  81 #endif
  82
  83 #ifdef CONFIG_SD_BOOT
  84 #ifdef CONFIG_SD_BOOT_QSPI
  85 #define CONFIG_SYS_FSL_PBL_RCW \
  86         board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
  87 #else
  88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
  89 #endif
  90 #endif
  91
  92 /* LPUART */
  93 #ifdef CONFIG_LPUART
  94 #define CONFIG_LPUART_32B_REG
  95 #endif
  96
  97 /* SATA */
  98 #define CONFIG_LIBATA
  99 #define CONFIG_SCSI_AHCI
 100 #define CONFIG_SCSI_AHCI_PLAT
 101
 102 /* EEPROM */
 103 #define CONFIG_ID_EEPROM
 104 #define CONFIG_SYS_I2C_EEPROM_NXID
 105 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 106 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 107 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 108 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 109 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 110
 111 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
 112
 113 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
 114 #define CONFIG_SYS_SCSI_MAX_LUN                 1
 115 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 116                                                 CONFIG_SYS_SCSI_MAX_LUN)
 117
 118 /*
 119  * IFC Definitions
 120  */
 121 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 122 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 123 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 124                                 CSPR_PORT_SIZE_16 | \
 125                                 CSPR_MSEL_NOR | \
 126                                 CSPR_V)
 127 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 128 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 129                                 + 0x8000000) | \
 130                                 CSPR_PORT_SIZE_16 | \
 131                                 CSPR_MSEL_NOR | \
 132                                 CSPR_V)
 133 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 134
 135 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 136                                         CSOR_NOR_TRHZ_80)
 137 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 138                                         FTIM0_NOR_TEADC(0x5) | \
 139                                         FTIM0_NOR_TEAHC(0x5))
 140 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 141                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 142                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 143 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 144                                         FTIM2_NOR_TCH(0x4) | \
 145                                         FTIM2_NOR_TWPH(0xe) | \
 146                                         FTIM2_NOR_TWP(0x1c))
 147 #define CONFIG_SYS_NOR_FTIM3            0
 148
 149 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 150 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 151 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 152 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 153
 154 #define CONFIG_SYS_FLASH_EMPTY_INFO
 155 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 156                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 157
 158 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 159 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 160
 161 /*
 162  * NAND Flash Definitions
 163  */
 164 #define CONFIG_NAND_FSL_IFC
 165
 166 #define CONFIG_SYS_NAND_BASE            0x7e800000
 167 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 168
 169 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 170
 171 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 172                                 | CSPR_PORT_SIZE_8      \
 173                                 | CSPR_MSEL_NAND        \
 174                                 | CSPR_V)
 175 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 176 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 177                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 178                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 179                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 180                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 181                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 182                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 183
 184 #define CONFIG_SYS_NAND_ONFI_DETECTION
 185
 186 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 187                                         FTIM0_NAND_TWP(0x18)   | \
 188                                         FTIM0_NAND_TWCHT(0x7) | \
 189                                         FTIM0_NAND_TWH(0xa))
 190 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 191                                         FTIM1_NAND_TWBE(0x39)  | \
 192                                         FTIM1_NAND_TRR(0xe)   | \
 193                                         FTIM1_NAND_TRP(0x18))
 194 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 195                                         FTIM2_NAND_TREH(0xa) | \
 196                                         FTIM2_NAND_TWHRE(0x1e))
 197 #define CONFIG_SYS_NAND_FTIM3           0x0
 198
 199 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 200 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 201 #define CONFIG_MTD_NAND_VERIFY_WRITE
 202 #define CONFIG_CMD_NAND
 203
 204 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 205 #endif
 206
 207 #ifdef CONFIG_NAND_BOOT
 208 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 209 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 210 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 211 #endif
 212
 213 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 214 #define CONFIG_QIXIS_I2C_ACCESS
 215 #define CONFIG_SYS_I2C_EARLY_INIT
 216 #endif
 217
 218 /*
 219  * QIXIS Definitions
 220  */
 221 #define CONFIG_FSL_QIXIS
 222
 223 #ifdef CONFIG_FSL_QIXIS
 224 #define QIXIS_BASE                      0x7fb00000
 225 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 226 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 227 #define QIXIS_LBMAP_SWITCH              6
 228 #define QIXIS_LBMAP_MASK                0x0f
 229 #define QIXIS_LBMAP_SHIFT               0
 230 #define QIXIS_LBMAP_DFLTBANK            0x00
 231 #define QIXIS_LBMAP_ALTBANK             0x04
 232 #define QIXIS_LBMAP_NAND                0x09
 233 #define QIXIS_LBMAP_SD                  0x00
 234 #define QIXIS_LBMAP_SD_QSPI             0xff
 235 #define QIXIS_LBMAP_QSPI                0xff
 236 #define QIXIS_RCW_SRC_NAND              0x106
 237 #define QIXIS_RCW_SRC_SD                0x040
 238 #define QIXIS_RCW_SRC_QSPI              0x045
 239 #define QIXIS_RST_CTL_RESET             0x41
 240 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 241 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 242 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 243
 244 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 245 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 246                                         CSPR_PORT_SIZE_8 | \
 247                                         CSPR_MSEL_GPCM | \
 248                                         CSPR_V)
 249 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 250 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 251                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 252                                         CSOR_NOR_TRHZ_80)
 253
 254 /*
 255  * QIXIS Timing parameters for IFC GPCM
 256  */
 257 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 258                                         FTIM0_GPCM_TEADC(0x20) | \
 259                                         FTIM0_GPCM_TEAHC(0x10))
 260 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 261                                         FTIM1_GPCM_TRAD(0x1f))
 262 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 263                                         FTIM2_GPCM_TCH(0x8) | \
 264                                         FTIM2_GPCM_TWP(0xf0))
 265 #define CONFIG_SYS_FPGA_FTIM3           0x0
 266 #endif
 267
 268 #ifdef CONFIG_NAND_BOOT
 269 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 270 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 271 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 272 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 273 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 274 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 275 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 276 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 277 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 278 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 279 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 280 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 281 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 282 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 283 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 284 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 285 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 286 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 287 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 288 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 289 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 290 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 291 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 292 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 293 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 294 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 295 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 296 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 297 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 298 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 299 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 300 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 301 #else
 302 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 303 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 304 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 305 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 306 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 307 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 308 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 309 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 310 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 311 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 312 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 313 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 314 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 315 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 316 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 317 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 318 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 319 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 320 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 321 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 322 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 323 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 324 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 325 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 326 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 327 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 328 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 329 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 330 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 331 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 332 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 333 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 334 #endif
 335
 336 /*
 337  * I2C bus multiplexer
 338  */
 339 #define I2C_MUX_PCA_ADDR_PRI            0x77
 340 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 341 #define I2C_RETIMER_ADDR                0x18
 342 #define I2C_MUX_CH_DEFAULT              0x8
 343 #define I2C_MUX_CH_CH7301               0xC
 344 #define I2C_MUX_CH5                     0xD
 345 #define I2C_MUX_CH7                     0xF
 346
 347 #define I2C_MUX_CH_VOL_MONITOR 0xa
 348
 349 /* Voltage monitor on channel 2*/
 350 #define I2C_VOL_MONITOR_ADDR           0x40
 351 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 352 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 353 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 354
 355 #define CONFIG_VID_FLS_ENV              "ls1043aqds_vdd_mv"
 356 #ifndef CONFIG_SPL_BUILD
 357 #define CONFIG_VID
 358 #endif
 359 #define CONFIG_VOL_MONITOR_IR36021_SET
 360 #define CONFIG_VOL_MONITOR_INA220
 361 /* The lowest and highest voltage allowed for LS1043AQDS */
 362 #define VDD_MV_MIN                      819
 363 #define VDD_MV_MAX                      1212
 364
 365 /* QSPI device */
 366 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 367 #define CONFIG_FSL_QSPI
 368 #ifdef CONFIG_FSL_QSPI
 369 #define CONFIG_SPI_FLASH_SPANSION
 370 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 371 #define FSL_QSPI_FLASH_NUM              2
 372 #endif
 373 #endif
 374
 375 /* USB */
 376 #define CONFIG_HAS_FSL_XHCI_USB
 377 #ifdef CONFIG_HAS_FSL_XHCI_USB
 378 #define CONFIG_USB_XHCI_FSL
 379 #define CONFIG_USB_MAX_CONTROLLER_COUNT         3
 380 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 381 #endif
 382
 383 /*
 384  * Miscellaneous configurable options
 385  */
 386 #define CONFIG_MISC_INIT_R
 387 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 388 #define CONFIG_AUTO_COMPLETE
 389 #define CONFIG_SYS_PBSIZE               \
 390                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 391 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 392
 393 #define CONFIG_SYS_MEMTEST_START        0x80000000
 394 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 395
 396 #define CONFIG_SYS_HZ                   1000
 397
 398 #define CONFIG_SYS_INIT_SP_OFFSET \
 399         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 400
 401 #ifdef CONFIG_SPL_BUILD
 402 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 403 #else
 404 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 405 #endif
 406
 407 /*
 408  * Environment
 409  */
 410 #define CONFIG_ENV_OVERWRITE
 411
 412 #ifdef CONFIG_NAND_BOOT
 413 #define CONFIG_ENV_SIZE                 0x2000
 414 #define CONFIG_ENV_OFFSET               (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
 415 #elif defined(CONFIG_SD_BOOT)
 416 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 417 #define CONFIG_SYS_MMC_ENV_DEV          0
 418 #define CONFIG_ENV_SIZE                 0x2000
 419 #elif defined(CONFIG_QSPI_BOOT)
 420 #define CONFIG_ENV_IS_IN_SPI_FLASH
 421 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 422 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 423 #define CONFIG_ENV_SECT_SIZE            0x10000
 424 #else
 425 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 426 #define CONFIG_ENV_SECT_SIZE            0x20000
 427 #define CONFIG_ENV_SIZE                 0x20000
 428 #endif
 429
 430 #define CONFIG_CMDLINE_TAG
 431
 432 #include <asm/fsl_secure_boot.h>
 433
 434 #endif /* __LS1043AQDS_H__ */