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post/i2c: Rename I2C_ADDR_LIST to CONFIG_SYS_POST_I2C_ADDRS
[people/ms/u-boot.git] / include / configs / lwmon5.h
1 /*
2 * (C) Copyright 2007-2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 /*
22 * lwmon5.h - configuration for lwmon5 board
23 */
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28 * Liebherr extra version info
29 */
30 #define CONFIG_IDENT_STRING " - v2.0"
31
32 /*
33 * High Level Configuration Options
34 */
35 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
36 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
37 #define CONFIG_440 1 /* ... PPC440 family */
38 #define CONFIG_4xx 1 /* ... PPC4xx family */
39
40 #ifndef CONFIG_SYS_TEXT_BASE
41 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
42 #endif
43
44 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
45
46 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
47 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
48 #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
49 #define CONFIG_MISC_INIT_R /* Call misc_init_r */
50 #define CONFIG_BOARD_RESET /* Call board_reset */
51
52 /*
53 * Base addresses -- Note these are effective addresses where the
54 * actual resources get mapped (not physical addresses)
55 */
56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
57 #define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
58 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
59
60 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
61 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
62 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
63 #define CONFIG_SYS_LIME_BASE_0 0xc0000000
64 #define CONFIG_SYS_LIME_BASE_1 0xc1000000
65 #define CONFIG_SYS_LIME_BASE_2 0xc2000000
66 #define CONFIG_SYS_LIME_BASE_3 0xc3000000
67 #define CONFIG_SYS_FPGA_BASE_0 0xc4000000
68 #define CONFIG_SYS_FPGA_BASE_1 0xc4200000
69 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
70 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
71 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
72 #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
73 #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
74 #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
75
76 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
77 #define CONFIG_SYS_USB_DEVICE 0xe0000000
78 #define CONFIG_SYS_USB_HOST 0xe0000400
79
80 /*
81 * Initial RAM & stack pointer
82 *
83 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
84 * the POST_WORD from OCM to a 440EPx register that preserves it's
85 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
86 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
87 */
88 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
89 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
90 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
91 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
92 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
93 CONFIG_SYS_GBL_DATA_SIZE)
94 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
95 /* unused GPT0 COMP reg */
96 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
97 #define CONFIG_SYS_OCM_SIZE (16 << 10)
98 /* 440EPx errata CHIP 11: don't use last 4kbytes */
99 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
100
101 /* Additional registers for watchdog timer post test */
102 #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
103 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
104 #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
105 #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
106 #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
107 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
108 #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
109 #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
110 #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
111 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
112
113 /*
114 * Serial Port
115 */
116 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
117 #define CONFIG_SYS_NS16550
118 #define CONFIG_SYS_NS16550_SERIAL
119 #define CONFIG_SYS_NS16550_REG_SIZE 1
120 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
121 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
122 #define CONFIG_BAUDRATE 115200
123 #define CONFIG_SERIAL_MULTI
124
125 #define CONFIG_SYS_BAUDRATE_TABLE \
126 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
127
128 /*
129 * Environment
130 */
131 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
132
133 /*
134 * FLASH related
135 */
136 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
137 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
138
139 #define CONFIG_SYS_FLASH0 0xFC000000
140 #define CONFIG_SYS_FLASH1 0xF8000000
141 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
142
143 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
144 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
145
146 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
147 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
148
149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
150 #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
151
152 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
153 #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
154
155 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
156 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
157 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
158
159 /* Address and size of Redundant Environment Sector */
160 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
161 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
162
163 /*
164 * DDR SDRAM
165 */
166 #define CONFIG_SYS_MBYTES_SDRAM 256
167 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
168 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
169 #define CONFIG_DDR_ECC /* enable ECC */
170
171 /* POST support */
172 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
173 CONFIG_SYS_POST_CPU | \
174 CONFIG_SYS_POST_ECC | \
175 CONFIG_SYS_POST_ETHER | \
176 CONFIG_SYS_POST_FPU | \
177 CONFIG_SYS_POST_I2C | \
178 CONFIG_SYS_POST_MEMORY | \
179 CONFIG_SYS_POST_OCM | \
180 CONFIG_SYS_POST_RTC | \
181 CONFIG_SYS_POST_SPR | \
182 CONFIG_SYS_POST_UART | \
183 CONFIG_SYS_POST_SYSMON | \
184 CONFIG_SYS_POST_WATCHDOG | \
185 CONFIG_SYS_POST_DSP | \
186 CONFIG_SYS_POST_BSPEC1 | \
187 CONFIG_SYS_POST_BSPEC2 | \
188 CONFIG_SYS_POST_BSPEC3 | \
189 CONFIG_SYS_POST_BSPEC4 | \
190 CONFIG_SYS_POST_BSPEC5)
191
192 /* Define here the base-addresses of the UARTs to test in POST */
193 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
194 CONFIG_SYS_NS16550_COM2 }
195
196 #define CONFIG_POST_UART { \
197 "UART test", \
198 "uart", \
199 "This test verifies the UART operation.", \
200 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
201 &uart_post_test, \
202 NULL, \
203 NULL, \
204 CONFIG_SYS_POST_UART \
205 }
206
207 #define CONFIG_POST_WATCHDOG { \
208 "Watchdog timer test", \
209 "watchdog", \
210 "This test checks the watchdog timer.", \
211 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
212 &lwmon5_watchdog_post_test, \
213 NULL, \
214 NULL, \
215 CONFIG_SYS_POST_WATCHDOG \
216 }
217
218 #define CONFIG_POST_BSPEC1 { \
219 "dsPIC init test", \
220 "dspic_init", \
221 "This test returns result of dsPIC READY test run earlier.", \
222 POST_RAM | POST_ALWAYS, \
223 &dspic_init_post_test, \
224 NULL, \
225 NULL, \
226 CONFIG_SYS_POST_BSPEC1 \
227 }
228
229 #define CONFIG_POST_BSPEC2 { \
230 "dsPIC test", \
231 "dspic", \
232 "This test gets result of dsPIC POST and dsPIC version.", \
233 POST_RAM | POST_ALWAYS, \
234 &dspic_post_test, \
235 NULL, \
236 NULL, \
237 CONFIG_SYS_POST_BSPEC2 \
238 }
239
240 #define CONFIG_POST_BSPEC3 { \
241 "FPGA test", \
242 "fpga", \
243 "This test checks FPGA registers and memory.", \
244 POST_RAM | POST_ALWAYS | POST_MANUAL, \
245 &fpga_post_test, \
246 NULL, \
247 NULL, \
248 CONFIG_SYS_POST_BSPEC3 \
249 }
250
251 #define CONFIG_POST_BSPEC4 { \
252 "GDC test", \
253 "gdc", \
254 "This test checks GDC registers and memory.", \
255 POST_RAM | POST_ALWAYS | POST_MANUAL,\
256 &gdc_post_test, \
257 NULL, \
258 NULL, \
259 CONFIG_SYS_POST_BSPEC4 \
260 }
261
262 #define CONFIG_POST_BSPEC5 { \
263 "SYSMON1 test", \
264 "sysmon1", \
265 "This test checks GPIO_62_EPX pin indicating power failure.", \
266 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
267 &sysmon1_post_test, \
268 NULL, \
269 NULL, \
270 CONFIG_SYS_POST_BSPEC5 \
271 }
272
273 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
274 #define CONFIG_LOGBUFFER
275 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
276 #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
277 #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
278 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
279
280 /*
281 * I2C
282 */
283 #define CONFIG_HARD_I2C /* I2C with hardware support */
284 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
285 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
286 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
287 #define CONFIG_SYS_I2C_SLAVE 0x7F
288
289 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
290 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
291 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
292 #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
293 #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
294 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
295 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
296
297 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
298 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
299 /* 64 byte page write mode using*/
300 /* last 6 bits of the address */
301 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
302 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
303
304 #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
305 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
306 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
307 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
308
309 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
310 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
311 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
312 CONFIG_SYS_I2C_DSPIC_ADDR, \
313 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
314 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
315 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
316
317 /*
318 * Pass open firmware flat tree
319 */
320 #define CONFIG_OF_LIBFDT
321 #define CONFIG_OF_BOARD_SETUP
322 /* Update size in "reg" property of NOR FLASH device tree nodes */
323 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
324
325 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
326
327 #define CONFIG_PREBOOT "setenv bootdelay 15"
328
329 #undef CONFIG_BOOTARGS
330
331 #define CONFIG_EXTRA_ENV_SETTINGS \
332 "hostname=lwmon5\0" \
333 "netdev=eth0\0" \
334 "unlock=yes\0" \
335 "logversion=2\0" \
336 "nfsargs=setenv bootargs root=/dev/nfs rw " \
337 "nfsroot=${serverip}:${rootpath}\0" \
338 "ramargs=setenv bootargs root=/dev/ram rw\0" \
339 "addip=setenv bootargs ${bootargs} " \
340 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
341 ":${hostname}:${netdev}:off panic=1\0" \
342 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
343 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
344 "flash_nfs=run nfsargs addip addtty addmisc;" \
345 "bootm ${kernel_addr}\0" \
346 "flash_self=run ramargs addip addtty addmisc;" \
347 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
348 "net_nfs=tftp 200000 ${bootfile};" \
349 "run nfsargs addip addtty addmisc;bootm\0" \
350 "rootpath=/opt/eldk/ppc_4xxFP\0" \
351 "bootfile=/tftpboot/lwmon5/uImage\0" \
352 "kernel_addr=FC000000\0" \
353 "ramdisk_addr=FC180000\0" \
354 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
355 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
356 "cp.b 200000 FFF80000 80000\0" \
357 "upd=run load update\0" \
358 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
359 "autoscr 200000\0" \
360 ""
361 #define CONFIG_BOOTCOMMAND "run flash_self"
362
363 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
364
365 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
366 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
367
368 #define CONFIG_PPC4xx_EMAC
369 #define CONFIG_IBM_EMAC4_V4 1
370 #define CONFIG_MII 1 /* MII PHY management */
371 #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
372
373 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
374 #define CONFIG_PHY_RESET_DELAY 300
375
376 #define CONFIG_HAS_ETH0
377 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
378
379 #define CONFIG_NET_MULTI 1
380 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
381 #define CONFIG_PHY1_ADDR 1
382
383 /* Video console */
384 #define CONFIG_VIDEO
385 #define CONFIG_VIDEO_MB862xx
386 #define CONFIG_VIDEO_MB862xx_ACCEL
387 #define CONFIG_CFB_CONSOLE
388 #define CONFIG_VIDEO_LOGO
389 #define CONFIG_CONSOLE_EXTRA_INFO
390 #define VIDEO_FB_16BPP_PIXEL_SWAP
391 #define VIDEO_FB_16BPP_WORD_SWAP
392
393 #define CONFIG_VGA_AS_SINGLE_DEVICE
394 #define CONFIG_VIDEO_SW_CURSOR
395 #define CONFIG_SPLASH_SCREEN
396
397 /* USB */
398 #ifdef CONFIG_440EPX
399 #define CONFIG_USB_OHCI
400 #define CONFIG_USB_STORAGE
401
402 /* Comment this out to enable USB 1.1 device */
403 #define USB_2_0_DEVICE
404
405 #endif /* CONFIG_440EPX */
406
407 /* Partitions */
408 #define CONFIG_MAC_PARTITION
409 #define CONFIG_DOS_PARTITION
410 #define CONFIG_ISO_PARTITION
411
412 /*
413 * BOOTP options
414 */
415 #define CONFIG_BOOTP_BOOTFILESIZE
416 #define CONFIG_BOOTP_BOOTPATH
417 #define CONFIG_BOOTP_GATEWAY
418 #define CONFIG_BOOTP_HOSTNAME
419
420 /*
421 * Command line configuration.
422 */
423 #include <config_cmd_default.h>
424
425 #define CONFIG_CMD_ASKENV
426 #define CONFIG_CMD_DATE
427 #define CONFIG_CMD_DHCP
428 #define CONFIG_CMD_DIAG
429 #define CONFIG_CMD_EEPROM
430 #define CONFIG_CMD_ELF
431 #define CONFIG_CMD_FAT
432 #define CONFIG_CMD_I2C
433 #define CONFIG_CMD_IRQ
434 #define CONFIG_CMD_LOG
435 #define CONFIG_CMD_MII
436 #define CONFIG_CMD_NET
437 #define CONFIG_CMD_NFS
438 #define CONFIG_CMD_PCI
439 #define CONFIG_CMD_PING
440 #define CONFIG_CMD_REGINFO
441 #define CONFIG_CMD_SDRAM
442
443 #ifdef CONFIG_VIDEO
444 #define CONFIG_CMD_BMP
445 #endif
446
447 #ifdef CONFIG_440EPX
448 #define CONFIG_CMD_USB
449 #endif
450
451 /*
452 * Miscellaneous configurable options
453 */
454 #define CONFIG_SUPPORT_VFAT
455
456 #define CONFIG_SYS_LONGHELP /* undef to save memory */
457 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
458
459 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
460 #ifdef CONFIG_SYS_HUSH_PARSER
461 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
462 #endif
463
464 #if defined(CONFIG_CMD_KGDB)
465 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
466 #else
467 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
468 #endif
469 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
470 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
471 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
472
473 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
474 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
475
476 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
477 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
478
479 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
480
481 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
482 #define CONFIG_LOOPW 1 /* enable loopw command */
483 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
484 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
485
486 /*
487 * PCI stuff
488 */
489 /* General PCI */
490 #define CONFIG_PCI /* include pci support */
491 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
492 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
493 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
494
495 /* Board-specific PCI */
496 #define CONFIG_SYS_PCI_TARGET_INIT
497 #define CONFIG_SYS_PCI_MASTER_INIT
498
499 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
500 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
501
502 #ifndef DEBUG
503 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
504 #endif
505 #define CONFIG_WD_PERIOD 40000 /* in usec */
506 #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
507
508 /*
509 * For booting Linux, the board info and command line data
510 * have to be in the first 16 MB of memory, since this is
511 * the maximum mapped by the 40x Linux kernel during initialization.
512 */
513 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
514 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
515
516 /*
517 * External Bus Controller (EBC) Setup
518 */
519 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
520
521 /* Memory Bank 0 (NOR-FLASH) initialization */
522 #define CONFIG_SYS_EBC_PB0AP 0x03000280
523 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
524
525 /* Memory Bank 1 (Lime) initialization */
526 #define CONFIG_SYS_EBC_PB1AP 0x01004380
527 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
528
529 /* Memory Bank 2 (FPGA) initialization */
530 #define CONFIG_SYS_EBC_PB2AP 0x01004400
531 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
532
533 /* Memory Bank 3 (FPGA2) initialization */
534 #define CONFIG_SYS_EBC_PB3AP 0x01004400
535 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
536
537 #define CONFIG_SYS_EBC_CFG 0xb8400000
538
539 /*
540 * Graphics (Fujitsu Lime)
541 */
542 /* SDRAM Clock frequency adjustment register */
543 #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
544 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
545 /* Lime Clock frequency is to set 100MHz */
546 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
547 #else
548 /* Lime Clock frequency for 133MHz */
549 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
550 #endif
551
552 /* SDRAM Parameter register */
553 #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
554 /*
555 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
556 * and pixel flare on display when 133MHz was configured. According to
557 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
558 * Grade
559 */
560 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
561 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
562 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
563 #else
564 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
565 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
566 #endif
567
568 /*
569 * GPIO Setup
570 */
571 #define CONFIG_SYS_GPIO_PHY1_RST 12
572 #define CONFIG_SYS_GPIO_FLASH_WP 14
573 #define CONFIG_SYS_GPIO_PHY0_RST 22
574 #define CONFIG_SYS_GPIO_DSPIC_READY 51
575 #define CONFIG_SYS_GPIO_CAN_ENABLE 53
576 #define CONFIG_SYS_GPIO_LSB_ENABLE 54
577 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
578 #define CONFIG_SYS_GPIO_HIGHSIDE 56
579 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
580 #define CONFIG_SYS_GPIO_BOARD_RESET 58
581 #define CONFIG_SYS_GPIO_LIME_S 59
582 #define CONFIG_SYS_GPIO_LIME_RST 60
583 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
584 #define CONFIG_SYS_GPIO_WATCHDOG 63
585
586 /*
587 * PPC440 GPIO Configuration
588 */
589 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
590 { \
591 /* GPIO Core 0 */ \
592 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
593 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
594 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
595 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
596 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
597 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
598 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
599 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
600 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
601 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
602 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
603 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
604 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
605 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
606 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
607 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
608 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
609 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
610 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
611 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
612 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
613 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
614 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
615 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
616 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
617 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
618 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
619 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
620 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
621 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
622 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
623 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
624 }, \
625 { \
626 /* GPIO Core 1 */ \
627 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
628 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
629 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
630 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
631 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
632 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
633 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
634 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
635 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
636 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
637 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
638 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
639 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
640 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
641 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
642 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
643 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
644 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
645 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
646 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
647 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
648 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
649 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
650 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
651 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
652 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
653 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
654 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
655 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
656 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
657 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
658 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
659 } \
660 }
661
662 #if defined(CONFIG_CMD_KGDB)
663 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
664 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
665 #endif
666 #endif /* __CONFIG_H */
"Das U-Boot" Source Tree