include/configs/mcc200.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15
  16 #define CONFIG_MPC5200
  17 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  18 #define CONFIG_MCC200           1       /* ... on MCC200 board                  */
  19
  20 /*
  21  * Valid values for CONFIG_SYS_TEXT_BASE are:
  22  * 0xFC000000   boot low (standard configuration)
  23  * 0xFFF00000   boot high
  24  * 0x00100000   boot from RAM (for testing only)
  25  */
  26 #ifndef CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  28 #endif
  29
  30 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz                */
  31
  32 #define CONFIG_MISC_INIT_R
  33
  34 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  35
  36 /*
  37  * Serial console configuration
  38  *
  39  *  To select console on the one of 8 external UARTs,
  40  * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
  41  * or as 5, 6, 7, or 8 for the second Quad UART.
  42  * COM11, COM12, COM13, COM14 are located on the second Quad UART.
  43  *
  44  *  CONFIG_PSC_CONSOLE must be undefined in this case.
  45  */
  46 #if !defined(CONFIG_PRS200)
  47 /* MCC200 configuration: */
  48 #ifdef CONFIG_CONSOLE_COM12
  49 #define CONFIG_QUART_CONSOLE    6       /* console is on UARTF of QUART2        */
  50 #else
  51 #define CONFIG_QUART_CONSOLE    8       /* console is on UARTH of QUART2        */
  52 #endif
  53 #else
  54 /* PRS200 configuration: */
  55 #undef CONFIG_QUART_CONSOLE
  56 #endif /* CONFIG_PRS200 */
  57 /*
  58  *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
  59  * and undefine CONFIG_QUART_CONSOLE.
  60  */
  61 #if !defined(CONFIG_PRS200)
  62 /* MCC200 configuration: */
  63 #define CONFIG_PSC_CONSOLE      1       /* PSC1 may be COM */
  64 #define CONFIG_PSC_CONSOLE2     2       /* PSC2 is PSoC */
  65 #else
  66 /* PRS200 configuration: */
  67 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  68 #endif
  69 #define CONFIG_BAUDRATE         115200
  70 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  71
  72 #define CONFIG_MII              1
  73
  74 #define CONFIG_DOS_PARTITION
  75
  76 /* USB */
  77 #define CONFIG_USB_OHCI
  78 #define CONFIG_USB_STORAGE
  79 /* automatic software updates (see board/mcc200/auto_update.c) */
  80 #define CONFIG_AUTO_UPDATE 1
  81
  82
  83 /*
  84  * BOOTP options
  85  */
  86 #define CONFIG_BOOTP_BOOTFILESIZE
  87 #define CONFIG_BOOTP_BOOTPATH
  88 #define CONFIG_BOOTP_GATEWAY
  89 #define CONFIG_BOOTP_HOSTNAME
  90
  91
  92 /*
  93  * Command line configuration.
  94  */
  95 #include <config_cmd_default.h>
  96
  97 #define CONFIG_CMD_BEDBUG
  98 #define CONFIG_CMD_FAT
  99 #define CONFIG_CMD_I2C
 100 #define CONFIG_CMD_USB
 101
 102 #undef  CONFIG_CMD_NET
 103 #undef  CONFIG_CMD_NFS
 104
 105 /*
 106  * Autobooting
 107  */
 108 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 109
 110 #define CONFIG_PREBOOT  "echo;" \
 111         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 112         "echo"
 113
 114 #undef  CONFIG_BOOTARGS
 115
 116 #ifdef CONFIG_PRS200
 117 # define CONFIG_SYS__BOARDNAME          "prs200"
 118 # define CONFIG_SYS__LINUX_CONSOLE      "ttyS0"
 119 #else
 120 # define CONFIG_SYS__BOARDNAME          "mcc200"
 121 # define CONFIG_SYS__LINUX_CONSOLE      "ttyEU5"
 122 #endif
 123
 124 /* Network */
 125 #define CONFIG_ETHADDR  00:17:17:ff:00:00
 126 #define CONFIG_IPADDR   10.76.9.29
 127 #define CONFIG_SERVERIP 10.76.9.1
 128
 129 #include <version.h> /* For U-Boot version */
 130
 131 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 132         "ubootver=" U_BOOT_VERSION "\0"                                 \
 133         "netdev=eth0\0"                                                 \
 134         "hostname=" CONFIG_SYS__BOARDNAME "\0"                          \
 135         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 136                 "nfsroot=${serverip}:${rootpath}\0"                     \
 137         "ramargs=setenv bootargs root=/dev/mtdblock2 "                  \
 138                 "rootfstype=cramfs\0"                                   \
 139         "addip=setenv bootargs ${bootargs} "                            \
 140                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 141                 ":${hostname}:${netdev}:off panic=1\0"                  \
 142         "addcons=setenv bootargs ${bootargs} "                          \
 143                 "console=${console},${baudrate} "                       \
 144                 "ubootver=${ubootver} board=${board}\0"                 \
 145         "flash_nfs=run nfsargs addip addcons;"                          \
 146                 "bootm ${kernel_addr}\0"                                \
 147         "flash_self=run ramargs addip addcons;"                         \
 148                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 149         "net_nfs=tftp 200000 ${bootfile};"                              \
 150                 "run nfsargs addip addcons;bootm\0"                     \
 151         "console=" CONFIG_SYS__LINUX_CONSOLE "\0"                               \
 152         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 153         "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0"         \
 154         "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0"     \
 155         "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 156         "kernel_addr=0xFC0C0000\0"                                      \
 157         "update=protect off ${text_base} +${filesize};"                 \
 158                 "era ${text_base} +${filesize};"                        \
 159                 "cp.b 200000 ${text_base} ${filesize}\0"                \
 160         "unlock=yes\0"                                                  \
 161         ""
 162
 163 #define CONFIG_BOOTCOMMAND      "run flash_self"
 164
 165 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 166
 167 /*
 168  * IPB Bus clocking configuration.
 169  */
 170 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 171
 172 /*
 173  * I2C configuration
 174  */
 175 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 176 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 177
 178 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 179 #define CONFIG_SYS_I2C_SLAVE            0x7F
 180
 181 /*
 182  * Flash configuration (8,16 or 32 MB)
 183  * TEXT base always at 0xFFF00000
 184  * ENV_ADDR always at  0xFFF40000
 185  * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 186  *               0xFE000000 for 32 MB
 187  *               0xFF000000 for 16 MB
 188  *               0xFF800000 for  8 MB
 189  */
 190 #define CONFIG_SYS_FLASH_BASE           0xfc000000
 191 #define CONFIG_SYS_FLASH_SIZE           0x04000000
 192
 193 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 194 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 195
 196 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 197
 198 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 199 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 200
 201 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 202 #define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection            */
 203
 204 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 205 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 206
 207 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 208 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 209
 210 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars       */
 211
 212 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector  */
 213 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 214 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 215
 216 /* Address and size of Redundant Environment Sector     */
 217 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 218 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 219
 220 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 221
 222 #if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
 223 #define CONFIG_SYS_LOWBOOT      1
 224 #endif
 225
 226 /*
 227  * Memory map
 228  */
 229 #define CONFIG_SYS_MBAR         0xf0000000
 230 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 231 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 232
 233 /* Use SRAM until RAM will be available */
 234 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 235 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 236
 237
 238 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 239 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 240
 241 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 242 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 243 #   define CONFIG_SYS_RAMBOOT           1
 244 #endif
 245
 246 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 247 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 248 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 249
 250 /*
 251  * Ethernet configuration
 252  */
 253 /* #define CONFIG_MPC5xxx_FEC   1 */
 254 /* #define CONFIG_MPC5xxx_FEC_MII100 */
 255 /*
 256  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 257  */
 258 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 259 #define CONFIG_PHY_ADDR         1
 260
 261 /*
 262  * LCD Splash Screen
 263  */
 264 #if !defined(CONFIG_PRS200)
 265 #define CONFIG_LCD              1
 266 #define CONFIG_PROGRESSBAR 1
 267 #endif
 268
 269 #if defined(CONFIG_LCD)
 270 #define CONFIG_SPLASH_SCREEN    1
 271 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 272 #define LCD_BPP                 LCD_MONOCHROME
 273 #endif
 274
 275 /*
 276  * GPIO configuration
 277  */
 278 /* 0x10000004 = 32MB SDRAM */
 279 /* 0x90000004 = 64MB SDRAM */
 280 #if defined(CONFIG_LCD)
 281 /* set PSC2 in UART mode */
 282 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00000044
 283 #else
 284 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00000004
 285 #endif
 286
 287 /*
 288  * Miscellaneous configurable options
 289  */
 290 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 291 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 292 #if defined(CONFIG_CMD_KGDB)
 293 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 294 #else
 295 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 296 #endif
 297 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
 298 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 299 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 300
 301 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 302 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 303
 304 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 305
 306 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 307
 308 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 309 #if defined(CONFIG_CMD_KGDB)
 310 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 311 #endif
 312
 313 /*
 314  * Various low-level settings
 315  */
 316 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 317 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 318
 319 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 320 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 321 #define CONFIG_SYS_BOOTCS_CFG           0x0004fb00
 322 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 323 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 324
 325 /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 326 #define CONFIG_SYS_CS2_START            0x80000000
 327 #define CONFIG_SYS_CS2_SIZE             0x00001000
 328 #define CONFIG_SYS_CS2_CFG              0x1d300
 329
 330 /* Second Quad UART @0x80010000 */
 331 #define CONFIG_SYS_CS1_START            0x80010000
 332 #define CONFIG_SYS_CS1_SIZE             0x00001000
 333 #define CONFIG_SYS_CS1_CFG              0x1d300
 334
 335 /* Leica - build revision resistors */
 336 /*
 337 #define CONFIG_SYS_CS3_START            0x80020000
 338 #define CONFIG_SYS_CS3_SIZE             0x00000004
 339 #define CONFIG_SYS_CS3_CFG              0x1d300
 340 */
 341
 342 /*
 343  *  Select one of quarts as a default
 344  * console. If undefined - PSC console
 345  * wil be default
 346  */
 347 #define CONFIG_SYS_CS_BURST             0x00000000
 348 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 349
 350 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 351
 352 /*
 353  * QUART Expanders support
 354  */
 355 #if defined(CONFIG_QUART_CONSOLE)
 356 /*
 357  * We'll use NS16550 chip routines,
 358  */
 359 #define CONFIG_SYS_NS16550              1
 360 #define CONFIG_SYS_NS16550_SERIAL       1
 361 #define CONFIG_CONS_INDEX       1
 362 /*
 363  *  To achieve necessary offset on SC16C554
 364  * A0-A2 (register select) pins with NS16550
 365  * functions (in struct NS16550), REG_SIZE
 366  * should be 4, because A0-A2 pins are connected
 367  * to DA2-DA4 address bus lines.
 368  */
 369 #define CONFIG_SYS_NS16550_REG_SIZE     4
 370 /*
 371  * LocalPlus Bus already inited in cpu_init_f(),
 372  * so can work with QUART's chip selects.
 373  * One of four SC16C554 UARTs is selected with
 374  * A3-A4 (DA5-DA6) lines.
 375  */
 376 #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
 377 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
 378 #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
 379 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
 380 #else
 381 #error "Wrong QUART expander number."
 382 #endif
 383
 384 /*
 385  * SC16C554 chip's external crystal oscillator frequency
 386  * is 7.3728 MHz
 387  */
 388 #define CONFIG_SYS_NS16550_CLK          7372800
 389 #endif /* CONFIG_QUART_CONSOLE */
 390 /*-----------------------------------------------------------------------
 391  * USB stuff
 392  *-----------------------------------------------------------------------
 393  */
 394 #define CONFIG_USB_CLOCK        0x0001BBBB
 395 #define CONFIG_USB_CONFIG       0x00005000
 396
 397 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot     */
 398 #define CONFIG_AUTOBOOT_STOP_STR        "432"
 399 #define CONFIG_SILENT_CONSOLE   1
 400
 401 #endif /* __CONFIG_H */