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1 /*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Configuration settings for the AVR32 Network Gateway
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 #include <asm/arch/memory-map.h>
28
29 #define CONFIG_AVR32 1
30 #define CONFIG_AT32AP 1
31 #define CONFIG_AT32AP7000 1
32 #define CONFIG_MIMC200 1
33
34 #define CONFIG_MIMC200_EXT_FLASH 1
35
36 #define CONFIG_SYS_HZ 1000
37
38 /*
39 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
40 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
41 * and the PBA bus to run at 1/4 the PLL frequency.
42 */
43 #define CONFIG_PLL 1
44 #define CONFIG_SYS_POWER_MANAGER 1
45 #define CONFIG_SYS_OSC0_HZ 10000000
46 #define CONFIG_SYS_PLL0_DIV 1
47 #define CONFIG_SYS_PLL0_MUL 15
48 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
49 #define CONFIG_SYS_CLKDIV_CPU 0
50 #define CONFIG_SYS_CLKDIV_HSB 1
51 #define CONFIG_SYS_CLKDIV_PBA 2
52 #define CONFIG_SYS_CLKDIV_PBB 1
53
54 /*
55 * The PLLOPT register controls the PLL like this:
56 * icp = PLLOPT<2>
57 * ivco = PLLOPT<1:0>
58 *
59 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
60 */
61 #define CONFIG_SYS_PLL0_OPT 0x04
62
63 #define CONFIG_USART1 1
64 #define CONFIG_MIMC200_DBGLINK 1
65
66 /* User serviceable stuff */
67 #define CONFIG_DOS_PARTITION 1
68
69 #define CONFIG_CMDLINE_TAG 1
70 #define CONFIG_SETUP_MEMORY_TAGS 1
71 #define CONFIG_INITRD_TAG 1
72
73 #define CONFIG_STACKSIZE (2048)
74
75 #define CONFIG_BAUDRATE 115200
76 #define CONFIG_BOOTARGS \
77 "console=ttyS0 root=/dev/mtdblock1 fbmem=600k rootfstype=jffs2"
78 #define CONFIG_BOOTCOMMAND \
79 "fsload; bootm"
80
81 #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
82 #define CONFIG_SILENT_CONSOLE_INPUT 1 /* disable console inputs */
83 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
84
85 /*
86 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
87 * data on the serial line may interrupt the boot sequence.
88 */
89 #define CONFIG_BOOTDELAY 0
90 #define CONFIG_ZERO_BOOTDELAY_CHECK 1
91 #define CONFIG_AUTOBOOT 1
92
93 /*
94 * After booting the board for the first time, new ethernet addresses
95 * should be generated and assigned to the environment variables
96 * "ethaddr" and "eth1addr". This is normally done during production.
97 */
98 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
99 #define CONFIG_NET_MULTI 1
100
101 /*
102 * BOOTP/DHCP options
103 */
104 #define CONFIG_BOOTP_SUBNETMASK
105 #define CONFIG_BOOTP_GATEWAY
106
107 #define CONFIG_DOS_PARTITION 1
108
109 /*
110 * Command line configuration.
111 */
112 #include <config_cmd_default.h>
113
114 #define CONFIG_CMD_ASKENV
115 #define CONFIG_CMD_DHCP
116 #define CONFIG_CMD_EXT2
117 #define CONFIG_CMD_FAT
118 #define CONFIG_CMD_JFFS2
119 #define CONFIG_CMD_MMC
120 #define CONFIG_CMD_NET
121
122 #define CONFIG_ATMEL_USART 1
123 #define CONFIG_MACB 1
124 #define CONFIG_PORTMUX_PIO 1
125 #define CONFIG_SYS_NR_PIOS 5
126 #define CONFIG_SYS_HSDRAMC 1
127 #define CONFIG_MMC 1
128 #define CONFIG_ATMEL_MCI 1
129
130 #define CONFIG_SYS_DCACHE_LINESZ 32
131 #define CONFIG_SYS_ICACHE_LINESZ 32
132
133 #define CONFIG_NR_DRAM_BANKS 1
134
135 #define CONFIG_SYS_FLASH_CFI 1
136 #define CONFIG_FLASH_CFI_DRIVER 1
137
138 #define CONFIG_SYS_FLASH_BASE 0x00000000
139 #define CONFIG_SYS_FLASH_SIZE 0x800000
140 #define CONFIG_SYS_MAX_FLASH_BANKS 1
141 #define CONFIG_SYS_MAX_FLASH_SECT 135
142
143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
144
145 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
146 #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
147 #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
148
149 #define CONFIG_SYS_FRAM_BASE 0x08000000
150 #define CONFIG_SYS_FRAM_SIZE 0x20000
151
152 #define CONFIG_ENV_IS_IN_FLASH 1
153 #define CONFIG_ENV_SIZE 65536
154 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
155
156 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
157
158 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
159 #define CONFIG_SYS_DMA_ALLOC_LEN (16384)
160
161 /* Allow 4MB for the kernel run-time image */
162 #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
163 #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
164
165 /* Other configuration settings that shouldn't have to change all that often */
166 #define CONFIG_SYS_PROMPT "U-Boot> "
167 #define CONFIG_SYS_CBSIZE 256
168 #define CONFIG_SYS_MAXARGS 16
169 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
170 #define CONFIG_SYS_LONGHELP 1
171
172 #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
173 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
174
175 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
176
177 #endif /* __CONFIG_H */