include/configs/sc520_spunk.h

   1 /*
   2  * (C) Copyright 2002
   3  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_X86              1       /* This is a X86 CPU            */
  37 #define CONFIG_SC520            1       /* Include support for AMD SC520 */
  38
  39 #define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6     /* 6T */
  40 #define CONFIG_SYS_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
  41 #define CONFIG_SYS_SDRAM_RAS_CAS_DELAY   3     /* 3T */
  42
  43 /* define at most one of these */
  44 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
  45 #define CONFIG_SYS_SDRAM_CAS_LATENCY_3T
  46
  47 #define CONFIG_SYS_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
  48 #define CONFIG_SYS_RESET_GENERIC       1       /* use tripple-fault to reset cpu */
  49 #undef  CONFIG_SYS_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
  50 #undef  CONFIG_SYS_TIMER_SC520                 /* use SC520 swtimers */
  51 #define CONFIG_SYS_TIMER_GENERIC       1       /* use the i8254 PIT timers */
  52 #undef  CONFIG_SYS_TIMER_TSC                   /* use the Pentium TSC timers */
  53
  54 #define CONFIG_SYS_STACK_SIZE          0x8000  /* Size of bootloader stack */
  55
  56 #define CONFIG_SHOW_BOOT_PROGRESS 1
  57 #define CONFIG_LAST_STAGE_INIT    1
  58
  59 /*
  60  * Size of malloc() pool
  61  */
  62 #define CONFIG_MALLOC_SIZE      (CONFIG_ENV_SIZE + 128*1024)
  63
  64
  65 #define CONFIG_BAUDRATE         9600
  66
  67
  68 /*
  69  * BOOTP options
  70  */
  71 #define CONFIG_BOOTP_BOOTFILESIZE
  72 #define CONFIG_BOOTP_BOOTPATH
  73 #define CONFIG_BOOTP_GATEWAY
  74 #define CONFIG_BOOTP_HOSTNAME
  75
  76
  77 /*
  78  * Command line configuration.
  79  */
  80 #include <config_cmd_default.h>
  81
  82 #define CONFIG_CMD_PCI
  83 #define CONFIG_CMD_JFFS2
  84 #define CONFIG_CMD_IDE
  85 #define CONFIG_CMD_NET
  86 #define CONFIG_CMD_PCMCIA
  87 #define CONFIG_CMD_EEPROM
  88
  89
  90 #define CONFIG_BOOTDELAY        15
  91 #define CONFIG_BOOTARGS         "root=/dev/mtdblock1 console=ttyS0,9600 " \
  92                                         "mtdparts=phys:7936k(root),256k(uboot) "
  93 #define CONFIG_BOOTCOMMAND      "setenv bootargs root=/dev/nfs ip=autoconf " \
  94                                         "console=ttyS0,9600 " \
  95                                         "mtdparts=phys:7808k(root),128k(env),256k(uboot);" \
  96                                         "bootp;bootm"
  97
  98 #if defined(CONFIG_CMD_KGDB)
  99 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 100 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 101 #endif
 102
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 108 #define CONFIG_SYS_PROMPT               "boot > "       /* Monitor Command Prompt       */
 109 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 110 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 111 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 112 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 113
 114 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 115 #define CONFIG_SYS_MEMTEST_END          0x01000000      /* 1 ... 16 MB in DRAM  */
 116
 117 #undef  CONFIG_SYS_CLKS_IN_HZ           /* everything, incl board info, in Hz */
 118
 119 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 120
 121 #define CONFIG_SYS_HZ                   1024            /* incrementer freq: 1kHz */
 122
 123                                                 /* valid baudrates */
 124 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 125
 126
 127 /*-----------------------------------------------------------------------
 128  * Physical Memory Map
 129  */
 130 #define CONFIG_NR_DRAM_BANKS    4          /* we have 4 banks of DRAM */
 131
 132 /*-----------------------------------------------------------------------
 133  * FLASH and environment organization
 134  */
 135
 136
 137 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 138 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 139
 140 /* timeout values are in ticks */
 141 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 142 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 143
 144
 145 #define CONFIG_SPI_EEPROM       /* SPI EEPROMs such as AT25010 or AT25640 */
 146 #define CONFIG_MW_EEPROM        /* MicroWire EEPROMS such as AT93LC46 */
 147 #define CONFIG_DTT_DS1722       /* Dallas DS1722 SPI Temperature probe */
 148
 149
 150 /* allow to overwrite serial and ethaddr */
 151 #define CONFIG_ENV_OVERWRITE
 152
 153
 154 #if 0
 155 /* Environment in flash */
 156 #define CONFIG_ENV_IS_IN_FLASH     1
 157 # define CONFIG_ENV_ADDR                (0x387a0000)    /* Addr of Environment Sector   */
 158 # define CONFIG_ENV_SIZE                0x20000 /* Total Size of Environment Sector (or 0x10000) */
 159 # define CONFIG_ENV_OFFSET         0
 160
 161 #else
 162 /* Environment in EEPROM */
 163
 164 # define CONFIG_ENV_IS_IN_EEPROM   1
 165 # define CONFIG_SPI
 166 # define CONFIG_SPI_X 1
 167 # define CONFIG_ENV_SIZE                0x2000  /* Total Size of Environment EEPROM     */
 168 # define CONFIG_ENV_OFFSET         0x1c00
 169
 170 #endif
 171
 172 /*
 173  * JFFS2 partitions
 174  *
 175  */
 176 /* No command line, one static partition, whole device */
 177 #undef CONFIG_JFFS2_CMDLINE
 178 #define CONFIG_JFFS2_DEV                "nor0"
 179 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 180 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 181
 182 /* mtdparts command line support */
 183 /* Note: fake mtd_id used, no linux mtd map file */
 184 /*
 185 #define CONFIG_JFFS2_CMDLINE
 186 #define MTDIDS_DEFAULT          "nor0=sc520_spunk-0"
 187 #define MTDPARTS_DEFAULT        "mtdparts=sc520_spunk-0:-(jffs2)"
 188 */
 189
 190 /*-----------------------------------------------------------------------
 191  * Device drivers
 192  */
 193 #define CONFIG_NET_MULTI        /* Multi ethernet cards support */
 194 #define CONFIG_EEPRO100
 195 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 196
 197 /************************************************************
 198  * IDE/ATA stuff
 199  ************************************************************/
 200 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 201 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 202 #define CONFIG_SYS_ATA_BASE_ADDR       0
 203 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01f0  /* ide0 offset */
 204 #define CONFIG_SYS_ATA_IDE1_OFFSET      0xe000  /* ide1 offset */
 205 #define CONFIG_SYS_ATA_DATA_OFFSET      0       /* data reg offset      */
 206 #define CONFIG_SYS_ATA_REG_OFFSET       0       /* reg offset */
 207 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200   /* alternate register offset */
 208
 209 #define CONFIG_SYS_FIRST_PCMCIA_BUS    1
 210
 211 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 212 #undef  CONFIG_IDE_RESET                /* reset for ide unsupported... */
 213 #undef  CONFIG_IDE_RESET_ROUTINE        /* no special reset function */
 214
 215 #define CONFIG_IDE_TI_CARDBUS
 216 #define CONFIG_SYS_PCMCIA_CIS_WIN          0x27f00000
 217 #define CONFIG_SYS_PCMCIA_CIS_WIN_SIZE     0x00100000
 218 #define CONFIG_SYS_PCMCIA_IO_WIN           0xe000
 219 #define CONFIG_SYS_PCMCIA_IO_WIN_SIZE      16
 220
 221 /************************************************************
 222  * DISK Partition support
 223  ************************************************************/
 224 #define CONFIG_DOS_PARTITION
 225 #define CONFIG_MAC_PARTITION
 226 #define CONFIG_ISO_PARTITION /* Experimental */
 227
 228
 229 /************************************************************
 230  * RTC
 231  ***********************************************************/
 232 #define CONFIG_RTC_MC146818
 233 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 234
 235 /*
 236  * PCI stuff
 237  */
 238 #define CONFIG_PCI                                /* include pci support */
 239 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 240 #define CONFIG_PCI_SCAN_SHOW
 241
 242 #define CONFIG_SYS_FIRST_PCI_IRQ   9
 243 #define CONFIG_SYS_SECOND_PCI_IRQ  10
 244 #define CONFIG_SYS_THIRD_PCI_IRQ   11
 245 #define CONFIG_SYS_FORTH_PCI_IRQ   12
 246
 247 #endif  /* __CONFIG_H */