include/configs/sh7785lcr.h

   1 /*
   2  * Configuation settings for the Renesas Technology R0P7785LC0011RL board
   3  *
   4  * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __SH7785LCR_H
  10 #define __SH7785LCR_H
  11
  12 #define CONFIG_CPU_SH7785       1
  13 #define CONFIG_SH7785LCR        1
  14
  15 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  16         "bootdevice=0:1\0"                                              \
  17         "usbload=usb reset;usbboot;usb stop;bootm\0"
  18
  19 #define CONFIG_DISPLAY_BOARDINFO
  20 #undef  CONFIG_SHOW_BOOT_PROGRESS
  21
  22 /* MEMORY */
  23 #if defined(CONFIG_SH_32BIT)
  24 #define CONFIG_SYS_TEXT_BASE            0x8FF80000
  25 /* 0x40000000 - 0x47FFFFFF does not use */
  26 #define CONFIG_SH_SDRAM_OFFSET          (0x8000000)
  27 #define SH7785LCR_SDRAM_PHYS_BASE       (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
  28 #define SH7785LCR_SDRAM_BASE            (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
  29 #define SH7785LCR_SDRAM_SIZE            (384 * 1024 * 1024)
  30 #define SH7785LCR_FLASH_BASE_1          (0xa0000000)
  31 #define SH7785LCR_FLASH_BANK_SIZE       (64 * 1024 * 1024)
  32 #define SH7785LCR_USB_BASE              (0xa6000000)
  33 #else
  34 #define CONFIG_SYS_TEXT_BASE            0x0FF80000
  35 #define SH7785LCR_SDRAM_BASE            (0x08000000)
  36 #define SH7785LCR_SDRAM_SIZE            (128 * 1024 * 1024)
  37 #define SH7785LCR_FLASH_BASE_1          (0xa0000000)
  38 #define SH7785LCR_FLASH_BANK_SIZE       (64 * 1024 * 1024)
  39 #define SH7785LCR_USB_BASE              (0xb4000000)
  40 #endif
  41
  42 #define CONFIG_SYS_LONGHELP
  43 #define CONFIG_SYS_PBSIZE               256
  44 #define CONFIG_SYS_BARGSIZE             512
  45 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }
  46
  47 /* SCIF */
  48 #define CONFIG_CONS_SCIF1       1
  49 #define CONFIG_SCIF_EXT_CLOCK   1
  50
  51 #define CONFIG_SYS_MEMTEST_START        (SH7785LCR_SDRAM_BASE)
  52 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
  53                                         (SH7785LCR_SDRAM_SIZE) - \
  54                                          4 * 1024 * 1024)
  55 #undef  CONFIG_SYS_ALT_MEMTEST
  56 #undef  CONFIG_SYS_MEMTEST_SCRATCH
  57 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
  58
  59 #define CONFIG_SYS_SDRAM_BASE   (SH7785LCR_SDRAM_BASE)
  60 #define CONFIG_SYS_SDRAM_SIZE   (SH7785LCR_SDRAM_SIZE)
  61 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
  62
  63 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
  64 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  65 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
  66 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
  67
  68 /* FLASH */
  69 #define CONFIG_FLASH_CFI_DRIVER
  70 #define CONFIG_SYS_FLASH_CFI
  71 #undef  CONFIG_SYS_FLASH_QUIET_TEST
  72 #define CONFIG_SYS_FLASH_EMPTY_INFO
  73 #define CONFIG_SYS_FLASH_BASE           (SH7785LCR_FLASH_BASE_1)
  74 #define CONFIG_SYS_MAX_FLASH_SECT       512
  75
  76 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  77 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE + \
  78                                  (0 * SH7785LCR_FLASH_BANK_SIZE) }
  79
  80 #define CONFIG_SYS_FLASH_ERASE_TOUT     (3 * 1000)
  81 #define CONFIG_SYS_FLASH_WRITE_TOUT     (3 * 1000)
  82 #define CONFIG_SYS_FLASH_LOCK_TOUT      (3 * 1000)
  83 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (3 * 1000)
  84
  85 #undef  CONFIG_SYS_FLASH_PROTECTION
  86 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
  87
  88 /* R8A66597 */
  89 #define CONFIG_USB_R8A66597_HCD
  90 #define CONFIG_R8A66597_BASE_ADDR       SH7785LCR_USB_BASE
  91 #define CONFIG_R8A66597_XTAL            0x0000  /* 12MHz */
  92 #define CONFIG_R8A66597_LDRV            0x8000  /* 3.3V */
  93 #define CONFIG_R8A66597_ENDIAN          0x0000  /* little */
  94
  95 /* PCI Controller */
  96 #define CONFIG_SH4_PCI
  97 #define CONFIG_SH7780_PCI
  98 #if defined(CONFIG_SH_32BIT)
  99 #define CONFIG_SH7780_PCI_LSR   0x1ff00001
 100 #define CONFIG_SH7780_PCI_LAR   0x5f000000
 101 #define CONFIG_SH7780_PCI_BAR   0x5f000000
 102 #else
 103 #define CONFIG_SH7780_PCI_LSR   0x07f00001
 104 #define CONFIG_SH7780_PCI_LAR   CONFIG_SYS_SDRAM_SIZE
 105 #define CONFIG_SH7780_PCI_BAR   CONFIG_SYS_SDRAM_SIZE
 106 #endif
 107 #define CONFIG_PCI_SCAN_SHOW    1
 108
 109 #define CONFIG_PCI_MEM_BUS      0xFD000000      /* Memory space base addr */
 110 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 111 #define CONFIG_PCI_MEM_SIZE     0x01000000      /* Size of Memory window */
 112
 113 #define CONFIG_PCI_IO_BUS       0xFE200000      /* IO space base address */
 114 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 115 #define CONFIG_PCI_IO_SIZE      0x00200000      /* Size of IO window */
 116
 117 #if defined(CONFIG_SH_32BIT)
 118 #define CONFIG_PCI_SYS_PHYS     SH7785LCR_SDRAM_PHYS_BASE
 119 #else
 120 #define CONFIG_PCI_SYS_PHYS     CONFIG_SYS_SDRAM_BASE
 121 #endif
 122 #define CONFIG_PCI_SYS_BUS      CONFIG_SYS_SDRAM_BASE
 123 #define CONFIG_PCI_SYS_SIZE     CONFIG_SYS_SDRAM_SIZE
 124
 125 /* ENV setting */
 126 #define CONFIG_ENV_OVERWRITE    1
 127 #define CONFIG_ENV_SECT_SIZE    (256 * 1024)
 128 #define CONFIG_ENV_SIZE         (CONFIG_ENV_SECT_SIZE)
 129 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 130 #define CONFIG_ENV_OFFSET               (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 131 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
 132
 133 /* Board Clock */
 134 /* The SCIF used external clock. system clock only used timer. */
 135 #define CONFIG_SYS_CLK_FREQ     50000000
 136 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 137 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 138 #define CONFIG_SYS_TMU_CLK_DIV          4
 139
 140 #endif  /* __SH7785LCR_H */