include/configs/trats.h

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  *
   5  * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  * (easy to change)
  32  */
  33 #define CONFIG_SAMSUNG          /* in a SAMSUNG core */
  34 #define CONFIG_S5P              /* which is in a S5P Family */
  35 #define CONFIG_EXYNOS4210       /* which is in a EXYNOS4210 */
  36 #define CONFIG_TRATS            /* working with TRATS */
  37 #define CONFIG_TIZEN            /* TIZEN lib */
  38
  39 #include <asm/arch/cpu.h>       /* get chip and board defs */
  40
  41 #define CONFIG_ARCH_CPU_INIT
  42 #define CONFIG_DISPLAY_CPUINFO
  43 #define CONFIG_DISPLAY_BOARDINFO
  44
  45 #ifndef CONFIG_SYS_L2CACHE_OFF
  46 #define CONFIG_SYS_L2_PL310
  47 #define CONFIG_SYS_PL310_BASE   0x10502000
  48 #endif
  49
  50 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  51 #define CONFIG_SYS_TEXT_BASE            0x63300000
  52
  53 /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
  54 #define CONFIG_SYS_CLK_FREQ_C210        24000000
  55 #define CONFIG_SYS_CLK_FREQ             CONFIG_SYS_CLK_FREQ_C210
  56
  57 #define CONFIG_SETUP_MEMORY_TAGS
  58 #define CONFIG_CMDLINE_TAG
  59 #define CONFIG_REVISION_TAG
  60 #define CONFIG_CMDLINE_EDITING
  61 #define CONFIG_SKIP_LOWLEVEL_INIT
  62 #define CONFIG_BOARD_EARLY_INIT_F
  63
  64 /* MACH_TYPE_TRATS macro will be removed once added to mach-types */
  65 #define MACH_TYPE_TRATS                 3928
  66 #define CONFIG_MACH_TYPE                MACH_TYPE_TRATS
  67
  68 /* Size of malloc() pool */
  69 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (16 << 20))
  70
  71 /* select serial console configuration */
  72 #define CONFIG_SERIAL2                  /* use SERIAL 2 */
  73 #define CONFIG_BAUDRATE                 115200
  74
  75 /* MMC */
  76 #define CONFIG_GENERIC_MMC
  77 #define CONFIG_MMC
  78 #define CONFIG_S5P_SDHCI
  79 #define CONFIG_SDHCI
  80 #define CONFIG_MMC_SDMA
  81
  82 /* PWM */
  83 #define CONFIG_PWM
  84
  85 /* It should define before config_cmd_default.h */
  86 #define CONFIG_SYS_NO_FLASH
  87
  88 /* Command definition */
  89 #include <config_cmd_default.h>
  90
  91 #undef CONFIG_CMD_FPGA
  92 #undef CONFIG_CMD_MISC
  93 #undef CONFIG_CMD_NET
  94 #undef CONFIG_CMD_NFS
  95 #undef CONFIG_CMD_XIMG
  96 #undef CONFIG_CMD_CACHE
  97 #undef CONFIG_CMD_ONENAND
  98 #undef CONFIG_CMD_MTDPARTS
  99 #define CONFIG_CMD_MMC
 100 #define CONFIG_CMD_DFU
 101 #define CONFIG_CMD_GPT
 102 #define CONFIG_CMD_SETEXPR
 103
 104 /* FAT */
 105 #define CONFIG_CMD_FAT
 106 #define CONFIG_FAT_WRITE
 107
 108 /* USB Composite download gadget - g_dnl */
 109 #define CONFIG_USBDOWNLOAD_GADGET
 110 #define CONFIG_DFU_FUNCTION
 111 #define CONFIG_DFU_MMC
 112
 113 /* USB Samsung's IDs */
 114 #define CONFIG_G_DNL_VENDOR_NUM 0x04E8
 115 #define CONFIG_G_DNL_PRODUCT_NUM 0x6601
 116 #define CONFIG_G_DNL_MANUFACTURER "Samsung"
 117
 118 #define CONFIG_BOOTDELAY                1
 119 #define CONFIG_ZERO_BOOTDELAY_CHECK
 120 #define CONFIG_BOOTARGS                 "Please use defined boot"
 121 #define CONFIG_BOOTCOMMAND              "run mmcboot"
 122
 123 #define CONFIG_DEFAULT_CONSOLE          "console=ttySAC2,115200n8\0"
 124 #define CONFIG_BOOTBLOCK                "10"
 125 #define CONFIG_ENV_COMMON_BOOT          "${console} ${meminfo}"
 126
 127 /* Tizen - partitions definitions */
 128 #define PARTS_CSA               "csa-mmc"
 129 #define PARTS_BOOTLOADER        "u-boot"
 130 #define PARTS_BOOT              "boot"
 131 #define PARTS_ROOT              "platform"
 132 #define PARTS_DATA              "data"
 133 #define PARTS_CSC               "csc"
 134 #define PARTS_UMS               "ums"
 135
 136 #define PARTS_DEFAULT \
 137         "uuid_disk=${uuid_gpt_disk};" \
 138         "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
 139         "name="PARTS_BOOTLOADER",size=60MiB," \
 140                 "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
 141         "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
 142         "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
 143         "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
 144         "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
 145         "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
 146
 147 #define CONFIG_DFU_ALT \
 148         "u-boot mmc 80 400;" \
 149         "uImage ext4 0 2;" \
 150         "exynos4210-trats.dtb ext4 0 2\0"
 151
 152 #define CONFIG_ENV_OVERWRITE
 153 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 154 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 155
 156 #define CONFIG_EXTRA_ENV_SETTINGS \
 157         "bootk=" \
 158                 "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
 159         "updatemmc=" \
 160                 "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
 161                 "mmc boot 0 1 1 0\0" \
 162         "updatebackup=" \
 163                 "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
 164                 "mmc boot 0 1 1 0\0" \
 165         "updatebootb=" \
 166                 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
 167         "lpj=lpj=3981312\0" \
 168         "nfsboot=" \
 169                 "setenv bootargs root=/dev/nfs rw " \
 170                 "nfsroot=${nfsroot},nolock,tcp " \
 171                 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 172                 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
 173                 "; run bootk\0" \
 174         "ramfsboot=" \
 175                 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
 176                 "${console} ${meminfo} " \
 177                 "initrd=0x43000000,8M ramdisk=8192\0" \
 178         "mmcboot=" \
 179                 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 180                 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
 181                 "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
 182         "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
 183         "boottrace=setenv opts initcall_debug; run bootcmd\0" \
 184         "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
 185         "verify=n\0" \
 186         "rootfstype=ext4\0" \
 187         "console=" CONFIG_DEFAULT_CONSOLE \
 188         "meminfo=crashkernel=32M@0x50000000\0" \
 189         "nfsroot=/nfsroot/arm\0" \
 190         "bootblock=" CONFIG_BOOTBLOCK "\0" \
 191         "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
 192         "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
 193                 "${fdtfile}\0" \
 194         "mmcdev=0\0" \
 195         "mmcbootpart=2\0" \
 196         "mmcrootpart=5\0" \
 197         "opts=always_resume=1\0" \
 198         "partitions=" PARTS_DEFAULT \
 199         "dfu_alt_info=" CONFIG_DFU_ALT \
 200         "spladdr=0x40000100\0" \
 201         "splsize=0x200\0" \
 202         "splfile=falcon.bin\0" \
 203         "spl_export=" \
 204                    "setexpr spl_imgsize ${splsize} + 8 ;" \
 205                    "setenv spl_imgsize 0x${spl_imgsize};" \
 206                    "setexpr spl_imgaddr ${spladdr} - 8 ;" \
 207                    "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
 208                    "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
 209                    "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 210                    "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
 211                    "spl export atags 0x40007FC0;" \
 212                    "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
 213                    "mw.l ${spl_addr_tmp} ${splsize};" \
 214                    "ext4write mmc ${mmcdev}:${mmcbootpart}" \
 215                    " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
 216                    "setenv spl_imgsize;" \
 217                    "setenv spl_imgaddr;" \
 218                    "setenv spl_addr_tmp;\0" \
 219         "fdtaddr=40800000\0" \
 220         "fdtfile=exynos4210-trats.dtb\0"
 221
 222
 223 /* Miscellaneous configurable options */
 224 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 225 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 226 #define CONFIG_SYS_PROMPT               "TRATS # "
 227 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 228 #define CONFIG_SYS_PBSIZE               384     /* Print Buffer Size */
 229 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 230 /* Boot Argument Buffer Size */
 231 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 232 /* memtest works on */
 233 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 234 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x5000000)
 235 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x4800000)
 236
 237 #define CONFIG_SYS_HZ                   1000
 238
 239 /* TRATS has 4 banks of DRAM */
 240 #define CONFIG_NR_DRAM_BANKS    4
 241 #define SDRAM_BANK_SIZE         (256UL << 20UL) /* 256 MB */
 242 #define PHYS_SDRAM_1            CONFIG_SYS_SDRAM_BASE
 243 #define PHYS_SDRAM_1_SIZE       SDRAM_BANK_SIZE
 244 #define PHYS_SDRAM_2            (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
 245 #define PHYS_SDRAM_2_SIZE       SDRAM_BANK_SIZE
 246 #define PHYS_SDRAM_3            (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
 247 #define PHYS_SDRAM_3_SIZE       SDRAM_BANK_SIZE
 248 #define PHYS_SDRAM_4            (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
 249 #define PHYS_SDRAM_4_SIZE       SDRAM_BANK_SIZE
 250
 251 #define CONFIG_SYS_MEM_TOP_HIDE         (1 << 20)       /* ram console */
 252
 253 #define CONFIG_SYS_MONITOR_BASE         0x00000000
 254 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 255
 256 #define CONFIG_ENV_IS_IN_MMC
 257 #define CONFIG_SYS_MMC_ENV_DEV          0
 258 #define CONFIG_ENV_SIZE                 4096
 259 #define CONFIG_ENV_OFFSET               ((32 - 4) << 10) /* 32KiB - 4KiB */
 260
 261 #define CONFIG_DOS_PARTITION
 262 #define CONFIG_EFI_PARTITION
 263
 264 /* EXT4 */
 265 #define CONFIG_CMD_EXT4
 266 #define CONFIG_CMD_EXT4_WRITE
 267 /* Falcon mode definitions */
 268 #define CONFIG_CMD_SPL
 269 #define CONFIG_SYS_SPL_ARGS_ADDR        PHYS_SDRAM_1 + 0x100
 270
 271 /* GPT */
 272 #define CONFIG_EFI_PARTITION
 273 #define CONFIG_PARTITION_UUIDS
 274
 275 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
 276 #define CONFIG_SYS_CACHELINE_SIZE       32
 277
 278 #define CONFIG_SOFT_I2C
 279 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 280 #define CONFIG_SYS_I2C_INIT_BOARD
 281 #define CONFIG_SYS_I2C_SPEED    50000
 282 #define CONFIG_I2C_MULTI_BUS
 283 #define CONFIG_SOFT_I2C_MULTI_BUS
 284 #define CONFIG_SYS_MAX_I2C_BUS  15
 285
 286 #include <asm/arch/gpio.h>
 287
 288 /* I2C PMIC */
 289 #define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
 290 #define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
 291
 292 /* I2C FG */
 293 #define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
 294 #define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
 295
 296 #define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
 297 #define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
 298 #define I2C_INIT multi_i2c_init()
 299
 300 #define CONFIG_POWER
 301 #define CONFIG_POWER_I2C
 302 #define CONFIG_POWER_MAX8997
 303
 304 #define CONFIG_POWER_FG
 305 #define CONFIG_POWER_FG_MAX17042
 306 #define CONFIG_POWER_MUIC
 307 #define CONFIG_POWER_MUIC_MAX8997
 308 #define CONFIG_POWER_BATTERY
 309 #define CONFIG_POWER_BATTERY_TRATS
 310 #define CONFIG_USB_GADGET
 311 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 312 #define CONFIG_USB_GADGET_DUALSPEED
 313 #define CONFIG_USB_GADGET_VBUS_DRAW     2
 314
 315 /* LCD */
 316 #define CONFIG_EXYNOS_FB
 317 #define CONFIG_LCD
 318 #define CONFIG_CMD_BMP
 319 #define CONFIG_BMP_32BPP
 320 #define CONFIG_FB_ADDR          0x52504000
 321 #define CONFIG_S6E8AX0
 322 #define CONFIG_EXYNOS_MIPI_DSIM
 323 #define CONFIG_VIDEO_BMP_GZIP
 324 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
 325
 326 #define CONFIG_CMD_USB_MASS_STORAGE
 327 #if defined(CONFIG_CMD_USB_MASS_STORAGE)
 328 #define CONFIG_USB_GADGET_MASS_STORAGE
 329 #endif
 330
 331 /* Pass open firmware flat tree */
 332 #define CONFIG_OF_LIBFDT    1
 333
 334 #endif  /* __CONFIG_H */