include/configs/utx8245.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2002
   6  * Gregory E. Allen, gallen@arlut.utexas.edu
   7  * Matthew E. Karger, karger@arlut.utexas.edu
   8  * Applied Research Laboratories, The University of Texas at Austin
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 /*
  14  *
  15  * Configuration settings for the utx8245 board.
  16  *
  17  */
  18
  19 /* ------------------------------------------------------------------------- */
  20
  21 /*
  22  * board/config.h - configuration options, board specific
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * High Level Configuration Options
  30  * (easy to change)
  31  */
  32
  33 #define CONFIG_MPC824X          1
  34 #define CONFIG_MPC8245          1
  35 #define CONFIG_UTX8245          1
  36
  37 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  38
  39 #define DEBUG                           1
  40
  41 #define CONFIG_IDENT_STRING     " [UTX5] "
  42
  43 #define CONFIG_CONS_INDEX       1
  44 #define CONFIG_BAUDRATE         57600
  45
  46 #define CONFIG_BOOTDELAY        2
  47 #define CONFIG_AUTOBOOT_PROMPT  "autoboot in %d seconds\n", bootdelay
  48 #define CONFIG_BOOTCOMMAND      "run nfsboot"   /* autoboot command     */
  49 #define CONFIG_BOOTARGS         "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
  50 #define CONFIG_ETHADDR          00:AA:00:14:00:05       /* UTX5 */
  51 #define CONFIG_SERVERIP         10.8.17.105     /* Spree */
  52
  53 #define CONFIG_EXTRA_ENV_SETTINGS \
  54         "kernel_addr=FFA00000\0" \
  55         "ramdisk_addr=FF800000\0" \
  56         "u-boot_startaddr=FFB00000\0" \
  57         "u-boot_endaddr=FFB2FFFF\0" \
  58         "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
  59 nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
  60         "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
  61         "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
  62         "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
  63         "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
  64         "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  65         "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  66         "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  67         "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
  68 ${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
  69 ${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
  70 protect on ${u-boot_startaddr} ${u-boot_endaddr}"
  71
  72 #define CONFIG_ENV_OVERWRITE
  73
  74
  75 /*
  76  * BOOTP options
  77  */
  78 #define CONFIG_BOOTP_BOOTFILESIZE
  79 #define CONFIG_BOOTP_BOOTPATH
  80 #define CONFIG_BOOTP_GATEWAY
  81 #define CONFIG_BOOTP_HOSTNAME
  82
  83
  84 /*
  85  * Command line configuration.
  86  */
  87 #include <config_cmd_default.h>
  88
  89 #define CONFIG_CMD_BDI
  90 #define CONFIG_CMD_PCI
  91 #define CONFIG_CMD_FLASH
  92 #define CONFIG_CMD_MEMORY
  93 #define CONFIG_CMD_SAVEENV
  94 #define CONFIG_CMD_CONSOLE
  95 #define CONFIG_CMD_LOADS
  96 #define CONFIG_CMD_LOADB
  97 #define CONFIG_CMD_IMI
  98 #define CONFIG_CMD_CACHE
  99 #define CONFIG_CMD_REGINFO
 100 #define CONFIG_CMD_NET
 101 #define CONFIG_CMD_DHCP
 102 #define CONFIG_CMD_I2C
 103 #define CONFIG_CMD_DATE
 104
 105
 106 /*
 107  * Miscellaneous configurable options
 108  */
 109 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 110 #define CONFIG_SYS_PROMPT       "=> "                   /* Monitor Command Prompt       */
 111 #define CONFIG_SYS_CBSIZE       256                             /* Console I/O Buffer Size      */
 112
 113 /* Print Buffer Size */
 114 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 115
 116 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 117 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 118 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
 119
 120
 121 /*-----------------------------------------------------------------------
 122  * PCI configuration
 123  *-----------------------------------------------------------------------
 124  */
 125 #define CONFIG_PCI                              /* include pci support          */
 126 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
 127 #undef CONFIG_PCI_PNP
 128 #define CONFIG_PCI_SCAN_SHOW
 129 #define CONFIG_EEPRO100
 130 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 131 #define CONFIG_EEPRO100_SROM_WRITE
 132
 133 #define PCI_ENET0_IOADDR        0xF0000000
 134 #define PCI_ENET0_MEMADDR       0xF0000000
 135
 136 #define PCI_FIREWIRE_IOADDR             0xF1000000
 137 #define PCI_FIREWIRE_MEMADDR    0xF1000000
 138 /*
 139 #define PCI_ENET0_IOADDR        0xFE000000
 140 #define PCI_ENET0_MEMADDR       0x80000000
 141
 142 #define PCI_FIREWIRE_IOADDR     0x81000000
 143 #define PCI_FIREWIRE_MEMADDR    0x81000000
 144 */
 145
 146 /*-----------------------------------------------------------------------
 147  * Start addresses for the final memory configuration
 148  * (Set up by the startup code)
 149  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 150  */
 151 #define CONFIG_SYS_SDRAM_BASE       0x00000000
 152 #define CONFIG_SYS_MAX_RAM_SIZE    0x10000000   /* 256MB  */
 153 /*#define CONFIG_SYS_VERY_BIG_RAM       1 */
 154
 155 /* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
 156  * is actually located at FFF00100.  Therefore, U-Boot is
 157  * physically located at 0xFFB0_0000, but is also mirrored at
 158  * 0xFFF0_0000.
 159  */
 160 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 161
 162 #define CONFIG_SYS_EUMB_ADDR        0xFC000000
 163
 164 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 165
 166 #define CONFIG_SYS_MONITOR_LEN      (256 << 10) /* Reserve 256 kB for Monitor   */
 167 #define CONFIG_SYS_MALLOC_LEN       (128 << 10) /* Reserve 128 kB for malloc()  */
 168
 169 /*#define CONFIG_SYS_DRAM_TEST          1 */
 170 #define CONFIG_SYS_MEMTEST_START   0x00003000   /* memtest works on     0...256 MB      */
 171 #define CONFIG_SYS_MEMTEST_END      0x0ff8ffa7  /* in SDRAM, skips exception */
 172                                                                                 /* vectors and U-Boot */
 173
 174
 175 /*--------------------------------------------------------------------
 176  * Definitions for initial stack pointer and data area
 177  *------------------------------------------------------------------*/
 178 #define CONFIG_SYS_INIT_DATA_SIZE    128        /* Size in bytes reserved for */
 179                                                                         /* initial data */
 180 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 181 #define CONFIG_SYS_INIT_RAM_SIZE      0x1000
 182 #define CONFIG_SYS_INIT_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 183 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 184
 185 /*--------------------------------------------------------------------
 186  * NS16550 Configuration
 187  *------------------------------------------------------------------*/
 188 #define CONFIG_SYS_NS16550
 189 #define CONFIG_SYS_NS16550_SERIAL
 190
 191 #define CONFIG_SYS_NS16550_REG_SIZE     1
 192
 193 #if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
 194 #       define CONFIG_SYS_NS16550_CLK           get_bus_freq(0)
 195 #else
 196 #       define CONFIG_SYS_NS16550_CLK 33000000
 197 #endif
 198
 199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
 201 #define CONFIG_SYS_NS16550_COM3 0xFF000000
 202 #define CONFIG_SYS_NS16550_COM4 0xFF000008
 203
 204 /*--------------------------------------------------------------------
 205  * Low Level Configuration Settings
 206  * (address mappings, register initial values, etc.)
 207  * You should know what you are doing if you make changes here.
 208  * For the detail description refer to the MPC8240 user's manual.
 209  *------------------------------------------------------------------*/
 210
 211 #define CONFIG_SYS_CLK_FREQ  33000000
 212 #define CONFIG_SYS_HZ                           1000
 213
 214 /*#define CONFIG_SYS_ETH_DEV_FN      0x7800 */
 215 /*#define CONFIG_SYS_ETH_IOBASE      0x00104000 */
 216
 217 /*--------------------------------------------------------------------
 218  * I2C Configuration
 219  *------------------------------------------------------------------*/
 220 #if 1
 221 #define CONFIG_HARD_I2C         1               /* To enable I2C support        */
 222 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 223 #define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address  */
 224 #define CONFIG_SYS_I2C_SLAVE            0x7F
 225 #endif
 226
 227 #define CONFIG_RTC_PCF8563      1               /* enable I2C support for */
 228                                                                         /* Philips PCF8563 RTC */
 229 #define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* Philips PCF8563 RTC address */
 230
 231 /*--------------------------------------------------------------------
 232  *      Memory Control Configuration Register values
 233  *      - see sec. 4.12 of MPC8245 UM
 234  *------------------------------------------------------------------*/
 235
 236 /**** MCCR1 ****/
 237 #define CONFIG_SYS_ROMNAL           0
 238 #define CONFIG_SYS_ROMFAL           10          /* (tacc=70ns)*mem_freq - 2,
 239                                                                         mem_freq = 100MHz */
 240
 241 #define CONFIG_SYS_BANK7_ROW    0               /* SDRAM bank 7-0 row address */
 242 #define CONFIG_SYS_BANK6_ROW    0               /*      bit count */
 243 #define CONFIG_SYS_BANK5_ROW    0
 244 #define CONFIG_SYS_BANK4_ROW    0
 245 #define CONFIG_SYS_BANK3_ROW    0
 246 #define CONFIG_SYS_BANK2_ROW    0
 247 #define CONFIG_SYS_BANK1_ROW    2
 248 #define CONFIG_SYS_BANK0_ROW    2
 249
 250 /**** MCCR2, refresh interval clock cycles ****/
 251 #define CONFIG_SYS_REFINT           480     /* 33 MHz SDRAM clock was 480 */
 252
 253 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
 254 #define CONFIG_SYS_BSTOPRE          1023        /* burst to precharge[0..9], */
 255                                                                 /* sets open page interval */
 256
 257 /**** MCCR3 ****/
 258 #define CONFIG_SYS_REFREC           7       /* Refresh to activate interval, trc */
 259
 260 /**** MCCR4 ****/
 261 #define CONFIG_SYS_PRETOACT         2       /* trp */
 262 #define CONFIG_SYS_ACTTOPRE         7       /* trcd + (burst length - 1) + trdl */
 263 #define CONFIG_SYS_SDMODE_CAS_LAT  3        /* SDMODE CAS latancy */
 264 #define CONFIG_SYS_SDMODE_WRAP      0       /* SDMODE wrap type, sequential */
 265 #define CONFIG_SYS_ACTORW               2               /* trcd min */
 266 #define CONFIG_SYS_DBUS_SIZE2           1               /* set for 8-bit RCS1, clear for 32,64 */
 267 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 268 #define CONFIG_SYS_EXTROM           0                   /* we don't need extended ROM space */
 269 #define CONFIG_SYS_REGDIMM          0
 270
 271 /* calculate according to formula in sec. 6-22 of 8245 UM */
 272 #define CONFIG_SYS_PGMAX           50           /* how long the 8245 retains the */
 273                                                                         /* currently accessed page in memory */
 274                                                                         /* was 45 */
 275
 276 #define CONFIG_SYS_SDRAM_DSCD   0x20    /* SDRAM data in sample clock delay - note */
 277                                                                 /* bits 7,6, and 3-0 MUST be 0 */
 278
 279 #if 0
 280 #define CONFIG_SYS_DLL_MAX_DELAY        0x04
 281 #else
 282 #define CONFIG_SYS_DLL_MAX_DELAY        0
 283 #endif
 284 #if 0                                                   /* need for 33MHz SDRAM */
 285 #define CONFIG_SYS_DLL_EXTEND   0x80
 286 #else
 287 #define CONFIG_SYS_DLL_EXTEND   0
 288 #endif
 289 #define CONFIG_SYS_PCI_HOLD_DEL 0x20
 290
 291
 292 /* Memory bank settings.
 293  * Only bits 20-29 are actually used from these values to set the
 294  * start/end addresses. The upper two bits will always be 0, and the lower
 295  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 296  * address. Refer to the MPC8245 user manual.
 297  */
 298
 299 #define CONFIG_SYS_BANK0_START      0x00000000
 300 #define CONFIG_SYS_BANK0_END        (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
 301 #define CONFIG_SYS_BANK0_ENABLE    1
 302 #define CONFIG_SYS_BANK1_START      CONFIG_SYS_MAX_RAM_SIZE/2
 303 #define CONFIG_SYS_BANK1_END        (CONFIG_SYS_MAX_RAM_SIZE - 1)
 304 #define CONFIG_SYS_BANK1_ENABLE    1
 305 #define CONFIG_SYS_BANK2_START      0x3ff00000          /* not available in this design */
 306 #define CONFIG_SYS_BANK2_END        0x3fffffff
 307 #define CONFIG_SYS_BANK2_ENABLE    0
 308 #define CONFIG_SYS_BANK3_START      0x3ff00000
 309 #define CONFIG_SYS_BANK3_END        0x3fffffff
 310 #define CONFIG_SYS_BANK3_ENABLE    0
 311 #define CONFIG_SYS_BANK4_START      0x3ff00000
 312 #define CONFIG_SYS_BANK4_END        0x3fffffff
 313 #define CONFIG_SYS_BANK4_ENABLE    0
 314 #define CONFIG_SYS_BANK5_START      0x3ff00000
 315 #define CONFIG_SYS_BANK5_END        0x3fffffff
 316 #define CONFIG_SYS_BANK5_ENABLE    0
 317 #define CONFIG_SYS_BANK6_START      0x3ff00000
 318 #define CONFIG_SYS_BANK6_END        0x3fffffff
 319 #define CONFIG_SYS_BANK6_ENABLE    0
 320 #define CONFIG_SYS_BANK7_START      0x3ff00000
 321 #define CONFIG_SYS_BANK7_END        0x3fffffff
 322 #define CONFIG_SYS_BANK7_ENABLE    0
 323
 324 /*--------------------------------------------------------------------*/
 325 /* 4.4 - Output Driver Control Register */
 326 /*--------------------------------------------------------------------*/
 327 #define CONFIG_SYS_ODCR     0xe5
 328
 329 /*--------------------------------------------------------------------*/
 330 /* 4.8 - Error Handling Registers */
 331 /*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
 332 #define CONFIG_SYS_ERRENR1      0x11    /* enable SDRAM refresh overflow error */
 333
 334 /* SDRAM 0-256 MB */
 335 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 336 /*#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
 337 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 338
 339 /* stack in dcache */
 340 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 341 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 342
 343
 344 #define CONFIG_SYS_IBAT2L  (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 345 #define CONFIG_SYS_IBAT2U  (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
 346
 347 /* PCI memory */
 348 /*#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
 349 /*#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
 350
 351 /*Flash, config addrs, etc. */
 352 #define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 353 #define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 354
 355 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 356 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 357 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 358 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 359 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 360 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 361 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 362 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 363
 364 /*
 365  * For booting Linux, the board info and command line data
 366  * have to be in the first 8 MB of memory, since this is
 367  * the maximum mapped by the Linux kernel during initialization.
 368  */
 369 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)   /* Initial Memory map for Linux */
 370
 371 /*-----------------------------------------------------------------------
 372  * FLASH organization
 373  *----------------------------------------------------------------------*/
 374 #define CONFIG_SYS_FLASH_BASE       0xFF800000
 375 #define CONFIG_SYS_MAX_FLASH_BANKS      1                       /* Max number of flash banks */
 376
 377 /*      NOTE: environment is not EMBEDDED in the u-boot code.
 378         It's stored in flash in its own separate sector.  */
 379 #define CONFIG_ENV_IS_IN_FLASH      1
 380
 381 #if 1   /* AMD AM29LV033C */
 382 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* Max number of sectors in one bank */
 383 #define CONFIG_ENV_ADDR         0xFFBF0000      /* flash sector SA63 */
 384 #define CONFIG_ENV_SECT_SIZE    (64*1024)       /* Size of the Environment Sector */
 385 #else   /* AMD AM29LV116D */
 386 #define CONFIG_SYS_MAX_FLASH_SECT       35      /* Max number of sectors in one bank */
 387 #define CONFIG_ENV_ADDR         0xFF9FA000      /* flash sector SA33 */
 388 #define CONFIG_ENV_SECT_SIZE    (8*1024)        /* Size of the Environment Sector */
 389 #endif /* #if */
 390
 391 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE            /* Size of the Environment */
 392 #define CONFIG_ENV_OFFSET               0                       /* starting right at the beginning */
 393
 394 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 395 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Timeout for Flash Write (in ms)      */
 396
 397 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 398 #undef CONFIG_SYS_RAMBOOT
 399 #else
 400 #define CONFIG_SYS_RAMBOOT
 401 #endif
 402
 403
 404 /*-----------------------------------------------------------------------
 405  * Cache Configuration
 406  */
 407 #define CONFIG_SYS_CACHELINE_SIZE       32
 408 #if defined(CONFIG_CMD_KGDB)
 409 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 410 #endif
 411
 412 #endif  /* __CONFIG_H */