include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef _MMC_H_
  27 #define _MMC_H_
  28
  29 #include <linux/list.h>
  30
  31 #define SD_VERSION_SD   0x20000
  32 #define SD_VERSION_2    (SD_VERSION_SD | 0x20)
  33 #define SD_VERSION_1_0  (SD_VERSION_SD | 0x10)
  34 #define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
  35 #define MMC_VERSION_MMC         0x10000
  36 #define MMC_VERSION_UNKNOWN     (MMC_VERSION_MMC)
  37 #define MMC_VERSION_1_2         (MMC_VERSION_MMC | 0x12)
  38 #define MMC_VERSION_1_4         (MMC_VERSION_MMC | 0x14)
  39 #define MMC_VERSION_2_2         (MMC_VERSION_MMC | 0x22)
  40 #define MMC_VERSION_3           (MMC_VERSION_MMC | 0x30)
  41 #define MMC_VERSION_4           (MMC_VERSION_MMC | 0x40)
  42
  43 #define MMC_MODE_HS             0x001
  44 #define MMC_MODE_HS_52MHz       0x010
  45 #define MMC_MODE_4BIT           0x100
  46 #define MMC_MODE_8BIT           0x200
  47 #define MMC_MODE_SPI            0x400
  48 #define MMC_MODE_HC             0x800
  49
  50 #define SD_DATA_4BIT    0x00040000
  51
  52 #define IS_SD(x) (x->version & SD_VERSION_SD)
  53
  54 #define MMC_DATA_READ           1
  55 #define MMC_DATA_WRITE          2
  56
  57 #define NO_CARD_ERR             -16 /* No SD/MMC card inserted */
  58 #define UNUSABLE_ERR            -17 /* Unusable Card */
  59 #define COMM_ERR                -18 /* Communications Error */
  60 #define TIMEOUT                 -19
  61
  62 #define MMC_CMD_GO_IDLE_STATE           0
  63 #define MMC_CMD_SEND_OP_COND            1
  64 #define MMC_CMD_ALL_SEND_CID            2
  65 #define MMC_CMD_SET_RELATIVE_ADDR       3
  66 #define MMC_CMD_SET_DSR                 4
  67 #define MMC_CMD_SWITCH                  6
  68 #define MMC_CMD_SELECT_CARD             7
  69 #define MMC_CMD_SEND_EXT_CSD            8
  70 #define MMC_CMD_SEND_CSD                9
  71 #define MMC_CMD_SEND_CID                10
  72 #define MMC_CMD_STOP_TRANSMISSION       12
  73 #define MMC_CMD_SEND_STATUS             13
  74 #define MMC_CMD_SET_BLOCKLEN            16
  75 #define MMC_CMD_READ_SINGLE_BLOCK       17
  76 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  77 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  78 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  79 #define MMC_CMD_ERASE_GROUP_START       35
  80 #define MMC_CMD_ERASE_GROUP_END         36
  81 #define MMC_CMD_ERASE                   38
  82 #define MMC_CMD_APP_CMD                 55
  83 #define MMC_CMD_SPI_READ_OCR            58
  84 #define MMC_CMD_SPI_CRC_ON_OFF          59
  85
  86 #define SD_CMD_SEND_RELATIVE_ADDR       3
  87 #define SD_CMD_SWITCH_FUNC              6
  88 #define SD_CMD_SEND_IF_COND             8
  89
  90 #define SD_CMD_APP_SET_BUS_WIDTH        6
  91 #define SD_CMD_ERASE_WR_BLK_START       32
  92 #define SD_CMD_ERASE_WR_BLK_END         33
  93 #define SD_CMD_APP_SEND_OP_COND         41
  94 #define SD_CMD_APP_SEND_SCR             51
  95
  96 /* SCR definitions in different words */
  97 #define SD_HIGHSPEED_BUSY       0x00020000
  98 #define SD_HIGHSPEED_SUPPORTED  0x00020000
  99
 100 #define MMC_HS_TIMING           0x00000100
 101 #define MMC_HS_52MHZ            0x2
 102
 103 #define OCR_BUSY                0x80000000
 104 #define OCR_HCS                 0x40000000
 105 #define OCR_VOLTAGE_MASK        0x007FFF80
 106 #define OCR_ACCESS_MODE         0x60000000
 107
 108 #define SECURE_ERASE            0x80000000
 109
 110 #define MMC_STATUS_MASK         (~0x0206BF7F)
 111 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 112 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 113 #define MMC_STATUS_ERROR        (1 << 19)
 114
 115 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 116 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 117 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 118 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 119 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 120 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 121 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 122 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 123 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 124 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 125 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 126 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 127 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 128 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 129 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 130 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 131 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 132
 133 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 134 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 135                                                 addressed by index which are
 136                                                 1 in value field */
 137 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 138                                                 addressed by index, which are
 139                                                 1 in value field */
 140 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 141
 142 #define SD_SWITCH_CHECK         0
 143 #define SD_SWITCH_SWITCH        1
 144
 145 /*
 146  * EXT_CSD fields
 147  */
 148
 149 #define EXT_CSD_PART_CONF       179     /* R/W */
 150 #define EXT_CSD_BUS_WIDTH       183     /* R/W */
 151 #define EXT_CSD_HS_TIMING       185     /* R/W */
 152 #define EXT_CSD_CARD_TYPE       196     /* RO */
 153 #define EXT_CSD_REV             192     /* RO */
 154 #define EXT_CSD_SEC_CNT         212     /* RO, 4 bytes */
 155
 156 /*
 157  * EXT_CSD field definitions
 158  */
 159
 160 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 161 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 162 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 163
 164 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 165 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 166
 167 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 168 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 169 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 170
 171 #define R1_ILLEGAL_COMMAND              (1 << 22)
 172 #define R1_APP_CMD                      (1 << 5)
 173
 174 #define MMC_RSP_PRESENT (1 << 0)
 175 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 176 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 177 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 178 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 179
 180 #define MMC_RSP_NONE    (0)
 181 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 182 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 183                         MMC_RSP_BUSY)
 184 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 185 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 186 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 187 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 188 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 189 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 190
 191 #define MMCPART_NOAVAILABLE     (0xff)
 192 #define PART_ACCESS_MASK        (0x7)
 193 #define PART_SUPPORT            (0x1)
 194
 195 struct mmc_cid {
 196         unsigned long psn;
 197         unsigned short oid;
 198         unsigned char mid;
 199         unsigned char prv;
 200         unsigned char mdt;
 201         char pnm[7];
 202 };
 203
 204 /*
 205  * WARNING!
 206  *
 207  * This structure is used by atmel_mci.c only.
 208  * It works for the AVR32 architecture but NOT
 209  * for ARM/AT91 architectures.
 210  * Its use is highly depreciated.
 211  * After the atmel_mci.c driver for AVR32 has
 212  * been replaced this structure will be removed.
 213  */
 214 struct mmc_csd
 215 {
 216         u8      csd_structure:2,
 217                 spec_vers:4,
 218                 rsvd1:2;
 219         u8      taac;
 220         u8      nsac;
 221         u8      tran_speed;
 222         u16     ccc:12,
 223                 read_bl_len:4;
 224         u64     read_bl_partial:1,
 225                 write_blk_misalign:1,
 226                 read_blk_misalign:1,
 227                 dsr_imp:1,
 228                 rsvd2:2,
 229                 c_size:12,
 230                 vdd_r_curr_min:3,
 231                 vdd_r_curr_max:3,
 232                 vdd_w_curr_min:3,
 233                 vdd_w_curr_max:3,
 234                 c_size_mult:3,
 235                 sector_size:5,
 236                 erase_grp_size:5,
 237                 wp_grp_size:5,
 238                 wp_grp_enable:1,
 239                 default_ecc:2,
 240                 r2w_factor:3,
 241                 write_bl_len:4,
 242                 write_bl_partial:1,
 243                 rsvd3:5;
 244         u8      file_format_grp:1,
 245                 copy:1,
 246                 perm_write_protect:1,
 247                 tmp_write_protect:1,
 248                 file_format:2,
 249                 ecc:2;
 250         u8      crc:7;
 251         u8      one:1;
 252 };
 253
 254 struct mmc_cmd {
 255         ushort cmdidx;
 256         uint resp_type;
 257         uint cmdarg;
 258         uint response[4];
 259         uint flags;
 260 };
 261
 262 struct mmc_data {
 263         union {
 264                 char *dest;
 265                 const char *src; /* src buffers don't get written to */
 266         };
 267         uint flags;
 268         uint blocks;
 269         uint blocksize;
 270 };
 271
 272 struct mmc {
 273         struct list_head link;
 274         char name[32];
 275         void *priv;
 276         uint voltages;
 277         uint version;
 278         uint has_init;
 279         uint f_min;
 280         uint f_max;
 281         int high_capacity;
 282         uint bus_width;
 283         uint clock;
 284         uint card_caps;
 285         uint host_caps;
 286         uint ocr;
 287         uint scr[2];
 288         uint csd[4];
 289         uint cid[4];
 290         ushort rca;
 291         char part_config;
 292         char part_num;
 293         uint tran_speed;
 294         uint read_bl_len;
 295         uint write_bl_len;
 296         uint erase_grp_size;
 297         u64 capacity;
 298         block_dev_desc_t block_dev;
 299         int (*send_cmd)(struct mmc *mmc,
 300                         struct mmc_cmd *cmd, struct mmc_data *data);
 301         void (*set_ios)(struct mmc *mmc);
 302         int (*init)(struct mmc *mmc);
 303         uint b_max;
 304 };
 305
 306 int mmc_register(struct mmc *mmc);
 307 int mmc_initialize(bd_t *bis);
 308 int mmc_init(struct mmc *mmc);
 309 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 310 void mmc_set_clock(struct mmc *mmc, uint clock);
 311 struct mmc *find_mmc_device(int dev_num);
 312 int mmc_set_dev(int dev_num);
 313 void print_mmc_devices(char separator);
 314 int get_mmc_num(void);
 315 int board_mmc_getcd(u8 *cd, struct mmc *mmc);
 316 int mmc_switch_part(int dev_num, unsigned int part_num);
 317
 318 #ifdef CONFIG_GENERIC_MMC
 319 int atmel_mci_init(void *regs);
 320 #define mmc_host_is_spi(mmc)    ((mmc)->host_caps & MMC_MODE_SPI)
 321 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 322 #else
 323 int mmc_legacy_init(int verbose);
 324 #endif
 325
 326 #endif /* _MMC_H_ */