the hosted environment to call out to the emulator to
retrieve files from the host machine.
+config SYS_L2CACHE_OFF
+ bool "L2cache off"
+ help
+ If SoC does not support L2CACHE or one do not want to enable
+ L2CACHE, choose this option.
+
choice
prompt "Target select"
default ARCH_VERSATILE
bool "Support vision2"
select CPU_V7
-config TARGET_UDOO
- bool "Support udoo"
- select CPU_V7
-
-config TARGET_WANDBOARD
- bool "Support wandboard"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_WARP
- bool "Support WaRP"
- select CPU_V7
-
-config TARGET_TITANIUM
- bool "Support titanium"
- select CPU_V7
-
-config TARGET_NITROGEN6X
- bool "Support nitrogen6x"
- select CPU_V7
-
-config TARGET_CGTQMX6EVAL
- bool "Support cgtqmx6eval"
- select CPU_V7
-
-config TARGET_EMBESTMX6BOARDS
- bool "Support embestmx6boards"
- select CPU_V7
-
-config TARGET_ARISTAINETOS
- bool "Support aristainetos"
- select CPU_V7
-
-config TARGET_ARISTAINETOS2
- bool "Support aristainetos2"
- select CPU_V7
-
-config TARGET_MX6QARM2
- bool "Support mx6qarm2"
- select CPU_V7
-
-config TARGET_MX6QSABREAUTO
- bool "Support mx6qsabreauto"
- select CPU_V7
- select DM
- select DM_THERMAL
-
-config TARGET_MX6SABRESD
- bool "Support mx6sabresd"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_THERMAL
-
-config TARGET_MX6CUBOXI
- bool "Support Solid-run mx6 boards"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_MX6SLEVK
- bool "Support mx6slevk"
- select CPU_V7
-
-config TARGET_MX6SXSABRESD
- bool "Support mx6sxsabresd"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_THERMAL
-
-config TARGET_MX6UL_14X14_EVK
- bool "Support mx6ul_14x14_evk"
- select CPU_V7
- select DM
- select DM_THERMAL
- select SUPPORT_SPL
-
-config TARGET_GW_VENTANA
- bool "Support gw_ventana"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_KOSAGI_NOVENA
- bool "Support Kosagi Novena"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_TBS2910
- bool "Support tbs2910"
- select CPU_V7
-
-config TARGET_OT1200
- bool "Bachmann OT1200"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_PLATINUM_PICON
- bool "Support platinum-picon"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_PLATINUM_TITANIUM
- bool "Support platinum-titanium"
- select CPU_V7
- select SUPPORT_SPL
-
config OMAP34XX
bool "OMAP34XX SoC"
select CPU_V7
bool "Support snowball"
select CPU_V7
+config TARGET_TS4800
+ bool "Support TS4800"
+ select CPU_V7
+
config TARGET_U8500_HREF
bool "Support u8500_href"
select CPU_V7
source "arch/arm/imx-common/Kconfig"
-source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
-source "board/hisilicon/hikey/Kconfig"
-source "board/bachmann/ot1200/Kconfig"
source "board/balloon3/Kconfig"
-source "board/barco/platinum/Kconfig"
-source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
-source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
-source "board/compulab/cm_t43/Kconfig"
-source "board/compulab/cm_fx6/Kconfig"
-source "board/congatec/cgtqmx6eval/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
-source "board/embest/mx6boards/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
-source "board/freescale/mx6qarm2/Kconfig"
-source "board/freescale/mx6qsabreauto/Kconfig"
-source "board/freescale/mx6sabresd/Kconfig"
-source "board/freescale/mx6slevk/Kconfig"
-source "board/freescale/mx6sxsabresd/Kconfig"
-source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/vf610twr/Kconfig"
-source "board/gateworks/gw_ventana/Kconfig"
source "board/genesi/mx51_efikamx/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
-source "board/kosagi/novena/Kconfig"
source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
source "board/silica/pengwyn/Kconfig"
-source "board/solidrun/mx6cuboxi/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/zmx25/Kconfig"
-source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
source "board/trizepsiv/Kconfig"
+source "board/technologic/ts4800/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
-source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
-source "board/wandboard/Kconfig"
-source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
source "board/xaeniax/Kconfig"
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev)
- return mx31_cpu_type[i].v;
+ return mx31_cpu_type[i].v | (MXC_CPU_MX31 << 12);
return srev | 0x8000;
}
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
+#include <asm/imx-common/sys_proto.h>
#ifdef CONFIG_MXC_MMC
#include <asm/arch/mxcmmc.h>
#endif
}
+u32 get_cpu_rev(void)
+{
+ return MXC_CPU_MX27 << 12;
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
%.sig: %.csf
$(call if_changed,mkcst_mxs)
-quiet_cmd_mkimage_mxs = MKIMAGE $@
-cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
+MKIMAGEFLAGS_u-boot.sb = -n $< -T mxsimage
u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
- $(call if_changed,mkimage_mxs)
+ $(call if_changed,mkimage)
+MKIMAGEFLAGS_u-boot-signed.sb = -n $< -T mxsimage
u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE
- $(call if_changed,mkimage_mxs)
+ $(call if_changed,mkimage)
return 0;
}
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static const char *get_cpu_type(void)
-{
- struct mxs_digctl_regs *digctl_regs =
- (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
-
- switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
- case HW_DIGCTL_CHIPID_MX23:
- return "23";
- case HW_DIGCTL_CHIPID_MX28:
- return "28";
- default:
- return "??";
- }
-}
-
-static const char *get_cpu_rev(void)
+u32 get_cpu_rev(void)
{
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
case HW_DIGCTL_CHIPID_MX23:
switch (rev) {
case 0x0:
- return "1.0";
case 0x1:
- return "1.1";
case 0x2:
- return "1.2";
case 0x3:
- return "1.3";
case 0x4:
- return "1.4";
+ return (MXC_CPU_MX23 << 12) | (rev + 0x10);
default:
- return "??";
+ return 0;
}
case HW_DIGCTL_CHIPID_MX28:
switch (rev) {
case 0x1:
- return "1.2";
+ return (MXC_CPU_MX28 << 12) | 0x12;
default:
- return "??";
+ return 0;
}
+ default:
+ return 0;
+ }
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+const char *get_imx_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case MXC_CPU_MX23:
+ return "23"; /* Quad-Plus version of the mx6 */
+ case MXC_CPU_MX28:
+ return "28"; /* Dual-Plus version of the mx6 */
default:
return "??";
}
int print_cpuinfo(void)
{
+ u32 cpurev;
struct mxs_spl_data *data = (struct mxs_spl_data *)
((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
- printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
- get_cpu_type(),
- get_cpu_rev(),
+ cpurev = get_cpu_rev();
+ printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
+ get_imx_type((cpurev & 0xFF000) >> 12),
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
return 0;
prompt "MX6 board select"
optional
+config TARGET_ARISTAINETOS
+ bool "aristainetos"
+ select CPU_V7
+
+config TARGET_ARISTAINETOS2
+ bool "aristainetos2"
+ select CPU_V7
+
+config TARGET_ARISTAINETOS2B
+ bool "Support aristainetos2-revB"
+ select CPU_V7
+
+config TARGET_CGTQMX6EVAL
+ bool "cgtqmx6eval"
+ select CPU_V7
+
config TARGET_CM_FX6
- bool "Support CM-FX6"
+ bool "CM-FX6"
select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_GPIO
+config TARGET_EMBESTMX6BOARDS
+ bool "embestmx6boards"
+ select CPU_V7
+
+config TARGET_GW_VENTANA
+ bool "gw_ventana"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_KOSAGI_NOVENA
+ bool "Kosagi Novena"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_MX6CUBOXI
+ bool "Solid-run mx6 boards"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_MX6QARM2
+ bool "mx6qarm2"
+ select CPU_V7
+
+config TARGET_MX6QSABREAUTO
+ bool "mx6qsabreauto"
+ select CPU_V7
+ select DM
+ select DM_THERMAL
+
+config TARGET_MX6SABRESD
+ bool "mx6sabresd"
+ select CPU_V7
+ select SUPPORT_SPL
+ select DM
+ select DM_THERMAL
+
+config TARGET_MX6SLEVK
+ bool "mx6slevk"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_MX6SXSABRESD
+ bool "mx6sxsabresd"
+ select CPU_V7
+ select SUPPORT_SPL
+ select DM
+ select DM_THERMAL
+
+config TARGET_MX6UL_14X14_EVK
+ bool "mx6ul_14x14_evk"
+ select MX6UL
+ select CPU_V7
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config TARGET_NITROGEN6X
+ bool "nitrogen6x"
+ select CPU_V7
+
+config TARGET_OT1200
+ bool "Bachmann OT1200"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_PLATINUM_PICON
+ bool "platinum-picon"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_PLATINUM_TITANIUM
+ bool "platinum-titanium"
+ select CPU_V7
+ select SUPPORT_SPL
+
config TARGET_SECOMX6
- bool "Support secomx6 boards"
+ bool "secomx6 boards"
+
+config TARGET_TBS2910
+ bool "TBS2910 Matrix ARM mini PC"
+ select CPU_V7
+
+config TARGET_TITANIUM
+ bool "titanium"
+ select CPU_V7
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
+config TARGET_UDOO
+ bool "udoo"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_WANDBOARD
+ bool "wandboard"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_WARP
+ bool "WaRP"
+ select CPU_V7
+
endchoice
config SYS_SOC
default "mx6"
+source "board/aristainetos/Kconfig"
+source "board/bachmann/ot1200/Kconfig"
+source "board/barco/platinum/Kconfig"
+source "board/barco/titanium/Kconfig"
+source "board/boundary/nitrogen6x/Kconfig"
+source "board/compulab/cm_fx6/Kconfig"
+source "board/congatec/cgtqmx6eval/Kconfig"
+source "board/embest/mx6boards/Kconfig"
+source "board/freescale/mx6qarm2/Kconfig"
+source "board/freescale/mx6qsabreauto/Kconfig"
+source "board/freescale/mx6sabresd/Kconfig"
+source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sxsabresd/Kconfig"
+source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/gateworks/gw_ventana/Kconfig"
+source "board/kosagi/novena/Kconfig"
source "board/seco/Kconfig"
+source "board/solidrun/mx6cuboxi/Kconfig"
+source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig"
+source "board/udoo/Kconfig"
+source "board/wandboard/Kconfig"
+source "board/warp/Kconfig"
endif
#endif
#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(enum enet_freq freq)
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
- reg = readl(&anatop->pll_enet);
- reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
- reg |= freq;
+ if (fec_id == 0) {
+ reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+ } else if (fec_id == 1) {
+ /* Only i.MX6SX/UL support ENET2 */
+ if (!(is_cpu_type(MXC_CPU_MX6SX) ||
+ is_cpu_type(MXC_CPU_MX6UL)))
+ return -EINVAL;
+ reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+ } else {
+ return -EINVAL;
+ }
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
}
/* Enable FEC clock */
- reg |= BM_ANADIG_PLL_ENET_ENABLE;
+ if (fec_id == 0)
+ reg |= BM_ANADIG_PLL_ENET_ENABLE;
+ else
+ reg |= BM_ANADIG_PLL_ENET2_ENABLE;
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
writel(reg, &anatop->pll_enet);
#include <common.h>
#include <linux/types.h>
+#include <asm/arch/clock.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
}
#endif
+#if defined(CONFIG_MX6SL)
+void mx6sl_dram_iocfg(unsigned width,
+ const struct mx6sl_iomux_ddr_regs *ddr,
+ const struct mx6sl_iomux_grp_regs *grp)
+{
+ struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+ mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+ /* CLOCK */
+ mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+
+ /* ADDRESS */
+ mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+ mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+ mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+ mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+ mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+ mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+ mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+ mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+ }
+
+ /* Data */
+ mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+ mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+ mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+ if (width >= 32) {
+ mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+ mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+ }
+
+ mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+ mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+ mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+ }
+}
+#endif
+
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
/* Configure MX6DQ mmdc iomux */
void mx6dq_dram_iocfg(unsigned width,
* Configure mx6 mmdc registers based on:
* - board-specific memory configuration
* - board-specific calibration data
- * - ddr3 chip details
+ * - ddr3/lpddr2 chip details
*
* The various calculations here are derived from the Freescale
- * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
- * configuration registers based on memory system and memory chip parameters.
+ * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
+ * MMDC configuration registers based on memory system and memory chip
+ * parameters.
+ *
+ * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
+ * configuration registers based on memory system and memory chip
+ * parameters.
*
* The defaults here are those which were specified in the spreadsheet.
* For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
- * section titled MMDC initialization
+ * and/or IMX6SLRM section titled MMDC initialization.
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
- if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
+ if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
+ !is_cpu_type(MXC_CPU_MX6SL)) \
mmdc1->entry = value; \
} while (0)
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+/*
+ * According JESD209-2B-LPDDR2: Table 103
+ * WL: write latency
+ */
+static int lpddr2_wl(uint32_t mem_speed)
+{
+ switch (mem_speed) {
+ case 1066:
+ case 933:
+ return 4;
+ case 800:
+ return 3;
+ case 677:
+ case 533:
+ return 2;
+ case 400:
+ case 333:
+ return 1;
+ default:
+ puts("invalid memory speed\n");
+ hang();
+ }
+
+ return 0;
+}
+
+/*
+ * According JESD209-2B-LPDDR2: Table 103
+ * RL: read latency
+ */
+static int lpddr2_rl(uint32_t mem_speed)
+{
+ switch (mem_speed) {
+ case 1066:
+ return 8;
+ case 933:
+ return 7;
+ case 800:
+ return 6;
+ case 677:
+ return 5;
+ case 533:
+ return 4;
+ case 400:
+ case 333:
+ return 3;
+ default:
+ puts("invalid memory speed\n");
+ hang();
+ }
+
+ return 0;
+}
+
+void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+ const struct mx6_mmdc_calibration *calib,
+ const struct mx6_lpddr2_cfg *lpddr2_cfg)
+{
+ volatile struct mmdc_p_regs *mmdc0;
+ u32 val;
+ u8 tcke, tcksrx, tcksre, trrd;
+ u8 twl, txp, tfaw, tcl;
+ u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
+ u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
+ u16 cs0_end;
+ u8 coladdr;
+ int clkper; /* clock period in picoseconds */
+ int clock; /* clock freq in mHz */
+ int cs;
+
+ /* only support 16/32 bits */
+ if (sysinfo->dsize > 1)
+ hang();
+
+ mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+
+ clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
+ clkper = (1000 * 1000) / clock; /* pico seconds */
+
+ twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
+
+ /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
+ switch (lpddr2_cfg->density) {
+ case 1:
+ case 2:
+ case 4:
+ trfc = DIV_ROUND_UP(130000, clkper) - 1;
+ txsr = DIV_ROUND_UP(140000, clkper) - 1;
+ break;
+ case 8:
+ trfc = DIV_ROUND_UP(210000, clkper) - 1;
+ txsr = DIV_ROUND_UP(220000, clkper) - 1;
+ break;
+ default:
+ /*
+ * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
+ */
+ hang();
+ break;
+ }
+ /*
+ * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
+ * set them to 0. */
+ txp = DIV_ROUND_UP(7500, clkper) - 1;
+ tcke = 3;
+ if (lpddr2_cfg->mem_speed == 333)
+ tfaw = DIV_ROUND_UP(60000, clkper) - 1;
+ else
+ tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+ trrd = DIV_ROUND_UP(10000, clkper) - 1;
+
+ /* tckesr for LPDDR2 */
+ tcksre = DIV_ROUND_UP(15000, clkper);
+ tcksrx = tcksre;
+ twr = DIV_ROUND_UP(15000, clkper) - 1;
+ /*
+ * tMRR: 2, tMRW: 5
+ * tMRD should be set to max(tMRR, tMRW)
+ */
+ tmrd = 5;
+ tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
+ /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
+ trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
+ trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
+ clkper / 10) - 1;
+ trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
+ trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
+ /* To LPDDR2, CL in MDCFG0 refers to RL */
+ tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
+ twtr = DIV_ROUND_UP(7500, clkper) - 1;
+ trtp = DIV_ROUND_UP(7500, clkper) - 1;
+
+ cs0_end = 4 * sysinfo->cs_density - 1;
+
+ debug("density:%d Gb (%d Gb per chip)\n",
+ sysinfo->cs_density, lpddr2_cfg->density);
+ debug("clock: %dMHz (%d ps)\n", clock, clkper);
+ debug("memspd:%d\n", lpddr2_cfg->mem_speed);
+ debug("trcd_lp=%d\n", trcd_lp);
+ debug("trppb_lp=%d\n", trppb_lp);
+ debug("trpab_lp=%d\n", trpab_lp);
+ debug("trc_lp=%d\n", trc_lp);
+ debug("tcke=%d\n", tcke);
+ debug("tcksrx=%d\n", tcksrx);
+ debug("tcksre=%d\n", tcksre);
+ debug("trfc=%d\n", trfc);
+ debug("txsr=%d\n", txsr);
+ debug("txp=%d\n", txp);
+ debug("tfaw=%d\n", tfaw);
+ debug("tcl=%d\n", tcl);
+ debug("tras=%d\n", tras);
+ debug("twr=%d\n", twr);
+ debug("tmrd=%d\n", tmrd);
+ debug("twl=%d\n", twl);
+ debug("trtp=%d\n", trtp);
+ debug("twtr=%d\n", twtr);
+ debug("trrd=%d\n", trrd);
+ debug("cs0_end=%d\n", cs0_end);
+ debug("ncs=%d\n", sysinfo->ncs);
+
+ /*
+ * board-specific configuration:
+ * These values are determined empirically and vary per board layout
+ */
+ mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
+ mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
+ mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
+ mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
+ mmdc0->mprddlctl = calib->p0_mprddlctl;
+ mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
+ mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
+
+ /* Read data DQ Byte0-3 delay */
+ mmdc0->mprddqby0dl = 0x33333333;
+ mmdc0->mprddqby1dl = 0x33333333;
+ if (sysinfo->dsize > 0) {
+ mmdc0->mprddqby2dl = 0x33333333;
+ mmdc0->mprddqby3dl = 0x33333333;
+ }
+
+ /* Write data DQ Byte0-3 delay */
+ mmdc0->mpwrdqby0dl = 0xf3333333;
+ mmdc0->mpwrdqby1dl = 0xf3333333;
+ if (sysinfo->dsize > 0) {
+ mmdc0->mpwrdqby2dl = 0xf3333333;
+ mmdc0->mpwrdqby3dl = 0xf3333333;
+ }
+
+ /*
+ * In LPDDR2 mode this register should be cleared,
+ * so no termination will be activated.
+ */
+ mmdc0->mpodtctrl = 0;
+
+ /* complete calibration */
+ val = (1 << 11); /* Force measurement on delay-lines */
+ mmdc0->mpmur0 = val;
+
+ /* Step 1: configuration request */
+ mmdc0->mdscr = (u32)(1 << 15); /* config request */
+
+ /* Step 2: Timing configuration */
+ mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
+ (tfaw << 4) | tcl;
+ mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
+ mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
+ mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
+ (trppb_lp << 4) | trpab_lp;
+ mmdc0->mdotc = 0;
+
+ mmdc0->mdasp = cs0_end; /* CS addressing */
+
+ /* Step 3: Configure DDR type */
+ mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
+ (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
+ (sysinfo->ralat << 6) | (1 << 3);
+
+ /* Step 4: Configure delay while leaving reset */
+ mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
+ (sysinfo->rst_to_cke << 0);
+
+ /* Step 5: Configure DDR physical parameters (density and burst len) */
+ coladdr = lpddr2_cfg->coladdr;
+ if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
+ coladdr += 4;
+ else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
+ coladdr += 1;
+ mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
+ (coladdr - 9) << 20 | /* COL */
+ (0 << 19) | /* Burst Length = 4 for LPDDR2 */
+ (sysinfo->dsize << 16); /* DDR data bus size */
+
+ /* Step 6: Perform ZQ calibration */
+ val = 0xa1390003; /* one-time HW ZQ calib */
+ mmdc0->mpzqhwctrl = val;
+
+ /* Step 7: Enable MMDC with desired chip select */
+ mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
+ ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
+
+ /* Step 8: Write Mode Registers to Init LPDDR2 devices */
+ for (cs = 0; cs < sysinfo->ncs; cs++) {
+ /* MR63: reset */
+ mmdc0->mdscr = MR(63, 0, 3, cs);
+ /* MR10: calibration,
+ * 0xff is calibration command after intilization.
+ */
+ val = 0xA | (0xff << 8);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ /* MR1 */
+ val = 0x1 | (0x82 << 8);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ /* MR2 */
+ val = 0x2 | (0x04 << 8);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ /* MR3 */
+ val = 0x3 | (0x02 << 8);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ }
+
+ /* Step 10: Power down control and self-refresh */
+ mmdc0->mdpdc = (tcke & 0x7) << 16 |
+ 5 << 12 | /* PWDT_1: 256 cycles */
+ 5 << 8 | /* PWDT_0: 256 cycles */
+ 1 << 6 | /* BOTH_CS_PD */
+ (tcksrx & 0x7) << 3 |
+ (tcksre & 0x7);
+ mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
+
+ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
+ val = 0xa1310003;
+ mmdc0->mpzqhwctrl = val;
+
+ /* Step 12: Configure and activate periodic refresh */
+ mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
+ (3 << 11); /* REFR: Refresh Rate - 4 refreshes */
+
+ /* Step 13: Deassert config request - init complete */
+ mmdc0->mdscr = 0x00000000;
+
+ /* wait for auto-ZQ calibration to complete */
+ mdelay(1);
+}
+
+void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *ddr3_cfg)
{
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
+ if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
+ !is_cpu_type(MXC_CPU_MX6SL))
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */
txs = DIV_ROUND_UP(170000, clkper) - 1;
break;
case 4: /* 4Gb per chip */
- trfc = DIV_ROUND_UP(260000, clkper) - 1;
- txs = DIV_ROUND_UP(270000, clkper) - 1;
+ trfc = DIV_ROUND_UP(300000, clkper) - 1;
+ txs = DIV_ROUND_UP(310000, clkper) - 1;
break;
case 8: /* 8Gb per chip */
trfc = DIV_ROUND_UP(350000, clkper) - 1;
/* wait for auto-ZQ calibration to complete */
mdelay(1);
}
+
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+ const struct mx6_mmdc_calibration *calib,
+ const void *ddr_cfg)
+{
+ if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
+ mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
+ } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
+ mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
+ } else {
+ puts("Unsupported ddr type\n");
+ hang();
+ }
+}
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
+#include <asm/imx-common/sys_proto.h>
#include <netdev.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
}
#endif
+u32 get_cpu_rev(void)
+{
+ return MXC_CPU_VF610 << 12;
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
-void set_pgtable_section(u64 *page_table, u64 index, u64 section,
- u64 memory_type)
+inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+ u64 memory_type, u64 share)
{
u64 value;
value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
+ value |= share;
+ page_table[index] = value;
+}
+
+inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
+{
+ u64 value;
+
+ value = (u64)table_addr | PMD_TYPE_TABLE;
page_table[index] = value;
}
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
set_pgtable_section(page_table, i, i << SECTION_SHIFT,
- MT_DEVICE_NGNRNE);
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
}
/* Setup an identity-mapping for all RAM space */
for (j = start >> SECTION_SHIFT;
j < end >> SECTION_SHIFT; j++) {
set_pgtable_section(page_table, j, j << SECTION_SHIFT,
- MT_NORMAL);
+ MT_NORMAL, PMD_SECT_NON_SHARE);
}
}
Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
to match board NAND device with 4KB/page, block size 512KB.
+
+MMU Translation Tables
+======================
+
+(1) Early MMU Tables:
+
+ Level 0 Level 1 Level 2
+------------------ ------------------ ------------------
+| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
+------------------ ------------------ ------------------
+| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
+------------------ | ------------------ ------------------
+| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
+------------------ | ------------------ ------------------
+ | | 0x00_c000_0000 | | 0x00_0060_0000 |
+ | ------------------ ------------------
+ | | 0x01_0000_0000 | | 0x00_0080_0000 |
+ | ------------------ ------------------
+ | ... ...
+ | ------------------
+ | | 0x05_8000_0000 | --|
+ | ------------------ |
+ | | 0x05_c000_0000 | |
+ | ------------------ |
+ | ... |
+ | ------------------ | ------------------
+ |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 |
+ ------------------ ------------------
+ | 0x80_4000_0000 | | 0x00_3020_0000 |
+ ------------------ ------------------
+ | 0x80_8000_0000 | | 0x00_3040_0000 |
+ ------------------ ------------------
+ | 0x80_c000_0000 | | 0x00_3060_0000 |
+ ------------------ ------------------
+ | 0x81_0000_0000 | | 0x00_3080_0000 |
+ ------------------ ------------------
+ ... ...
+
+(2) Final MMU Tables:
+
+ Level 0 Level 1 Level 2
+------------------ ------------------ ------------------
+| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
+------------------ ------------------ ------------------
+| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
+------------------ | ------------------ ------------------
+| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
+------------------ | ------------------ ------------------
+ | | 0x00_c000_0000 | | 0x00_0060_0000 |
+ | ------------------ ------------------
+ | | 0x01_0000_0000 | | 0x00_0080_0000 |
+ | ------------------ ------------------
+ | ... ...
+ | ------------------
+ | | 0x08_0000_0000 | --|
+ | ------------------ |
+ | | 0x08_4000_0000 | |
+ | ------------------ |
+ | ... |
+ | ------------------ | ------------------
+ |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 |
+ ------------------ ------------------
+ | 0x80_4000_0000 | | 0x08_0020_0000 |
+ ------------------ ------------------
+ | 0x80_8000_0000 | | 0x08_0040_0000 |
+ ------------------ ------------------
+ | 0x80_c000_0000 | | 0x08_0060_0000 |
+ ------------------ ------------------
+ | 0x81_0000_0000 | | 0x08_0080_0000 |
+ ------------------ ------------------
+ ... ...
#include <common.h>
#include <asm/io.h>
+#include <asm/errno.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
}
#ifndef CONFIG_SYS_DCACHE_OFF
-/*
- * To start MMU before DDR is available, we create MMU table in SRAM.
- * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
- * levels of translation tables here to cover 40-bit address space.
- * We use 4KB granule size, with 40 bits physical address, T0SZ=24
- * Level 0 IA[39], table address @0
- * Level 1 IA[31:30], table address @0x1000, 0x2000
- * Level 2 IA[29:21], table address @0x3000, 0x4000
- * Address above 0x5000 is free for other purpose.
- */
-#define SECTION_SHIFT_L0 39UL
-#define SECTION_SHIFT_L1 30UL
-#define SECTION_SHIFT_L2 21UL
-#define BLOCK_SIZE_L0 0x8000000000UL
-#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
-#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
-#define CONFIG_SYS_IFC_BASE 0x30000000
-#define CONFIG_SYS_IFC_SIZE 0x10000000
-#define CONFIG_SYS_IFC_BASE2 0x500000000
-#define CONFIG_SYS_IFC_SIZE2 0x100000000
+#define SECTION_SHIFT_L0 39UL
+#define SECTION_SHIFT_L1 30UL
+#define SECTION_SHIFT_L2 21UL
+#define BLOCK_SIZE_L0 0x8000000000
+#define BLOCK_SIZE_L1 0x40000000
+#define BLOCK_SIZE_L2 0x200000
+
+#define NUM_OF_ENTRY 512
+
#define TCR_EL2_PS_40BIT (2 << 16)
#define LSCH3_VA_BITS (40)
#define LSCH3_TCR (TCR_TG0_4K | \
TCR_IRGN_WBWA | \
TCR_T0SZ(LSCH3_VA_BITS))
+#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
+#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
+#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
+#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
+#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
+#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
+#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
+#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
+#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
+#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
+#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
+#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
+#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
+#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
+#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
+#define CONFIG_SYS_FSL_NI_BASE 0x810000000
+#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
+#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
+#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
+#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
+#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
+#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
+#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
+#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
+#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
+
+struct sys_mmu_table {
+ u64 virt_addr;
+ u64 phys_addr;
+ u64 size;
+ u64 memory_type;
+ u64 share;
+};
+
+static const struct sys_mmu_table lsch3_early_mmu_table[] = {
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ /* For IFC Region #1, only the first 4MB is cache-enabled */
+ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+};
+
+static const struct sys_mmu_table lsch3_final_mmu_table[] = {
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+ CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+ CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+ CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ /* For QBMAN portal, only the first 64MB is cache-enabled */
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+ CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#ifdef CONFIG_LS2085A
+ { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
+ CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#endif
+ { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+ CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+ CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+ CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+};
+
+struct table_info {
+ u64 *ptr;
+ u64 table_base;
+ u64 entry_size;
+};
+
/*
- * Final MMU
- * Let's start from the same layout as early MMU and modify as needed.
- * IFC regions will be cache-inhibit.
+ * Set the block entries according to the information of the table.
*/
-#define FINAL_QBMAN_CACHED_MEM 0x818000000UL
-#define FINAL_QBMAN_CACHED_SIZE 0x4000000
+static int set_block_entry(const struct sys_mmu_table *list,
+ struct table_info *table)
+{
+ u64 block_size = 0, block_shift = 0;
+ u64 block_addr, index;
+ int j;
+
+ if (table->entry_size == BLOCK_SIZE_L1) {
+ block_size = BLOCK_SIZE_L1;
+ block_shift = SECTION_SHIFT_L1;
+ } else if (table->entry_size == BLOCK_SIZE_L2) {
+ block_size = BLOCK_SIZE_L2;
+ block_shift = SECTION_SHIFT_L2;
+ } else {
+ return -EINVAL;
+ }
+ block_addr = list->phys_addr;
+ index = (list->virt_addr - table->table_base) >> block_shift;
+
+ for (j = 0; j < (list->size >> block_shift); j++) {
+ set_pgtable_section(table->ptr,
+ index,
+ block_addr,
+ list->memory_type,
+ list->share);
+ block_addr += block_size;
+ index++;
+ }
-static inline void early_mmu_setup(void)
+ return 0;
+}
+
+/*
+ * Find the corresponding table entry for the list.
+ */
+static int find_table(const struct sys_mmu_table *list,
+ struct table_info *table, u64 *level0_table)
{
- int el;
- u64 i;
- u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1;
- u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
- u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
- u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
- u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
- u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
+ u64 index = 0, level = 0;
+ u64 *level_table = level0_table;
+ u64 temp_base = 0, block_size = 0, block_shift = 0;
+
+ while (level < 3) {
+ if (level == 0) {
+ block_size = BLOCK_SIZE_L0;
+ block_shift = SECTION_SHIFT_L0;
+ } else if (level == 1) {
+ block_size = BLOCK_SIZE_L1;
+ block_shift = SECTION_SHIFT_L1;
+ } else if (level == 2) {
+ block_size = BLOCK_SIZE_L2;
+ block_shift = SECTION_SHIFT_L2;
+ }
- level0_table[0] =
- (u64)level1_table_0 | PMD_TYPE_TABLE;
- level0_table[1] =
- (u64)level1_table_1 | PMD_TYPE_TABLE;
+ index = 0;
+ while (list->virt_addr >= temp_base) {
+ index++;
+ temp_base += block_size;
+ }
- /*
- * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
- * set level 1 table 1 to cache enabled, covering 512GB to 1TB
- * set level 2 table to cache-inhibit, covering 0 to 1GB
- */
- section_l1t0 = 0;
- section_l1t1 = BLOCK_SIZE_L0;
- section_l2t0 = 0;
- section_l2t1 = CONFIG_SYS_FLASH_BASE;
- for (i = 0; i < 512; i++) {
- set_pgtable_section(level1_table_0, i, section_l1t0,
- MT_DEVICE_NGNRNE);
- set_pgtable_section(level1_table_1, i, section_l1t1,
- MT_NORMAL);
- set_pgtable_section(level2_table_0, i, section_l2t0,
- MT_DEVICE_NGNRNE);
- set_pgtable_section(level2_table_1, i, section_l2t1,
- MT_DEVICE_NGNRNE);
- section_l1t0 += BLOCK_SIZE_L1;
- section_l1t1 += BLOCK_SIZE_L1;
- section_l2t0 += BLOCK_SIZE_L2;
- section_l2t1 += BLOCK_SIZE_L2;
+ temp_base -= block_size;
+
+ if ((level_table[index - 1] & PMD_TYPE_MASK) ==
+ PMD_TYPE_TABLE) {
+ level_table = (u64 *)(level_table[index - 1] &
+ ~PMD_TYPE_MASK);
+ level++;
+ continue;
+ } else {
+ if (level == 0)
+ return -EINVAL;
+
+ if ((list->phys_addr + list->size) >
+ (temp_base + block_size * NUM_OF_ENTRY))
+ return -EINVAL;
+
+ /*
+ * Check the address and size of the list member is
+ * aligned with the block size.
+ */
+ if (((list->phys_addr & (block_size - 1)) != 0) ||
+ ((list->size & (block_size - 1)) != 0))
+ return -EINVAL;
+
+ table->ptr = level_table;
+ table->table_base = temp_base -
+ ((index - 1) << block_shift);
+ table->entry_size = block_size;
+
+ return 0;
+ }
}
+ return -EINVAL;
+}
- level1_table_0[0] =
- (u64)level2_table_0 | PMD_TYPE_TABLE;
- level1_table_0[1] =
- 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_DEVICE_NGNRNE);
- level1_table_0[2] =
- 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_NORMAL);
- level1_table_0[3] =
- 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_NORMAL);
-
- /* Rewerite table to enable cache for OCRAM */
- set_pgtable_section(level2_table_0,
- CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
- CONFIG_SYS_FSL_OCRAM_BASE,
- MT_NORMAL);
-
-#if defined(CONFIG_SYS_NOR0_CSPR_EARLY) && defined(CONFIG_SYS_NOR_AMASK_EARLY)
- /* Rewrite table to enable cache for two entries (4MB) */
- section_l2t1 = CONFIG_SYS_IFC_BASE;
- set_pgtable_section(level2_table_0,
- section_l2t1 >> SECTION_SHIFT_L2,
- section_l2t1,
- MT_NORMAL);
- section_l2t1 += BLOCK_SIZE_L2;
- set_pgtable_section(level2_table_0,
- section_l2t1 >> SECTION_SHIFT_L2,
- section_l2t1,
- MT_NORMAL);
-#endif
-
- /* Create a mapping for 256MB IFC region to final flash location */
- level1_table_0[CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1] =
- (u64)level2_table_1 | PMD_TYPE_TABLE;
- section_l2t1 = CONFIG_SYS_IFC_BASE;
- for (i = 0; i < 0x10000000 >> SECTION_SHIFT_L2; i++) {
- set_pgtable_section(level2_table_1, i,
- section_l2t1, MT_DEVICE_NGNRNE);
- section_l2t1 += BLOCK_SIZE_L2;
+/*
+ * To start MMU before DDR is available, we create MMU table in SRAM.
+ * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * levels of translation tables here to cover 40-bit address space.
+ * We use 4KB granule size, with 40 bits physical address, T0SZ=24
+ * Level 0 IA[39], table address @0
+ * Level 1 IA[38:30], table address @0x1000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000, 0x4000
+ * Address above 0x5000 is free for other purpose.
+ */
+static inline void early_mmu_setup(void)
+{
+ unsigned int el, i;
+ u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
+ u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
+ u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
+ u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
+ u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
+ struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
+
+ /* Invalidate all table entries */
+ memset(level0_table, 0, 0x5000);
+
+ /* Fill in the table entries */
+ set_pgtable_table(level0_table, 0, level1_table0);
+ set_pgtable_table(level0_table, 1, level1_table1);
+ set_pgtable_table(level1_table0, 0, level2_table0);
+ set_pgtable_table(level1_table0,
+ CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
+ level2_table1);
+
+ /* Find the table and fill in the block entries */
+ for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) {
+ if (find_table(&lsch3_early_mmu_table[i],
+ &table, level0_table) == 0) {
+ /*
+ * If find_table() returns error, it cannot be dealt
+ * with here. Breakpoint can be added for debugging.
+ */
+ set_block_entry(&lsch3_early_mmu_table[i], &table);
+ /*
+ * If set_block_entry() returns error, it cannot be
+ * dealt with here too.
+ */
+ }
}
el = current_el();
}
/*
- * This final tale looks similar to early table, but different in detail.
- * These tables are in regular memory. Cache on IFC is disabled. One sub table
- * is added to enable cache for QBMan.
+ * The final tables look similar to early tables, but different in detail.
+ * These tables are in DRAM. Sub tables are added to enable cache for
+ * QBMan and OCRAM.
+ *
+ * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
+ * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
+ * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
+ * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
*/
static inline void final_mmu_setup(void)
{
- int el;
- u64 i, tbl_base, tbl_limit, section_base;
- u64 section_l1t0, section_l1t1, section_l2;
+ unsigned int el, i;
u64 *level0_table = (u64 *)gd->arch.tlb_addr;
- u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
- u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
- u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
- u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
-
-
- level0_table[0] =
- (u64)level1_table_0 | PMD_TYPE_TABLE;
- level0_table[1] =
- (u64)level1_table_1 | PMD_TYPE_TABLE;
-
- /*
- * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
- * set level 1 table 1 to cache enabled, covering 512GB to 1TB
- * set level 2 table 0 to cache-inhibit, covering 0 to 1GB
- */
- section_l1t0 = 0;
- section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE;
- section_l2 = 0;
- for (i = 0; i < 512; i++) {
- set_pgtable_section(level1_table_0, i, section_l1t0,
- MT_DEVICE_NGNRNE);
- set_pgtable_section(level1_table_1, i, section_l1t1,
- MT_NORMAL);
- set_pgtable_section(level2_table_0, i, section_l2,
- MT_DEVICE_NGNRNE);
- section_l1t0 += BLOCK_SIZE_L1;
- section_l1t1 += BLOCK_SIZE_L1;
- section_l2 += BLOCK_SIZE_L2;
- }
-
- level1_table_0[0] =
- (u64)level2_table_0 | PMD_TYPE_TABLE;
- level1_table_0[2] =
- 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
- level1_table_0[3] =
- 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
-
- /* Rewrite table to enable cache */
- set_pgtable_section(level2_table_0,
- CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
- CONFIG_SYS_FSL_OCRAM_BASE,
- MT_NORMAL);
+ u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
+ u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
+ u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
+ u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+ struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
+
+ /* Invalidate all table entries */
+ memset(level0_table, 0, PGTABLE_SIZE);
+
+ /* Fill in the table entries */
+ set_pgtable_table(level0_table, 0, level1_table0);
+ set_pgtable_table(level0_table, 1, level1_table1);
+ set_pgtable_table(level1_table0, 0, level2_table0);
+ set_pgtable_table(level1_table0,
+ CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
+ level2_table1);
+
+ /* Find the table and fill in the block entries */
+ for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) {
+ if (find_table(&lsch3_final_mmu_table[i],
+ &table, level0_table) == 0) {
+ if (set_block_entry(&lsch3_final_mmu_table[i],
+ &table) != 0) {
+ printf("MMU error: could not set block entry for %p\n",
+ &lsch3_final_mmu_table[i]);
+ }
- /*
- * Fill in other part of tables if cache is needed
- * If finer granularity than 1GB is needed, sub table
- * should be created.
- */
- section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1);
- i = section_base >> SECTION_SHIFT_L1;
- level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE;
- section_l2 = section_base;
- for (i = 0; i < 512; i++) {
- set_pgtable_section(level2_table_1, i, section_l2,
- MT_DEVICE_NGNRNE);
- section_l2 += BLOCK_SIZE_L2;
- }
- tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1);
- tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) &
- (BLOCK_SIZE_L1 - 1);
- for (i = tbl_base >> SECTION_SHIFT_L2;
- i < tbl_limit >> SECTION_SHIFT_L2; i++) {
- section_l2 = section_base + (i << SECTION_SHIFT_L2);
- set_pgtable_section(level2_table_1, i,
- section_l2, MT_NORMAL);
+ } else {
+ printf("MMU error: could not find the table for %p\n",
+ &lsch3_final_mmu_table[i]);
+ }
}
/* flush new MMU table */
flush_dcache_range(gd->arch.tlb_addr,
- gd->arch.tlb_addr + gd->arch.tlb_size);
+ gd->arch.tlb_addr + gd->arch.tlb_size);
/* point TTBR to the new table */
el = current_el();
else {
serdes_prtcl_map[lane_prtcl] = 1;
#ifdef CONFIG_FSL_MC_ENET
- wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl);
+ switch (lane_prtcl) {
+ case QSGMII_A:
+ wriop_init_dpmac(sd, 5, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 6, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 7, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 8, (int)lane_prtcl);
+ break;
+ case QSGMII_B:
+ wriop_init_dpmac(sd, 1, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 2, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 3, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 4, (int)lane_prtcl);
+ break;
+ case QSGMII_C:
+ wriop_init_dpmac(sd, 13, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 14, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 15, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 16, (int)lane_prtcl);
+ break;
+ case QSGMII_D:
+ wriop_init_dpmac(sd, 9, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 10, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 11, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 12, (int)lane_prtcl);
+ break;
+ default:
+ if (lane_prtcl >= SGMII1 &&
+ lane_prtcl <= SGMII16)
+ wriop_init_dpmac(sd, lane + 1,
+ (int)lane_prtcl);
+ break;
+ }
#endif
}
}
mov x29, lr /* Save LR */
/* Add fully-coherent masters to DVM domain */
- ldr x1, =CCI_MN_BASE
- ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST]
- str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
-1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
- mvn x0, x3
- tst x0, x3 /* Wait for domain addition to complete */
- b.ne 1b
+ ldr x0, =CCI_MN_BASE
+ ldr x1, =CCI_MN_RNF_NODEID_LIST
+ ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
+ bl ccn504_add_masters_to_dvm
+
+ /* Set all RN-I ports to QoS of 15 */
+ ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+
+ ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+
+ ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+
+ ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+
+ ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+
+ ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
+ ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
+ ldr x1, =0x00FF000C
+ bl ccn504_set_qos
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
- {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
- QSGMII_A} },
- {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
+ QSGMII_B} },
+ {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
}
#endif
+#ifdef CONFIG_IOMUX_LPSR
+ u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
+
+ if (lpsr == IOMUX_CONFIG_LPSR) {
+ base = (void *)IOMUXC_LPSR_BASE_ADDR;
+ mux_mode &= ~IOMUX_CONFIG_LPSR;
+ /* set daisy chain sel_input */
+ if (sel_input_ofs)
+ sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
+ }
+#endif
+
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
#endif
+
+#ifdef CONFIG_IOMUX_LPSR
+ if (lpsr == IOMUX_CONFIG_LPSR)
+ base = (void *)IOMUXC_BASE_ADDR;
+#endif
+
}
/* configures a list of pads within declared with IOMUX_PADS macro */
#define CONFIG_MP
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
+#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
+#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
+#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
+#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
+#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
+
+#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
+#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
+#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+
/* Device Configuration */
#define DCFG_BASE 0x01e00000
#define DCFG_PORSR1 0x000
* SPDX-License-Identifier: GPL-2.0+
*/
+#define MXC_CPU_MX23 0x23
+#define MXC_CPU_MX25 0x25
+#define MXC_CPU_MX27 0x27
+#define MXC_CPU_MX28 0x28
+#define MXC_CPU_MX31 0x31
+#define MXC_CPU_MX35 0x35
#define MXC_CPU_MX51 0x51
#define MXC_CPU_MX53 0x53
#define MXC_CPU_MX6SL 0x60
#define MXC_CPU_MX6D 0x67
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
+#define MXC_CPU_VF610 0xF6 /* dummy ID */
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
-#define CONFIG_KEY_REVOCATION
-#define CONFIG_FSL_ISBC_KEY_EXT
-
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_ESBC_VALIDATE
-#define CONFIG_FSL_SEC_MON
-#define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_DM
-#define CONFIG_RSA
-#define CONFIG_RSA_FREESCALE_EXP
-#ifndef CONFIG_FSL_CAAM
-#define CONFIG_FSL_CAAM
-#endif
-#endif
#define DCU_LAYER_MAX_NUM 16
u32 sdhcpcr;
};
-#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
+#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_DEVDIS_H_
+#define __FSL_LS102XA_DEVDIS_H_
+
+#include <fsl_devdis.h>
+
+const struct devdis_table devdis_tbl[] = {
+ { "pbl", 0x0, 0x80000000 }, /* PBL */
+ { "esdhc", 0x0, 0x20000000 }, /* eSDHC */
+ { "qdma", 0x0, 0x800000 }, /* qDMA */
+ { "edma", 0x0, 0x400000 }, /* eDMA */
+ { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/
+ { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */
+ { "sata", 0x0, 0x8000 }, /* SATA */
+ { "sec", 0x0, 0x200 }, /* SEC */
+ { "dcu", 0x0, 0x2 }, /* Display controller Unit */
+ { "qe", 0x0, 0x1 }, /* QUICC Engine */
+ { "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */
+ { "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */
+ { "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */
+ { "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */
+ { "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */
+ { "duart1", 0x3, 0x20000000 }, /* DUART1 */
+ { "duart2", 0x3, 0x10000000 }, /* DUART2 */
+ { "qspi", 0x3, 0x8000000 }, /* QSPI */
+ { "ddr", 0x4, 0x80000000 }, /* DDR */
+ { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */
+ { "ifc", 0x4, 0x800000 }, /* IFC */
+ { "gpio", 0x4, 0x400000 }, /* GPIO */
+ { "dbg", 0x4, 0x200000 }, /* DBG */
+ { "can1", 0x4, 0x80000 }, /* FlexCAN1 */
+ { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */
+ { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */
+ { "secmon", 0x4, 0x4000 }, /* Security Monitor */
+ { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */
+ { "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */
+ { "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */
+ { "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */
+ { "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */
+ { "asrc", 0x4, 0x20 }, /* ASRC */
+ { "spdif", 0x4, 0x10 }, /* SPDIF */
+ { "i2c1", 0x4, 0x4 }, /* I2C1 */
+ { "lpuart1", 0x4, 0x2 }, /* LPUART1 */
+ { "ftm1", 0x4, 0x1 }, /* FlexTimer1 */
+};
+
+#endif
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
+#ifndef _MX31_SYS_PROTO_H_
+#define _MX31_SYS_PROTO_H_
+
+#include <asm/imx-common/sys_proto.h>
struct mxc_weimcs {
u32 upper;
void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs);
int mxc_mmc_init(bd_t *bis);
-u32 get_cpu_rev(void);
#endif
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
+#ifndef _MX35_SYS_PROTO_H_
+#define _MX35_SYS_PROTO_H_
-u32 get_cpu_rev(void);
-void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
- u32 row, u32 col, u32 dsize, u32 refresh);
-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+#include <asm/imx-common/sys_proto.h>
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
+ u32 col, u32 dsize, u32 refresh);
#endif
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74C, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP2_DAT6__FEC_TDAT1 = IOMUX_PAD(0x774, 0x36C, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_DISP2_DAT7__FEC_TDAT2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_DISP2_DAT8__FEC_TDAT3 = IOMUX_PAD(0x77C, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37C, 2, 0x94c, 0x1, MX51_PAD_CTRL_2),
+ MX51_PAD_DISP2_DAT11__FEC_RXCLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 0x1, MX51_PAD_CTRL_2),
+ MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78C, 0x384, 2, 0x96c, 0x1, MX51_PAD_CTRL_4),
+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 0x1, MX51_PAD_CTRL_4),
+ MX51_PAD_DISP2_DAT14__FEC_RDAT0 = IOMUX_PAD(0x794, 0x38C, 2, 0x958, 0x1, MX51_PAD_CTRL_4),
+ MX51_PAD_DISP2_DAT15__FEC_TDAT0 = IOMUX_PAD(0x798, 0x390, 2, 0x0, 0, MX51_PAD_CTRL_5),
MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-#include "../arch-imx/cpu.h"
-
-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
-u32 get_cpu_rev(void);
-unsigned imx_ddr_size(void);
-void sdelay(unsigned long);
-void set_chipselect_size(int const);
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-
-int fecmxc_initialize(bd_t *bis);
-u32 get_ahb_clk(void);
-u32 get_periph_clk(void);
-
-#endif
+#include <asm/imx-common/sys_proto.h>
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
-int enable_fec_anatop_clock(enum enet_freq freq);
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);
#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+/* ENET2 for i.MX6SX/UL */
+#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
+#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
+#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
+ (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
+
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
#define BP_ANADIG_PFD_480_PFD3_FRAC 24
u32 version;
u32 rsvd7[0xdb];
+ /* fuse banks */
struct fuse_bank {
u32 fuse_regs[0x20];
- } bank[16];
+ } bank[0];
};
struct fuse_bank0_regs {
#ifdef CONFIG_MX6UL
#include "mx6ul-ddr.h"
#else
+#ifdef CONFIG_MX6SL
+#include "mx6sl-ddr.h"
+#else
#error "Please select cpu"
+#endif /* CONFIG_MX6SL */
#endif /* CONFIG_MX6UL */
#endif /* CONFIG_MX6SX */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#else
+enum {
+ DDR_TYPE_DDR3,
+ DDR_TYPE_LPDDR2,
+};
+
/* MMDC P0/P1 Registers */
struct mmdc_p_regs {
u32 mdctl;
u32 res1[2];
u32 mdrwd;
u32 mdor;
- u32 res2[3];
+ u32 mdmrr;
+ u32 mdcfg3lp;
+ u32 mdmr4;
u32 mdasp;
- u32 res3[240];
+ u32 res2[239];
+ u32 maarcr;
u32 mapsr;
- u32 res4[254];
+ u32 maexidr0;
+ u32 maexidr1;
+ u32 madpcr0;
+ u32 madpcr1;
+ u32 madpsr0;
+ u32 madpsr1;
+ u32 madpsr2;
+ u32 madpsr3;
+ u32 madpsr4;
+ u32 madpsr5;
+ u32 masbs0;
+ u32 masbs1;
+ u32 res3[2];
+ u32 magenp;
+ u32 res4[239];
u32 mpzqhwctrl;
- u32 res5[2];
+ u32 mpzqswctrl;
+ u32 mpwlgcr;
u32 mpwldectrl0;
u32 mpwldectrl1;
- u32 res6;
+ u32 mpwldlst;
u32 mpodtctrl;
u32 mprddqby0dl;
u32 mprddqby1dl;
u32 mprddqby2dl;
u32 mprddqby3dl;
- u32 res7[4];
+ u32 mpwrdqby0dl;
+ u32 mpwrdqby1dl;
+ u32 mpwrdqby2dl;
+ u32 mpwrdqby3dl;
u32 mpdgctrl0;
u32 mpdgctrl1;
- u32 res8;
+ u32 mpdgdlst0;
u32 mprddlctl;
- u32 res9;
+ u32 mprddlst;
u32 mpwrdlctl;
- u32 res10[25];
+ u32 mpwrdlst;
+ u32 mpsdctrl;
+ u32 mpzqlp2ctl;
+ u32 mprddlhwctl;
+ u32 mpwrdlhwctl;
+ u32 mprddlhwst0;
+ u32 mprddlhwst1;
+ u32 mpwrdlhwst0;
+ u32 mpwrdlhwst1;
+ u32 mpwlhwerr;
+ u32 mpdghwst0;
+ u32 mpdghwst1;
+ u32 mpdghwst2;
+ u32 mpdghwst3;
+ u32 mppdcmpr1;
+ u32 mppdcmpr2;
+ u32 mpswdar0;
+ u32 mpswdrdr0;
+ u32 mpswdrdr1;
+ u32 mpswdrdr2;
+ u32 mpswdrdr3;
+ u32 mpswdrdr4;
+ u32 mpswdrdr5;
+ u32 mpswdrdr6;
+ u32 mpswdrdr7;
u32 mpmur0;
+ u32 mpwrcadl;
+ u32 mpdccr;
+};
+
+#define MX6SL_IOM_DDR_BASE 0x020e0300
+struct mx6sl_iomux_ddr_regs {
+ u32 dram_cas;
+ u32 dram_cs0_b;
+ u32 dram_cs1_b;
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_dqm2;
+ u32 dram_dqm3;
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 dram_sdba0;
+ u32 dram_sdba1;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_odt0;
+ u32 dram_odt1;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_sdqs2;
+ u32 dram_sdqs3;
+ u32 dram_sdwe_b;
+};
+
+#define MX6SL_IOM_GRP_BASE 0x020e0500
+struct mx6sl_iomux_grp_regs {
+ u32 res1[43];
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 grp_ddrpke;
+ u32 grp_ddrpk;
+ u32 grp_ddrhys;
+ u32 grp_ddrmode;
+ u32 grp_b0ds;
+ u32 grp_ctlds;
+ u32 grp_b1ds;
+ u32 grp_ddr_type;
+ u32 grp_b2ds;
+ u32 grp_b3ds;
};
#define MX6UL_IOM_DDR_BASE 0x020e0200
u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
};
+/* Device Information: Varies per LPDDR2 part number and speed grade */
+struct mx6_lpddr2_cfg {
+ u16 mem_speed; /* ie 800 for LPDDR2-800 */
+ u8 density; /* chip density (Gb) (1,2,4,8) */
+ u8 width; /* bus width (bits) (4,8,16) */
+ u8 banks; /* number of banks */
+ u8 rowaddr; /* row address bits (11-16)*/
+ u8 coladdr; /* col address bits (9-12) */
+ u16 trcd_lp;
+ u16 trppb_lp;
+ u16 trpab_lp;
+ u16 trcmin; /* tRC min (ns*100) */
+ u16 trasmin; /* tRAS min (ns*100) */
+};
+
/* System Information: Varies per board design, layout, and term choices */
struct mx6_ddr_sysinfo {
u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
u8 rst_to_cke; /* Time from SDE enable to CKE rise */
u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
+ u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
};
/*
/* write delay */
u32 p0_mpwrdlctl;
u32 p1_mpwrdlctl;
+ /* lpddr2 zq hw calibration */
+ u32 mpzqlp2ctl;
};
/* configure iomux (pinctl/padctl) */
void mx6ul_dram_iocfg(unsigned width,
const struct mx6ul_iomux_ddr_regs *,
const struct mx6ul_iomux_grp_regs *);
+void mx6sl_dram_iocfg(unsigned width,
+ const struct mx6sl_iomux_ddr_regs *,
+ const struct mx6sl_iomux_grp_regs *);
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
const struct mx6_mmdc_calibration *,
- const struct mx6_ddr3_cfg *);
+ const void *);
#endif /* CONFIG_SPL_BUILD */
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX6SL_DDR_H__
+#define __ASM_ARCH_MX6SL_DDR_H__
+
+#ifndef CONFIG_MX6SL
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_CAS_B 0x020e0300
+#define MX6_IOM_DRAM_CS0_B 0x020e0304
+#define MX6_IOM_DRAM_CS1_B 0x020e0308
+
+#define MX6_IOM_DRAM_DQM0 0x020e030c
+#define MX6_IOM_DRAM_DQM1 0x020e0310
+#define MX6_IOM_DRAM_DQM2 0x020e0314
+#define MX6_IOM_DRAM_DQM3 0x020e0318
+
+#define MX6_IOM_DRAM_RAS_B 0x020e031c
+#define MX6_IOM_DRAM_RESET 0x020e0320
+
+#define MX6_IOM_DRAM_SDBA0 0x020e0324
+#define MX6_IOM_DRAM_SDBA1 0x020e0328
+#define MX6_IOM_DRAM_SDBA2 0x020e032c
+
+#define MX6_IOM_DRAM_SDCKE0 0x020e0330
+#define MX6_IOM_DRAM_SDCKE1 0x020e0334
+
+#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338
+
+#define MX6_IOM_DRAM_ODT0 0x020e033c
+#define MX6_IOM_DRAM_ODT1 0x020e0340
+
+#define MX6_IOM_DRAM_SDQS0_P 0x020e0344
+#define MX6_IOM_DRAM_SDQS1_P 0x020e0348
+#define MX6_IOM_DRAM_SDQS2_P 0x020e034c
+#define MX6_IOM_DRAM_SDQS3_P 0x020e0350
+
+#define MX6_IOM_DRAM_SDWE_B 0x020e0354
+
+#endif /*__ASM_ARCH_MX6SL_DDR_H__ */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-#include <asm/imx-common/regs-common.h>
-#include "../arch-imx/cpu.h"
-
-#define soc_rev() (get_cpu_rev() & 0xFF)
-#define is_soc_rev(rev) (soc_rev() == rev)
-
-u32 get_nr_cpus(void);
-u32 get_cpu_rev(void);
-u32 get_cpu_speed_grade_hz(void);
-u32 get_cpu_temp_grade(int *minc, int *maxc);
-
-/* returns MXC_CPU_ value */
-#define cpu_type(rev) (((rev) >> 12) & 0xff)
-
-/* both macros return/take MXC_CPU_ constants */
-#define get_cpu_type() (cpu_type(get_cpu_rev()))
-#define is_cpu_type(cpu) (get_cpu_type() == cpu)
-
-const char *get_imx_type(u32 imxtype);
-unsigned imx_ddr_size(void);
-void set_chipselect_size(int const);
-
-#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-
-int fecmxc_initialize(bd_t *bis);
-u32 get_ahb_clk(void);
-u32 get_periph_clk(void);
-
-int mxs_reset_block(struct mxs_register_32 *reg);
-int mxs_wait_mask_set(struct mxs_register_32 *reg,
- uint32_t mask,
- unsigned int timeout);
-int mxs_wait_mask_clr(struct mxs_register_32 *reg,
- uint32_t mask,
- unsigned int timeout);
-#endif
+#include <asm/imx-common/sys_proto.h>
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX7_GPIO_H
+#define __ASM_ARCH_MX7_GPIO_H
+
+#include <asm/imx-common/gpio.h>
+
+#endif /* __ASM_ARCH_MX7_GPIO_H */
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_MX7_PINS_H__
+#define __ASM_ARCH_MX7_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+#if defined(CONFIG_MX7D)
+#include "mx7d_pins.h"
+#elif defined(CONFIG_MX7S)
+#include "mx7s_pins.h"
+#else
+#error "Please select cpu"
+#endif /* CONFIG_MX7D */
+
+#endif /*__ASM_ARCH_MX7_PINS_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX7D_PINS_H__
+#define __ASM_ARCH_IMX7D_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+ MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
+
+ MX7D_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
+
+ MX7D_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO02__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0),
+ MX7D_PAD_GPIO1_IO02__SAI2_MCLK = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO02__CCM_CLKO1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO02__USB_OTG1_ID = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0),
+
+ MX7D_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO03__PWM3_OUT = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0),
+ MX7D_PAD_GPIO1_IO03__SAI3_MCLK = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO03__CCM_CLKO2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO03__USB_OTG2_ID = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0),
+
+ MX7D_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO04__USB_OTG1_OC = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0),
+ MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0),
+ MX7D_PAD_GPIO1_IO04__UART5_CTS_B = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0),
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0),
+
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0),
+ MX7D_PAD_GPIO1_IO05__UART5_RTS_B = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0),
+ MX7D_PAD_GPIO1_IO05__I2C1_SDA = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0),
+
+ MX7D_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO06__USB_OTG2_OC = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0),
+ MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0),
+ MX7D_PAD_GPIO1_IO06__UART5_RX_DATA = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0),
+ MX7D_PAD_GPIO1_IO06__I2C2_SCL = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0),
+ MX7D_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO06__KPP_ROW4 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0),
+
+ MX7D_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0),
+ MX7D_PAD_GPIO1_IO07__UART5_TX_DATA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0),
+ MX7D_PAD_GPIO1_IO07__I2C2_SDA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0),
+ MX7D_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO07__KPP_COL4 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0),
+};
+
+enum {
+ MX7D_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO08__SD1_VSELECT = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO08__UART3_DCE_RX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0),
+ MX7D_PAD_GPIO1_IO08__UART3_DTE_TX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO08__I2C3_SCL = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0),
+ MX7D_PAD_GPIO1_IO08__KPP_COL5 = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0),
+ MX7D_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO09__SD1_LCTL = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO09__UART3_DCE_TX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO09__UART3_DTE_RX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0),
+ MX7D_PAD_GPIO1_IO09__I2C3_SDA = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0),
+ MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0),
+ MX7D_PAD_GPIO1_IO09__KPP_ROW5 = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0),
+ MX7D_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO10__SD2_LCTL = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO10__ENET1_MDIO = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0),
+ MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0),
+ MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO10__I2C4_SCL = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0),
+ MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0),
+ MX7D_PAD_GPIO1_IO10__KPP_COL6 = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0),
+ MX7D_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO11__SD3_LCTL = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO11__ENET1_MDC = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0),
+ MX7D_PAD_GPIO1_IO11__I2C4_SDA = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0),
+ MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0),
+ MX7D_PAD_GPIO1_IO11__KPP_ROW6 = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0),
+ MX7D_PAD_GPIO1_IO11__PWM4_OUT = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO12__SD2_VSELECT = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0),
+ MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0),
+ MX7D_PAD_GPIO1_IO12__CM4_NMI = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0),
+ MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO12__USB_OTG1_ID = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0),
+
+ MX7D_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO13__SD3_VSELECT = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0),
+ MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0),
+ MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0),
+ MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO13__USB_OTG2_ID = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0),
+
+ MX7D_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO14__SD3_CD_B = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0),
+ MX7D_PAD_GPIO1_IO14__ENET2_MDIO = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0),
+ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0),
+ MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0),
+ MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0),
+
+ MX7D_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO15__SD3_WP = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0),
+ MX7D_PAD_GPIO1_IO15__ENET2_MDC = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0),
+ MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0),
+ MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0),
+
+ MX7D_PAD_EPDC_DATA00__EPDC_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA00__KPP_ROW3 = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0),
+ MX7D_PAD_EPDC_DATA00__EIM_AD0 = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA00__GPIO2_IO0 = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA00__LCD_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0),
+ MX7D_PAD_EPDC_DATA00__LCD_CLK = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA01__EPDC_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA01__KPP_COL3 = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0),
+ MX7D_PAD_EPDC_DATA01__EIM_AD1 = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA01__GPIO2_IO1 = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA01__LCD_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0),
+ MX7D_PAD_EPDC_DATA01__LCD_ENABLE = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA02__EPDC_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA02__KPP_ROW2 = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0),
+ MX7D_PAD_EPDC_DATA02__EIM_AD2 = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA02__GPIO2_IO2 = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA02__LCD_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0),
+ MX7D_PAD_EPDC_DATA02__LCD_VSYNC = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0),
+
+ MX7D_PAD_EPDC_DATA03__EPDC_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA03__KPP_COL2 = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0),
+ MX7D_PAD_EPDC_DATA03__EIM_AD3 = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA03__GPIO2_IO3 = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA03__LCD_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0),
+ MX7D_PAD_EPDC_DATA03__LCD_HSYNC = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA04__EPDC_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA04__QSPI_A_DQS = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA04__KPP_ROW1 = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0),
+ MX7D_PAD_EPDC_DATA04__EIM_AD4 = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA04__LCD_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0),
+ MX7D_PAD_EPDC_DATA04__JTAG_FAIL = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA05__EPDC_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA05__KPP_COL1 = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0),
+ MX7D_PAD_EPDC_DATA05__EIM_AD5 = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA05__GPIO2_IO5 = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA05__LCD_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0),
+ MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA06__EPDC_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA06__KPP_ROW0 = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0),
+ MX7D_PAD_EPDC_DATA06__EIM_AD6 = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA06__GPIO2_IO6 = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA06__LCD_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0),
+ MX7D_PAD_EPDC_DATA06__JTAG_DE_B = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA07__EPDC_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA07__KPP_COL0 = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0),
+ MX7D_PAD_EPDC_DATA07__EIM_AD7 = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA07__GPIO2_IO7 = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA07__LCD_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0),
+ MX7D_PAD_EPDC_DATA07__JTAG_DONE = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA08__EPDC_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0),
+ MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA08__UART6_DCE_RX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0),
+ MX7D_PAD_EPDC_DATA08__UART6_DTE_TX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA08__EIM_OE = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA08__GPIO2_IO8 = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA08__LCD_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0),
+ MX7D_PAD_EPDC_DATA08__LCD_BUSY = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0),
+ MX7D_PAD_EPDC_DATA08__EPDC_SDCLK = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA09__EPDC_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA09__UART6_DCE_TX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA09__UART6_DTE_RX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0),
+ MX7D_PAD_EPDC_DATA09__EIM_RW = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA09__GPIO2_IO9 = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA09__LCD_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0),
+ MX7D_PAD_EPDC_DATA09__LCD_DATA0 = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0),
+ MX7D_PAD_EPDC_DATA09__EPDC_SDLE = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0),
+ MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA10__EIM_CS0_B = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA10__GPIO2_IO10 = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA10__LCD_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0),
+ MX7D_PAD_EPDC_DATA10__LCD_DATA9 = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0),
+ MX7D_PAD_EPDC_DATA10__EPDC_SDOE = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0),
+ MX7D_PAD_EPDC_DATA11__EIM_BCLK = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA11__GPIO2_IO11 = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA11__LCD_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0),
+ MX7D_PAD_EPDC_DATA11__LCD_DATA1 = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0),
+ MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0),
+ MX7D_PAD_EPDC_DATA12__QSPI_B_DQS = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA12__UART7_DCE_RX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0),
+ MX7D_PAD_EPDC_DATA12__UART7_DTE_TX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA12__EIM_LBA_B = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA12__GPIO2_IO12 = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA12__LCD_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0),
+ MX7D_PAD_EPDC_DATA12__LCD_DATA21 = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0),
+ MX7D_PAD_EPDC_DATA12__EPDC_GDCLK = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0),
+ MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA13__UART7_DCE_TX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA13__UART7_DTE_RX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0),
+ MX7D_PAD_EPDC_DATA13__EIM_WAIT = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA13__LCD_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0),
+ MX7D_PAD_EPDC_DATA13__LCD_CS = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA13__EPDC_GDOE = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0),
+ MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA14__EIM_EB_B0 = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA14__GPIO2_IO14 = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA14__LCD_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0),
+ MX7D_PAD_EPDC_DATA14__LCD_DATA22 = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0),
+ MX7D_PAD_EPDC_DATA14__EPDC_GDSP = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0),
+ MX7D_PAD_EPDC_DATA15__EIM_CS1_B = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA15__LCD_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0),
+ MX7D_PAD_EPDC_DATA15__LCD_WR_RWN = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0),
+
+ MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCLK__KPP_ROW4 = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0),
+ MX7D_PAD_EPDC_SDCLK__EIM_AD10 = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCLK__LCD_CLK = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCLK__LCD_DATA20 = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0),
+
+ MX7D_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDLE__KPP_COL4 = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0),
+ MX7D_PAD_EPDC_SDLE__EIM_AD11 = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDLE__GPIO2_IO17 = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDLE__LCD_DATA16 = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0),
+ MX7D_PAD_EPDC_SDLE__LCD_DATA8 = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0),
+
+ MX7D_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0),
+ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDOE__KPP_COL5 = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0),
+ MX7D_PAD_EPDC_SDOE__EIM_AD12 = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDOE__GPIO2_IO18 = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDOE__LCD_DATA17 = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0),
+ MX7D_PAD_EPDC_SDOE__LCD_DATA23 = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0),
+
+ MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0),
+ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDSHR__KPP_ROW5 = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0),
+ MX7D_PAD_EPDC_SDSHR__EIM_AD13 = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDSHR__LCD_DATA18 = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0),
+ MX7D_PAD_EPDC_SDSHR__LCD_DATA10 = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0),
+
+ MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0),
+ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE0__EIM_AD14 = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE0__LCD_DATA19 = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0),
+ MX7D_PAD_EPDC_SDCE0__LCD_DATA5 = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0),
+
+ MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0),
+ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0),
+ MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE1__EIM_AD15 = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE1__LCD_DATA20 = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0),
+ MX7D_PAD_EPDC_SDCE1__LCD_DATA4 = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0),
+
+ MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE2__KPP_COL6 = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0),
+ MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE2__LCD_DATA21 = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0),
+ MX7D_PAD_EPDC_SDCE2__LCD_DATA3 = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0),
+
+ MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0),
+ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE3__KPP_ROW6 = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0),
+ MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_SDCE3__LCD_DATA22 = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0),
+ MX7D_PAD_EPDC_SDCE3__LCD_DATA2 = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0),
+
+ MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0),
+ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDCLK__KPP_COL7 = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0),
+ MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDCLK__LCD_DATA23 = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0),
+ MX7D_PAD_EPDC_GDCLK__LCD_DATA16 = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0),
+
+ MX7D_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0),
+ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDOE__KPP_ROW7 = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0),
+ MX7D_PAD_EPDC_GDOE__EIM_ADDR19 = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDOE__GPIO2_IO25 = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDOE__LCD_WR_RWN = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDOE__LCD_DATA18 = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0),
+
+ MX7D_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0),
+ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDRL__EIM_ADDR20 = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDRL__GPIO2_IO26 = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDRL__LCD_RD_E = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDRL__LCD_DATA19 = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0),
+
+ MX7D_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0),
+ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDSP__ENET2_TX_ER = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDSP__EIM_ADDR21 = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDSP__GPIO2_IO27 = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_GDSP__LCD_BUSY = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0),
+ MX7D_PAD_EPDC_GDSP__LCD_DATA17 = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0),
+
+ MX7D_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0),
+ MX7D_PAD_EPDC_BDR0__EIM_ADDR22 = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR0__LCD_CS = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR0__LCD_DATA7 = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0),
+
+ MX7D_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0),
+ MX7D_PAD_EPDC_BDR1__EIM_AD8 = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR1__GPIO2_IO29 = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR1__LCD_ENABLE = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_BDR1__LCD_DATA6 = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0),
+
+ MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0),
+ MX7D_PAD_EPDC_PWR_COM__ENET2_CRS = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_PWR_COM__EIM_AD9 = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0),
+
+ MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0),
+ MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0),
+ MX7D_PAD_EPDC_PWR_STAT__ENET2_COL = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0),
+ MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0),
+ MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0),
+
+ MX7D_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0),
+ MX7D_PAD_LCD_CLK__ECSPI4_MISO = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0),
+ MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_CLK__CSI_DATA16 = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_CLK__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0),
+ MX7D_PAD_LCD_CLK__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_CLK__GPIO3_IO0 = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0),
+ MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0),
+ MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_ENABLE__CSI_DATA17 = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_ENABLE__UART2_DCE_TX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_ENABLE__UART2_DTE_RX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0),
+ MX7D_PAD_LCD_ENABLE__GPIO3_IO1 = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0),
+ MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0),
+ MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_HSYNC__CSI_DATA18 = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0),
+ MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_HSYNC__GPIO3_IO2 = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0),
+ MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0),
+ MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_VSYNC__CSI_DATA19 = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0),
+ MX7D_PAD_LCD_VSYNC__GPIO3_IO3 = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0),
+ MX7D_PAD_LCD_RESET__GPT1_COMPARE1 = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0),
+ MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_RESET__CSI_FIELD = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_RESET__EIM_DTACK_B = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_RESET__GPIO3_IO4 = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA00__LCD_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0),
+ MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA00__CSI_DATA20 = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA00__EIM_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA00__GPIO3_IO5 = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA01__LCD_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0),
+ MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA01__CSI_DATA21 = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA01__EIM_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA01__GPIO3_IO6 = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA02__LCD_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0),
+ MX7D_PAD_LCD_DATA02__GPT1_CLK = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA02__CSI_DATA22 = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA02__EIM_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA02__GPIO3_IO7 = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA03__LCD_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0),
+ MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA03__CSI_DATA23 = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA03__EIM_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA03__GPIO3_IO8 = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA04__LCD_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0),
+ MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0),
+ MX7D_PAD_LCD_DATA04__EIM_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA04__GPIO3_IO9 = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA05__LCD_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0),
+ MX7D_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0),
+ MX7D_PAD_LCD_DATA05__EIM_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA06__LCD_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0),
+ MX7D_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0),
+ MX7D_PAD_LCD_DATA06__EIM_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA07__LCD_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0),
+ MX7D_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA07__EIM_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA08__LCD_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0),
+ MX7D_PAD_LCD_DATA08__CSI_DATA9 = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0),
+ MX7D_PAD_LCD_DATA08__EIM_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA09__LCD_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0),
+ MX7D_PAD_LCD_DATA09__CSI_DATA8 = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0),
+ MX7D_PAD_LCD_DATA09__EIM_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0),
+ MX7D_PAD_LCD_DATA10__CSI_DATA7 = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0),
+ MX7D_PAD_LCD_DATA10__EIM_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0),
+ MX7D_PAD_LCD_DATA11__CSI_DATA6 = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0),
+ MX7D_PAD_LCD_DATA11__EIM_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0),
+ MX7D_PAD_LCD_DATA12__CSI_DATA5 = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0),
+ MX7D_PAD_LCD_DATA12__EIM_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0),
+ MX7D_PAD_LCD_DATA13__CSI_DATA4 = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0),
+ MX7D_PAD_LCD_DATA13__EIM_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0),
+ MX7D_PAD_LCD_DATA14__CSI_DATA3 = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0),
+ MX7D_PAD_LCD_DATA14__EIM_DATA14 = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0),
+ MX7D_PAD_LCD_DATA15__CSI_DATA2 = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0),
+ MX7D_PAD_LCD_DATA15__EIM_DATA15 = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0),
+ MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0),
+ MX7D_PAD_LCD_DATA16__CSI_DATA1 = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA16__EIM_CRE = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0),
+ MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0),
+ MX7D_PAD_LCD_DATA17__CSI_DATA0 = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0),
+ MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0),
+ MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA18__EIM_CS2_B = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA19__EIM_CS3_B = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0),
+ MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0),
+ MX7D_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA20__EIM_ADDR23 = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA20__I2C3_SCL = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0),
+
+ MX7D_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0),
+ MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0),
+ MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0),
+
+ MX7D_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0),
+ MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0),
+ MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA21__EIM_ADDR24 = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA21__I2C3_SDA = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0),
+
+ MX7D_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0),
+ MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0),
+ MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA22__EIM_ADDR25 = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA22__I2C4_SCL = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0),
+
+ MX7D_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0),
+ MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0),
+ MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA23__EIM_ADDR26 = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0),
+ MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0),
+
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
+
+ MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
+ MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0),
+ MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0),
+ MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0),
+ MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0),
+ MX7D_PAD_UART1_RX_DATA__ENET1_MDIO = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0),
+
+ MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0),
+ MX7D_PAD_UART1_TX_DATA__I2C1_SDA = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0),
+ MX7D_PAD_UART1_TX_DATA__SAI3_MCLK = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0),
+ MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0),
+ MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0),
+ MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0),
+ MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
+
+ MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
+ MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0),
+ MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0),
+ MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0),
+ MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0),
+ MX7D_PAD_UART2_RX_DATA__ENET2_MDIO = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
+
+ MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0),
+ MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0),
+ MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0),
+ MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0),
+ MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0),
+ MX7D_PAD_UART2_TX_DATA__ENET2_MDC = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0),
+
+ MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0),
+ MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0),
+ MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0),
+ MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RX_DATA__SD1_LCTL = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0),
+
+ MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0),
+ MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0),
+ MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0),
+ MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0),
+ MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0),
+ MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0),
+ MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
+
+ MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RTS_B__GPIO4_IO6 = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RTS_B__SD3_LCTL = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0),
+
+ MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0),
+ MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0),
+ MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0),
+ MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0),
+ MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0),
+ MX7D_PAD_UART3_CTS_B__GPIO4_IO7 = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0),
+ MX7D_PAD_UART3_CTS_B__SD1_VSELECT = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0),
+ MX7D_PAD_I2C1_SCL__UART4_DCE_CTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0),
+ MX7D_PAD_I2C1_SCL__UART4_DTE_RTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0),
+ MX7D_PAD_I2C1_SCL__FLEXCAN1_RX = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0),
+ MX7D_PAD_I2C1_SCL__ECSPI3_MISO = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0),
+ MX7D_PAD_I2C1_SCL__GPIO4_IO8 = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0),
+ MX7D_PAD_I2C1_SCL__SD2_VSELECT = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0),
+ MX7D_PAD_I2C1_SDA__UART4_DCE_RTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0),
+ MX7D_PAD_I2C1_SDA__UART4_DTE_CTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0),
+ MX7D_PAD_I2C1_SDA__FLEXCAN1_TX = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0),
+ MX7D_PAD_I2C1_SDA__ECSPI3_MOSI = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0),
+ MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0),
+ MX7D_PAD_I2C1_SDA__GPIO4_IO9 = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0),
+ MX7D_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0),
+ MX7D_PAD_I2C2_SCL__UART4_DCE_RX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0),
+ MX7D_PAD_I2C2_SCL__UART4_DTE_TX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0),
+ MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0),
+ MX7D_PAD_I2C2_SCL__ECSPI3_SCLK = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0),
+ MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0),
+ MX7D_PAD_I2C2_SCL__GPIO4_IO10 = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0),
+ MX7D_PAD_I2C2_SCL__SD3_CD_B = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0),
+
+ MX7D_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0),
+ MX7D_PAD_I2C2_SDA__UART4_DCE_TX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0),
+ MX7D_PAD_I2C2_SDA__UART4_DTE_RX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0),
+ MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0),
+ MX7D_PAD_I2C2_SDA__ECSPI3_SS0 = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0),
+ MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0),
+ MX7D_PAD_I2C2_SDA__GPIO4_IO11 = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0),
+ MX7D_PAD_I2C2_SDA__SD3_WP = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0),
+
+ MX7D_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0),
+ MX7D_PAD_I2C3_SCL__UART5_DCE_CTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0),
+ MX7D_PAD_I2C3_SCL__UART5_DTE_RTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0),
+ MX7D_PAD_I2C3_SCL__FLEXCAN2_RX = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0),
+ MX7D_PAD_I2C3_SCL__CSI_VSYNC = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0),
+ MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0),
+ MX7D_PAD_I2C3_SCL__GPIO4_IO12 = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0),
+ MX7D_PAD_I2C3_SCL__EPDC_BDR0 = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0),
+ MX7D_PAD_I2C3_SDA__UART5_DCE_RTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0),
+ MX7D_PAD_I2C3_SDA__UART5_DTE_CTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0),
+ MX7D_PAD_I2C3_SDA__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0),
+ MX7D_PAD_I2C3_SDA__CSI_HSYNC = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0),
+ MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0),
+ MX7D_PAD_I2C3_SDA__GPIO4_IO13 = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0),
+ MX7D_PAD_I2C3_SDA__EPDC_BDR1 = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0),
+ MX7D_PAD_I2C4_SCL__UART5_DCE_RX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0),
+ MX7D_PAD_I2C4_SCL__UART5_DTE_TX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0),
+ MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0),
+ MX7D_PAD_I2C4_SCL__CSI_PIXCLK = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0),
+ MX7D_PAD_I2C4_SCL__USB_OTG1_ID = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0),
+ MX7D_PAD_I2C4_SCL__GPIO4_IO14 = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0),
+ MX7D_PAD_I2C4_SCL__EPDC_VCOM0 = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0),
+ MX7D_PAD_I2C4_SDA__UART5_DCE_TX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0),
+ MX7D_PAD_I2C4_SDA__UART5_DTE_RX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0),
+ MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0),
+ MX7D_PAD_I2C4_SDA__CSI_MCLK = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0),
+ MX7D_PAD_I2C4_SDA__USB_OTG2_ID = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0),
+ MX7D_PAD_I2C4_SDA__GPIO4_IO15 = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0),
+ MX7D_PAD_I2C4_SDA__EPDC_VCOM1 = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0),
+ MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0),
+ MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0),
+ MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0),
+ MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0),
+ MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0),
+ MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0),
+
+ MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0),
+ MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0),
+ MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_MISO__SD2_DATA6 = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_MISO__CSI_DATA4 = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0),
+ MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0),
+
+ MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0),
+ MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0),
+ MX7D_PAD_ECSPI1_SS0__SD2_DATA7 = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_SS0__CSI_DATA5 = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0),
+ MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0),
+ MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0),
+ MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0),
+ MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0),
+ MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0),
+ MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0),
+ MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0),
+ MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0),
+ MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0),
+ MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0),
+ MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_MISO__SD1_DATA6 = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_MISO__CSI_DATA8 = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0),
+ MX7D_PAD_ECSPI2_MISO__LCD_DATA15 = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0),
+
+ MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0),
+ MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0),
+ MX7D_PAD_ECSPI2_SS0__SD1_DATA7 = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_SS0__CSI_DATA9 = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0),
+ MX7D_PAD_ECSPI2_SS0__LCD_RESET = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0),
+ MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_SD1_CD_B__SD1_CD_B = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_CD_B__UART6_DCE_RX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0),
+ MX7D_PAD_SD1_CD_B__UART6_DTE_TX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD1_CD_B__ECSPI4_MISO = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0),
+ MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0),
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0),
+ MX7D_PAD_SD1_CD_B__CCM_CLKO1 = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_SD1_WP__SD1_WP = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_WP__UART6_DCE_TX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD1_WP__UART6_DTE_RX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0),
+ MX7D_PAD_SD1_WP__ECSPI4_MOSI = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0),
+ MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0),
+ MX7D_PAD_SD1_WP__GPIO5_IO1 = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0),
+ MX7D_PAD_SD1_WP__CCM_CLKO2 = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_SD1_RESET_B__SD1_RESET_B = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_RESET_B__SAI3_MCLK = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0),
+ MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0),
+ MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0),
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0),
+ MX7D_PAD_SD1_CLK__UART6_DCE_CTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD1_CLK__UART6_DTE_RTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0),
+ MX7D_PAD_SD1_CLK__ECSPI4_SS0 = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0),
+ MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0),
+ MX7D_PAD_SD1_CLK__GPIO5_IO3 = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0),
+ MX7D_PAD_SD1_CMD__ECSPI4_SS1 = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0),
+ MX7D_PAD_SD1_CMD__GPIO5_IO4 = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0),
+ MX7D_PAD_SD1_DATA0__UART7_DCE_RX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0),
+ MX7D_PAD_SD1_DATA0__UART7_DTE_TX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA0__ECSPI4_SS2 = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0),
+ MX7D_PAD_SD1_DATA0__GPIO5_IO5 = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0),
+
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0),
+ MX7D_PAD_SD1_DATA1__UART7_DCE_TX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA1__UART7_DTE_RX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0),
+ MX7D_PAD_SD1_DATA1__ECSPI4_SS3 = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0),
+ MX7D_PAD_SD1_DATA1__GPIO5_IO6 = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0),
+
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0),
+ MX7D_PAD_SD1_DATA2__UART7_DCE_CTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA2__UART7_DTE_RTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0),
+ MX7D_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0),
+ MX7D_PAD_SD1_DATA2__GPIO5_IO7 = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0),
+
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA3__UART7_DCE_RTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0),
+ MX7D_PAD_SD1_DATA3__UART7_DTE_CTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA3__ECSPI3_SS1 = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0),
+ MX7D_PAD_SD1_DATA3__GPIO5_IO8 = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0),
+ MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0),
+
+ MX7D_PAD_SD2_CD_B__SD2_CD_B = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CD_B__ENET1_MDIO = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0),
+ MX7D_PAD_SD2_CD_B__ENET2_MDIO = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0),
+ MX7D_PAD_SD2_CD_B__ECSPI3_SS2 = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0),
+ MX7D_PAD_SD2_CD_B__GPIO5_IO9 = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0),
+
+ MX7D_PAD_SD2_WP__SD2_WP = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_WP__ENET1_MDC = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD2_WP__ENET2_MDC = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD2_WP__ECSPI3_SS3 = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_WP__USB_OTG1_ID = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0),
+ MX7D_PAD_SD2_WP__GPIO5_IO10 = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0),
+ MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0),
+
+ MX7D_PAD_SD2_RESET_B__SD2_RESET_B = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_RESET_B__SAI2_MCLK = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD2_RESET_B__SD2_RESET = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD2_RESET_B__ECSPI3_RDY = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_RESET_B__USB_OTG2_ID = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0),
+ MX7D_PAD_SD2_RESET_B__GPIO5_IO11 = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CLK__SAI2_RX_SYNC = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0),
+ MX7D_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CLK__GPT4_CLK = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CLK__GPIO5_IO12 = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CMD__SAI2_RX_BCLK = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0),
+ MX7D_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0),
+ MX7D_PAD_SD2_CMD__GPIO5_IO13 = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0),
+ MX7D_PAD_SD2_DATA0__UART4_DCE_RX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0),
+ MX7D_PAD_SD2_DATA0__UART4_DTE_TX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA0__GPIO5_IO14 = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0),
+ MX7D_PAD_SD2_DATA1__UART4_DCE_TX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA1__UART4_DTE_RX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0),
+ MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA1__GPIO5_IO15 = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0),
+ MX7D_PAD_SD2_DATA2__UART4_DCE_CTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA2__UART4_DTE_RTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0),
+ MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA2__GPIO5_IO16 = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA3__UART4_DCE_RTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0),
+ MX7D_PAD_SD2_DATA3__UART4_DTE_CTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0),
+ MX7D_PAD_SD2_DATA3__GPIO5_IO17 = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_CLK__NAND_CLE = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_CLK__ECSPI4_MISO = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0),
+ MX7D_PAD_SD3_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0),
+ MX7D_PAD_SD3_CLK__GPT3_CLK = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD3_CLK__GPIO6_IO0 = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_CMD__NAND_ALE = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0),
+ MX7D_PAD_SD3_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0),
+ MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD3_CMD__GPIO6_IO1 = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA0__NAND_DATA00 = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA0__ECSPI4_SS0 = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0),
+ MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0),
+ MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA0__GPIO6_IO2 = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA1__NAND_DATA01 = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0),
+ MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0),
+ MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA1__GPIO6_IO3 = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA2__NAND_DATA02 = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA2__I2C3_SDA = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0),
+ MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0),
+ MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA2__GPIO6_IO4 = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA3__NAND_DATA03 = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA3__I2C3_SCL = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0),
+ MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA3__GPIO6_IO5 = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA4__NAND_DATA04 = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA4__UART3_DCE_RX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0),
+ MX7D_PAD_SD3_DATA4__UART3_DTE_TX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA4__FLEXCAN2_RX = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0),
+ MX7D_PAD_SD3_DATA4__GPIO6_IO6 = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA5__NAND_DATA05 = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA5__UART3_DCE_TX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA5__UART3_DTE_RX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0),
+ MX7D_PAD_SD3_DATA5__FLEXCAN1_TX = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA5__GPIO6_IO7 = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA6__NAND_DATA06 = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA6__SD3_WP = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0),
+ MX7D_PAD_SD3_DATA6__UART3_DCE_RTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0),
+ MX7D_PAD_SD3_DATA6__UART3_DTE_CTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA6__FLEXCAN2_TX = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA6__GPIO6_IO8 = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA7__NAND_DATA07 = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA7__SD3_CD_B = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0),
+ MX7D_PAD_SD3_DATA7__UART3_DCE_CTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD3_DATA7__UART3_DTE_RTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0),
+ MX7D_PAD_SD3_DATA7__FLEXCAN1_RX = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0),
+ MX7D_PAD_SD3_DATA7__GPIO6_IO9 = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_STROBE__SD3_STROBE = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_STROBE__NAND_RE_B = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_STROBE__GPIO6_IO10 = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SD3_RESET_B__SD3_RESET_B = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0),
+ MX7D_PAD_SD3_RESET_B__NAND_WE_B = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0),
+ MX7D_PAD_SD3_RESET_B__SD3_RESET = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0),
+ MX7D_PAD_SD3_RESET_B__SAI3_MCLK = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0),
+ MX7D_PAD_SD3_RESET_B__GPIO6_IO11 = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0),
+ MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0),
+ MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0),
+ MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0),
+ MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0),
+ MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0),
+ MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0),
+ MX7D_PAD_SAI1_TX_SYNC__NAND_DQS = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0),
+ MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0),
+ MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_DATA__NAND_READY_B = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0),
+ MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0),
+ MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0),
+ MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0),
+ MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0),
+ MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0),
+ MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0),
+ MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0),
+ MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0),
+ MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_MCLK__NAND_WP_B = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_MCLK__SAI2_MCLK = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0),
+ MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0),
+ MX7D_PAD_SAI1_MCLK__GPIO6_IO18 = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0),
+ MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0),
+ MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0),
+ MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0),
+ MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0),
+ MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0),
+ MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0),
+ MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0),
+ MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0),
+ MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0),
+ MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0),
+ MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0),
+ MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0),
+ MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0),
+ MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0),
+ MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_RX_DATA__KPP_COL7 = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0),
+
+ MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0),
+ MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0),
+ MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0),
+ MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0),
+ MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0),
+ MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0),
+
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0),
+ MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0),
+ MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0),
+
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0),
+ MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0),
+ MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0),
+
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0),
+ MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0),
+ MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0),
+ MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0),
+
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0),
+ MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0),
+ MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0),
+
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0),
+
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0),
+
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0),
+
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0),
+
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0),
+ MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0),
+ MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0),
+ MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0),
+ MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0),
+ MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0),
+
+ MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0),
+ MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0),
+ MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0),
+ MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0),
+ MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0),
+ MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0),
+ MX7D_PAD_ENET1_RX_CLK__GPT2_CLK = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0),
+ MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0),
+ MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_CRS__GPIO7_IO14 = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0),
+ MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0),
+
+ MX7D_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_COL__GPIO7_IO15 = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0),
+ MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0),
+ MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_IMX7D_PINS_H__ */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __SYS_PROTO_H__
-#define __SYS_PROTO_H__
+#ifndef __MXS_SYS_PROTO_H__
+#define __MXS_SYS_PROTO_H__
-#include <asm/imx-common/regs-common.h>
-
-int mxs_reset_block(struct mxs_register_32 *reg);
-int mxs_wait_mask_set(struct mxs_register_32 *reg,
- uint32_t mask,
- unsigned int timeout);
-int mxs_wait_mask_clr(struct mxs_register_32 *reg,
- uint32_t mask,
- unsigned int timeout);
+#include <asm/imx-common/sys_proto.h>
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
/*
* Section
*/
+#define PMD_SECT_NON_SHARE (0 << 8)
#define PMD_SECT_OUTER_SHARE (2 << 8)
#define PMD_SECT_INNER_SHARE (3 << 8)
#define PMD_SECT_AF (1 << 10)
TCR_T0SZ(VA_BITS))
#ifndef __ASSEMBLY__
+
void set_pgtable_section(u64 *page_table, u64 index,
- u64 section, u64 memory_type);
+ u64 section, u64 memory_type,
+ u64 share);
+void set_pgtable_table(u64 *page_table, u64 index,
+ u64 *table_addr);
+
static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
asm volatile("dsb sy");
#define __FSL_SECURE_BOOT_H
#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_DM
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+
+#define CONFIG_KEY_REVOCATION
+#ifndef CONFIG_SYS_RAMBOOT
+/* The key used for verification of next level images
+ * is picked up from an Extension Table which has
+ * been verified by the ISBC (Internal Secure boot Code)
+ * in boot ROM of the SoC.
+ * The feature is only applicable in case of NOR boot and is
+ * not applicable in case of RAMBOOT (NAND, SD, SPI).
+ */
+#define CONFIG_FSL_ISBC_KEY_EXT
+#endif
+
#ifndef CONFIG_FIT_SIGNATURE
#define CONFIG_EXTRA_ENV \
#define NO_PAD_CTRL (1 << 17)
+#ifdef CONFIG_MX7
+
+#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
+#define IOMUX_CONFIG_LPSR 0x8
+#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
+ MUX_MODE_SHIFT)
+
+#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
+#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
+#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0)
+#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0)
+
+#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0)
+#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0)
+#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0)
+#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0)
+
+#define PAD_CTL_SRE_FAST (0 << 2)
+#define PAD_CTL_SRE_SLOW (0x1 << 2)
+
+#define PAD_CTL_HYS (0x1 << 3)
+#define PAD_CTL_PUE (0x1 << 4)
+
+#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE)
+
+#else
+
#ifdef CONFIG_MX6
#define PAD_CTL_HYS (1 << 16)
#define PAD_CTL_SRE_SLOW (0 << 0)
#define PAD_CTL_SRE_FAST (1 << 0)
+#endif
+
#define IOMUX_CONFIG_SION 0x10
#define GPIO_PIN_MASK 0x1f
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/imx-common/regs-common.h>
+#include <common.h>
+#include "../arch-imx/cpu.h"
+
+#define soc_rev() (get_cpu_rev() & 0xFF)
+#define is_soc_rev(rev) (soc_rev() == rev)
+
+/* returns MXC_CPU_ value */
+#define cpu_type(rev) (((rev) >> 12) & 0xff)
+/* both macros return/take MXC_CPU_ constants */
+#define get_cpu_type() (cpu_type(get_cpu_rev()))
+#define is_cpu_type(cpu) (get_cpu_type() == cpu)
+
+#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
+
+u32 get_nr_cpus(void);
+u32 get_cpu_rev(void);
+u32 get_cpu_speed_grade_hz(void);
+u32 get_cpu_temp_grade(int *minc, int *maxc);
+const char *get_imx_type(u32 imxtype);
+u32 imx_ddr_size(void);
+void sdelay(unsigned long);
+void set_chipselect_size(int const);
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+#endif
ifdef CONFIG_CPU_V7M
obj-y += interrupts_m.o
else ifdef CONFIG_ARM64
+obj-y += ccn504.o
obj-y += gic_64.o
obj-y += interrupts_64.o
else
--- /dev/null
+/*
+ * (C) Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Extracted from gic_64.S
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+/*************************************************************************
+ *
+ * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
+ * CCI_MN_DVM_DOMAIN_CTL_SET);
+ *
+ * Add fully-coherent masters to DVM domain
+ *
+ *************************************************************************/
+ENTRY(ccn504_add_masters_to_dvm)
+ /*
+ * x0: CCI_MN_BASE
+ * x1: CCI_MN_RNF_NODEID_LIST
+ * x2: CCI_MN_DVM_DOMAIN_CTL_SET
+ */
+
+ /* Add fully-coherent masters to DVM domain */
+ ldr x9, [x0, x1]
+ str x9, [x0, x2]
+1: ldr x10, [x0, x2]
+ mvn x11, x10
+ tst x11, x10 /* Wait for domain addition to complete */
+ b.ne 1b
+
+ ret
+ENDPROC(ccn504_add_masters_to_dvm)
+
+/*************************************************************************
+ *
+ * void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value);
+ *
+ * Initialize QoS settings for AR/AW override.
+ * Right now, this function sets the same QoS value for all RN-I ports
+ *
+ *************************************************************************/
+ENTRY(ccn504_set_qos)
+ /*
+ * x0: CCI_Sx_QOS_CONTROL_BASE
+ * x1: QoS Value
+ */
+
+ /* Set all RN-I ports to QoS value denoted by x1 */
+ ldr x9, [x0]
+ mov x10, x1
+ orr x9, x9, x10
+ str x9, [x0]
+
+ ret
+ENDPROC(ccn504_set_qos)
+
#define CONFIG_FSL_TRUST_ARCH_v1
#endif
-#if defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
/* The key used for verification of next level images
* is picked up from an Extension Table which has
* been verified by the ISBC (Internal Secure boot Code)
- * in boot ROM of the SoC
+ * in boot ROM of the SoC.
+ * The feature is only applicable in case of NOR boot and is
+ * not applicable in case of RAMBOOT (NAND, SD, SPI).
*/
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
default "aristainetos2"
endif
+
+if TARGET_ARISTAINETOS2B
+
+config SYS_BOARD
+ default "aristainetos"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "aristainetos2b"
+
+endif
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
- ret = enable_fec_anatop_clock(ENET_50MHZ);
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
if (ret)
return ret;
#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-#define ECSPI1_CS0 IMX_GPIO_NR(4, 9) /* 4.3 display controller */
-#define ECSPI4_CS0 IMX_GPIO_NR(3, 29)
+#if (CONFIG_SYS_BOARD_VERSION == 2)
+ /* 4.3 display controller */
+ #define ECSPI1_CS0 IMX_GPIO_NR(4, 9)
+ #define ECSPI4_CS0 IMX_GPIO_NR(3, 29)
+#elif (CONFIG_SYS_BOARD_VERSION == 3)
+ #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */
+ /* 4.3 display controller */
+ #define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
+#endif
+
#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13)
#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8)
/* LED yellow */
MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED red */
+#if (CONFIG_SYS_BOARD_VERSION == 2)
MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#elif (CONFIG_SYS_BOARD_VERSION == 3)
+ MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#endif
/* LED green */
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED blue */
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+#if (CONFIG_SYS_BOARD_VERSION == 2)
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+#elif (CONFIG_SYS_BOARD_VERSION == 3)
+ MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#endif
};
static void setup_iomux_enet(void)
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
+#if (CONFIG_SYS_BOARD_VERSION == 2)
iomux_v3_cfg_t const ecspi4_pads[] = {
MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+#endif
static iomux_v3_cfg_t const display_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
- MX6_PAD_DI0_PIN4__GPIO4_IO20,
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+#if (CONFIG_SYS_BOARD_VERSION == 2)
return IMX_GPIO_NR(5, 2);
if (bus == 0 && cs == 0)
return IMX_GPIO_NR(4, 9);
+#elif (CONFIG_SYS_BOARD_VERSION == 3)
+ return ECSPI1_CS0;
+ if (bus == 0 && cs == 1)
+ return ECSPI1_CS1;
+#endif
return -1;
}
int i;
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+
+#if (CONFIG_SYS_BOARD_VERSION == 2)
imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
+#endif
+
for (i = 0; i < 4; i++)
enable_spi_clk(true, i);
gpio_direction_output(ECSPI1_CS0, 1);
+#if (CONFIG_SYS_BOARD_VERSION == 2)
gpio_direction_output(ECSPI4_CS1, 0);
-
/* set cs0 to high (second device on spi bus #4) */
gpio_direction_output(ECSPI4_CS0, 1);
+#elif (CONFIG_SYS_BOARD_VERSION == 3)
+ gpio_direction_output(ECSPI1_CS1, 1);
+#endif
}
static void setup_iomux_uart(void)
gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
/* switch off Status LEDs */
+#if (CONFIG_SYS_BOARD_VERSION == 2)
gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
+#elif (CONFIG_SYS_BOARD_VERSION == 3)
+ gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
+ gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
+ gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */
+ gpio_direction_output(IMX_GPIO_NR(5, 0), 0);
+ gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+ gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
+ gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
+#endif
}
static void setup_board_spi(void)
{
- /* enable spi bus #2 SS drivers */
+ /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
}
/* if we have the lg panel, we can initialze it now */
if (panel)
if (!strcmp(panel, displays[1].mode.name))
- lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0);
+ lg4573_spi_startup(CONFIG_LG4573_BUS,
+ CONFIG_LG4573_CS,
+ 10000000, SPI_MODE_0);
return 0;
}
-
#if (CONFIG_SYS_BOARD_VERSION == 1)
#include "./aristainetos-v1.c"
-#elif (CONFIG_SYS_BOARD_VERSION == 2)
+#elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
#include "./aristainetos-v2.c"
#endif
.refresh = 60,
.xres = 800,
.yres = 480,
- .pixclock = 33246,
+ .pixclock = 30066,
.left_margin = 88,
.right_margin = 88,
- .upper_margin = 10,
- .lower_margin = 10,
+ .upper_margin = 20,
+ .lower_margin = 20,
.hsync_len = 80,
- .vsync_len = 25,
- .sync = 0,
+ .vsync_len = 5,
+ .sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
}
}
-#if (CONFIG_SYS_BOARD_VERSION == 2)
+#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
, {
.bus = -1,
.addr = 0,
.enable = enable_spi_display,
.mode = {
.name = "lg4573",
- .refresh = 60,
+ .refresh = 57,
.xres = 480,
.yres = 800,
.pixclock = 37037,
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
- return enable_fec_anatop_clock(ENET_50MHZ);
+ return enable_fec_anatop_clock(0, ENET_50MHZ);
}
int platinum_setup_i2c(void)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
};
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
};
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
NITROGEN6X BOARD
-M: Eric Nelson <eric.nelson@boundarydevices.com>
+M: Troy Kisky <troy.kisky@boundarydevices.com>
S: Maintained
F: board/boundary/nitrogen6x/
F: include/configs/nitrogen6x.h
#include <miiphy.h>
#include <netdev.h>
#include <errno.h>
+#include <usb.h>
#include <fdt_support.h>
#include <sata.h>
#include <splash.h>
return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
}
+int board_usb_phy_mode(int port)
+{
+ return USB_INIT_HOST;
+}
+
int board_ehci_hcd_init(int port)
{
int ret;
return 0;
}
+int misc_init_r(void)
+{
+ cl_print_pcb_info();
+
+ return 0;
+}
+
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
#include <power/pfuze100_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <micrel.h>
DECLARE_GLOBAL_DATA_PTR;
#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+static iomux_v3_cfg_t enet_pads_ksz9031[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t enet_pads_ar8035[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+ unsigned short id1, id2;
+ int ret;
+
+ iomux_v3_cfg_t enet_reset = MX6_PAD_EIM_D23__GPIO3_IO23 |
+ MUX_PAD_CTRL(NO_PAD_CTRL);
+
+ /* check whether KSZ9031 or AR8035 has to be configured */
+ imx_iomux_v3_setup_multiple_pads(enet_pads_ar8035,
+ ARRAY_SIZE(enet_pads_ar8035));
+ imx_iomux_v3_setup_pad(enet_reset);
+
+ /* phy reset */
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+ udelay(2000);
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+ udelay(500);
+
+ bus = fec_get_miibus(IMX_FEC_BASE, -1);
+ if (!bus)
+ return -EINVAL;
+ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ printf("Error: phy device not found.\n");
+ ret = -ENODEV;
+ goto free_bus;
+ }
+
+ /* get the PHY id */
+ id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
+ id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
+
+ if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
+ /* re-configure for Micrel KSZ9031 */
+ printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
+ phydev->addr);
+
+ /* phy reset: gpio3-23 */
+ gpio_set_value(IMX_GPIO_NR(3, 23), 0);
+ gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
+ gpio_set_value(IMX_GPIO_NR(6, 25), 1);
+ gpio_set_value(IMX_GPIO_NR(6, 27), 1);
+ gpio_set_value(IMX_GPIO_NR(6, 28), 1);
+ gpio_set_value(IMX_GPIO_NR(6, 29), 1);
+ imx_iomux_v3_setup_multiple_pads(enet_pads_ksz9031,
+ ARRAY_SIZE(enet_pads_ksz9031));
+ gpio_set_value(IMX_GPIO_NR(6, 24), 1);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+ imx_iomux_v3_setup_multiple_pads(enet_pads_final_ksz9031,
+ ARRAY_SIZE(enet_pads_final_ksz9031));
+ } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
+ /* configure Atheros AR8035 - actually nothing to do */
+ printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
+ phydev->addr);
+ } else {
+ printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
+ ret = -EINVAL;
+ goto free_phydev;
+ }
+
+ ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
+ if (ret)
+ goto free_phydev;
+
+ return 0;
+
+free_phydev:
+ free(phydev);
+free_bus:
+ free(bus);
+ return ret;
+}
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short id1, id2;
+ unsigned short val;
+
+ /* check whether KSZ9031 or AR8035 has to be configured */
+ id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
+ id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
+
+ if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
+ /* finalize phy configuration for Micrel KSZ9031 */
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
+
+ /* fix KSZ9031 link up issue */
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
+ }
+
+ if ((id1 == 0x004d) && (id2 == 0xd072)) {
+ /* enable AR8035 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
+ val &= 0xfe63;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ /* disable hibernation */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
+ }
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
static void setup_iomux_uart(void)
{
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/arch/ls102xa_devdis.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
#include <spl.h>
+#include <fsl_devdis.h>
#include "../common/sleep.h"
#include "../common/qixis.h"
unsigned int major;
#ifdef CONFIG_TSEC_ENET
- out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ /* clear BD & FR bits for BE BD's and frame data */
+ clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
#endif
#ifdef CONFIG_FSL_IFC
else if (hwconfig("sdhc"))
config_board_mux(MUX_TYPE_SDHC);
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+ device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+#endif
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/arch/ls102xa_devdis.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <fsl_sec.h>
+#include <fsl_devdis.h>
#include <spl.h>
#include "../common/sleep.h"
#ifdef CONFIG_U_QE
unsigned int major;
#ifdef CONFIG_TSEC_ENET
- out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ /* clear BD & FR bits for BE BD's and frame data */
+ clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+ device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+#endif
#ifndef CONFIG_QSPI_BOOT
config_board_mux();
#endif
F: board/freescale/ls2085a/
F: include/configs/ls2085a_emu.h
F: configs/ls2085a_emu_defconfig
-F: configs/ls2085a_emu_D4_defconfig
F: include/configs/ls2085a_simu.h
F: configs/ls2085a_simu_defconfig
earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
hugepages=16 mem=2048M'
+
+X-QSGMII-16PORT riser card
+----------------------------
+The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
+interfaces implemented in PCIe form factor board.
+It supports followings
+ - Card can operate with up to 4 QSGMII lane simultaneously
+ - Card can operate with up to 8 SGMII lane simultaneously
+
+Supported card configuration
+ - CSEL : ON ON ON ON
+ - MSEL1 : ON ON ON ON OFF OFF OFF OFF
+ - MSEL2 : OFF OFF OFF OFF ON ON ON ON
+
+To enable this card: modify hwconfig to add "xqsgmii" variable.
+
+Supported PHY addresses during SGMII:
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+
+Mapping DPMACx to PHY during QSGMII
+DPMAC1 -> PHY1-P0
+DPMAC2 -> PHY2-P0
+DPMAC3 -> PHY3-P0
+DPMAC4 -> PHY4-P0
+DPMAC5 -> PHY3-P2
+DPMAC6 -> PHY1-P2
+DPMAC7 -> PHY4-P1
+DPMAC8 -> PHY2-P2
+DPMAC9 -> PHY1-P0
+DPMAC10 -> PHY2-P0
+DPMAC11 -> PHY3-P0
+DPMAC12 -> PHY4-P0
+DPMAC13 -> PHY3-P2
+DPMAC14 -> PHY1-P2
+DPMAC15 -> PHY4-P1
+DPMAC16 -> PHY2-P2
+
+
+Supported PHY address during QSGMII
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
+Mapping DPMACx to PHY during QSGMII
+DPMAC1 -> PHY1-P3
+DPMAC2 -> PHY1-P2
+DPMAC3 -> PHY1-P1
+DPMAC4 -> PHY1-P0
+DPMAC5 -> PHY2-P3
+DPMAC6 -> PHY2-P2
+DPMAC7 -> PHY2-P1
+DPMAC8 -> PHY2-P0
+DPMAC9 -> PHY3-P0
+DPMAC10 -> PHY3-P1
+DPMAC11 -> PHY3-P2
+DPMAC12 -> PHY3-P3
+DPMAC13 -> PHY4-P0
+DPMAC14 -> PHY4-P1
+DPMAC15 -> PHY4-P2
+DPMAC16 -> PHY4-P3
+
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <hwconfig.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fm_eth.h>
+#include <i2c.h>
+#include <miiphy.h>
#include <fsl-mc/ldpaa_wriop.h>
#include "../common/qixis.h"
* maps to something other than a board slot.
*/
+static u8 lane_to_slot_fsm1[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
static u8 lane_to_slot_fsm2[] = {
0, 0, 0, 0, 0, 0, 0, 0
};
/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
* housed.
*/
-static int riser_phy_addr[] = {
+
+static int xqsgii_riser_phy_addr[] = {
+ XQSGMII_CARD_PHY1_PORT0_ADDR,
+ XQSGMII_CARD_PHY2_PORT0_ADDR,
+ XQSGMII_CARD_PHY3_PORT0_ADDR,
+ XQSGMII_CARD_PHY4_PORT0_ADDR,
+ XQSGMII_CARD_PHY3_PORT2_ADDR,
+ XQSGMII_CARD_PHY1_PORT2_ADDR,
+ XQSGMII_CARD_PHY4_PORT2_ADDR,
+ XQSGMII_CARD_PHY2_PORT2_ADDR,
+};
+
+static int sgmii_riser_phy_addr[] = {
SGMII_CARD_PORT1_PHY_ADDR,
SGMII_CARD_PORT2_PHY_ADDR,
SGMII_CARD_PORT3_PHY_ADDR,
struct mii_dev *realbus;
};
+static void sgmii_configure_repeater(int serdes_port)
+{
+ struct mii_dev *bus;
+ uint8_t a = 0xf;
+ int i, j, ret;
+ int dpmac_id = 0, dpmac, mii_bus = 0;
+ unsigned short value;
+ char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"};
+ uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
+
+ uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+ int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
+
+ /* Set I2c to Slot 1 */
+ i2c_write(0x77, 0, 0, &a, 1);
+
+ for (dpmac = 0; dpmac < 8; dpmac++) {
+ /* Check the PHY status */
+ switch (serdes_port) {
+ case 1:
+ mii_bus = 0;
+ dpmac_id = dpmac + 1;
+ break;
+ case 2:
+ mii_bus = 1;
+ dpmac_id = dpmac + 9;
+ a = 0xb;
+ i2c_write(0x76, 0, 0, &a, 1);
+ break;
+ }
+
+ ret = miiphy_set_current_dev(dev[mii_bus]);
+ if (ret > 0)
+ goto error;
+
+ bus = mdio_get_current_dev();
+ debug("Reading from bus %s\n", bus->name);
+
+ ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
+ 3);
+ if (ret > 0)
+ goto error;
+
+ mdelay(10);
+ ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
+ &value);
+ if (ret > 0)
+ goto error;
+
+ mdelay(10);
+
+ if ((value & 0xfff) == 0x40f) {
+ printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
+ continue;
+ }
+
+ for (i = 0; i < 4; i++) {
+ for (j = 0; j < 4; j++) {
+ a = 0x18;
+ i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
+ a = 0x38;
+ i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
+ a = 0x4;
+ i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
+
+ i2c_write(i2c_addr[dpmac], 0xf, 1,
+ &ch_a_eq[i], 1);
+ i2c_write(i2c_addr[dpmac], 0x11, 1,
+ &ch_a_ctl2[j], 1);
+
+ i2c_write(i2c_addr[dpmac], 0x16, 1,
+ &ch_b_eq[i], 1);
+ i2c_write(i2c_addr[dpmac], 0x18, 1,
+ &ch_b_ctl2[j], 1);
+
+ a = 0x14;
+ i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
+ a = 0xb5;
+ i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
+ a = 0x20;
+ i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
+ mdelay(100);
+ ret = miiphy_read(dev[mii_bus],
+ riser_phy_addr[dpmac],
+ 0x11, &value);
+ if (ret > 0)
+ goto error;
+
+ mdelay(1);
+ ret = miiphy_read(dev[mii_bus],
+ riser_phy_addr[dpmac],
+ 0x11, &value);
+ if (ret > 0)
+ goto error;
+ mdelay(10);
+
+ if ((value & 0xfff) == 0x40f) {
+ printf("DPMAC %d :PHY is configured ",
+ dpmac_id);
+ printf("after setting repeater 0x%x\n",
+ value);
+ i = 5;
+ j = 5;
+ } else
+ printf("DPMAC %d :PHY is failed to ",
+ dpmac_id);
+ printf("configure the repeater 0x%x\n",
+ value);
+ }
+ }
+ }
+error:
+ if (ret)
+ printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
+ return;
+}
+
+static void qsgmii_configure_repeater(int dpmac)
+{
+ uint8_t a = 0xf;
+ int i, j;
+ int i2c_phy_addr = 0;
+ int phy_addr = 0;
+ int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
+
+ uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+ const char *dev = "LS2085A_QDS_MDIO0";
+ int ret = 0;
+ unsigned short value;
+
+ /* Set I2c to Slot 1 */
+ i2c_write(0x77, 0, 0, &a, 1);
+
+ switch (dpmac) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ i2c_phy_addr = i2c_addr[0];
+ phy_addr = 0;
+ break;
+
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ i2c_phy_addr = i2c_addr[1];
+ phy_addr = 4;
+ break;
+
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ i2c_phy_addr = i2c_addr[2];
+ phy_addr = 8;
+ break;
+
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ i2c_phy_addr = i2c_addr[3];
+ phy_addr = 0xc;
+ break;
+ }
+
+ /* Check the PHY status */
+ ret = miiphy_set_current_dev(dev);
+ ret = miiphy_write(dev, phy_addr, 0x1f, 3);
+ mdelay(10);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ mdelay(10);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ mdelay(10);
+ if ((value & 0xf) == 0xf) {
+ printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
+ return;
+ }
+
+ for (i = 0; i < 4; i++) {
+ for (j = 0; j < 4; j++) {
+ a = 0x18;
+ i2c_write(i2c_phy_addr, 6, 1, &a, 1);
+ a = 0x38;
+ i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ a = 0x4;
+ i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+
+ i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
+ i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
+
+ i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
+ i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
+
+ a = 0x14;
+ i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
+ a = 0xb5;
+ i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
+ a = 0x20;
+ i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ mdelay(100);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+ mdelay(1);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+ mdelay(10);
+ if ((value & 0xf) == 0xf) {
+ printf("DPMAC %d :PHY is ..... Configured\n",
+ dpmac);
+ return;
+ }
+ }
+ }
+error:
+ printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
+ return;
+}
+
static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+ char *env_hwconfig;
+ env_hwconfig = getenv("hwconfig");
switch (serdes1_prtcl) {
+ case 0x07:
+ case 0x09:
+ case 0x33:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ lane_to_slot_fsm1[0] = EMI1_SLOT1;
+ lane_to_slot_fsm1[1] = EMI1_SLOT1;
+ lane_to_slot_fsm1[2] = EMI1_SLOT1;
+ lane_to_slot_fsm1[3] = EMI1_SLOT1;
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm1[4] = EMI1_SLOT1;
+ lane_to_slot_fsm1[5] = EMI1_SLOT1;
+ lane_to_slot_fsm1[6] = EMI1_SLOT1;
+ lane_to_slot_fsm1[7] = EMI1_SLOT1;
+ } else {
+ lane_to_slot_fsm1[4] = EMI1_SLOT2;
+ lane_to_slot_fsm1[5] = EMI1_SLOT2;
+ lane_to_slot_fsm1[6] = EMI1_SLOT2;
+ lane_to_slot_fsm1[7] = EMI1_SLOT2;
+ }
+ break;
+
case 0x2A:
- printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
break;
default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+ printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
break;
}
switch (serdes2_prtcl) {
case 0x07:
case 0x08:
+ case 0x09:
case 0x49:
- printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
+ printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
lane_to_slot_fsm2[0] = EMI1_SLOT4;
lane_to_slot_fsm2[1] = EMI1_SLOT4;
lane_to_slot_fsm2[2] = EMI1_SLOT4;
lane_to_slot_fsm2[3] = EMI1_SLOT4;
- /* No MDIO physical connection */
- lane_to_slot_fsm2[4] = EMI1_SLOT6;
- lane_to_slot_fsm2[5] = EMI1_SLOT6;
- lane_to_slot_fsm2[6] = EMI1_SLOT6;
- lane_to_slot_fsm2[7] = EMI1_SLOT6;
+
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm2[4] = EMI1_SLOT4;
+ lane_to_slot_fsm2[5] = EMI1_SLOT4;
+ lane_to_slot_fsm2[6] = EMI1_SLOT4;
+ lane_to_slot_fsm2[7] = EMI1_SLOT4;
+ } else {
+ /* No MDIO physical connection */
+ lane_to_slot_fsm2[4] = EMI1_SLOT6;
+ lane_to_slot_fsm2[5] = EMI1_SLOT6;
+ lane_to_slot_fsm2[6] = EMI1_SLOT6;
+ lane_to_slot_fsm2[7] = EMI1_SLOT6;
+ }
break;
default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+ printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
break;
}
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+ int *riser_phy_addr;
+ char *env_hwconfig = getenv("hwconfig");
+
+ if (hwconfig_f("xqsgmii", env_hwconfig))
+ riser_phy_addr = &xqsgii_riser_phy_addr[0];
+ else
+ riser_phy_addr = &sgmii_riser_phy_addr[0];
+
+ if (dpmac_id > WRIOP1_DPMAC9)
+ goto serdes2;
+
switch (serdes1_prtcl) {
+ case 0x07:
+
+ lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
+ slot = lane_to_slot_fsm1[lane];
+
+ switch (++slot) {
+ case 1:
+ /* Slot housing a SGMII riser card? */
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 1]);
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+ bus = mii_dev_for_muxval(EMI1_SLOT1);
+ wriop_set_mdio(dpmac_id, bus);
+ dpmac_info[dpmac_id].phydev = phy_connect(
+ dpmac_info[dpmac_id].bus,
+ dpmac_info[dpmac_id].phy_addr,
+ NULL,
+ dpmac_info[dpmac_id].enet_if);
+ phy_config(dpmac_info[dpmac_id].phydev);
+ break;
+ case 2:
+ /* Slot housing a SGMII riser card? */
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 1]);
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
+ bus = mii_dev_for_muxval(EMI1_SLOT2);
+ wriop_set_mdio(dpmac_id, bus);
+ dpmac_info[dpmac_id].phydev = phy_connect(
+ dpmac_info[dpmac_id].bus,
+ dpmac_info[dpmac_id].phy_addr,
+ NULL,
+ dpmac_info[dpmac_id].enet_if);
+ phy_config(dpmac_info[dpmac_id].phydev);
+ break;
+ case 3:
+ break;
+ case 4:
+ break;
+ case 5:
+ break;
+ case 6:
+ break;
+ }
+ break;
+ default:
+ printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
}
+serdes2:
switch (serdes2_prtcl) {
case 0x07:
case 0x08:
}
break;
default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+ printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
break;
}
}
+
+void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
+{
+ int lane = 0, slot;
+ struct mii_dev *bus;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ switch (serdes1_prtcl) {
+ case 0x33:
+ switch (dpmac_id) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
+ break;
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
+ break;
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
+ break;
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
+ break;
+ }
+
+ slot = lane_to_slot_fsm1[lane];
+
+ switch (++slot) {
+ case 1:
+ /* Slot housing a QSGMII riser card? */
+ wriop_set_phy_address(dpmac_id, dpmac_id - 1);
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+ bus = mii_dev_for_muxval(EMI1_SLOT1);
+ wriop_set_mdio(dpmac_id, bus);
+ dpmac_info[dpmac_id].phydev = phy_connect(
+ dpmac_info[dpmac_id].bus,
+ dpmac_info[dpmac_id].phy_addr,
+ NULL,
+ dpmac_info[dpmac_id].enet_if);
+
+ phy_config(dpmac_info[dpmac_id].phydev);
+ break;
+ case 3:
+ break;
+ case 4:
+ break;
+ case 5:
+ break;
+ case 6:
+ break;
+ }
+ break;
+ default:
+ printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+
+ qsgmii_configure_repeater(dpmac_id);
+}
+
void ls2085a_handle_phy_interface_xsgmii(int i)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
{
int error;
#ifdef CONFIG_FSL_MC_ENET
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+ int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
struct memac_mdio_info *memac_mdio0_info;
struct memac_mdio_info *memac_mdio1_info;
unsigned int i;
+ char *env_hwconfig;
+
+ env_hwconfig = getenv("hwconfig");
initialize_dpmac_to_slot();
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
+ ls2085a_handle_phy_interface_qsgmii(i);
break;
case PHY_INTERFACE_MODE_SGMII:
ls2085a_handle_phy_interface_sgmii(i);
break;
default:
break;
+
+ if (i == 16)
+ i = NUM_WRIOP_PORTS;
}
}
error = cpu_eth_init(bis);
+
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ if (serdes1_prtcl == 0x7)
+ sgmii_configure_repeater(1);
+ if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
+ serdes2_prtcl == 0x49)
+ sgmii_configure_repeater(2);
+ }
#endif
error = pci_eth_init(bis);
return error;
}
+
+#ifdef CONFIG_FSL_MC_ENET
+
+#endif
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <i2c.h>
+#include <rtc.h>
#include <asm/arch-fsl-lsch3/soc.h>
#include <hwconfig.h>
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ rtc_enable_32khz_output();
return 0;
}
* select ENET MAC0 TX clock from PLL
*/
imx_iomux_set_gpr_register(5, 9, 1, 1);
- enable_fec_anatop_clock(ENET_125MHZ);
+ enable_fec_anatop_clock(0, ENET_125MHZ);
}
setup_iomux_enet();
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
};
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
+#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
int board_mmc_init(bd_t *bis)
{
+#ifndef CONFIG_SPL_BUILD
int i, ret;
/*
}
return 0;
+#else
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 val;
+ u32 port;
+
+ val = readl(&src_regs->sbmr1);
+
+ /* Boot from USDHC */
+ port = (val >> 11) & 0x3;
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+ ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+ ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+ ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ }
+
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
}
#ifdef CONFIG_SYS_I2C_MXC
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
- return enable_fec_anatop_clock(ENET_50MHZ);
+ return enable_fec_anatop_clock(0, ENET_50MHZ);
}
#endif
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_sdqs0 = 0x00003030,
+ .dram_sdqs1 = 0x00003030,
+ .dram_sdqs2 = 0x00003030,
+ .dram_sdqs3 = 0x00003030,
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_dqm2 = 0x00000030,
+ .dram_dqm3 = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_sdclk_0 = 0x00000028,
+ .dram_reset = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_odt0 = 0x00000008,
+ .dram_odt1 = 0x00000008,
+};
+
+const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_addds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x00080000,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpdgctrl0 = 0x20000000,
+ .p0_mpdgctrl1 = 0x00000000,
+ .p0_mprddlctl = 0x4241444a,
+ .p0_mpwrdlctl = 0x3030312b,
+ .mpzqlp2ctl = 0x1b4700c7,
+};
+
+static struct mx6_lpddr2_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 32,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .trcd_lp = 2000,
+ .trppb_lp = 2000,
+ .trpab_lp = 2250,
+ .trasmin = 4200,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+
+ writel(0x00260324, &ccm->cbcmr);
+}
+
+static void spl_dram_init(void)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ .dsize = mem_ddr.width / 32,
+ .cs_density = 20,
+ .ncs = 2,
+ .cs1_mirror = 0,
+ .walat = 0,
+ .ralat = 2,
+ .mif3_mode = 3,
+ .bi_on = 1,
+ .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
+ .rtt_nom = 0,
+ .sde_to_rst = 0, /* LPDDR2 does not need this field */
+ .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
+ .ddr_type = DDR_TYPE_LPDDR2,
+ };
+ mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
- return enable_fec_anatop_clock(ENET_125MHZ);
+ return enable_fec_anatop_clock(0, ENET_125MHZ);
}
int board_eth_init(bd_t *bis)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
};
mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
#include <common.h>
#include <fsl_esdhc.h>
#include <i2c.h>
+#include <miiphy.h>
#include <linux/sizes.h>
#include <mmc.h>
+#include <netdev.h>
#include <usb.h>
#include <usb/ehci-fsl.h>
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+
#define IOX_SDI IMX_GPIO_NR(5, 10)
#define IOX_STCP IMX_GPIO_NR(5, 7)
#define IOX_SHCP IMX_GPIO_NR(5, 11)
}
#endif
+#ifdef CONFIG_FEC_MXC
+/*
+ * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
+ * be used for ENET1 or ENET2, cannot be used for both.
+ */
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+ MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+ MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+ MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(int fec_id)
+{
+ if (fec_id == 0)
+ imx_iomux_v3_setup_multiple_pads(fec1_pads,
+ ARRAY_SIZE(fec1_pads));
+ else
+ imx_iomux_v3_setup_multiple_pads(fec2_pads,
+ ARRAY_SIZE(fec2_pads));
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_fec(CONFIG_FEC_ENET_DEV);
+
+ return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+}
+
+static int setup_fec(int fec_id)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ if (fec_id == 0) {
+ /*
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+ } else {
+ /*
+ * Use 50M anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+ }
+
+ ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ enable_enet_clk(1);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
int board_early_init_f(void)
{
setup_iomux_uart();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
+#ifdef CONFIG_FEC_MXC
+ setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
};
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.pd_fast_exit = 1, /* enable precharge power-down fast exit */
+ .ddr_type = DDR_TYPE_DDR3,
};
/*
struct mii_dev *bus;
struct phy_device *phydev;
- int ret = enable_fec_anatop_clock(ENET_25MHZ);
+ int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
if (ret)
return ret;
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
};
if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))
config SYS_VENDOR
default "tbs"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "tbs2910"
+config MX6Q
+ default y
+
+config IMX_CONFIG
+ default "board/boundary/nitrogen6x/nitrogen6q2g.cfg"
+
endif
--- /dev/null
+if TARGET_TS4800
+
+config SYS_BOARD
+ default "ts4800"
+
+config SYS_VENDOR
+ default "technologic"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "ts4800"
+
+endif
--- /dev/null
+TS4800 BOARD
+M: Lucile Quirion <lucile.quirion@savoirfairelinux.com>
+S: Maintained
+F: board/ts/ts4800/
+F: include/configs/ts4800.h
+F: configs/ts4800_defconfig
--- /dev/null
+#
+# (C) Copyright 2015 Savoir-faire Linux
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ts4800.o
--- /dev/null
+/*
+ * (C) Copyright 2015 Savoir-faire Linux Inc.
+ *
+ * Derived from MX51EVK code by
+ * Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx51.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/imx-common/mx5_video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <mc13892.h>
+
+#include <malloc.h>
+#include <netdev.h>
+#include <phy.h>
+#include "ts4800.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC2_BASE_ADDR},
+};
+#endif
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ u32 rev = get_cpu_rev();
+ if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
+ rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
+ return rev;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
+ PAD_CTL_HYS |
+ PAD_CTL_PUS_22K_UP |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ MX51_PAD_EIM_EB3__FEC_RDATA1,
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
+ MX51_PAD_EIM_CS3__FEC_RDATA3,
+ MX51_PAD_NANDF_CS2__FEC_TX_ER,
+ MX51_PAD_EIM_CS5__FEC_CRS,
+ MX51_PAD_EIM_CS4__FEC_RX_ER,
+ /* PAD used on TS4800 */
+ MX51_PAD_DI2_PIN2__FEC_MDC,
+ MX51_PAD_DISP2_DAT14__FEC_RDAT0,
+ MX51_PAD_DISP2_DAT10__FEC_COL,
+ MX51_PAD_DISP2_DAT11__FEC_RXCLK,
+ MX51_PAD_DISP2_DAT15__FEC_TDAT0,
+ MX51_PAD_DISP2_DAT6__FEC_TDAT1,
+ MX51_PAD_DISP2_DAT7__FEC_TDAT2,
+ MX51_PAD_DISP2_DAT8__FEC_TDAT3,
+ MX51_PAD_DISP2_DAT9__FEC_TX_EN,
+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
+ MX51_PAD_DISP2_DAT12__FEC_RX_DV,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
+ NO_PAD_CTRL));
+ gpio_direction_input(IMX_GPIO_NR(1, 0));
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+ NO_PAD_CTRL));
+ gpio_direction_input(IMX_GPIO_NR(1, 6));
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
+ else
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+ };
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+/*
+ * Read the MAC address from FEC's registers PALR PAUR.
+ * User is supposed to configure these registers when MAC address is known
+ * from another source (fuse), but on TS4800, MAC address is not fused and
+ * the bootrom configure these registers on startup.
+ */
+static int fec_get_mac_from_register(uint32_t base_addr)
+{
+ unsigned char ethaddr[6];
+ u32 reg_mac[2];
+ int i;
+
+ reg_mac[0] = in_be32(base_addr + 0xE4);
+ reg_mac[1] = in_be32(base_addr + 0xE8);
+
+ for(i = 0; i < 6; i++)
+ ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
+
+ if (is_valid_ethaddr(ethaddr)) {
+ eth_setenv_enetaddr("ethaddr", ethaddr);
+ return 0;
+ }
+
+ return -1;
+}
+
+#define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14)
+int board_eth_init(bd_t *bd)
+{
+ int dev_id = -1;
+ int phy_id = 0xFF;
+ uint32_t addr = IMX_FEC_BASE;
+
+ uint32_t base_mii;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ /* reset FEC phy */
+ imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
+ gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
+ mdelay(1);
+ gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
+ mdelay(1);
+
+ base_mii = addr;
+ debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
+ bus = fec_get_miibus(base_mii, dev_id);
+ if (!bus)
+ return -ENOMEM;
+
+ phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
+ if (!phydev) {
+ free(bus);
+ return -ENOMEM;
+ }
+
+ if (fec_get_mac_from_register(addr))
+ printf("eth_init: failed to get MAC address\n");
+
+ ret = fec_probe(bd, dev_id, addr, bus, phydev);
+ if (ret) {
+ free(phydev);
+ free(bus);
+ }
+
+ return ret;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: TS4800\n");
+
+ return 0;
+}
+
+void hw_watchdog_reset(void)
+{
+ struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
+ /* feed the watchdog for another 10s */
+ writew(0x2, &wtd->feed);
+}
+
+void hw_watchdog_init(void)
+{
+ return;
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 Savoir-faire Linux Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TS4800_H
+#define _TS4800_H
+
+#define TS4800_SYSCON_BASE 0xb0010000
+
+struct ts4800_wtd_regs {
+ u16 feed;
+};
+
+#endif
#include <mmc.h>
#include <power/pfuze100_pmic.h>
#include <power/pmic.h>
+#include <spi_flash.h>
#include "tqma6_bb.h"
+++ /dev/null
-/*
- * Copyright (C) 2013 Boundary Devices
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-
-DATA 4, MX6_MMDC_P0_MDOR, 0x00591023
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
-
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-
S: Maintained
F: board/udoo/
F: include/configs/udoo.h
-F: configs/udoo_quad_defconfig
+F: configs/udoo_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := udoo.o
+obj-y := udoo.o udoo_spl.o
+++ /dev/null
-/*
- * Copyright (C) 2013 Boundary Devices
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
-
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
+++ /dev/null
-/*
- * Copyright (C) 2013 Boundary Devices
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
- * memory bus width: 64 bits x16/x32/x64
- * MX6DL ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 64 bits x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 32 bits x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
int dram_init(void)
{
- gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+ gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const wdog_pads[] = {
- MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D19__GPIO3_IO19,
+ IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
};
int mx6_rgmii_rework(struct phy_device *phydev)
}
static iomux_v3_cfg_t const enet_pads1[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* RGMII reset */
- MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* Ethernet power supply */
- MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 32 - 1 - (MODE0) all */
- MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 31 - 1 - (MODE1) all */
- MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 28 - 1 - (MODE2) all */
- MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 27 - 1 - (MODE3) all */
- MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const enet_pads2[] = {
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
};
static void setup_iomux_enet(void)
{
- imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ SETUP_IOMUX_PADS(enet_pads1);
udelay(20);
gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
gpio_free(IMX_GPIO_NR(6, 28));
gpio_free(IMX_GPIO_NR(6, 29));
- imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ SETUP_IOMUX_PADS(enet_pads2);
}
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ SETUP_IOMUX_PADS(uart2_pads);
}
static void setup_iomux_wdog(void)
{
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+ SETUP_IOMUX_PADS(wdog_pads);
gpio_direction_output(WDT_TRG, 0);
gpio_direction_output(WDT_EN, 1);
gpio_direction_input(WDT_TRG);
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg.max_bus_width = 4;
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_CMD_SATA
- setup_sata();
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ setup_sata();
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ setenv("board_rev", "MX6Q");
+ else
+ setenv("board_rev", "MX6DL");
#endif
return 0;
}
int checkboard(void)
{
- puts("Board: Udoo\n");
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ puts("Board: Udoo Quad\n");
+ else
+ puts("Board: Udoo DualLite\n");
return 0;
}
+++ /dev/null
-/*
- * Copyright (C) 2013 Boundary Devices
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-#include "1066mhz_4x256mx16.cfg"
-#include "clocks.cfg"
--- /dev/null
+/*
+ * Copyright (C) 2015 Udoo
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ * Richard Hu <hakahu@gmail.com>
+ * Based on board/wandboard/spl.c
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+
+/*
+ * Driving strength:
+ * 0x30 == 40 Ohm
+ * 0x28 == 48 Ohm
+ */
+#define IMX6DQ_DRIVE_STRENGTH 0x30
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_cas = IMX6DQ_DRIVE_STRENGTH,
+ .dram_ras = IMX6DQ_DRIVE_STRENGTH,
+ .dram_reset = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+ /* quad = 1066, duallite = 800 */
+ .mem_speed = 1066,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x00350035,
+ .p0_mpwldectrl1 = 0x001F001F,
+ .p1_mpwldectrl0 = 0x00010001,
+ .p1_mpwldectrl1 = 0x00010001,
+ .p0_mpdgctrl0 = 0x43510360,
+ .p0_mpdgctrl1 = 0x0342033F,
+ .p1_mpdgctrl0 = 0x033F033F,
+ .p1_mpdgctrl1 = 0x03290266,
+ .p0_mprddlctl = 0x4B3E4141,
+ .p1_mprddlctl = 0x47413B4A,
+ .p0_mpwrdlctl = 0x42404843,
+ .p1_mpwrdlctl = 0x4C3F4C45,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x002F0038,
+ .p0_mpwldectrl1 = 0x001F001F,
+ .p1_mpwldectrl0 = 0x001F001F,
+ .p1_mpwldectrl1 = 0x001F001F,
+ .p0_mpdgctrl0 = 0x425C0251,
+ .p0_mpdgctrl1 = 0x021B021E,
+ .p1_mpdgctrl0 = 0x021B021E,
+ .p1_mpdgctrl1 = 0x01730200,
+ .p0_mprddlctl = 0x45474C45,
+ .p1_mprddlctl = 0x44464744,
+ .p0_mpwrdlctl = 0x3F3F3336,
+ .p1_mpwrdlctl = 0x32383630,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_qdl = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ /* quad = 2, duallite = 1 */
+ .rtt_nom = 2,
+ /* quad = 2, duallite = 1 */
+ .rtt_wr = 2,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* set the default clock gate to save power */
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000FF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6DL)) {
+ mt41k128m16jt_125.mem_speed = 800;
+ mem_qdl.rtt_nom = 1;
+ mem_qdl.rtt_wr = 1;
+
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
+ } else if (is_cpu_type(MXC_CPU_MX6Q)) {
+ mt41k128m16jt_125.mem_speed = 1066;
+ mem_qdl.rtt_nom = 2;
+ mem_qdl.rtt_wr = 2;
+
+ mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+ mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
+ }
+
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_ARISTAINETOS2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_ARISTAINETOS2B=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_ARISTAINETOS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_CGTQMX6EVAL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_SYS_PROMPT="CM-FX6 # "
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_EMU=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
CONFIG_ARM=y
CONFIG_TARGET_LS2085A_EMU=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU"
+CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6CUBOXI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
# CONFIG_CMD_IMLS is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_THERMAL=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
CONFIG_ARM=y
-CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_ARCH_MX6=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_TARGET_MX6UL_14X14_EVK=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_KOSAGI_NOVENA=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_OT1200=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_OT1200=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_PLATINUM_PICON=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_PLATINUM_TITANIUM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TBS2910=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068"
-CONFIG_SPI_FLASH=y
CONFIG_PCA9551_LED=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_TS4800=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+CONFIG_SPL=y
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
+CONFIG_TARGET_UDOO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_UDOO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_WANDBOARD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_WARP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
# CONFIG_CMD_IMLS is not set
U-boot config options used in fec_mxc.c
CONFIG_FEC_MXC
- Selects fec_mxc.c to be compiled into u-boot.
+ Selects fec_mxc.c to be compiled into u-boot. Can read out the
+ ethaddr from the SoC eFuses (see below).
CONFIG_MII
Must be defined if CONFIG_FEC_MXC is defined.
CONFIG_FEC_MXC_PHYADDR
Optional, selects the exact phy address that should be connected
and function fecmxc_initialize will try to initialize it.
+
+
+Reading the ethaddr from the SoC eFuses:
+if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the
+ethaddr variable, then its value gets read from the corresponding eFuses in
+the SoC. See the README files of the specific SoC for details.
2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the
natural MAC byte order (i.e. MSB first).
+
+ This is an example how to program an example MAC address 01:23:45:67:89:ab
+ into the eFuses. Assure that the programming voltage is available and then
+ execute:
+
+ => fuse prog -y 1 9 01 23 45 67 89 ab
+
+ After programming a MAC address, consider locking the MAC fuses. This is
+ done by programming the MAC_ADDR_LOCK fuse, which is bit 4 of word 0 in
+ bank 1:
+
+ => fuse prog -y 1 0 10
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
- defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+ defined(CONFIG_MX7)
[3] = GPIO4_BASE_ADDR,
#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+ defined(CONFIG_MX7)
[4] = GPIO5_BASE_ADDR,
#ifndef CONFIG_MX6UL
[5] = GPIO6_BASE_ADDR,
#endif
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
#ifndef CONFIG_MX6UL
[6] = GPIO7_BASE_ADDR,
#endif
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_RESET) += reset-uclass.o
+obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
/* Check if Image is in FIT format */
format = genimg_get_format(fit_hdr);
if (format != IMAGE_FORMAT_FIT) {
- printf("Error! Not a FIT image\n");
+ printf("Debug Server FW: Not a FIT image\n");
goto out_error;
}
if (!fit_check_format(fit_hdr)) {
- printf("Error! Bad FIT image format\n");
+ printf("Debug Server FW: Bad FIT image format\n");
goto out_error;
}
node_offset = fit_image_get_node(fit_hdr, uname);
if (node_offset < 0) {
- printf("Error! Can not find %s subimage\n", uname);
+ printf("Debug Server FW:Can not find %s subimage\n", uname);
goto out_error;
}
/* Verify Debug Server firmware image */
if (!fit_image_verify(fit_hdr, node_offset)) {
- printf("Error! Bad Debug Server firmware hash");
+ printf("Debug Server FW: Bad Debug Server firmware hash");
goto out_error;
}
if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) {
- printf("Error! Failed to get Debug Server fw description");
+ printf("Debug Server FW: Failed to get FW description");
goto out_error;
}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Author: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-ls102xa/immap_ls102xa.h>
+#include <asm/arch-ls102xa/config.h>
+#include <linux/compiler.h>
+#include <hwconfig.h>
+#include <fsl_devdis.h>
+
+void device_disable(const struct devdis_table *tbl, uint32_t num)
+{
+ int i;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ /*
+ * Extract hwconfig from environment and disable unused device.
+ */
+ for (i = 0; i < num; i++) {
+ if (hwconfig_sub("devdis", tbl[i].name))
+ setbits_be32(&gur->devdisr + tbl[i].offset,
+ tbl[i].mask);
+ }
+}
+
#define BM_CTRL_ERROR 0x00000200
#define BM_CTRL_BUSY 0x00000100
#define BO_CTRL_ADDR 0
+#ifdef CONFIG_MX7
+#define BM_CTRL_ADDR 0x0000000f
+#define BM_CTRL_RELOAD 0x00000400
+#else
#define BM_CTRL_ADDR 0x0000007f
-
+#endif
+
+#ifdef CONFIG_MX7
+#define BO_TIMING_FSOURCE 12
+#define BM_TIMING_FSOURCE 0x0007f000
+#define BV_TIMING_FSOURCE_NS 1001
+#define BO_TIMING_PROG 0
+#define BM_TIMING_PROG 0x00000fff
+#define BV_TIMING_PROG_US 10
+#else
#define BO_TIMING_STROBE_READ 16
#define BM_TIMING_STROBE_READ 0x003f0000
#define BV_TIMING_STROBE_READ_NS 37
#define BO_TIMING_STROBE_PROG 0
#define BM_TIMING_STROBE_PROG 0x00000fff
#define BV_TIMING_STROBE_PROG_US 10
+#endif
#define BM_READ_CTRL_READ_FUSE 0x00000001
#define WRITE_POSTAMBLE_US 2
+#if defined(CONFIG_MX6) || defined(CONFIG_VF610)
+#define FUSE_BANK_SIZE 0x80
+#ifdef CONFIG_MX6SL
+#define FUSE_BANKS 8
+#else
+#define FUSE_BANKS 16
+#endif
+#elif defined CONFIG_MX7
+#define FUSE_BANK_SIZE 0x40
+#define FUSE_BANKS 16
+#else
+#error "Unsupported architecture\n"
+#endif
+
+#if defined(CONFIG_MX6)
+#include <asm/arch/sys_proto.h>
+
+/*
+ * There is a hole in shadow registers address map of size 0x100
+ * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
+ * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
+ * we should account for this hole in address space.
+ *
+ * Similar hole exists between bank 14 and bank 15 of size
+ * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
+ * Note: iMX6SL has only 0-7 banks and there is no hole.
+ * Note: iMX6UL doesn't have this one.
+ *
+ * This function is to covert user input to physical bank index.
+ * Only needed when read fuse, because we use register offset, so
+ * need to calculate real register offset.
+ * When write, no need to consider hole, always use the bank/word
+ * index from fuse map.
+ */
+u32 fuse_bank_physical(int index)
+{
+ u32 phy_index;
+
+ if (is_cpu_type(MXC_CPU_MX6SL)) {
+ phy_index = index;
+ } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+ if (index >= 6)
+ phy_index = fuse_bank_physical(5) + (index - 6) + 3;
+ else
+ phy_index = index;
+ } else {
+ if (index >= 15)
+ phy_index = fuse_bank_physical(14) + (index - 15) + 2;
+ else if (index >= 6)
+ phy_index = fuse_bank_physical(5) + (index - 6) + 3;
+ else
+ phy_index = index;
+ }
+ return phy_index;
+}
+#else
+u32 fuse_bank_physical(int index)
+{
+ return index;
+}
+#endif
+
static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
{
while (readl(®s->ctrl) & BM_CTRL_BUSY)
{
*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- if (bank >= ARRAY_SIZE((*regs)->bank) ||
- word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
- !assert) {
+ if (bank >= FUSE_BANKS ||
+ word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
+ !assert) {
printf("mxc_ocotp %s(): Invalid argument\n", caller);
return -EINVAL;
}
{
struct ocotp_regs *regs;
int ret;
+ u32 phy_bank;
ret = prepare_read(®s, bank, word, val, __func__);
if (ret)
return ret;
- *val = readl(®s->bank[bank].fuse_regs[word << 2]);
+ phy_bank = fuse_bank_physical(bank);
+
+ *val = readl(®s->bank[phy_bank].fuse_regs[word << 2]);
return finish_access(regs, __func__);
}
+#ifdef CONFIG_MX7
+static void set_timing(struct ocotp_regs *regs)
+{
+ u32 ipg_clk;
+ u32 fsource, prog;
+ u32 timing;
+
+ ipg_clk = mxc_get_clock(MXC_IPG_CLK);
+
+ fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
+ + 1000000) + 1;
+ prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
+
+ timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
+
+ clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
+ timing);
+}
+#else
static void set_timing(struct ocotp_regs *regs)
{
u32 ipg_clk;
clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
BM_TIMING_STROBE_PROG, timing);
}
+#endif
static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
int write)
{
u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
+#ifdef CONFIG_MX7
+ u32 addr = bank;
+#else
u32 addr = bank << 3 | word;
+#endif
set_timing(regs);
clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
setup_direct_access(regs, bank, word, false);
writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
wait_busy(regs, 1);
+#ifdef CONFIG_MX7
+ *val = readl((®s->read_fuse_data0) + (word << 2));
+#else
*val = readl(®s->read_fuse_data);
+#endif
return finish_access(regs, __func__);
}
return ret;
setup_direct_access(regs, bank, word, true);
+#ifdef CONFIG_MX7
+ switch (word) {
+ case 0:
+ writel(0, ®s->data1);
+ writel(0, ®s->data2);
+ writel(0, ®s->data3);
+ writel(val, ®s->data0);
+ break;
+ case 1:
+ writel(val, ®s->data1);
+ writel(0, ®s->data2);
+ writel(0, ®s->data3);
+ writel(0, ®s->data0);
+ break;
+ case 2:
+ writel(0, ®s->data1);
+ writel(val, ®s->data2);
+ writel(0, ®s->data3);
+ writel(0, ®s->data0);
+ break;
+ case 3:
+ writel(0, ®s->data1);
+ writel(0, ®s->data2);
+ writel(val, ®s->data3);
+ writel(0, ®s->data0);
+ break;
+ }
+ wait_busy(regs, BV_TIMING_PROG_US);
+#else
writel(val, ®s->data);
wait_busy(regs, BV_TIMING_STROBE_PROG_US);
+#endif
udelay(WRITE_POSTAMBLE_US);
return finish_access(regs, __func__);
{
struct ocotp_regs *regs;
int ret;
+ u32 phy_bank;
ret = prepare_write(®s, bank, word, __func__);
if (ret)
return ret;
- writel(val, ®s->bank[bank].fuse_regs[word << 2]);
+ phy_bank = fuse_bank_physical(bank);
+
+ writel(val, ®s->bank[phy_bank].fuse_regs[word << 2]);
return finish_access(regs, __func__);
}
/* Return the original HCLK clock speed. */
*val = readl(&clkctrl_regs->hw_clkctrl_hbus);
*val &= CLKCTRL_HBUS_DIV_MASK;
+ *val >>= CLKCTRL_HBUS_DIV_OFFSET;
/* Scale the HCLK to 454/19 = 23.9 MHz . */
scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/sys_proto.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <linux/compiler.h>
writel(0x00000000, &fec->eth->gaddr2);
- /* clear MIB RAM */
- for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
- writel(0, i);
+ /* Do not access reserved register for i.MX6UL */
+ if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ /* clear MIB RAM */
+ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
+ writel(0, i);
- /* FIFO receive start register */
- writel(0x520, &fec->eth->r_fstart);
+ /* FIFO receive start register */
+ writel(0x520, &fec->eth->r_fstart);
+ }
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8584_driver = {
+ .name = "Vitesse VSC8584",
+ .uid = 0x707c0,
+ .mask = 0xffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8574_config,
+ .startup = &vitesse_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static struct phy_driver VSC8601_driver = {
.name = "Vitesse VSC8601",
.uid = 0x70420,
phy_register(&VSC8211_driver);
phy_register(&VSC8221_driver);
phy_register(&VSC8574_driver);
+ phy_register(&VSC8584_driver);
phy_register(&VSC8514_driver);
phy_register(&VSC8662_driver);
phy_register(&VSC8664_driver);
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
-#ifdef CONFIG_LS102XA
- setbits_be32(®s->dmactrl, DMACTRL_LE);
-#endif
do {
uint16_t status;
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
-#ifdef CONFIG_LS102XA
- setbits_be32(®s->dmactrl, DMACTRL_LE);
-#endif
}
/* This returns the status bits of the device. The return value
{
int count;
u32 stream_ids[MAX_STREAM_IDS];
+ u32 ctlr_streamid = 0x300;
#ifdef CONFIG_PCIE1
/* PEX1 stream ID fixup */
alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count);
+ append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000",
+ &ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE2
alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count);
+ append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000",
+ &ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE3
alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count);
+ append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000",
+ &ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE4
alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count);
+ append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000",
+ &ctlr_streamid, 1);
#endif
}
#endif
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
+obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+
+int power_pfuze3000_init(unsigned char bus)
+{
+ static const char name[] = "PFUZE3000";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = PMIC_NUM_OF_REGS;
+ p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR;
+ p->hw.i2c.tx_num = 1;
+ p->bus = bus;
+
+ return 0;
+}
#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
+#define RTC_STAT_BIT_BB32KHZ 0x40 /* Battery backed 32KHz Output */
+#define RTC_STAT_BIT_EN32KHZ 0x8 /* Enable 32KHz Output */
static uchar rtc_read (uchar reg);
rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
}
+/*
+ * Enable 32KHz output
+ */
+void rtc_enable_32khz_output(void)
+{
+ rtc_write(RTC_STAT_REG_ADDR,
+ RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ);
+}
/*
* Helper functions
static int do_lgset(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0);
+ lg4573_spi_startup(CONFIG_LG4573_BUS, CONFIG_LG4573_CS, 10000000,
+ SPI_MODE_0);
return 0;
}
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
-#define CONFIG_SF_DEFAULT_BUS 3
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
"ubiboot=echo Booting from ubi ...; " \
"run ubiargs addmtd addmisc set_fit_default;" \
"bootm ${fit_addr_r}\0" \
- "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
- "ubifsload ${fit_addr_r} /boot/system.itb; " \
- "imi ${fit_addr_r}\0 " \
"rescueargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/ram rw\0 " \
"rescueboot=echo Booting rescue system from NOR ...; " \
#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_SF_DEFAULT_BUS 3
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
"addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"ubiargs=setenv bootargs console=${console},${baudrate} " \
- "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 "
+ "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \
+ "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
+ "ubifsload ${fit_addr_r} /boot/system.itb; " \
+ "imi ${fit_addr_r}\0 "
#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15)
#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31)
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_PHY_MICREL_KSZ9031
+#define CONFIG_SF_DEFAULT_BUS 3
#define CONFIG_SF_DEFAULT_CS 1
#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
"-(rescue-system);gpmi-nand:-(ubi)\0" \
"addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \
"ubiargs=setenv bootargs console=${console},${baudrate} " \
- "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 "
+ "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \
+ "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \
+ "ubifsload ${fit_addr_r} /boot/system.itb; " \
+ "imi ${fit_addr_r}\0 "
#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
/* Framebuffer */
#define CONFIG_SYS_LDB_CLOCK 33246000
#define CONFIG_LG4573
+#define CONFIG_LG4573_BUS 0
+#define CONFIG_LG4573_CS 0
#define CONFIG_CMD_BMP
--- /dev/null
+/*
+ * (C) Copyright 2015
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6DL aristainetos2 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ARISTAINETOS2B_CONFIG_H
+#define __ARISTAINETOS2B_CONFIG_H
+
+#define CONFIG_SYS_BOARD_VERSION 3
+#define CONFIG_HOSTNAME aristainetos2
+#define CONFIG_BOARDNAME "aristainetos2-revB"
+
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART_BASE UART2_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc1"
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+
+#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
+ "board_type=aristainetos2_7@1\0" \
+ "nor_bootdelay=-2\0" \
+ "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \
+ "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
+ "-(rescue-system);gpmi-nand:-(ubi)\0" \
+ "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \
+ "ubiargs=setenv bootargs console=${console},${baudrate} " \
+ "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \
+ "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \
+ "ubifsload ${fit_addr_r} /boot/system.itb; " \
+ "imi ${fit_addr_r}\0 " \
+
+#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
+
+#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15)
+#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0)
+#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
+
+/* Framebuffer */
+#define CONFIG_SYS_LDB_CLOCK 33246000
+#define CONFIG_LG4573
+#define CONFIG_LG4573_BUS 0
+#define CONFIG_LG4573_CS 1
+
+#define CONFIG_CMD_BMP
+
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+
+#include "aristainetos-common.h"
+
+#endif /* __ARISTAINETOS2B_CONFIG_H */
#define CONFIG_LBA48
#define CONFIG_LIBATA
+/* Ethernet */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
/* Command definition */
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_MISC_INIT_R
/* SPL */
#include "imx6_spl.h"
#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
#define CONFIG_SPL_BSS_START_ADDR 0x88200000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_SPL_MALLOC_START 0x88300000
#define CONFIG_TIMER_CLK_FREQ 12500000
#define CONFIG_HWCONFIG
-#define HWCONFIG_BUFFER_SIZE 128
+#define HWCONFIG_BUFFER_SIZE 256
+
+#define CONFIG_FSL_DEVICE_DISABLE
#define CONFIG_BOOTDELAY 3
#define CONFIG_TIMER_CLK_FREQ 12500000
#define CONFIG_HWCONFIG
-#define HWCONFIG_BUFFER_SIZE 128
+#define HWCONFIG_BUFFER_SIZE 256
+
+#define CONFIG_FSL_DEVICE_DISABLE
#define CONFIG_BOOTDELAY 3
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
+#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
"kernel_size=0x2800000\0" \
"console=ttyAMA0,38400n8\0"
-#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0600,115200 " \
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0500,115200 " \
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=16"
#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "DPNI1"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0600,115200 " \
+ "ramdisk_size=0x2000000 default_hugepagesz=2m" \
+ " hugepagesz=2m hugepages=16"
+
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_PHYLIB_10G
#include "mx6_common.h"
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#include "imx6_spl.h"
+#endif
+
#define MACH_TYPE_MX6SLEVK 4307
#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
#include "imx6_spl.h"
#endif
#define CONFIG_SPL_FAT_SUPPORT
#include "imx6_spl.h"
-#define CONFIG_MX6
#define CONFIG_ROM_UNIFIED_SECTIONS
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_ENET_DEV 1
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x2
+#define CONFIG_FEC_XCV_TYPE RMII
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+#define CONFIG_FEC_XCV_TYPE RMII
+#endif
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_DMA_MINALIGN 64
+#endif
+
#define CONFIG_IMX6_THERMAL
#endif
#define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_BOOTCOUNT_BE
+/*
+ * Remove all unused interfaces / commands that are defined in
+ * the common header tqms6.h
+ */
+#undef CONFIG_CMD_SF
+#undef CONFIG_CMD_SPI
+#undef CONFIG_MXC_SPI
+
#endif /* __CONFIG_TQMA6_WRU4_H */
--- /dev/null
+/*
+ * Copyright (C) 2015, Savoir-faire Linux Inc.
+ *
+ * Derived from MX51EVK code by
+ * Guennadi Liakhovetski <lg@denx.de>
+ * Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the TS4800 Board
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MX51
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-boot is a 2nd stage bootloader */
+
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
+
+/* text base address used when linking */
+#define CONFIG_SYS_TEXT_BASE 0x90008000
+
+#include <asm/arch/imx-regs.h>
+
+/* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* use common/board_f.c instead of arch/<arch>/lib/<board>.c */
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_MXC_GPIO
+
+/*
+ * SPI Configs
+ * */
+#define CONFIG_HARD_SPI /* puts SPI: ready */
+#define CONFIG_MXC_SPI /* driver for the SPI controllers*/
+#define CONFIG_CMD_SPI /* SPI serial bus support */
+
+/*
+ * MMC Configs
+ * */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
+
+#define CONFIG_MMC
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */
+#define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */
+#define CONFIG_BAUDRATE 115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#define CONFIG_CMD_BOOTZ
+#undef CONFIG_CMD_IMLS
+
+/* Environment variables */
+
+#define CONFIG_BOOTDELAY 1
+
+#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=uImage\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs addtty; " \
+ "bootm; "
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi; "
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Low level init */
+#define CONFIG_SYS_DDR_CLKSEL 0
+#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
+
+/*-----------------------------------------------------------------------
+ * Environment organization
+ */
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
#include "mx6_common.h"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include "imx6_spl.h"
+
#define MACH_TYPE_UDOO 4800
#define CONFIG_MACH_TYPE MACH_TYPE_UDOO
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb"
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_file=undefined\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"fi; " \
"else " \
"bootz; " \
- "fi;\0"
+ "fi;\0" \
+ "findfdt=" \
+ "if test $board_rev = MX6Q ; then " \
+ "setenv fdt_file imx6q-udoo.dtb; fi; " \
+ "if test $board_rev = MX6DL ; then " \
+ "setenv fdt_file imx6dl-udoo.dtb; fi; " \
+ "if test $fdt_file = undefined; then " \
+ "echo WARNING: Could not determine dtb to use; fi; \0"
#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_DEVDIS_H_
+#define __FSL_DEVDIS_H_
+
+struct devdis_table {
+ char name[32];
+ u32 offset;
+ u32 mask;
+};
+
+void device_disable(const struct devdis_table *tbl, uint32_t num);
+
+#endif
#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
+/* Registers */
+#define MMD_ACCESS_CONTROL 0xd
+#define MMD_ACCESS_REG_DATA 0xe
+
struct phy_device;
int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __PFUZE3000_PMIC_H_
+#define __PFUZE3000_PMIC_H_
+
+/* PFUZE3000 registers */
+enum {
+ PFUZE3000_DEVICEID = 0x00,
+
+ PFUZE3000_REVID = 0x03,
+ PFUZE3000_FABID = 0x04,
+ PFUZE3000_INTSTAT0 = 0x05,
+ PFUZE3000_INTMASK0 = 0x06,
+ PFUZE3000_INTSENSE0 = 0x07,
+ PFUZE3000_INTSTAT1 = 0x08,
+ PFUZE3000_INTMASK1 = 0x09,
+ PFUZE3000_INTSENSE1 = 0x0A,
+
+ PFUZE3000_INTSTAT3 = 0x0E,
+ PFUZE3000_INTMASK3 = 0x0F,
+ PFUZE3000_INTSENSE3 = 0x10,
+ PFUZE3000_INTSTAT4 = 0x11,
+ PFUZE3000_INTMASK4 = 0x12,
+ PFUZE3000_INTSENSE4 = 0x13,
+
+ PFUZE3000_COINCTL = 0x1A,
+ PFUZE3000_PWRCTL = 0x1B,
+ PFUZE3000_MEMA = 0x1C,
+ PFUZE3000_MEMB = 0x1D,
+ PFUZE3000_MEMC = 0x1E,
+ PFUZE3000_MEMD = 0x1F,
+
+ PFUZE3000_SW1AVOLT = 0x20,
+ PFUZE3000_SW1ASTBY = 0x21,
+ PFUZE3000_SW1AOFF = 0x22,
+ PFUZE3000_SW1AMODE = 0x23,
+ PFUZE3000_SW1ACONF = 0x24,
+
+ PFUZE3000_SW1BVOLT = 0x2E,
+ PFUZE3000_SW1BSTBY = 0x2F,
+ PFUZE3000_SW1BOFF = 0x30,
+ PFUZE3000_SW1BMODE = 0x31,
+ PFUZE3000_SW1BCONF = 0x32,
+
+ PFUZE3000_SW2VOLT = 0x35,
+ PFUZE3000_SW2STBY = 0x36,
+ PFUZE3000_SW2OFF = 0x37,
+ PFUZE3000_SW2MODE = 0x38,
+ PFUZE3000_SW2CONF = 0x39,
+
+ PFUZE3000_SW3VOLT = 0x3C,
+ PFUZE3000_SW3STBY = 0x3D,
+ PFUZE3000_SW3OFF = 0x3E,
+ PFUZE3000_SW3MODE = 0x3F,
+ PFUZE3000_SW3CONF = 0x40,
+
+ PFUZE3000_SWBSTCTL = 0x66,
+
+ PFUZE3000_LDOGCTL = 0x69,
+ PFUZE3000_VREFDDRCTL = 0x6A,
+ PFUZE3000_VSNVSCTL = 0x6B,
+ PFUZE3000_VLDO1CTL = 0x6C,
+ PFUZE3000_VLDO2CTL = 0x6D,
+ PFUZE3000_VCC_SDCTL = 0x6E,
+ PFUZE3000_V33CTL = 0x6F,
+ PFUZE3000_VLDO3CTL = 0x70,
+ PFUZE3000_VLD4CTL = 0x71,
+
+ PMIC_NUM_OF_REGS = 0x7F,
+};
+
+int power_pfuze3000_init(unsigned char bus);
+
+#endif
int rtc_get (struct rtc_time *);
int rtc_set (struct rtc_time *);
void rtc_reset (void);
+void rtc_enable_32khz_output(void);
/**
* rtc_read8() - Read an 8-bit register
hdr_base = entry_point - imximage_init_loadsize +
flash_offset;
fhdr_v2->self = hdr_base;
- fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
+ if (dcd_len > 0)
+ fhdr_v2->dcd_ptr = hdr_base
+ + offsetof(imx_header_v2_t, dcd_table);
+ else
+ fhdr_v2->dcd_ptr = 0;
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
hdr_v2->boot_data.start = entry_point - imximage_init_loadsize;
fcb->ecc_block_0_size = 512;
fcb->ecc_block_n_size = 512;
fcb->metadata_bytes = 10;
-
- if (nand_writesize == 2048) {
- fcb->ecc_block_n_ecc_type = 4;
- fcb->ecc_block_0_ecc_type = 4;
- } else if (nand_writesize == 4096) {
- if (nand_oobsize == 128) {
- fcb->ecc_block_n_ecc_type = 4;
- fcb->ecc_block_0_ecc_type = 4;
- } else if (nand_oobsize == 218) {
- fcb->ecc_block_n_ecc_type = 8;
- fcb->ecc_block_0_ecc_type = 8;
- } else if (nand_oobsize == 224) {
- fcb->ecc_block_n_ecc_type = 8;
- fcb->ecc_block_0_ecc_type = 8;
- }
- }
-
+ fcb->ecc_block_n_ecc_type = mx28_nand_get_ecc_strength(
+ nand_writesize, nand_oobsize) >> 1;
+ fcb->ecc_block_0_ecc_type = mx28_nand_get_ecc_strength(
+ nand_writesize, nand_oobsize) >> 1;
if (fcb->ecc_block_n_ecc_type == 0) {
printf("MX28 NAND: Unsupported NAND geometry\n");
goto err;
projects / people / ms / u-boot.git / commitdiff
