If defined, don't allow the -f switch to env set override variable
access flags.
-- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
- This is set by OMAP boards for the max time that reset should
- be asserted. See doc/README.omap-reset-time for details on how
- the value can be calculated on a given board.
-
- CONFIG_USE_STDINT
If stdint.h is available with your toolchain you can define this
option to enable it. You can provide option 'USE_STDINT=1' when
select DM_GPIO
select DM_SPI
select DM_SPI_FLASH
+ select USB_EHCI_HCD
config XTENSA
bool "Xtensa architecture"
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o
-obj-y += reset.o
+++ /dev/null
-/*
- * OMAP1 CPU identification code
- *
- * Copyright (C) 2004 Nokia Corporation
- * Written by Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <command.h>
-#include <linux/compiler.h>
-
-#if defined(CONFIG_OMAP)
-
-#define omap_readw(x) *(volatile unsigned short *)(x)
-#define omap_readl(x) *(volatile unsigned long *)(x)
-
-#define OMAP_DIE_ID_0 0xfffe1800
-#define OMAP_DIE_ID_1 0xfffe1804
-#define OMAP_PRODUCTION_ID_0 0xfffe2000
-#define OMAP_PRODUCTION_ID_1 0xfffe2004
-#define OMAP32_ID_0 0xfffed400
-#define OMAP32_ID_1 0xfffed404
-
-struct omap_id {
- u16 jtag_id; /* Used to determine OMAP type */
- u8 die_rev; /* Processor revision */
- u32 omap_id; /* OMAP revision */
- u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */
-};
-
-/* Register values to detect the OMAP version */
-static struct omap_id omap_ids[] = {
- { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
- { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
- { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
- { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
- { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
- { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
- { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00},
- { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00},
- { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
- { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
- { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000},
- { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00},
- { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00},
- { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300},
- { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300},
- { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300},
- { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000},
- { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000},
- { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000},
-};
-
-/*
- * Get OMAP type from PROD_ID.
- * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
- * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
- * Undocumented register in TEST BLOCK is used as fallback; This seems to
- * work on 1510, 1610 & 1710. The official way hopefully will work in future
- * processors.
- */
-static u16 omap_get_jtag_id(void)
-{
- u32 prod_id, omap_id;
-
- prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
- omap_id = omap_readl(OMAP32_ID_1);
-
- /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
- if (((prod_id >> 20) == 0) || (prod_id == omap_id))
- prod_id = 0;
- else
- prod_id &= 0xffff;
-
- if (prod_id)
- return prod_id;
-
- /* Use OMAP32_ID_1 as fallback */
- prod_id = ((omap_id >> 12) & 0xffff);
-
- return prod_id;
-}
-
-/*
- * Get OMAP revision from DIE_REV.
- * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
- * Undocumented register in the TEST BLOCK is used as fallback.
- * REVISIT: This does not seem to work on 1510
- */
-static u8 omap_get_die_rev(void)
-{
- u32 die_rev;
-
- die_rev = omap_readl(OMAP_DIE_ID_1);
-
- /* Check for broken OMAP_DIE_ID on early 1710 */
- if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
- die_rev = 0;
-
- die_rev = (die_rev >> 17) & 0xf;
- if (die_rev)
- return die_rev;
-
- die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
-
- return die_rev;
-}
-
-static unsigned long dpll1(void)
-{
- unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG);
- unsigned long rate;
-
- rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */
- if (pll_ctl_val & 0x10) {
- /* PLL enabled, apply multiplier and divisor */
- if (pll_ctl_val & 0xf80)
- rate *= (pll_ctl_val & 0xf80) >> 7;
- rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
- } else {
- /* PLL disabled, apply bypass divisor */
- switch (pll_ctl_val & 0xc) {
- case 0:
- break;
- case 0x4:
- rate /= 2;
- break;
- default:
- rate /= 4;
- break;
- }
- }
-
- return rate;
-}
-
-static unsigned long armcore(void)
-{
- unsigned short arm_ckctl = omap_readw(ARM_CKCTL);
-
- return (dpll1() >> ((arm_ckctl & 0x0030) >> 4));
-}
-
-int print_cpuinfo (void)
-{
- int i;
- u16 jtag_id;
- u8 die_rev;
- u32 omap_id;
- u8 cpu_type;
- __maybe_unused u32 system_serial_high;
- __maybe_unused u32 system_serial_low;
- u32 system_rev = 0;
-
- jtag_id = omap_get_jtag_id();
- die_rev = omap_get_die_rev();
- omap_id = omap_readl(OMAP32_ID_0);
-
-#ifdef DEBUG
- printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
- printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
- omap_readl(OMAP_DIE_ID_1),
- (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
- printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0));
- printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
- omap_readl(OMAP_PRODUCTION_ID_1),
- omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
- printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
- printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
- printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
-#endif
-
- system_serial_high = omap_readl(OMAP_DIE_ID_0);
- system_serial_low = omap_readl(OMAP_DIE_ID_1);
-
- /* First check only the major version in a safe way */
- for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
- if (jtag_id == (omap_ids[i].jtag_id)) {
- system_rev = omap_ids[i].type;
- break;
- }
- }
-
- /* Check if we can find the die revision */
- for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
- if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) {
- system_rev = omap_ids[i].type;
- break;
- }
- }
-
- /* Finally check also the omap_id */
- for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
- if (jtag_id == omap_ids[i].jtag_id
- && die_rev == omap_ids[i].die_rev
- && omap_id == omap_ids[i].omap_id) {
- system_rev = omap_ids[i].type;
- break;
- }
- }
-
- /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
- cpu_type = system_rev >> 24;
-
- switch (cpu_type) {
- case 0x07:
- system_rev |= 0x07;
- break;
- case 0x03:
- case 0x15:
- system_rev |= 0x15;
- break;
- case 0x16:
- case 0x17:
- system_rev |= 0x16;
- break;
- case 0x24:
- system_rev |= 0x24;
- break;
- default:
- printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
- }
-
- printf("CPU: OMAP%04x", system_rev >> 16);
- if ((system_rev >> 8) & 0xff)
- printf("%x", (system_rev >> 8) & 0xff);
-#ifdef DEBUG
- printf(" revision %i handled as %02xxx id: %08x%08x",
- die_rev, system_rev & 0xff, system_serial_low, system_serial_high);
-#endif
- printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n",
- armcore() / 1000000, (armcore() / 100000) % 10,
- dpll1() / 1000000, (dpll1() / 100000) % 10);
-
- return 0;
-}
-
-#endif /* #if defined(CONFIG_OMAP) */
+++ /dev/null
-/*
- * armboot - Startup Code for ARM926EJS CPU-core
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003 Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
-_loop_forever:
- b _loop_forever
-
-rstctl1:
- .word 0xfffece10
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+8) \
- / (TIMER_CLOCK / CONFIG_SYS_HZ)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-int timer_init (void)
-{
- int32_t val;
-
- /* Start the decrementer ticking down from 0xffffffff */
- *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
- *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
-
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- }else{ /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- tmp = get_timer (0); /* get current timestamp */
- if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
- else
- tmo += tmp; /* else, set advancing stamp wake up time */
-
- while (get_timer_masked () < tmo)/* loop till event */
- /*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER; /* capure current decrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (lastdec >= now) { /* normal mode (non roll) */
- /* normal mode */
- timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
- } else { /* we have overflow of the count down timer */
- /* nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll and cause problems.
- */
- timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK /
- CONFIG_SYS_HZ)) - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- endtime = get_timer_masked () + tmo;
-
- do {
- ulong now = get_timer_masked ();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return CONFIG_SYS_HZ;
-}
0:
/*
- * Enalbe SMPEN bit for coherency.
+ * Enable SMPEN bit for coherency.
* This register is not architectural but at the moment
* this bit should be set for A53/A57/A72.
*/
#ifdef CONFIG_ARMV8_SET_SMPEN
- mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
+ mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
orr x0, x0, #0x40
msr S3_1_c15_c2_1, x0
#endif
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable);
#endif
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
void enable_usboh3_clk(unsigned char enable);
#endif
void init_clk_usdhc(u32 index);
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
-/*
- * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
- * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
- * into microsec and passing the value.
- */
-#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-
#if defined(CONFIG_DRA7XX)
#define V_OSCK 20000000 /* Clock output from T2 */
#else
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
-#if defined(CONFIG_OMAP) \
+#if defined(CONFIG_ARCH_OMAP2PLUS) \
|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
|| defined(CONFIG_EXYNOS4210)
/* Platform-specific defines */
}
#endif
-#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
void at91_uhp_hw_init(void)
{
/* Enable VBus on UHP ports */
* USB/EHCI
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MARVELL
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */
if OMAP34XX
+# We only enable the clocks for the GPIO banks that a given board requies.
+config OMAP3_GPIO_2
+ bool
+
+config OMAP3_GPIO_3
+ bool
+
+config OMAP3_GPIO_4
+ bool
+
+config OMAP3_GPIO_5
+ bool
+
+config OMAP3_GPIO_6
+ bool
+
choice
prompt "OMAP3 board select"
optional
config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
+ select OMAP3_GPIO_4
+ select OMAP3_GPIO_5 if USB_EHCI_HCD
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select DM
select DM_SERIAL
select DM_GPIO
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6
config TARGET_CM_T35
bool "CompuLab CM-T3530 and CM-T3730 boards"
+ select OMAP3_GPIO_2
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6 if LED_STATUS
config TARGET_CM_T3517
bool "CompuLab CM-T3517 boards"
+ select OMAP3_GPIO_2
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6 if LED_STATUS
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
select DM
select DM_SERIAL
select DM_GPIO
+ select OMAP3_GPIO_3
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6
config TARGET_OMAP3_OVERO
bool "OMAP35xx Gumstix Overo"
select DM
select DM_SERIAL
select DM_GPIO
+ select OMAP3_GPIO_2
+ select OMAP3_GPIO_3
+ select OMAP3_GPIO_4
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6
config TARGET_OMAP3_ZOOM1
bool "TI Zoom1"
config TARGET_OMAP3_PANDORA
bool "OMAP3 Pandora"
+ select OMAP3_GPIO_4
+ select OMAP3_GPIO_6
config TARGET_ECO5PK
bool "ECO5PK"
+ select OMAP3_GPIO_5 if USB_EHCI_HCD
config TARGET_TRICORDER
bool "Tricorder"
+ select OMAP3_GPIO_2
config TARGET_MCX
bool "MCX"
select BOARD_LATE_INIT
+ select OMAP3_GPIO_2 if USB_EHCI_HCD
+ select OMAP3_GPIO_5 if USB_EHCI_HCD
config TARGET_OMAP3_LOGIC
bool "OMAP3 Logic"
select DM
select DM_SERIAL
select DM_GPIO
+ select OMAP3_GPIO_4
+ select OMAP3_GPIO_6
config TARGET_NOKIA_RX51
bool "Nokia RX51"
config TARGET_TAO3530
bool "TAO3530"
+ select OMAP3_GPIO_2
+ select OMAP3_GPIO_3
+ select OMAP3_GPIO_4
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6
config TARGET_TWISTER
bool "Twister"
+ select OMAP3_GPIO_2
+ select OMAP3_GPIO_5 if USB_EHCI_HCD
config TARGET_OMAP3_CAIRO
bool "QUIPOS CAIRO"
select DM
select DM_SERIAL
select DM_GPIO
+ select OMAP3_GPIO_2
+ select OMAP3_GPIO_3
+ select OMAP3_GPIO_4
+ select OMAP3_GPIO_5
+ select OMAP3_GPIO_6
endchoice
using hardware memory firewalls. This value must be smaller than the
TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
+config OMAP_PLATFORM_RESET_TIME_MAX_USEC
+ int "Something"
+ range 0 31219
+ default 31219
+ help
+ Most OMAPs' provide a way to specify the time for which the reset
+ should be held low while the voltages and Oscillator outputs
+ stabilize.
+ This time is mostly board and PMIC dependent. Hence the boards are
+ expected to specify a pre-computed time using the above option.
+ This value can be computed using a summation of the below 3
+ parameters
+ 1: Time taken by the Osciallator to stop and restart
+ 2: PMIC OTP time
+ 3: Voltage ramp time, which can be derived using the PMIC slew rate
+ and value of voltage ramp needed.
+
if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM
menu "Voltage Domain OPP selections"
{
u32 rst_time, rst_val;
-#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
- rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
-#else
- rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
-#endif
- rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
+ /*
+ * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
+ * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
+ * into microsec and passing the value.
+ */
+ rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC)
+ << RSTTIME1_SHIFT;
if (rst_time > RSTTIME1_MASK)
rst_time = RSTTIME1_MASK;
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
-/*
- * Define Master code if there are multiple masters on the I2C_SR bus.
- * Normally not required
- */
-#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE
-#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0
-#endif
-
/* Register defines and masks for VC IP Block */
/* PRM_VC_CFG_I2C_MODE */
#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6)
(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
- val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
- PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
+ /*
+ * Master code if there are multiple masters on the I2C_SR bus.
+ */
+ val = 0x0 << PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
/* No HS mode for now */
val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
/* TODO: use "mmc-pwrseq-emmc" */
writel(1, SDCTRL_EMMC_HW_RESET);
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
{
/* FIXME: the current clk driver can not handle parents */
u32 tmp;
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
select CREATE_ARCH_SYMLINK
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
+ imply USB_EHCI_HCD if USB
config MPC86xx
bool "MPC86xx"
at91sam9x5ek_nand_hw_init();
#endif
-#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
at91_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
}
#endif
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
static void setup_net_chip(void);
#endif
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
return rc;
}
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
#include <asm/arch/clock.h>
#include <errno.h>
#include <i2c.h>
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
/* Address of the framebuffer in RAM. */
#define FB_START_ADDRESS 0x88000000
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
config SYS_CONFIG_NAME
default "omap3_logic"
+source "board/ti/common/Kconfig"
+
endif
#include <asm/mach-types.h>
#include "overo.h"
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
}
#endif
-#if defined(CONFIG_USB_EHCI)
+#if defined(CONFIG_USB_EHCI_HCD)
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
return omap_ehci_hcd_stop();
}
-#endif /* CONFIG_USB_EHCI */
+#endif /* CONFIG_USB_EHCI_HCD */
DECLARE_GLOBAL_DATA_PTR;
-/*
- * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
- */
-u8 omap3_evm_need_extvbus(void)
-{
- u8 retval = 0;
-
- /* TODO: verify if cairo handheld platform needs extvbus programming */
-
- return retval;
-}
-
/*
* Routine: board_init
* Description: Early hardware init.
}
#endif
-#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
{
{
return omap_ehci_hcd_stop();
}
-#endif /* CONFIG_USB_EHCI */
+#endif /* CONFIG_USB_EHCI_HCD */
#include <spl.h>
#include <mmc.h>
#include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
XR16L2751_GPMC_CONFIG6,
};
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
#include <i2c.h>
#include <spartan3.h>
#include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
FPGA_GPMC_CONFIG6,
};
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
#include "beagle.h"
#include <command.h>
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
}
#endif
-#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
{
return omap_ehci_hcd_stop();
}
-#endif /* CONFIG_USB_EHCI */
+#endif /* CONFIG_USB_EHCI_HCD */
#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
int board_eth_init(bd_t *bis)
#include "mux_data.h"
-#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
#include <sata.h>
#include <usb.h>
#include <asm/gpio.h>
return 0;
}
-#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
static void enable_host_clocks(void)
{
int auxclk;
}
#endif
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
#include "panda_mux_data.h"
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#endif
#endif
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
/* get CPU and bus clocks according to the environment variable */
get_clocks, /* get CPU and bus clocks (etc.) */
#endif
+#if !defined(CONFIG_M68K)
timer_init, /* initialize timer */
+#endif
#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init,
#endif
means of transmitting U-Boot over a serial line for using in SPL,
with a checksum to ensure correctness.
+config SPL_ATF_SUPPORT
+ bool "Support ARM Trusted Firmware"
+ depends on SPL && ARM64
+ help
+ ATF(ARM Trusted Firmware) is a component for ARM arch64 which which
+ is loaded by SPL(which is considered as BL2 in ATF terminology).
+ More detail at: https://github.com/ARM-software/arm-trusted-firmware
+
+config SPL_ATF_TEXT_BASE
+ depends on SPL_ATF_SUPPORT
+ hex "ATF BL31 base address"
+ help
+ This is the base address in memory for ATF BL31 text and entry point.
+
config TPL_ENV_SUPPORT
bool "Support an environment"
depends on TPL
obj-$(CONFIG_SPL_UBI) += spl_ubi.o
obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o
obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o
gd->malloc_ptr / 1024);
#endif
+ if (IS_ENABLED(CONFIG_SPL_ATF_SUPPORT)) {
+ debug("loaded - jumping to U-Boot via ATF BL31.\n");
+ bl31_entry();
+ }
+
debug("loaded - jumping to U-Boot...\n");
spl_board_prepare_for_boot();
jump_to_image_no_args(&spl_image);
--- /dev/null
+/*
+ * Reference to the ARM TF Project,
+ * plat/arm/common/arm_bl2_setup.c
+ * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
+ * reserved.
+ * Copyright (C) 2016 Rockchip Electronic Co.,Ltd
+ * Written by Kever Yang <kever.yang@rock-chips.com>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <atf_common.h>
+#include <errno.h>
+#include <spl.h>
+
+static struct bl2_to_bl31_params_mem bl31_params_mem;
+static struct bl31_params *bl2_to_bl31_params;
+
+/**
+ * bl2_plat_get_bl31_params() - prepare params for bl31.
+ *
+ * This function assigns a pointer to the memory that the platform has kept
+ * aside to pass platform specific and trusted firmware related information
+ * to BL31. This memory is allocated by allocating memory to
+ * bl2_to_bl31_params_mem structure which is a superset of all the
+ * structure whose information is passed to BL31
+ * NOTE: This function should be called only once and should be done
+ * before generating params to BL31
+ *
+ * @return bl31 params structure pointer
+ */
+struct bl31_params *bl2_plat_get_bl31_params(void)
+{
+ struct entry_point_info *bl33_ep_info;
+
+ /*
+ * Initialise the memory for all the arguments that needs to
+ * be passed to BL31
+ */
+ memset(&bl31_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem));
+
+ /* Assign memory for TF related information */
+ bl2_to_bl31_params = &bl31_params_mem.bl31_params;
+ SET_PARAM_HEAD(bl2_to_bl31_params, ATF_PARAM_BL31, ATF_VERSION_1, 0);
+
+ /* Fill BL31 related information */
+ SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info,
+ ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
+
+ /* Fill BL32 related information if it exists */
+#ifdef BL32_BASE
+ bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
+ SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, ATF_PARAM_EP,
+ ATF_VERSION_1, 0);
+ bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
+ SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
+ ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
+#endif /* BL32_BASE */
+
+ /* Fill BL33 related information */
+ bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
+ bl33_ep_info = &bl31_params_mem.bl33_ep_info;
+ SET_PARAM_HEAD(bl33_ep_info, ATF_PARAM_EP, ATF_VERSION_1,
+ ATF_EP_NON_SECURE);
+
+ /* BL33 expects to receive the primary CPU MPID (through x0) */
+ bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
+ bl33_ep_info->pc = CONFIG_SYS_TEXT_BASE;
+ bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
+ DISABLE_ALL_EXECPTIONS);
+
+ bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
+ SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info,
+ ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
+
+ return bl2_to_bl31_params;
+}
+
+void raw_write_daif(unsigned int daif)
+{
+ __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
+}
+
+void bl31_entry(void)
+{
+ struct bl31_params *bl31_params;
+ void (*entry)(struct bl31_params *params, void *plat_params) = NULL;
+
+ bl31_params = bl2_plat_get_bl31_params();
+ entry = (void *)CONFIG_SPL_ATF_TEXT_BASE;
+
+ raw_write_daif(SPSR_EXCEPTION_MASK);
+ dcache_disable();
+
+ entry(bl31_params, NULL);
+}
trans_cmnd transport; /* transport routine */
};
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
/*
* The U-Boot EHCI driver can handle any transfer length as long as there is
* enough free heap space left, but the SCSI READ(10) and WRITE(10) commands are
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BAUDRATE=38400
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_CMD_UBI=y
CONFIG_MMC_MXS=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
+CONFIG_OMAP_WATCHDOG=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
+CONFIG_OMAP_WATCHDOG=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
+CONFIG_OMAP_WATCHDOG=y
CONFIG_OF_LIBFDT=y
CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_CM_T54=y
+CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
+CONFIG_OMAP_WATCHDOG=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_OMAP is not set
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
+CONFIG_OMAP_WATCHDOG=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BAUDRATE=38400
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_CMD_DHRYSTONE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BAUDRATE=38400
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BAUDRATE=38400
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_THERMAL=y
+CONFIG_USB=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_THERMAL=y
+CONFIG_USB=y
CONFIG_OF_LIBFDT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_LED_STATUS_CMD=y
CONFIG_MMC_MXS=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
CONFIG_MMC_MXS=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_PHY_SAMSUNG=y
CONFIG_DM_REGULATOR_MAX77686=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_LOGIC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
-CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP Logic # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
+# CONFIG_CMD_USB is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DM_I2C=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_OMAP5_UEVM=y
+CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_ARMV7_LPAE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BAUDRATE=38400
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_SYS_CONSOLE_BG_COL=0xff
CONFIG_SYS_CONSOLE_FG_COL=0x00
+CONFIG_OMAP_WATCHDOG=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
+CONFIG_OMAP_WATCHDOG=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_MMC_MXS=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
CONFIG_MMC_MXS=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BAUDRATE=38400
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_ERRNO_STR=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BAUDRATE=38400
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
+CONFIG_OMAP_WATCHDOG=y
CONFIG_TEGRA20_SFLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
CONFIG_MMC_MXS=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+++ /dev/null
-README on how reset time on OMAPs should be calculated
-
-CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC:
-Most OMAPs' provide a way to specify the time for
-which the reset should be held low while the voltages
-and Oscillator outputs stabilize.
-
-This time is mostly board and PMIC dependent. Hence the
-boards are expected to specify a pre-computed time
-using the above option, (the details on how to compute
-the value are given below) without which a default time
-as specified by CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
-is used.
-
-The value for CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
-can be computed using a summation of the below 3 parameters
--1- Time taken by the Osciallator to stop and restart
--2- PMIC OTP time
--3- Voltage ramp time, which can be derived using the
-PMIC slew rate and value of voltage ramp needed.
- APQ8016
- MSM8916
+config OMAP_GPIO
+ bool "TI OMAP GPIO driver"
+ depends on ARCH_OMAP2PLUS
+ default y
+ help
+ Support GPIO controllers on the TI OMAP3/4/5 and related (such as
+ AM335x/AM43xx/AM57xx/DRA7xx/etc) families of SoCs.
+
config PM8916_GPIO
bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
depends on DM_GPIO && PMIC_PM8916
u16 stat;
writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
#else
/* Read RAW status */
do {
udelay(waitdelay);
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
status = readw(&i2c_base->stat);
#else
/* Read RAW status */
/* own address */
writew(slaveadd, &i2c_base->oa);
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
/*
* Have to enable interrupts for OMAP2/3, these IPs don't have
* an 'irqstatus_raw' register and we shall have to poll 'stat'
config TWL4030_POWER
depends on OMAP34XX
bool "Enable driver for TI TWL4030 power management chip"
+ imply CMD_POWEROFF
---help---
The TWL4030 in a combination audio CODEC/power management with
GPIO and it is commonly used with the OMAP3 family of processors
;
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
-#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \
- defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
+#if defined(CONFIG_ARCH_OMAP2PLUS)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(ns16550_getfcr(com_port), &com_port->fcr);
if (baud_divisor != -1)
NS16550_setbrg(com_port, baud_divisor);
-#if defined(CONFIG_OMAP) || \
- defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
- defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
-
+#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX)
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, &com_port->mdr1);
-#endif /* CONFIG_OMAP */
+#endif
#if defined(CONFIG_SOC_KEYSTONE)
serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
#endif
priv->freq = max_hz;
priv->mode = mode;
priv->wordlen = priv->slave.wordlen;
-#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
+#if 0
+ /* Please migrate to DM_SPI support for this feature. */
priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
#endif
config USB_EHCI_HCD
bool "EHCI HCD (USB 2.0) support"
+ default y if ARCH_MX5 || ARCH_MX6
select USB_HOST
---help---
The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
You may want to read <file:Documentation/usb/ehci.txt>.
-config USB_EHCI
- bool
- default USB_EHCI_HCD
- ---help---
- TODO: rename after most boards switch to Kconfig
-
if USB_EHCI_HCD
config USB_EHCI_ATMEL
Enables support for the on-chip EHCI controller on Atmel chips.
config USB_EHCI_MARVELL
- bool "Support for MVEBU (AXP / A38x) on-chip EHCI USB controller"
- depends on ARCH_MVEBU
+ bool "Support for Marvell on-chip EHCI USB controller"
+ depends on ARCH_MVEBU || KIRKWOOD || ORION5X
default y
---help---
Enables support for the on-chip EHCI controller on MVEBU SoCs.
---help---
Enables support for the on-chip EHCI controller on i.MX7 SoCs.
+config USB_EHCI_OMAP
+ bool "Support for OMAP3+ on-chip EHCI USB controller"
+ depends on ARCH_OMAP2PLUS
+ default y
+ ---help---
+ Enables support for the on-chip EHCI controller on OMAP3 and later
+ SoCs.
+
if USB_EHCI_MX7
config MXC_USB_OTG_HACTIVE
obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
# echi
-obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
+obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
ifdef CONFIG_MPC512X
#define CONFIG_SOC_OMAP3430
#endif
-#ifdef CONFIG_OMAP4430
+#ifdef CONFIG_OMAP44XX
#define CONFIG_ARCH_OMAP4
#endif
twl6030_usb_device_settings();
#endif
-#ifdef CONFIG_OMAP4430
+#ifdef CONFIG_OMAP44XX
u32 *usbotghs_control = (u32 *)((*ctrl)->control_usbotghs_ctrl);
*usbotghs_control = USBOTGHS_CONTROL_AVALID |
USBOTGHS_CONTROL_VBUSVALID | USBOTGHS_CONTROL_IDDIG;
#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001
/* OMAP4430 has an internal PHY, use it */
-#ifdef CONFIG_OMAP4430
+#ifdef CONFIG_OMAP44XX
#define OMAP3_OTG_INTERFSEL_OMAP 0x0000
#else
#define OMAP3_OTG_INTERFSEL_OMAP 0x0001
stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY;
writel(stdby, &otg->forcestdby);
-#ifdef CONFIG_OMAP3_EVM
+#ifdef CONFIG_TARGET_OMAP3_EVM
musb_cfg.extvbus = omap3_evm_need_extvbus();
#endif
-#ifdef CONFIG_OMAP4430
+#ifdef CONFIG_OMAP44XX
u32 *usbotghs_control =
(u32 *)((*ctrl)->control_usbotghs_ctrl);
*usbotghs_control = 0x15;
int musb_platform_init(void);
-#ifdef CONFIG_OMAP3_EVM
+#ifdef CONFIG_TARGET_OMAP3_EVM
extern u8 omap3_evm_need_extvbus(void);
#endif
This provides basic infrastructure to support BCM2835/2836 watchdog
hardware, with a max timeout of ~15secs.
+config OMAP_WATCHDOG
+ bool "TI OMAP watchdog driver"
+ depends on ARCH_OMAP2PLUS
+ select HW_WATCHDOG
+ default y if AM33XX
+ help
+ Say Y here to enable the OMAP3+ watchdog driver.
+
config ULP_WATCHDOG
bool "i.MX7ULP watchdog"
help
--- /dev/null
+/*
+ * This is from the ARM TF Project,
+ * Repository: https://github.com/ARM-software/arm-trusted-firmware.git
+ * File: include/common/bl_common.h
+ * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
+ * reserved.
+ * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __BL_COMMON_H__
+#define __BL_COMMON_H__
+
+#define ATF_PARAM_EP 0x01
+#define ATF_PARAM_IMAGE_BINARY 0x02
+#define ATF_PARAM_BL31 0x03
+
+#define ATF_VERSION_1 0x01
+
+#define ATF_EP_SECURE 0x0
+#define ATF_EP_NON_SECURE 0x1
+
+#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
+ (_p)->h.type = (uint8_t)(_type); \
+ (_p)->h.version = (uint8_t)(_ver); \
+ (_p)->h.size = (uint16_t)sizeof(*_p); \
+ (_p)->h.attr = (uint32_t)(_attr) ; \
+ } while (0)
+
+#define MODE_RW_SHIFT 0x4
+#define MODE_RW_MASK 0x1
+#define MODE_RW_64 0x0
+#define MODE_RW_32 0x1
+
+#define MODE_EL_SHIFT 0x2
+#define MODE_EL_MASK 0x3
+#define MODE_EL3 0x3
+#define MODE_EL2 0x2
+#define MODE_EL1 0x1
+#define MODE_EL0 0x0
+
+#define MODE_SP_SHIFT 0x0
+#define MODE_SP_MASK 0x1
+#define MODE_SP_EL0 0x0
+#define MODE_SP_ELX 0x1
+
+#define SPSR_DAIF_SHIFT 6
+#define SPSR_DAIF_MASK 0x0f
+
+#define SPSR_64(el, sp, daif) \
+ (MODE_RW_64 << MODE_RW_SHIFT | \
+ ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
+ ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
+ ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
+
+#define SPSR_FIQ (1 << 6)
+#define SPSR_IRQ (1 << 7)
+#define SPSR_SERROR (1 << 8)
+#define SPSR_DEBUG (1 << 9)
+#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
+
+#define DAIF_FIQ_BIT (1<<0)
+#define DAIF_IRQ_BIT (1<<1)
+#define DAIF_ABT_BIT (1<<2)
+#define DAIF_DBG_BIT (1<<3)
+#define DISABLE_ALL_EXECPTIONS \
+ (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
+
+#ifndef __ASSEMBLY__
+
+/*******************************************************************************
+ * Structure used for telling the next BL how much of a particular type of
+ * memory is available for its use and how much is already used.
+ ******************************************************************************/
+struct aapcs64_params {
+ unsigned long arg0;
+ unsigned long arg1;
+ unsigned long arg2;
+ unsigned long arg3;
+ unsigned long arg4;
+ unsigned long arg5;
+ unsigned long arg6;
+ unsigned long arg7;
+};
+
+/***************************************************************************
+ * This structure provides version information and the size of the
+ * structure, attributes for the structure it represents
+ ***************************************************************************/
+struct param_header {
+ uint8_t type; /* type of the structure */
+ uint8_t version; /* version of this structure */
+ uint16_t size; /* size of this structure in bytes */
+ uint32_t attr; /* attributes: unused bits SBZ */
+};
+
+/*****************************************************************************
+ * This structure represents the superset of information needed while
+ * switching exception levels. The only two mechanisms to do so are
+ * ERET & SMC. Security state is indicated using bit zero of header
+ * attribute
+ * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
+ * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
+ * processing SMC to jump to BL31.
+ *****************************************************************************/
+struct entry_point_info {
+ struct param_header h;
+ uintptr_t pc;
+ uint32_t spsr;
+ struct aapcs64_params args;
+};
+
+/*****************************************************************************
+ * Image info binary provides information from the image loader that
+ * can be used by the firmware to manage available trusted RAM.
+ * More advanced firmware image formats can provide additional
+ * information that enables optimization or greater flexibility in the
+ * common firmware code
+ *****************************************************************************/
+struct atf_image_info {
+ struct param_header h;
+ uintptr_t image_base; /* physical address of base of image */
+ uint32_t image_size; /* bytes read from image file */
+};
+
+/*****************************************************************************
+ * The image descriptor struct definition.
+ *****************************************************************************/
+struct image_desc {
+ /* Contains unique image id for the image. */
+ unsigned int image_id;
+ /*
+ * This member contains Image state information.
+ * Refer IMAGE_STATE_XXX defined above.
+ */
+ unsigned int state;
+ uint32_t copied_size; /* image size copied in blocks */
+ struct atf_image_info atf_image_info;
+ struct entry_point_info ep_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that can be passed to
+ * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
+ * populated only if BL2 detects its presence. A pointer to a structure of this
+ * type should be passed in X0 to BL31's cold boot entrypoint.
+ *
+ * Use of this structure and the X0 parameter is not mandatory: the BL31
+ * platform code can use other mechanisms to provide the necessary information
+ * about BL32 and BL33 to the common and SPD code.
+ *
+ * BL31 image information is mandatory if this structure is used. If either of
+ * the optional BL32 and BL33 image information is not provided, this is
+ * indicated by the respective image_info pointers being zero.
+ ******************************************************************************/
+struct bl31_params {
+ struct param_header h;
+ struct atf_image_info *bl31_image_info;
+ struct entry_point_info *bl32_ep_info;
+ struct atf_image_info *bl32_image_info;
+ struct entry_point_info *bl33_ep_info;
+ struct atf_image_info *bl33_image_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that is passed to
+ * BL31, e.g. while passing control to it from BL2, bl31_params
+ * and other platform specific params
+ ******************************************************************************/
+struct bl2_to_bl31_params_mem {
+ struct bl31_params bl31_params;
+ struct atf_image_info bl31_image_info;
+ struct atf_image_info bl32_image_info;
+ struct atf_image_info bl33_image_info;
+ struct entry_point_info bl33_ep_info;
+ struct entry_point_info bl32_ep_info;
+ struct entry_point_info bl31_ep_info;
+};
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* __BL_COMMON_H__ */
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_SHA_HW_ACCEL
#endif
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
-#define CONFIG_USB_EHCI /* USB */
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_HAS_FSL_DR_USB
/* USB */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_SCCR_USBDRCM 3
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_PHY_TYPE "utmi"
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/*
* Support USB
*/
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
/* Current USB implementation supports the only USB controller,
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_ENV_OVERWRITE
#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
*/
#define CONFIG_HAS_FSL_MPH_USB
#ifdef CONFIG_HAS_FSL_MPH_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
/*
* USB
*/
-#define CONFIG_USB_EHCI
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_PCI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_EHCI_DEVICE 0
/*
* USB
*/
-#define CONFIG_USB_EHCI
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_PCI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_EHCI_DEVICE 0
#define CONFIG_HAS_FSL_DR_USB
#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
|| defined(CONFIG_FSL_SATA)
#endif
*/
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
*/
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define __T208xQDS_H
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_USB_EHCI
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
/*
* USB
*/
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#define __T2080RDB_H
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_USB_EHCI
#define CONFIG_FSL_SATA_V2
/* High Level Configuration Options */
/*
* USB
*/
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
/*
* USB
*/
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
/*
* USB
*/
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_HAS_FSL_DR_USB
#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_EHCI
-
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#define CONFIG_BOUNCE_BUFFER
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
-
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-
-#define CONFIG_OMAP
-
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
/* Hardware drivers */
-/* OMAP GPIO configuration */
-#define CONFIG_OMAP_GPIO
-
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_MMC_ENV_PART 1
/* USB host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* PCI host support */
#define CONFIG_SYS_MMC_ENV_PART 1
/* USB host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* PCI host support */
#define CONFIG_RTC_M41T11
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_CMD_NAND
/*
- * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
+ * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
* NB: in this case, USB 1.1 devices won't be recognized.
*/
/* USB */
#ifdef CONFIG_CMD_USB
-#ifndef CONFIG_USB_EHCI
+#ifndef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_LCD_DT_SIMPLEFB
#define LCD_BPP LCD_COLOR32
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_OMAP_WATCHDOG
-
/* Bootcount using the RTC block */
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
#define CONFIG_BOOTCOUNT_LIMIT
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
#define CONFIG_AM33XX
-#define CONFIG_OMAP
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP24XX
-/* GPIO */
-#define CONFIG_OMAP_GPIO
/*
* Our platforms make use of SPL to initalize the hardware (primarily
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_SDRC /* The chip has SDRC controller */
/* USB */
#define CONFIG_USB_OMAP3
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_MUSB_UDC
#define CONFIG_TWL4030_USB
#define CONFIG_SPLASHIMAGE_GUARD
-/* GPIO banks */
-#ifdef CONFIG_LED_STATUS
-#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
-#endif
-
/* Display Configuration */
-#define CONFIG_OMAP3_GPIO_2
-#define CONFIG_OMAP3_GPIO_5
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP LCD_COLOR16
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_CM_T3517 /* working with CM-T3517 */
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_OMAP_GPIO
-
/* USB */
#define CONFIG_USB_MUSB_AM35X
#ifndef CONFIG_USB_MUSB_AM35X
#define CONFIG_USB_OMAP3
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
#else /* !CONFIG_USB_MUSB_AM35X */
/* Status LED */
#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
-/* GPIO banks */
-#ifdef CONFIG_LED_STATUS
-#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
-#endif
-
/* Display Configuration */
-#define CONFIG_OMAP3_GPIO_2
-#define CONFIG_OMAP3_GPIO_5
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/* USB UHH support options */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
-/* Max time to hold reset on this board, see doc/README.omap-reset-time */
-#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_I2C_TEGRA
/* USB host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_SYS_MMC_ENV_PART 1
/* USB host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#endif
/* USB Host Support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_VF
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/*
* USB
*/
-#define CONFIG_USB_EHCI
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_AT91_WANTS_COMMON_PHY
/* USB */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
/* USB DFU support */
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
/*
#define CONFIG_FACTORYSET
-/* Watchdog */
-#define CONFIG_OMAP_WATCHDOG
-
/* Define own nand partitions */
#define CONFIG_ENV_OFFSET_REDUND 0x2E0000
#define CONFIG_ENV_SIZE_REDUND 0x2000
#endif
#if !defined(CONFIG_USB_XHCI_HCD)
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MARVELL
#define CONFIG_EHCI_IS_TDI
#endif
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* USB UHH support options */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB2.0 Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#include "tam3517-common.h"
-#undef CONFIG_USB_EHCI
-#undef CONFIG_USB_EHCI_OMAP
#undef CONFIG_USB_OMAP3
/* Our console port is port3 */
* Common USB/EHCI configuration
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_MARVELL
#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
#define CONFIG_SYS_I2C_SPEED 100000
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_DCACHE_OFF
#endif
-/* Watchdog */
-#define CONFIG_OMAP_WATCHDOG
-
/* Define own nand partitions */
#define CONFIG_ENV_OFFSET_REDUND 0xB80000
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
#define CONFIG_USB_XHCI_EXYNOS
/* USB Configs */
#ifdef CONFIG_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_ENV_SIZE 0x4000
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_ARMADA100
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */
#define CONFIG_ARP_TIMEOUT 200UL
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
-/*
- * Platform
- */
-
-#define CONFIG_OMAP
-#define CONFIG_OMAP4430
-
/*
* Board
*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
-/*
- * GPIO
- */
-
-#define CONFIG_OMAP_GPIO
-
/*
* I2C
*/
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_TMU_CLK_DIV 4
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* USB Configs */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/*#define CONFIG_HAS_FSL_DR_USB*/
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
/*#define CONFIG_HAS_FSL_DR_USB*/
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
/*#define CONFIG_HAS_FSL_DR_USB*/
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
/*
* USB/EHCI
*/
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
* USB
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX5
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
* USB
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* USB device */
"128k@0x19C0000(swupdate-kernel-dtb.nor)"
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP3_MCX /* working with mcx */
-#define CONFIG_OMAP_GPIO
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
115200}
/* EHCI */
-#define CONFIG_OMAP3_GPIO_2
-#define CONFIG_OMAP3_GPIO_5
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
/* USB host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
*/
#if defined(CONFIG_CMD_USB)
-#define CONFIG_USB_EHCI /* Enable EHCI Support */
#define CONFIG_USB_EHCI_FSL /* On a FSL platform */
#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_OMAP3_GPIO_4
#define CONFIG_HOSTNAME mt_ventoux
/*
* Common USB/EHCI configuration
*/
#if defined(CONFIG_CMD_USB) && !defined(CONFIG_DM)
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
#define CONFIG_SYS_NAND_LARGEPAGE
/* EHCI driver */
-#define CONFIG_USB_EHCI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX5
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX5
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX5
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_IMX_VIDEO_SKIP
/* USB */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
/* USB Configs */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* USB Configs */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* USB Configs */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* USB Configs */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
/* USB */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_IS_TDI
#endif
* USB/EHCI
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SUPPORT_VFAT
#define CONFIG_PHY_MICREL_KSZ9021
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
/*
* High Level Configuration Options
*/
-
-#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP3430 /* which is in a 3430 */
-#define CONFIG_OMAP3_RX51 /* working with RX51 */
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
#define CONFIG_TWL4030_LED
#define CONFIG_TWL4030_KEYPAD
-#define CONFIG_OMAP_GPIO
#define GPIO_SLIDE 71
/*
/* USB Configs */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_LIB_HW_RAND
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
/* DFU */
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
/* USB EHCI */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_USB_ETHER_SMSC95XX
-/* GPIO banks */
-#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
-#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
-
/* commands to include */
#define MTDIDS_DEFAULT "nand0=nand"
/*
* High level configuration options
*/
-#define CONFIG_OMAP /* This is TI OMAP core */
-#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
-#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
-
/*
* Clock related definitions
*/
#endif
#endif
-/* GPIO banks */
-#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */
-#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
-#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
-
/* USB */
#define CONFIG_USB_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
/* Hardware drivers */
-/* GPIO banks */
-#define CONFIG_OMAP3_GPIO_4 /* GPIO 96..128 is in GPIO bank 4 */
-#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
-
#define CONFIG_USB_OMAP3
/* commands to include */
#define CONFIG_TWL4030_LED
/* USB EHCI */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-/* Initialize GPIOs by default */
-#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */
-#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */
-#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */
-#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO Bank 5 */
-#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */
-
/* commands to include */
#ifdef CONFIG_NAND
/* TWL4030 LED */
#define CONFIG_TWL4030_LED
-/* Initialize GPIOs by default */
-#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */
-#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */
-
/*
* NS16550 Configuration
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
-
#define CONFIG_NAND
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#include <asm/arch/cpu.h> /* get chip and board defs */
*/
/* USB UHH support options */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
/* USB UHH support options */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONSOLEDEV "ttyO2"
-/* Max time to hold reset on this board, see doc/README.omap-reset-time */
-#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
-
#define CONFIG_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SYS_FSL_USDHC_NUM 2
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_HAS_FSL_DR_USB
#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#define CONFIG_HAS_FSL_DR_USB
#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB2.0 Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB2.0 Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB2.0 Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SUPPORT_EMMC_BOOT
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_AT91_WANTS_COMMON_PHY
/* USB */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_PHYLIB
/* USB config */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
/* USB host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_FACTORYSET
-/* Watchdog */
-#define CONFIG_OMAP_WATCHDOG
-
#ifndef CONFIG_SPL_BUILD
/* Use common default */
#define CONFIG_FACTORYSET
-/* Watchdog */
-#define CONFIG_OMAP_WATCHDOG
-
/* Define own nand partitions */
#define CONFIG_ENV_OFFSET_REDUND 0x2E0000
#define CONFIG_ENV_SIZE_REDUND 0x2000
#endif /* CONFIG_SPL_BUILD */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_HW_WATCHDOG
-#endif
-
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#endif
#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
/* USB */
#ifdef CONFIG_440EPX
-
-#undef CONFIG_USB_EHCI /* OHCI by default */
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_PPC4XX
#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#else /* CONFIG_USB_EHCI */
+#else /* CONFIG_USB_EHCI_HCD */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#define __CONFIG_SIEMENS_AM33X_COMMON_H
#define CONFIG_AM33XX
-#define CONFIG_OMAP
#include <asm/arch/omap.h>
#endif
#endif
-#define CONFIG_OMAP_GPIO
-
-/* Gpio cmd support */
-
-/* Watchdog */
-#define CONFIG_HW_WATCHDOG
-
/* Reboot after 60 sec if bootcmd fails */
#define CONFIG_RESET_TO_RETRY
#define CONFIG_BOOT_RETRY_TIME 60
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_TFTP_TSIZE
/* USB */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
/* MMC */
#define CONFIG_ARM_ARCH_CP15_ERRATA
-/*
- * Platform
- */
-
-#define CONFIG_OMAP
-
/*
* Board
*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
-/*
- * GPIO
- */
-
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP3_GPIO_2
-#define CONFIG_OMAP3_GPIO_3
-#define CONFIG_OMAP3_GPIO_4
-#define CONFIG_OMAP3_GPIO_5
-#define CONFIG_OMAP3_GPIO_6
-
/*
* I2C
*/
#define CONFIG_SYS_TMU_CLK_DIV 4
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
* A10 specific configuration
*/
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_SUNXI
#endif
* A64 specific configuration
*/
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_SUNXI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
* High Level Configuration Options
*/
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_SUNXI
#endif
* A31 specific configuration
*/
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_SUNXI
#endif
* A20 specific configuration
*/
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_SUNXI
#endif
* A23 specific configuration
*/
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_SUNXI
#endif
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80008000
/*
* DDR related
*/
-#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
/*
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
/* EHCI */
-#define CONFIG_OMAP3_GPIO_5
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP /* in a TI OMAP core */
-
-#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* Has an SDRC controller */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-/* GPIO banks */
-#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
-#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
-#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
-#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
-#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
-
/* commands to include */
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
*/
/* USB EHCI */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* USB */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
/* USB host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#endif
/* remove USB */
-#ifdef CONFIG_USB_EHCI
-#undef CONFIG_USB_EHCI
-#endif
#ifdef CONFIG_USB_EHCI_TEGRA
#undef CONFIG_USB_EHCI_TEGRA
#endif
#define CONFIG_FACTORYSET
-/* Watchdog */
-#define CONFIG_OMAP_WATCHDOG
-
/* Define own nand partitions */
#define CONFIG_ENV_OFFSET_REDUND 0x2E0000
#define CONFIG_ENV_SIZE_REDUND 0x2000
#define CONFIG_TI81XX
#define CONFIG_TI814X
-#define CONFIG_OMAP
#include <asm/arch/omap.h>
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
-#define CONFIG_OMAP_GPIO
-
/**
* Physical Memory Map
*/
#define CONFIG_TI81XX
#define CONFIG_TI816X
-#define CONFIG_OMAP
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_CMD_ASKENV
-#define CONFIG_OMAP_GPIO
#define CONFIG_FS_FAT
*/
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
-/* Enable the HW watchdog, since we can use this with bootcount */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_OMAP_WATCHDOG
-
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x402F0400 and 0x4030B800 as a download area and
#ifndef __CONFIG_TI_ARMV7_OMAP_H__
#define __CONFIG_TI_ARMV7_OMAP_H__
-/* Common defines for all OMAP architecture based SoCs */
-#define CONFIG_OMAP
-
/* I2C IP block */
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* SPI IP Block */
#define CONFIG_OMAP3_SPI
-/* GPIO block */
-#define CONFIG_OMAP_GPIO
-
/*
* GPMC NAND block. We support 1 device and the physical address to
* access CS0 at is 0x8000000.
#ifndef __CONFIG_TI_OMAP4_COMMON_H
#define __CONFIG_TI_OMAP4_COMMON_H
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_MISC_INIT_R
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_PHY_MICREL_KSZ9021
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_OMAP /* in a TI OMAP core */
-
#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
/* Hardware drivers */
-/* GPIO support */
-#define CONFIG_OMAP_GPIO
-
-/* GPIO banks */
-#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */
-
-/* LED support */
-
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_SPL_BOARD_INIT
-/* gpio 55 is used as SPL_OS_BOOT_KEY */
-#define CONFIG_OMAP3_GPIO_2
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* USB */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/*
* USB/EHCI
*/
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_VCT /* on VCT platform */
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
/* USB */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#endif
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
/* USB Configs */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* USB networking support */
#define CONFIG_FPGA_COUNT 1
/* USB EHCI options */
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SPEAR
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/*-----------------------------------------------------------------------
* USB configuration
*/
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_PCI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/*
* USB
*/
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */
/* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
* USB
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT 1
int spl_mmc_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev);
+void bl31_entry(void);
#endif
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, int interval);
-#if defined CONFIG_USB_EHCI || defined CONFIG_USB_MUSB_HOST || defined(CONFIG_DM_USB)
+#if defined CONFIG_USB_EHCI_HCD || defined CONFIG_USB_MUSB_HOST \
+ || defined(CONFIG_DM_USB)
struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe,
int queuesize, int elementsize, void *buffer, int interval);
int destroy_int_queue(struct usb_device *dev, struct int_queue *queue);
KBUILD_CFLAGS += $(warning)
+dtc-warning-2 += $(call dtc-option,-Wnode_name_chars_strict)
+dtc-warning-2 += $(call dtc-option,-Wproperty_name_chars_strict)
+
+dtc-warning := $(dtc-warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+dtc-warning += $(dtc-warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+dtc-warning += $(dtc-warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+
+DTC_FLAGS += $(dtc-warning)
+
else
# Disable noisy checks by default
DTC_FLAGS += $(call dtc-option,-Wno-unit_address_vs_reg)
+DTC_FLAGS += $(call dtc-option,-Wno-simple_bus_reg)
+DTC_FLAGS += $(call dtc-option,-Wno-unit_address_format)
+DTC_FLAGS += $(call dtc-option,-Wno-pci_bridge)
+DTC_FLAGS += $(call dtc-option,-Wno-pci_device_bus_num)
+DTC_FLAGS += $(call dtc-option,-Wno-pci_device_reg)
endif
CONFIG_DEFAULT
CONFIG_DEFAULT_CONSOLE
CONFIG_DEFAULT_IMMR
-CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
CONFIG_DEFAULT_SPI_BUS
CONFIG_DEFAULT_SPI_CS
CONFIG_DEFAULT_SPI_MODE
CONFIG_OF_SPI_FLASH
CONFIG_OF_STDOUT_PATH
CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
-CONFIG_OMAP
-CONFIG_OMAP3430
-CONFIG_OMAP3_AM3517CRANE
-CONFIG_OMAP3_DEVKIT8000
-CONFIG_OMAP3_EVM
-CONFIG_OMAP3_GPIO_2
-CONFIG_OMAP3_GPIO_3
-CONFIG_OMAP3_GPIO_4
-CONFIG_OMAP3_GPIO_5
-CONFIG_OMAP3_GPIO_6
-CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID
-CONFIG_OMAP3_MCX
-CONFIG_OMAP3_MICRON_DDR
-CONFIG_OMAP3_RX51
-CONFIG_OMAP3_SPI_D0_D1_SWAPPED
-CONFIG_OMAP3_ZOOM1
-CONFIG_OMAP4430
CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
-CONFIG_OMAP_GPIO
-CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
CONFIG_OMAP_USB2PHY2_HOST
CONFIG_OMAP_USB3PHY1_HOST
CONFIG_OMAP_USB_PHY
-CONFIG_OMAP_VC_I2C_HS_MCODE
-CONFIG_OMAP_WATCHDOG
CONFIG_OPTREX_BW
CONFIG_ORIGEN
CONFIG_OS1_ENV_ADDR
CONFIG_USB_EHCI_MX5
CONFIG_USB_EHCI_MXC
CONFIG_USB_EHCI_MXS
-CONFIG_USB_EHCI_OMAP
CONFIG_USB_EHCI_PCI
CONFIG_USB_EHCI_PPC4XX
CONFIG_USB_EHCI_RMOBILE
projects / people / ms / u-boot.git / commitdiff
