{
switch (imxtype) {
case MXC_CPU_MX23:
- return "23"; /* Quad-Plus version of the mx6 */
+ return "23";
case MXC_CPU_MX28:
- return "28"; /* Dual-Plus version of the mx6 */
+ return "28";
default:
return "??";
}
{
u32 mask, *addr;
- if (is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6ul()) {
mask = MXC_CCM_CCGR3_ENET_MASK;
addr = &imx_ccm->CCGR3;
} else {
{
u32 mask;
- if (is_cpu_type(MXC_CPU_MX6UL))
+ if (is_mx6ul())
mask = MXC_CCM_CCGR5_UART_MASK;
else
mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6sx() || is_mx6ul()) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = &imx_ccm->CCGR6;
} else {
switch (pll) {
case PLL_BUS:
- if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ if (!is_mx6ul()) {
if (pfd_num == 3) {
/* No PFD3 on PPL2 */
return 0;
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
- if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
- is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6sl() || is_mx6sx() ||
+ is_mx6dqp() || is_mx6ul()) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
}
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
- if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
- is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
- is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
- is_cpu_type(MXC_CPU_MX6SL)) {
+ if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
- if (is_cpu_type(MXC_CPU_MX6SL)) {
+ if (is_mx6sl()) {
if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
freq = MXC_HCLK;
else
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
- if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
+ if (!is_mx6sx() && !is_mx6ul()) {
debug("This chip not support lcd!\n");
return;
}
return;
}
- if (is_cpu_type(MXC_CPU_MX6SX)) {
+ if (is_mx6sx()) {
reg = readl(&imx_ccm->cscdr2);
/* Can't change clocks when clock not from pre-mux */
if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
((postd - 1) <<
MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
- } else if (is_cpu_type(MXC_CPU_MX6SX)) {
+ } else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
u32 reg = 0;
u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
- if (is_cpu_type(MXC_CPU_MX6SX)) {
+ if (is_mx6sx()) {
if ((base_addr != LCDIF1_BASE_ADDR) &&
(base_addr != LCDIF2_BASE_ADDR)) {
puts("Wrong LCD interface!\n");
MXC_CCM_CCGR3_DISP_AXI_MASK) :
(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
MXC_CCM_CCGR3_DISP_AXI_MASK);
- } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+ } else if (is_mx6ul()) {
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
} else if (fec_id == 1) {
/* Only i.MX6SX/UL support ENET2 */
- if (!(is_cpu_type(MXC_CPU_MX6SX) ||
- is_cpu_type(MXC_CPU_MX6UL)))
+ if (!(is_mx6sx() || is_mx6ul()))
return -EINVAL;
reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
- if (is_cpu_type(MXC_CPU_MX6SX))
+ if (is_mx6sx())
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
else
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
/* Make sure PFDs are disabled at boot. */
reg = readl(&mxc_ccm->analog_pfd_528);
/* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
- if (is_cpu_type(MXC_CPU_MX6DL))
+ if (is_mx6sdl())
reg |= 0x80008080;
else
reg |= 0x80808080;
int reg;
reg = readl(&mxc_ccm->analog_pfd_528);
- if (is_cpu_type(MXC_CPU_MX6DL))
+ if (is_mx6sdl())
reg &= ~(0x80008080);
else
reg &= ~(0x80808080);
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
- if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
- !is_cpu_type(MXC_CPU_MX6SL)) \
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \
mmdc1->entry = value; \
} while (0)
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
- !is_cpu_type(MXC_CPU_MX6SL))
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+ if (is_mx6dq() || is_mx6dqp()) {
if (mem_speed > 1066)
mem_speed = 1066; /* 1066 MT/s */
* Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
* up to 528 MHz, so reduce the clock to fit chip specs
*/
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+ if (is_mx6dq() || is_mx6dqp()) {
if (clock > 528)
clock = 528; /* 528 MHz */
}
#define OCOTP_CFG3_SPEED_1GHZ 2
#define OCOTP_CFG3_SPEED_1P2GHZ 3
+/*
+ * For i.MX6UL
+ */
+#define OCOTP_CFG3_SPEED_528MHZ 1
+#define OCOTP_CFG3_SPEED_696MHZ 2
+
u32 get_cpu_speed_grade_hz(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
+ if (is_mx6ul()) {
+ if (val == OCOTP_CFG3_SPEED_528MHZ)
+ return 528000000;
+ else if (val == OCOTP_CFG3_SPEED_696MHZ)
+ return 69600000;
+ else
+ return 0;
+ }
+
switch (val) {
/* Valid for IMX6DQ */
case OCOTP_CFG3_SPEED_1P2GHZ:
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ if (is_mx6dq() || is_mx6dqp())
return 1200000000;
/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
case OCOTP_CFG3_SPEED_1GHZ:
return 996000000;
/* Valid for IMX6DQ */
case OCOTP_CFG3_SPEED_850MHZ:
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ if (is_mx6dq() || is_mx6dqp())
return 852000000;
/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
case OCOTP_CFG3_SPEED_800MHZ:
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+ if (is_mx6sx() || is_mx6ul() || is_mx6sl())
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
else
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
- if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
- dev_id == 1) {
+ if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
u32 value = readl(&fuse->mac_addr2);
mac[0] = value >> 24 ;
mac[1] = value >> 16 ;
u32 mask528;
u32 reg, periph1, periph2;
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+ if (is_mx6sx() || is_mx6ul())
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
return;
}
+
+void reset_misc(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+ lcdif_power_down();
+#endif
+}
+
#define hab_rvt_report_event_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
)
#define hab_rvt_report_status_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
)
#define hab_rvt_authenticate_image_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
)
#define hab_rvt_entry_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
)
#define hab_rvt_exit_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
((hab_rvt_exit_t *)HAB_RVT_EXIT) \
)
*/
/* Check MMU enabled */
if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
- if (is_cpu_type(MXC_CPU_MX6Q) ||
- is_cpu_type(MXC_CPU_MX6D)) {
+ if (is_mx6dq()) {
/*
* This won't work on Rev 1.0.0 of
* i.MX6Q/D, since their ROM doesn't
*/
if (!is_mx6dqp())
writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
- } else if (is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO)) {
+ } else if (is_mx6sdl()) {
writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
- } else if (is_cpu_type(MXC_CPU_MX6SL)) {
+ } else if (is_mx6sl()) {
writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
}
}
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
- if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+ if (is_mx6sx() || is_mx7()) {
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
- is_soc_type(MXC_SOC_MX7))
+ if (is_mx6sx() || is_mx6ul() || is_mx7())
writew(enable, &wdog3->wmcr);
#ifdef CONFIG_MX7D
writew(enable, &wdog4->wmcr);
#if defined(CONFIG_MX6QDL)
stride = 2;
- if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ if (!is_mx6dq())
p += 1;
#else
stride = 1;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
- if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ if (!is_mx6dq() && !is_mx6dqp())
return 1;
ret = enable_sata_clock();
static inline int gpt_has_clk_source_osc(void)
{
#if defined(CONFIG_MX6)
- if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
- (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
- is_cpu_type(MXC_CPU_MX6UL))
+ if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
+ is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
return 1;
return 0;
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
/* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
- if (is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO) ||
- is_cpu_type(MXC_CPU_MX6SX) ||
- is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */
#define is_cpu_type(cpu) (get_cpu_type() == cpu)
#define is_soc_type(soc) (get_soc_type() == soc)
+#define is_mx6() (is_soc_type(MXC_SOC_MX6))
+#define is_mx7() (is_soc_type(MXC_SOC_MX7))
+
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
+#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
+#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
}
#endif
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
static void setup_fec(void)
{
if (is_mx6dqp()) {
if (is_mx6dqp())
setenv("board_rev", "MX6QP");
- else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ else if (is_mx6dq())
setenv("board_rev", "MX6Q");
- else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+ else if (is_mx6sdl())
setenv("board_rev", "MX6DL");
#endif
if (is_mx6dqp())
setenv("board_rev", "MX6QP");
- else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ else if (is_mx6dq())
setenv("board_rev", "MX6Q");
- else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+ else if (is_mx6sdl())
setenv("board_rev", "MX6DL");
#endif
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize "
- "mmc dev %d\n", i);
- return ret;
- }
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize "
+ "mmc dev %d\n", i);
+ return ret;
+ }
}
return 0;
The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel)
based on the return value of the spl_start_uboot() function. While often
this can simply be the state of a GPIO based pushbutton or DIP switch, for
-Gateworks Ventana, we use the U-Boot environment 'boot_os' variable which if
-set to '1' will choose to boot the OS rather than U-Boot. While the choice
-of adding env support to the SPL adds a little bit of time to the boot
-process as well as (significant really) SPL code space this was deemed most
-flexible as within the large variety of Gateworks Ventana boards not all of
-them have a user pushbutton and that pushbutton may be configured as a hard
-reset per user configuration.
+Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00:
+set to '0' will choose to boot to U-Boot and otherwise it will boot to OS.
To use Falcon mode it is required that you first 'prepare' the 'args' data
that is stored on your boot medium along with the kernel (which can be any
# flash args (at 17MB)
Ventana > nand erase.part args && nand write 18000000 args 100000
- # set boot_os env var to enable booting to Linux
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
Be sure to adjust 'bootargs' above to your OS needs (this will be different
for various distros such as OpenWrt, Yocto, Android, etc). You can use the
# write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
Ventana > mmc write 18000000 0x800 0x800
- # set boot_os to enable falcon mode
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
Be sure to adjust 'bootargs' above to your OS needs (this will be different
for various distros such as OpenWrt, Yocto, Android, etc). You can use the
/* common to add baseboards */
static iomux_v3_cfg_t const gw_gpio_pads[] = {
- /* MSATA_EN */
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+ /* SD3_VSELECT */
+ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
};
/* prototype */
};
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* USB_HUBRST# */
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* PANLEDG# */
};
static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* USBOTG_SEL */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* USB_HUBRST# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
+static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
+
+ /* VID_PWR */
+ IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
/*
* Board Specific GPIO
.vidin_en = IMX_GPIO_NR(3, 31),
.usb_sel = IMX_GPIO_NR(1, 2),
.wdis = IMX_GPIO_NR(7, 12),
+ .msata_en = GP_MSATA_SEL,
},
/* GW53xx */
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
+ .msata_en = GP_MSATA_SEL,
},
/* GW54xx */
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
.wdis = IMX_GPIO_NR(5, 17),
+ .msata_en = GP_MSATA_SEL,
},
/* GW551x */
.pcie_rst = IMX_GPIO_NR(1, 29),
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
+ .msata_en = GP_MSATA_SEL,
+ },
+
+ /* GW553x */
+ {
+ .gpio_pads = gw553x_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+ IMX_GPIO_NR(1, 18),
+ { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+ 4
+ },
+ },
+ .num_gpios = 4,
+ .leds = {
+ IMX_GPIO_NR(4, 10),
+ IMX_GPIO_NR(4, 11),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 0),
+ .vidin_en = IMX_GPIO_NR(5, 20),
+ .wdis = IMX_GPIO_NR(7, 12),
},
};
gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
gpio_direction_output(GP_USB_OTG_PWR, 0);
- /* MSATA Enable - default to PCI */
- gpio_request(GP_MSATA_SEL, "msata_en");
- gpio_direction_output(GP_MSATA_SEL, 0);
-
/* RS232_EN# */
gpio_request(GP_RS232_EN, "rs232_en");
gpio_direction_output(GP_RS232_EN, 0);
}
}
+ /* MSATA Enable - default to PCI */
+ if (gpio_cfg[board].msata_en) {
+ gpio_request(gpio_cfg[board].msata_en, "msata_en");
+ gpio_direction_output(gpio_cfg[board].msata_en, 0);
+ }
+
/* Expansion Mezzanine IO */
if (gpio_cfg[board].mezz_pwren) {
gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
gpio_request(gpio_cfg[board].wdis, "wlan_dis");
gpio_direction_output(gpio_cfg[board].wdis, 1);
}
+
+ /* sense vselect pin to see if we support uhs-i */
+ gpio_request(GP_SD3_VSELECT, "sd3_vselect");
+ gpio_direction_input(GP_SD3_VSELECT);
+ gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT);
}
/* setup GPIO pinmux and default configuration per baseboard and env */
gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
/* MSATA Enable */
- if (is_cpu_type(MXC_CPU_MX6Q) &&
- test_bit(EECONFIG_SATA, info->config)) {
+ if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
gpio_direction_output(GP_MSATA_SEL,
- (hwconfig("msata")) ? 1 : 0);
+ (hwconfig("msata")) ? 1 : 0);
}
/* USBOTG Select (PCISKT or FrontPanel) */
ctrl);
gpio_requestf(cfg->gpio_param, "dio%d", i);
gpio_direction_input(cfg->gpio_param);
- } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
+ } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
cfg->pwm_padmux) {
+ if (!cfg->pwm_param) {
+ printf("DIO%d: Error: pwm config invalid\n",
+ i);
+ continue;
+ }
if (!quiet)
printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
}
if (!quiet) {
- if (is_cpu_type(MXC_CPU_MX6Q) &&
- (test_bit(EECONFIG_SATA, info->config))) {
+ if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
printf("MSATA: %s\n", (hwconfig("msata") ?
"enabled" : "disabled"));
}
#define GP_SD3_CD IMX_GPIO_NR(7, 0)
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
+#define GP_SD3_VSELECT IMX_GPIO_NR(6, 14)
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
int pcie_sson;
int usb_sel;
int wdis;
+ int msata_en;
+ bool usd_vsel;
};
extern struct ventana gpio_cfg[GW_UNKNOWN];
} else if (info->model[4] == '2') {
type = GW552x;
break;
+ } else if (info->model[4] == '3') {
+ type = GW553x;
+ break;
}
/* fall through */
default:
/* list of config bits that the bootloader will remove from dtb if not set */
struct ventana_eeprom_config econfig[] = {
{ "eth0", "ethernet0", EECONFIG_ETH0 },
- { "eth1", "ethernet1", EECONFIG_ETH1 },
- { "sata", "ahci0", EECONFIG_SATA },
- { "pcie", NULL, EECONFIG_PCIE},
- { "lvds0", NULL, EECONFIG_LVDS0 },
- { "lvds1", NULL, EECONFIG_LVDS1 },
{ "usb0", NULL, EECONFIG_USB0 },
{ "usb1", NULL, EECONFIG_USB1 },
{ "mmc0", NULL, EECONFIG_SD0 },
{ "mmc1", NULL, EECONFIG_SD1 },
{ "mmc2", NULL, EECONFIG_SD2 },
{ "mmc3", NULL, EECONFIG_SD3 },
- { "uart0", NULL, EECONFIG_UART0 },
- { "uart1", NULL, EECONFIG_UART1 },
- { "uart2", NULL, EECONFIG_UART2 },
- { "uart3", NULL, EECONFIG_UART3 },
- { "uart4", NULL, EECONFIG_UART4 },
- { "ipu0", NULL, EECONFIG_IPU0 },
- { "ipu1", NULL, EECONFIG_IPU1 },
- { "can0", NULL, EECONFIG_FLEXCAN },
- { "i2c0", NULL, EECONFIG_I2C0 },
- { "i2c1", NULL, EECONFIG_I2C1 },
- { "i2c2", NULL, EECONFIG_I2C2 },
- { "vpu", NULL, EECONFIG_VPU },
- { "csi0", NULL, EECONFIG_CSI0 },
- { "csi1", NULL, EECONFIG_CSI1 },
- { "spi0", NULL, EECONFIG_ESPCI0 },
- { "spi1", NULL, EECONFIG_ESPCI1 },
- { "spi2", NULL, EECONFIG_ESPCI2 },
- { "spi3", NULL, EECONFIG_ESPCI3 },
- { "spi4", NULL, EECONFIG_ESPCI4 },
- { "spi5", NULL, EECONFIG_ESPCI5 },
- { "gps", "pps", EECONFIG_GPS },
- { "hdmi_in", NULL, EECONFIG_HDMI_IN },
- { "hdmi_out", NULL, EECONFIG_HDMI_OUT },
- { "cvbs_in", NULL, EECONFIG_VID_IN },
- { "cvbs_out", NULL, EECONFIG_VID_OUT },
- { "nand", NULL, EECONFIG_NAND },
{ /* Sentinel */ }
};
#include <i2c.h>
#include <linux/ctype.h>
+#include "ventana_eeprom.h"
#include "gsc.h"
/*
puts("fRD\n");
} else {
ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
+ if (reg == GSC_HWMON_TEMP && ui > 0x8000)
+ ui -= 0xffff;
if (ui == 0xffffff)
puts("invalid\n");
else
int gsc_info(int verbose)
{
- const char *model = getenv("model");
unsigned char buf[16];
i2c_set_bus_num(0);
gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
&buf[GSC_SC_STATUS], 1);
}
+ if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
+ int ui = buf[0] | buf[1]<<8;
+ if (ui > 0x8000)
+ ui -= 0xffff;
+ printf(" board temp at %dC", ui / 10);
+ }
puts("\n");
if (!verbose)
return CMD_RET_SUCCESS;
read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
- read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
+ if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
+ read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3);
- switch (model[3]) {
+ switch (ventana_info.model[3]) {
case '1': /* GW51xx */
read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
break;
}
#ifdef CONFIG_CMD_GSC
+static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned char reg;
+ unsigned long secs = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ secs = simple_strtoul(argv[1], NULL, 10);
+ printf("GSC Sleeping for %ld seconds\n", secs);
+
+ i2c_set_bus_num(0);
+ reg = (secs >> 24) & 0xff;
+ if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1))
+ goto error;
+ reg = (secs >> 16) & 0xff;
+ if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1))
+ goto error;
+ reg = (secs >> 8) & 0xff;
+ if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1))
+ goto error;
+ reg = secs & 0xff;
+ if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1))
+ goto error;
+ if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
+ goto error;
+ reg |= (1 << 2);
+ if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
+ goto error;
+ reg &= ~(1 << 2);
+ reg |= 0x3;
+ if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
+ goto error;
+
+ return CMD_RET_SUCCESS;
+
+error:
+ printf("i2c error\n");
+ return CMD_RET_FAILURE;
+}
+
static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned char reg;
if (strcasecmp(argv[1], "wd") == 0)
return do_gsc_wd(cmdtp, flag, --argc, ++argv);
+ else if (strcasecmp(argv[1], "sleep") == 0)
+ return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
return CMD_RET_USAGE;
}
U_BOOT_CMD(
gsc, 4, 1, do_gsc, "GSC configuration",
- "[wd enable [30|60]]|[wd disable]\n"
+ "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
);
#endif /* CONFIG_CMD_GSC */
#include <asm/io.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
+#include <hwconfig.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* CD */
- IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* ENET */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FEC_MXC
- if (board_type != GW551x && board_type != GW552x) {
+ struct ventana_board_info *info = &ventana_info;
+
+ if (test_bit(EECONFIG_ETH0, info->config)) {
setup_iomux_enet(GP_PHY_RST);
cpu_eth_init(bis);
}
writel(reg, &iomux->gpr[2]);
/* Enable Backlight */
+ gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
- /* Backlight CABEN on LVDS connector */
- gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+ /* LVDS Backlight GPIO on LVDS connector - output low */
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
setenv("model_base", str);
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file1", fdt);
- if (board_type != GW551x && board_type != GW552x)
+ if (board_type != GW551x &&
+ board_type != GW552x &&
+ board_type != GW553x)
str[4] = 'x';
str[5] = 'x';
str[6] = 0;
return 0;
}
+/* enable a property of a node if the node is found */
+static inline void ft_enable_path(void *blob, const char *path)
+{
+ int i = fdt_path_offset(blob, path);
+ if (i >= 0) {
+ debug("enabling %s\n", path);
+ fdt_status_okay(blob, i);
+ }
+}
+
+/* remove a property of a node if the node is found */
+static inline void ft_delprop_path(void *blob, const char *path,
+ const char *name)
+{
+ int i = fdt_path_offset(blob, path);
+ if (i) {
+ debug("removing %s/%s\n", path, name);
+ fdt_delprop(blob, i, name);
+ }
+}
+
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
range[1] = cpu_to_fdt32(23);
}
}
+
+ /* these have broken usd_vsel */
+ if (strstr((const char *)info->model, "SP318-B") ||
+ strstr((const char *)info->model, "SP331-B"))
+ gpio_cfg[board_type].usd_vsel = 0;
}
/*
ft_sethdmiinfmt(blob, "yuv422bt656");
}
+ /* Configure DIO */
+ for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
+ struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
+ char arg[10];
+
+ sprintf(arg, "dio%d", i);
+ if (!hwconfig(arg))
+ continue;
+ if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
+ {
+ char path[48];
+ sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
+ 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
+ printf(" Enabling pwm%d for DIO%d\n",
+ cfg->pwm_param, i);
+ ft_enable_path(blob, path);
+ }
+ }
+
+ /* remove no-1-8-v if UHS-I support is present */
+ if (gpio_cfg[board_type].usd_vsel) {
+ debug("Enabling UHS-I support\n");
+ ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
+ "no-1-8-v");
+ }
+
/*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <environment.h>
+#include <i2c.h>
#include <spl.h>
#include "gsc.h"
.trasmin = 3500,
};
+/* MT41K512M16HA-125 (8Gb density) */
+static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
+ .mem_speed = 1600,
+ .density = 8,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 16,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
/*
* calibration - these are the various CPU/DDR3 combinations we support
*/
.p1_mpwrdlctl = 0X40304239,
};
+static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x002A0025,
+ .p0_mpwldectrl1 = 0x003A002A,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43430356,
+ .p0_mpdgctrl1 = 0x033C0335,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x4B373F42,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x303E3C36,
+};
+
static void spl_dram_init(int width, int size_mb, int board_model)
{
struct mx6_ddr3_cfg *mem = NULL;
else
calib = &mx6sdl_256x32_mmdc_calib;
debug("4gB density\n");
+ } else if (width == 32 && size_mb == 2048) {
+ mem = &mt41k512m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_512x32_mmdc_calib;
+ debug("8gB density\n");
} else if (width == 64 && size_mb == 512) {
mem = &mt41k64m16jt_125;
debug("1gB density\n");
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* disable boot watchdog */
- gsc_boot_wd_disable();
}
/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* return 1 if we wish to boot to uboot vs os (falcon mode) */
int spl_start_uboot(void)
{
- int ret = 1;
+ unsigned char ret = 1;
debug("%s\n", __func__);
#ifdef CONFIG_SPL_ENV_SUPPORT
debug("boot_os=%s\n", getenv("boot_os"));
if (getenv_yesno("boot_os") == 1)
ret = 0;
+#else
+ /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
+ i2c_set_bus_num(0);
+ gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
#endif
+ if (!ret)
+ gsc_boot_wd_disable();
+
debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
return ret;
}
GW54xx,
GW551x,
GW552x,
+ GW553x,
GW_UNKNOWN,
GW_BADCRC,
};
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+
+#ifdef CONFIG_VIDEO_IPUV3
/* We need at least 200ms between power on and backlight on
* as per specifications from CHI MEI */
mdelay(250);
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
pwm_enable(0);
+#endif
return 0;
}
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
struct ahci_probe_ent *probe_ent = NULL;
#if defined(CONFIG_MX6)
- if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ if (!is_mx6dq() && !is_mx6dqp())
return 1;
#endif
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
{
u32 phy_index;
- if (is_cpu_type(MXC_CPU_MX6SL)) {
+ if (is_mx6sl()) {
phy_index = index;
- } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+ } else if (is_mx6ul()) {
if (index >= 6)
phy_index = fuse_bank_physical(5) + (index - 6) + 3;
else
int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
- if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
+ if (is_mx6sx() || is_mx7())
max_ecc_strength_supported = 62;
else
max_ecc_strength_supported = 40;
/* Do not access reserved register for i.MX6UL */
- if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ if (!is_mx6ul()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
#define CONFIG_MXC_OCOTP
/* SATA Configs */
-#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA
+#endif
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_DOS_PARTITION
/* USB Configs */
+#ifdef CONFIG_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "Advantech"
+#endif
/* Networking Configs */
+#ifdef CONFIG_NET
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
+#endif
/* Serial Flash */
#ifdef CONFIG_CMD_SF
"bootm; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "usb start; " \
- "setenv dev usb; " \
- "setenv devnum 0; " \
- "setenv rootdev sda1; " \
- "run tryboot; " \
- \
+#define CONFIG_MMCBOOTCOMMAND \
"setenv dev mmc; " \
- "setenv rootdev mmcblk0p1; " \
+ "setenv rootdev mmcblk0p${partnum}; " \
\
"setenv devnum ${sddev}; " \
"if mmc dev ${devnum}; then " \
"run tryboot; " \
- "setenv rootdev mmcblk1p1; " \
+ "setenv rootdev mmcblk1p${partnum}; " \
"fi; " \
\
"setenv devnum ${emmcdev}; " \
"if mmc dev ${devnum}; then " \
"run tryboot; " \
"fi; " \
+
+#define CONFIG_USBBOOTCOMMAND \
+ "usb start; " \
+ "setenv dev usb; " \
+ "setenv devnum 0; " \
+ "setenv rootdev sda${partnum}; " \
+ "run tryboot; " \
\
+ CONFIG_MMCBOOTCOMMAND \
"bmode usb; " \
+#ifdef CONFIG_CMD_USB
+#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
+#else
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+#endif
+
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+
/* Framebuffer */
-#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
+#endif
#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
/* Falcon Mode */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
+#undef CONFIG_SPL_EXT_SUPPORT
#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
#define CONFIG_DM_THERMAL
#endif
-/* GPIO */
-#define CONFIG_MXC_GPIO
-
/* Thermal */
#define CONFIG_IMX_THERMAL
/* Miscellaneous configurable options */
#define CONFIG_HWCONFIG
+#define CONFIG_PREBOOT
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
\
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
+ "disk=0\0" \
+ "part=1\0" \
\
"fdt_high=0xffffffff\0" \
"fdt_addr=0x18000000\0" \
"initrd_high=0xffffffff\0" \
+ "fixfdt=" \
+ "fdt addr ${fdt_addr}\0" \
"bootdir=boot\0" \
"loadfdt=" \
"if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \
"echo Loaded DTB from ${bootdir}/${fdt_file}; " \
+ "run fixfdt; " \
"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \
"echo Loaded DTB from ${bootdir}/${fdt_file1}; " \
+ "run fixfdt; " \
"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \
"echo Loaded DTB from ${bootdir}/${fdt_file2}; " \
+ "run fixfdt; " \
"fi\0" \
\
+ "fs=ext4\0" \
"script=6x_bootscript-ventana\0" \
"loadscript=" \
"if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \
- "source; " \
+ "source ${loadaddr}; " \
"fi\0" \
\
"uimage=uImage\0" \
- "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
+ "mmc_root=/dev/mmcblk0p1 rootfstype=${fs} rootwait rw\0" \
"mmc_boot=" \
- "setenv fsload 'ext2load mmc 0:1'; " \
- "mmc dev 0 && mmc rescan && " \
+ "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \
+ "mmc dev ${disk} && mmc rescan && " \
"setenv dtype mmc; run loadscript; " \
"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
"setenv bootargs console=${console},${baudrate} " \
- "root=/dev/mmcblk0p1 rootfstype=ext4 " \
+ "root=/dev/mmcblk0p1 rootfstype=${fs} " \
"rootwait rw ${video} ${extra}; " \
- "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"bootm; " \
"fi\0" \
\
"sata_boot=" \
- "setenv fsload 'ext2load sata 0:1'; sata init && " \
+ "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \
+ "sata init && " \
"setenv dtype sata; run loadscript; " \
"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
"setenv bootargs console=${console},${baudrate} " \
- "root=/dev/sda1 rootfstype=ext4 " \
+ "root=/dev/sda1 rootfstype=${fs} " \
"rootwait rw ${video} ${extra}; " \
- "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"bootm; " \
"fi; " \
"fi\0" \
"usb_boot=" \
- "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
+ "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \
+ "usb start && usb dev ${disk} && " \
"setenv dtype usb; run loadscript; " \
"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
"setenv bootargs console=${console},${baudrate} " \
- "root=/dev/sda1 rootfstype=ext4 " \
+ "root=/dev/sda1 rootfstype=${fs} " \
"rootwait rw ${video} ${extra}; " \
- "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"bootm; " \
"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
"setenv bootargs console=${console},${baudrate} " \
"root=${root} ${video} ${extra}; " \
- "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "if run loadfdt; then " \
"ubifsumount; " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
- "image=uImage\0" \
+ "image=zImage\0" \
+ "fdt_file=imx51-ts4800.dtb\0" \
+ "fdt_addr=0x90fe0000\0" \
"mmcdev=0\0" \
- "mmcpart=1\0" \
- "mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+ "mmcargs=setenv bootargs root=${mmcroot}\0" \
"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs addtty; " \
- "bootm; "
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo ERR: cannot load FDT; " \
+ "fi; "
+
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
projects / people / ms / u-boot.git / commitdiff
