TQM85xx MPC8540/8541/8555/8560
+ acadia PPC405EZ
alpr PPC440GX
bamboo PPC440EP
bunbinga PPC405EP
#########################################################################
LIST_4xx=" \
- ADCIOP alpr AP1000 AR405 \
- ASH405 bamboo bubinga CANBT \
- CMS700 CPCI2DP CPCI405 CPCI4052 \
- CPCI405AB CPCI405DT CPCI440 CPCIISER4 \
- CRAYL1 csb272 csb472 DASA_SIM \
- DP405 DU405 ebony ERIC \
- EXBITGEN G2000 HH405 HUB405 \
- JSE KAREF katmai luan \
- METROBOX MIP405 MIP405T ML2 \
- ml300 ocotea OCRTC ORSG \
- p3p440 PCI405 pcs440ep PIP405 \
- PLU405 PMC405 PPChameleonEVB sbc405 \
- sc3 sequoia sequoia_nand taishan \
- VOH405 VOM405 W7OLMC W7OLMG \
- walnut WUH405 XPEDITE1K yellowstone \
- yosemite yucca \
+ acadia ADCIOP alpr AP1000 \
+ AR405 ASH405 bamboo bubinga \
+ CANBT CMS700 CPCI2DP CPCI405 \
+ CPCI4052 CPCI405AB CPCI405DT CPCI440 \
+ CPCIISER4 CRAYL1 csb272 csb472 \
+ DASA_SIM DP405 DU405 ebony \
+ ERIC EXBITGEN G2000 HH405 \
+ HUB405 JSE KAREF katmai \
+ luan METROBOX MIP405 MIP405T \
+ ML2 ml300 ocotea OCRTC \
+ ORSG p3p440 PCI405 pcs440ep \
+ PIP405 PLU405 PMC405 PPChameleonEVB \
+ sbc405 sc3 sequoia sequoia_nand \
+ taishan VOH405 VOM405 W7OLMC \
+ W7OLMG walnut WUH405 XPEDITE1K \
+ yellowstone yosemite yucca \
"
#########################################################################
#########################################################################
xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))
+acadia_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc
+
ADCIOP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd
--- /dev/null
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o cpr.o memory.o
+SOBJS =
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+extern void board_pll_init_f(void);
+
+/* Some specific Acadia Defines */
+#define CPLD_BASE 0x80000000
+
+void liveoak_gpio_init(void)
+{
+ /*
+ * GPIO0 setup (select GPIO or alternate function)
+ */
+ out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+ out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
+ out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+ out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+ out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+
+ /*
+ * Ultra (405EZ) was nice enough to add another GPIO controller
+ */
+ out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
+ out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
+ out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
+ out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
+ out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
+ out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
+ out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
+}
+
+#if 0 /* test-only: not called at all??? */
+void ext_bus_cntlr_init(void)
+{
+#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
+ mtebc(pb4ap, EBC_PB4AP);
+ mtebc(pb4cr, EBC_PB4CR);
+#endif
+}
+#endif
+
+int board_early_init_f(void)
+{
+ unsigned int reg;
+
+#if 0 /* test-only */
+ /*
+ * If CRAM memory and SPI/NAND boot, and if the CRAM memory is
+ * already initialized by the pre-loader then we can't reinitialize
+ * CPR registers, GPIO registers and EBC registers as this will
+ * have the effect of un-initializing CRAM.
+ */
+ spr_reg = (volatile unsigned long) mfspr(SPRG7);
+ if (spr_reg != LOAK_CRAM) { /* != CRAM */
+ board_pll_init_f();
+ liveoak_gpio_init();
+ ext_bus_cntlr_init();
+
+ mtebc(pb1ap, CFG_EBC_PB1AP);
+ mtebc(pb1cr, CFG_EBC_PB1CR);
+
+ mtebc(pb2ap, CFG_EBC_PB2AP);
+ mtebc(pb2cr, CFG_EBC_PB2CR);
+ }
+#else
+ board_pll_init_f();
+ liveoak_gpio_init();
+/* ext_bus_cntlr_init(); */
+#endif
+
+#if 0 /* test-only (orig) */
+ /*
+ * If we boot from NAND Flash, we are running in
+ * RAM, so disable the EBC_CS0 so that it goes back
+ * to the NOR Flash. It will be enabled later
+ * for the NAND Flash on EBC_CS1
+ */
+ mfsdr(sdrultra0, reg);
+ mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
+#endif
+#if 0 /* test-only */
+ /* configure for NAND */
+ mfsdr(sdrultra0, reg);
+ reg &= ~SDR_ULTRA0_CSN_MASK;
+ reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS;
+ mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
+#endif
+
+ /* USB Host core needs this bit set */
+ mfsdr(sdrultra1, reg);
+ mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000010);
+ mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
+ mtdcr(uictr, 0x00000010); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+int misc_init_f(void)
+{
+ /* Set EPLD to take PHY out of reset */
+ out8(CPLD_BASE + 0x05, 0x00);
+ udelay(100000);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(TOPDIR)/board/amcc/liveoak/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFC0000
+endif
+
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
+
+ifeq ($(CONFIG_SPI_U_BOOT),y)
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds
+PAD_TO = 0x00840000
+endif
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc405.h>
+
+/* test-only: move into cpu directory!!! */
+
+#if defined(PLLMR0_200_133_66)
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 200.0 | 4 (0x02)|
+ * | PLB | 133.3 | 6 (0x06)|
+ * | OPB | 66.6 | 12 (0x0C)|
+ * | EBC | 66.6 | 12 (0x0C)|
+ * | SPI | 66.6 | 12 (0x0C)|
+ * | UART0 | 10.0 | 40 (0x28)|
+ * | UART1 | 10.0 | 40 (0x28)|
+ * | DAC | 2.0 | 200 (0xC8)|
+ * | ADC | 2.0 | 200 (0xC8)|
+ * | PWM | 100.0 | 4 (0x04)|
+ * | EMAC | 25.0 | 16 (0x10)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x0000033c);
+ mtcpr(cprplld, 0x0c010200);
+ mtcpr(cprprimad, 0x04060c0c);
+ mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_266_160_80)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 266.64 | 3 |
+ * | PLB | 159.98 | 5 (0x05)|
+ * | OPB | 79.99 | 10 (0x0A)|
+ * | EBC | 79.99 | 10 (0x0A)|
+ * | SPI | 79.99 | 10 (0x0A)|
+ * | UART0 | 28.57 | 7 (0x07)|
+ * | UART1 | 28.57 | 7 (0x07)|
+ * | DAC | 28.57 | 7 (0xA7)|
+ * | ADC | 4 | 50 (0x32)|
+ * | PWM | 28.57 | 7 (0x07)|
+ * | EMAC | 4 | 50 (0x32)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x20000238);
+ mtcpr(cprplld, 0x03010400);
+ mtcpr(cprprimad, 0x03050a0a);
+ mtcpr(cprperc0, 0x00000000);
+ mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0x07323200);
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_333_166_83)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 333.33 | 2 |
+ * | PLB | 166.66 | 4 (0x04)|
+ * | OPB | 83.33 | 8 (0x08)|
+ * | EBC | 83.33 | 8 (0x08)|
+ * | SPI | 83.33 | 8 (0x08)|
+ * | UART0 | 16.66 | 5 (0x05)|
+ * | UART1 | 16.66 | 5 (0x05)|
+ * | DAC | ???? | 166 (0xA6)|
+ * | ADC | ???? | 166 (0xA6)|
+ * | PWM | 41.66 | 3 (0x03)|
+ * | EMAC | ???? | 3 (0x03)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x0000033C);
+ mtcpr(cprplld, 0x0a010000);
+ mtcpr(cprprimad, 0x02040808);
+ mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0xA6A60300);
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_100_100_12)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------
+ * | CLK | FREQ (MHz) |
+ * ----------------------
+ * | CPU | 100.00 |
+ * | PLB | 100.00 |
+ * | OPB | 12.00 |
+ * | EBC | 49.00 |
+ * ----------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x000003BC);
+ mtcpr(cprplld, 0x06060600);
+ mtcpr(cprprimad, 0x02020004);
+ mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0xC8C81600);
+ mtcpr(cprclkupd, 0x40000000);
+}
+#endif /* CPU_<speed>_405EZ */
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk (void)
+{
+ unsigned long cpr_plld;
+ unsigned long cpr_primad;
+ unsigned long primad_cpudv;
+ unsigned long pllFbkDiv;
+ unsigned long freqProcessor;
+
+ /*
+ * Read PLL Mode registers
+ */
+ mfcpr(cprplld, cpr_plld);
+
+ /*
+ * Read CPR_PRIMAD register
+ */
+ mfcpr(cprprimad, cpr_primad);
+
+ /*
+ * Determine CPU clock frequency
+ */
+ primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
+ if (primad_cpudv == 0)
+ primad_cpudv = 16;
+
+ /*
+ * Determine FBK_DIV.
+ */
+ pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+ if (pllFbkDiv == 0)
+ pllFbkDiv = 256;
+
+ freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
+
+ return (freqProcessor);
+}
+#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
--- /dev/null
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+ {0xffc00001}, /* 0:boot from big flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ case FLASH_MAN_MX:
+ printf("MIXC ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ case FLASH_MXLV320T:
+ printf ("MXLV320T (32 Mbit, top sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ /* bit 0 used for big flash marking */
+ if ((ulong)addr & 0x1) {
+ return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+ } else {
+ return flash_get_size_1(addr, info);
+ }
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_1(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ int n;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+#if 0 /* TODO: remove ifdef when Flash responds correctly */
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
+ info->flash_id = FLASH_MAN_MX;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+#endif /* TODO: remove ifdef when Flash responds correctly */
+
+ /*
+ * TODO: Start
+ * uncomment block above when Flash responds correctly.
+ * also remove the lines below:
+ */
+ info->flash_id = FLASH_MAN_AMD;
+ DEBUGF("FLASH MANUFACT: FLASH_MAN_AMD\n");
+ /* TODO: End */
+
+ value = addr2[1]; /* device ID */
+
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+#if 0 /* TODO: remove ifdef when Flash responds correctly */
+ switch (value) {
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
+ info->flash_id += FLASH_MXLV320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+#endif /* TODO: remove ifdef when Flash responds correctly */
+
+ /*
+ * TODO: Start
+ * uncomment block above when Flash responds correctly.
+ * also remove the lines below:
+ */
+ DEBUGF("\nFLASH DEVICEID: FLASH_AM320T\n");
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; /* => 4 MB */
+ /* TODO: End */
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ /* 1 x 16k boot sector */
+ base -= 16 << 10;
+ --i;
+ info->start[i] = base;
+ /* 2 x 8k boot sectors */
+ for (n=0; n<2; ++n) {
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ /* 1 x 32k boot sector */
+ base -= 32 << 10;
+ --i;
+ info->start[i] = base;
+
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else if ( ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ) {
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ else {
+ if (info->flash_id & FLASH_BTYPE){
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address,(A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+/*
+ * TODO: FIX: this wait loop sometimes fails: DQ7 indicates the erase command
+ * never was accepted (i.e. didn't start) - why????
+ */
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last, counter = 0;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ DEBUGF("DQ7_2: start = 0x%08lx\n", start);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ DEBUGF("DQ7_2: start = 0x%08lx, now = 0x%08lx\n", start, now);
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ udelay(1000000); /* 1 sec */
+ putc('.');
+ counter++;
+ if (counter > 5) {
+ return -1;
+ }
+ DEBUGF("DQ7_2: now = 0x%08lx, last = 0x%08lx\n", now, last);
+ }
+ return 0;
+}
+
+static void wr_flash_cmd(ulong sector, ushort addr, CFG_FLASH_WORD_SIZE value)
+{
+ int fw_size;
+
+ fw_size = sizeof(value);
+ switch (fw_size)
+ {
+ case 1:
+ out8((ulong)(sector + addr), value);
+ break;
+ case 2:
+ out16((ulong)(sector + (addr << 1)), value);
+ break;
+ default:
+ printf("flash_erase: error incorrect chip programing size.\n");
+ }
+ return;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect, count = 0;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first, count = 0; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ /*
+ * TODO: fix code
+ */
+ wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00800080);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055);
+ wr_flash_cmd((ulong)addr2, 0, (CFG_FLASH_WORD_SIZE) 0x00300030);
+ udelay(2000000); /* 2 sec */
+ wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0);
+
+#if 0
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+#endif
+ }
+ l_sect = sect;
+ printf("..");
+ printf("..");
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ count++;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+
+ if (count > 0) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+ index = 0;
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define CRAM_BANK0_BASE 0x0
+#define CRAM_DIDR 0x00100000
+#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43
+#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343
+#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */
+#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */
+#define CRAM_DEVID_NOT_SUPPORTED 0x00000000
+
+#define PSRAM_PASS 0x50415353 /* "PASS" */
+#define PSRAM_FAIL 0x4641494C /* "FAIL" */
+
+static u32 is_cram_inited(void);
+static u32 is_cram(void);
+static long int cram_init(u32);
+static void cram_bcr_write(u32);
+void udelay (unsigned long);
+
+void sdram_init(void)
+{
+ volatile unsigned long spr_reg;
+
+ /*
+ * If CRAM not initialized or CRAM looks initialized because this
+ * is after a warm reboot then set SPRG7 to indicate CRAM needs
+ * initialization. Note that CRAM is initialized by the SPI and
+ * NAND preloader.
+ */
+ spr_reg = (volatile unsigned long) mfspr(SPRG6);
+ if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
+ mtspr(SPRG7, LOAK_NONE); /* "NONE" */
+ }
+
+#if 1
+ /*
+ * When running the NAND SPL, the normal EBC configuration is not
+ * done, so We need to enable EPLD access on EBC_CS_2 and the memory
+ * on EBC_CS_3
+ */
+
+ /* Enable CPLD - Needed for PSRAM Access */
+
+
+ /* Init SDRAM by setting EBC Bank 3 for PSRAM */
+ mtebc(pb1ap, CFG_EBC_PB1AP);
+ mtebc(pb1cr, CFG_EBC_PB1CR);
+
+ mtebc(pb2ap, CFG_EBC_PB2AP);
+ mtebc(pb2cr, CFG_EBC_PB2CR);
+
+ /* pre-boot loader code: we are in OCM */
+ mtspr(SPRG6, LOAK_SPL); /* "SPL " */
+ mtspr(SPRG7, LOAK_OCM); /* "OCM " */
+#endif
+
+ return;
+}
+
+static void cram_bcr_write(u32 wr_val)
+{
+ u32 tmp_reg;
+ u32 val;
+ volatile u32 gpio_reg;
+
+ /* # Program CRAM write */
+
+ /*
+ * set CRAM_CRE = 0x1
+ * set wr_val = wr_val << 2
+ */
+ gpio_reg = in32(GPIO1_OR);
+ out32(GPIO1_OR, gpio_reg | 0x00000400);
+ wr_val = wr_val << 2;
+ /* wr_val = 0x1c048; */
+
+
+ /*
+ * # stop PLL clock before programming CRAM
+ * set EPLD0_MUX_CTL.OESPR3 = 1
+ * delay 2
+ */
+
+
+ /*
+ * # CS1
+ * read 0x00200000
+ * #shift 2 bit left before write
+ * set val = wr_val + 0x00200000
+ * write dmem val 0
+ * read 0x00200000 val
+ * print val/8x
+ */
+ tmp_reg = in32(0x00200000);
+ val = wr_val + 0x00200000;
+ /* val = 0x0021c048; */
+ out32(val, 0x0000);
+ udelay(100000);
+ val = in32(0x00200000);
+
+ debug("CRAM VAL: %x for CS1 ", val);
+
+ /*
+ * # CS2
+ * read 0x02200000
+ * #shift 2 bit left before write
+ * set val = wr_val + 0x02200000
+ * write dmem val 0
+ * read 0x02200000 val
+ * print val/8x
+ */
+ tmp_reg = in32(0x02200000);
+ val = wr_val + 0x02200000;
+ /* val = 0x0221c048; */
+ out32(val, 0x0000);
+ udelay(100000);
+ val = in32(0x02200000);
+
+ debug("CRAM VAL: %x for CS2 ", val);
+
+ /*
+ * # Start PLL clock before programming CRAM
+ * set EPLD0_MUX_CTL.OESPR3 = 0
+ */
+
+
+ /*
+ * set CRAMCR = 0x1
+ */
+ gpio_reg = in32(GPIO1_OR);
+ out32(GPIO1_OR, gpio_reg | 0x00000400);
+
+ /*
+ * # read CRAM config BCR ( bit19:18 = 10b )
+ * #read 0x00200000
+ * # 1001_1001_0001_1111 ( 991f ) =>
+ * #10_0110_0100_0111_1100 => 2647c => 0022647c
+ * #0011_0010_0011_1110 (323e)
+ * #
+ */
+
+ /*
+ * set EPLD0_MUX_CTL.CRAMCR = 0x0
+ */
+ gpio_reg = in32(GPIO1_OR);
+ out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF);
+ return;
+}
+
+static u32 is_cram_inited()
+{
+ volatile unsigned long spr_reg;
+
+ /*
+ * If CRAM is initialized already, then don't reinitialize it again.
+ * In the case of NAND boot and SPI boot, CRAM will already be
+ * initialized by the pre-loader
+ */
+ spr_reg = (volatile unsigned long) mfspr(SPRG7);
+ if (spr_reg == LOAK_CRAM) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/******
+ * return 0 if not CRAM
+ * return 1 if CRAM and it's already inited by preloader
+ * else return cram_id (CRAM Device Identification Register)
+ ******/
+static u32 is_cram(void)
+{
+ u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
+ volatile u32 gpio_reg;
+ volatile u32 cram_id = 0;
+
+ if (is_cram_inited() == 1) {
+ /* this is CRAM and it is already inited (by preloader) */
+ cram_id = 1;
+ } else {
+ /*
+ * # CRAM CLOCK
+ * set GPIO0_TCR.G8 = 1
+ * set GPIO0_OSRL.G8 = 0
+ * set GPIO0_OR.G8 = 0
+ */
+ gpio_reg = in32(GPIO0_TCR);
+ gpio_TCR = gpio_reg;
+ out32(GPIO0_TCR, gpio_reg | 0x00800000);
+ gpio_reg = in32(GPIO0_OSRL);
+ gpio_OSRL = gpio_reg;
+ out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
+ gpio_reg = in32(GPIO0_OR);
+ gpio_OR = gpio_reg;
+ out32(GPIO0_OR, gpio_reg & 0xff7fffff);
+
+ /*
+ * # CRAM Addreaa Valid
+ * set GPIO0_TCR.G10 = 1
+ * set GPIO0_OSRL.G10 = 0
+ * set GPIO0_OR.G10 = 0
+ */
+ gpio_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, gpio_reg | 0x00200000);
+ gpio_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
+ gpio_reg = in32(GPIO0_OR);
+ out32(GPIO0_OR, gpio_reg & 0xffdfffff);
+
+ /*
+ * # config input (EBC_WAIT)
+ * set GPIO0_ISR1L.G9 = 1
+ * set GPIO0_TCR.G9 = 0
+ */
+ gpio_reg = in32(GPIO0_ISR1L);
+ gpio_ISR1L = gpio_reg;
+ out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
+ gpio_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
+
+ /*
+ * Enable CRE to read Registers
+ * set GPIO0_TCR.21 = 1
+ * set GPIO1_OR.21 = 1
+ */
+ gpio_reg = in32(GPIO1_TCR);
+ out32(GPIO1_TCR, gpio_reg | 0x00000400);
+
+ gpio_reg = in32(GPIO1_OR);
+ out32(GPIO1_OR, gpio_reg | 0x00000400);
+
+
+
+
+ /* Read Version ID */
+ cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
+ udelay(100000);
+
+ asm volatile(" sync");
+ asm volatile(" eieio");
+
+ debug("Cram ID: %X ", cram_id);
+
+ switch (cram_id) {
+ case MICRON_MT45W8MW16BGX_CRAM_ID:
+ case MICRON_MT45W8MW16BGX_CRAM_ID2:
+ /* supported CRAM vendor/part */
+ break;
+ case CRAM_DEVID_NOT_SUPPORTED:
+ default:
+ /* check for DIDR Vendor ID of Micron */
+ if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
+ MICRON_DIDR_VENDOR_ID)
+ {
+ /* supported CRAM vendor */
+ break;
+ }
+ /* this is not CRAM or not supported CRAM vendor/part */
+ cram_id = 0;
+ /*
+ * reset the GPIO registers to the values that were
+ * there before this routine
+ */
+ out32(GPIO0_TCR, gpio_TCR);
+ out32(GPIO0_OSRL, gpio_OSRL);
+ out32(GPIO0_OR, gpio_OR);
+ out32(GPIO0_ISR1L, gpio_ISR1L);
+ break;
+ }
+ }
+
+ return cram_id;
+}
+
+static long int cram_init(u32 already_inited)
+{
+ volatile u32 tmp_reg;
+ u32 cram_wr_val;
+
+ if (already_inited == 0) return 0;
+
+ /*
+ * If CRAM is initialized already, then don't reinitialize it again.
+ * In the case of NAND boot and SPI boot, CRAM will already be
+ * initialized by the pre-loader
+ */
+ if (already_inited != 1)
+ {
+ /*
+ * #o CRAM Card
+ * # - CRAMCRE @reg16 = 1; for CRAM to use
+ * # - CRAMCRE @reg16 = 0; for CRAM to program
+ *
+ * # enable CRAM SEL, move from setEPLD.cmd
+ * set EPLD0_MUX_CTL.OECRAM = 0
+ * set EPLD0_MUX_CTL.CRAMCR = 1
+ * set EPLD0_ETHRSTBOOT.SLCRAM = 0
+ * #end
+ */
+
+
+ /*
+ * #1. EBC need to program READY, CLK, ADV for ASync mode
+ * # config output
+ */
+
+ /*
+ * # CRAM CLOCK
+ * set GPIO0_TCR.G8 = 1
+ * set GPIO0_OSRL.G8 = 0
+ * set GPIO0_OR.G8 = 0
+ */
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x00800000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
+ tmp_reg = in32(GPIO0_OR);
+ out32(GPIO0_OR, tmp_reg & 0xff7fffff);
+
+ /*
+ * # CRAM Addreaa Valid
+ * set GPIO0_TCR.G10 = 1
+ * set GPIO0_OSRL.G10 = 0
+ * set GPIO0_OR.G10 = 0
+ */
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x00200000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
+ tmp_reg = in32(GPIO0_OR);
+ out32(GPIO0_OR, tmp_reg & 0xffdfffff);
+
+ /*
+ * # config input (EBC_WAIT)
+ * set GPIO0_ISR1L.G9 = 1
+ * set GPIO0_TCR.G9 = 0
+ */
+ tmp_reg = in32(GPIO0_ISR1L);
+ out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
+
+ /*
+ * # config CS4 from GPIO
+ * set GPIO0_TCR.G0 = 1
+ * set GPIO0_OSRL.G0 = 1
+ */
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x80000000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg | 0x40000000);
+
+ /*
+ * #2. EBC in Async mode
+ * # set EBC0_PB1AP = 0x078f0ec0
+ * set EBC0_PB1AP = 0x078f1ec0
+ * set EBC0_PB2AP = 0x078f1ec0
+ */
+ mtebc(pb1ap, 0x078F1EC0);
+ mtebc(pb2ap, 0x078F1EC0);
+
+ /*
+ * #set EBC0_PB1CR = 0x000bc000
+ * #enable CS2 for CRAM
+ * set EBC0_PB2CR = 0x020bc000
+ */
+ mtebc(pb1cr, 0x000BC000);
+ mtebc(pb2cr, 0x020BC000);
+
+ /*
+ * #3. set CRAM in Sync mode
+ * #exec cm_bcr_write.cmd { 0x701f }
+ * #3. set CRAM in Sync mode (full drv strength)
+ * exec cm_bcr_write.cmd { 0x701F }
+ */
+ cram_wr_val = 0x7012; /* CRAM burst setting */
+ cram_bcr_write(cram_wr_val);
+
+ /*
+ * #4. EBC in Sync mode
+ * #set EBC0_PB1AP = 0x9f800fc0
+ * #set EBC0_PB1AP = 0x900001c0
+ * set EBC0_PB2AP = 0x9C0201c0
+ * set EBC0_PB2AP = 0x9C0201c0
+ */
+ mtebc(pb1ap, 0x9C0201C0);
+ mtebc(pb2ap, 0x9C0201C0);
+
+ /*
+ * #5. EBC need to program READY, CLK, ADV for Sync mode
+ * # config output
+ * set GPIO0_TCR.G8 = 1
+ * set GPIO0_OSRL.G8 = 1
+ * set GPIO0_TCR.G10 = 1
+ * set GPIO0_OSRL.G10 = 1
+ */
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x00800000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg | 0x00004000);
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x00200000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg | 0x00000400);
+
+ /*
+ * # config input
+ * set GPIO0_ISR1L.G9 = 1
+ * set GPIO0_TCR.G9 = 0
+ */
+ tmp_reg = in32(GPIO0_ISR1L);
+ out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
+
+ /*
+ * # config EBC to use RDY
+ * set SDR0_ULTRA0.EBCREN = 1
+ */
+ mfsdr(sdrultra0, tmp_reg);
+ mtsdr(sdrultra0, tmp_reg | 0x04000000);
+
+ /*
+ * set EPLD0_MUX_CTL.OESPR3 = 0
+ */
+
+
+ mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */
+ } /* if (already_inited != 1) */
+
+ return (64 * 1024 * 1024);
+}
+
+/******
+ * return 0 if not PSRAM
+ * return 1 if is PSRAM
+ ******/
+static int is_psram(u32 addr)
+{
+ u32 test_pattern = 0xdeadbeef;
+ volatile u32 readback;
+
+ if (addr == CFG_SDRAM_BASE) {
+ /* This is to temp enable OE for PSRAM */
+ out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
+ udelay(10000);
+ }
+
+ out32(addr, test_pattern);
+ asm volatile(" sync");
+ asm volatile(" eieio");
+
+ readback = (volatile u32) in32(addr);
+ asm volatile(" sync");
+ asm volatile(" eieio");
+ if (readback == test_pattern) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static long int psram_init(void)
+{
+ u32 readback;
+ long psramsize = 0;
+ int i;
+
+ /* This is to temp enable OE for PSRAM */
+ out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
+ udelay(10000);
+
+ /*
+ * PSRAM bank 1: read then write to address 0x00000000
+ */
+ for (i = 0; i < 100; i++) {
+ if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) {
+ readback = PSRAM_PASS;
+ } else {
+ readback = PSRAM_FAIL;
+ break;
+ }
+ }
+ if (readback == PSRAM_PASS) {
+ debug("psram_init(bank0): pass\n");
+ psramsize = (16 * 1024 * 1024);
+ } else {
+ debug("psram_init(bank0): fail\n");
+ return 0;
+ }
+
+#if 0
+ /*
+ * PSRAM bank 1: read then write to address 0x01000000
+ */
+ for (i = 0; i < 100; i++) {
+ if (is_psram((1 << 24) + (i*256)) == 1) {
+ readback = PSRAM_PASS;
+ } else {
+ readback = PSRAM_FAIL;
+ break;
+ }
+ }
+ if (readback == PSRAM_PASS) {
+ debug("psram_init(bank1): pass\n");
+ psramsize = psramsize + (16 * 1024 * 1024);
+ }
+#endif
+
+ mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */
+
+ return psramsize;
+}
+
+long int initdram(int board_type)
+{
+ long int sram_size;
+ u32 cram_inited;
+
+ /* Determine Attached Memory Expansion Card*/
+ cram_inited = is_cram();
+ if (cram_inited != 0) { /* CRAM */
+ debug("CRAM Expansion Card attached\n");
+ sram_size = cram_init(cram_inited);
+ } else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */
+ debug("PSRAM Expansion Card attached\n");
+ sram_size = psram_init();
+ } else { /* no SRAM */
+ debug("No Memory Card Attached!!\n");
+ sram_size = 0;
+ }
+
+ return sram_size;
+}
+
+int testdram(void)
+{
+ return (0);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
}
}
mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
+#if defined(CONFIG_405EZ)
+ mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
+#endif /* defined(CONFIG_405EZ) */
}
while (serviced);
#if defined(CONFIG_440)
#define FREQ_EBC (sys_info.freqEPB)
+#elif defined(CONFIG_405EZ)
+#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
+ sys_info.pllExtBusDiv)
#else
#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif
puts("AMCC PowerPC 4");
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ)
puts("05");
#endif
#if defined(CONFIG_440)
puts("EP Rev. B");
break;
+ case PVR_405EZ_RA:
+ puts("EZ Rev. A");
+ break;
+
#if defined(CONFIG_440)
case PVR_440GP_RB:
puts("GP Rev. B");
}
printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
- sys_info.freqPLB / 1000000,
- sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
- FREQ_EBC / 1000000);
+ sys_info.freqPLB / 1000000,
+ get_OPB_freq() / 1000000,
+ FREQ_EBC / 1000000);
if (addstr[0] != 0)
printf(" %s\n", addstr);
putc('\n');
#endif
-#if defined(CONFIG_405EP)
+#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
printf (" 16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
printf (" 32 kB I-Cache 32 kB D-Cache");
*/
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || defined(CONFIG_405))
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+ defined(CONFIG_405))
/*
* Move the next instructions into icache, since these modify the flash
* we are running from!
#endif /* CONFIG_IOP480 */
/*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_440)
#if defined(CONFIG_440)
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
#endif /* #if defined(CONFIG_440GP) */
-#elif defined(CONFIG_405EP)
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
#define UCR0_MASK 0x0000007f
#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
static void serial_divs (int baudrate, unsigned long *pudiv,
- unsigned short *pbdiv )
+ unsigned short *pbdiv)
{
- sys_info_t sysinfo;
+ sys_info_t sysinfo;
unsigned long div; /* total divisor udiv * bdiv */
unsigned long umin; /* minimum udiv */
- unsigned short diff; /* smallest diff */
- unsigned long udiv; /* best udiv */
-
- unsigned short idiff; /* current diff */
- unsigned short ibdiv; /* current bdiv */
+ unsigned short diff; /* smallest diff */
+ unsigned long udiv; /* best udiv */
+ unsigned short idiff; /* current diff */
+ unsigned short ibdiv; /* current bdiv */
unsigned long i;
- unsigned long est; /* current estimate */
+ unsigned long est; /* current estimate */
- get_sys_info( &sysinfo );
+ get_sys_info(&sysinfo);
- udiv = 32; /* Assume lowest possible serial clk */
- div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
- umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
- diff = 32; /* highest possible */
+ udiv = 32; /* Assume lowest possible serial clk */
+ div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
+ umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
+ diff = 32; /* highest possible */
/* i is the test udiv value -- start with the largest
* possible (32) to minimize serial clock and constrain
* search to umin.
*/
- for( i = 32; i > umin; i-- ){
- ibdiv = div/i;
+ for (i = 32; i > umin; i--) {
+ ibdiv = div / i;
est = i * ibdiv;
idiff = (est > div) ? (est-div) : (div-est);
- if( idiff == 0 ){
+ if (idiff == 0) {
udiv = i;
break; /* can't do better */
- }
- else if( idiff < diff ){
+ } else if (idiff < diff) {
udiv = i; /* best so far */
diff = idiff; /* update lowest diff*/
}
}
*pudiv = udiv;
- *pbdiv = div/udiv;
+ *pbdiv = div / udiv;
+}
+
+#elif defined(CONFIG_405EZ)
+
+static void serial_divs (int baudrate, unsigned long *pudiv,
+ unsigned short *pbdiv)
+{
+ sys_info_t sysinfo;
+ unsigned long div; /* total divisor udiv * bdiv */
+ unsigned long umin; /* minimum udiv */
+ unsigned short diff; /* smallest diff */
+ unsigned long udiv; /* best udiv */
+ unsigned short idiff; /* current diff */
+ unsigned short ibdiv; /* current bdiv */
+ unsigned long i;
+ unsigned long est; /* current estimate */
+ unsigned long plloutb;
+ u32 reg;
+
+ get_sys_info(&sysinfo);
+ plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv)
+ / sysinfo.pllFwdDivB);
+ udiv = 256; /* Assume lowest possible serial clk */
+ div = plloutb / (16 * baudrate); /* total divisor */
+ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
+ diff = 256; /* highest possible */
+
+ /* i is the test udiv value -- start with the largest
+ * possible (256) to minimize serial clock and constrain
+ * search to umin.
+ */
+ for (i = 256; i > umin; i--) {
+ ibdiv = div / i;
+ est = i * ibdiv;
+ idiff = (est > div) ? (est-div) : (div-est);
+ if (idiff == 0) {
+ udiv = i;
+ break; /* can't do better */
+ } else if (idiff < diff) {
+ udiv = i; /* best so far */
+ diff = idiff; /* update lowest diff*/
+ }
+ }
+
+ *pudiv = udiv;
+ mfcpr(cprperd0, reg);
+ reg &= ~0x0000ffff;
+ reg |= ((udiv - 0) << 8) | (udiv - 0);
+ mtcpr(cprperd0, reg);
+ *pbdiv = div / udiv;
}
#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
unsigned short bdiv;
volatile char val;
+#if defined(CONFIG_405EZ)
+ serial_divs(gd->baudrate, &udiv, &bdiv);
+ clk = tmp = reg = 0;
+#else
#ifdef CONFIG_405EP
reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (cntrl0, reg);
#endif /* CONFIG_405EP */
-
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
+#endif /* CONFIG_405EZ */
out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
return val;
}
+#elif defined(CONFIG_405EZ)
+void get_sys_info (PPC405_SYS_INFO * sysInfo)
+{
+ unsigned long cpr_plld;
+ unsigned long cpr_primad;
+ unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
+ unsigned long primad_cpudv;
+ unsigned long m;
+
+ /*
+ * Read PLL Mode registers
+ */
+ mfcpr(cprplld, cpr_plld);
+
+ /*
+ * Determine forward divider A
+ */
+ sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
+
+ /*
+ * Determine forward divider B (should be equal to A)
+ */
+ sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
+ if (sysInfo->pllFwdDivB == 0) {
+ sysInfo->pllFwdDivB = 8;
+ }
+
+ /*
+ * Determine FBK_DIV.
+ */
+ sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+ if (sysInfo->pllFbkDiv == 0) {
+ sysInfo->pllFbkDiv = 256;
+ }
+
+ /*
+ * Read CPR_PRIMAD register
+ */
+ mfcpr(cprprimad, cpr_primad);
+ /*
+ * Determine PLB_DIV.
+ */
+ sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
+ if (sysInfo->pllPlbDiv == 0) {
+ sysInfo->pllPlbDiv = 16;
+ }
+
+ /*
+ * Determine EXTBUS_DIV.
+ */
+ sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
+ if (sysInfo->pllExtBusDiv == 0) {
+ sysInfo->pllExtBusDiv = 16;
+ }
+
+ /*
+ * Determine OPB_DIV.
+ */
+ sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
+ if (sysInfo->pllOpbDiv == 0) {
+ sysInfo->pllOpbDiv = 16;
+ }
+
+ /*
+ * Determine the M factor
+ */
+ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
+
+ /*
+ * Determine VCO clock frequency
+ */
+ sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
+ (unsigned long long)sysClkPeriodPs;
+
+ /*
+ * Determine CPU clock frequency
+ */
+ primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
+ if (primad_cpudv == 0) {
+ primad_cpudv = 16;
+ }
+
+ sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv;
+
+ /*
+ * Determine PLB clock frequency
+ */
+ sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv;
+}
+
+/********************************************
+ * get_OPB_freq
+ * return OPB bus freq in Hz
+ *********************************************/
+ulong get_OPB_freq (void)
+{
+ ulong val = 0;
+
+ PPC405_SYS_INFO sys_info;
+
+ get_sys_info (&sys_info);
+ val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv;
+
+ return val;
+}
+
#endif
int get_clocks (void)
{
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+ defined(CONFIG_440) || defined(CONFIG_405)
sys_info_t sys_info;
get_sys_info (&sys_info);
{
ulong val;
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+ defined(CONFIG_440) || defined(CONFIG_405)
sys_info_t sys_info;
get_sys_info (&sys_info);
#endif /* CONFIG_IOP480 */
/*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+ defined(CONFIG_405)
/*----------------------------------------------------------------------- */
/* Clear and set up some registers. */
/*----------------------------------------------------------------------- */
/*----------------------------------------------------------------------- */
/* Enable two 128MB cachable regions. */
/*----------------------------------------------------------------------- */
- addis r4,r0,0x8000
- addi r4,r4,0x0001
+ lis r4,0x8000
+ ori r4,r4,0x0001
mticcr r4 /* instruction cache */
isync
- addis r4,r0,0x0000
- addi r4,r4,0x0000
+ lis r4,0x0000
+ ori r4,r4,0x0000
mtdccr r4 /* data cache */
#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#endif /* CONFIG_405EP */
#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
+/* test-only... (clean up later when NAND booting is supported) */
+#if defined(CONFIG_405EZ)
+ /********************************************************************
+ * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
+ *******************************************************************/
+ /*
+ * We can map the OCM on the PLB3, so map it at
+ * CFG_OCM_DATA_ADDR + 0x8000
+ */
+ lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
+ ori r3,r3,CFG_OCM_DATA_ADDR@l
+ ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */
+ mtdcr ocmplb3cr1,r3 /* Set PLB Access */
+ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
+ mtdcr ocmplb3cr2,r3 /* Set PLB Access */
+ isync
+
+ lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
+ ori r3,r3,CFG_OCM_DATA_ADDR@l
+ ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
+ mtdcr ocmdscr1, r3 /* Set Data Side */
+ mtdcr ocmiscr1, r3 /* Set Instruction Side */
+ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
+ mtdcr ocmdscr2, r3 /* Set Data Side */
+ mtdcr ocmiscr2, r3 /* Set Instruction Side */
+ addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
+ mtdcr ocmdsisdpc,r4
+
+ isync
+
+#if defined(CONFIG_NAND_SPL)
+ /*
+ * 405EZ can boot from NAND Flash.
+ * If we are booting the SPL (Pre-loader), copy code from
+ * the mapped 4K NAND Flash to the OCM
+ */
+ li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
+ mtctr r4
+ lis r2,CFG_NAND_BOOT_SPL_SRC@h
+ ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
+ lis r3,CFG_NAND_BOOT_SPL_DST@h
+ ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
+spl_loop:
+ lwzu r4,4(r2)
+ stwu r4,4(r3)
+ bdnz spl_loop
+
+ /*
+ * Jump to code in OCM Ram
+ */
+ bl 00f
+00: mflr r10
+ lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
+ ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
+ sub r10,r10,r3
+ addi r10,r10,28
+ mtlr r10
+ blr
+start_ram:
+ sync
+ isync
+#endif
+#else
+/* ...test-only */
/********************************************************************
* Setup OCM - On Chip Memory
*******************************************************************/
addis r4, 0, 0xC000 /* OCM data area enabled */
mtdcr ocmdscntl, r4
isync
+#endif /* CONFIG_405EZ */
#endif
/*----------------------------------------------------------------------- */
#define m16_swap(x) swap_16(x)
#define m32_swap(x) swap_32(x)
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
+#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX)
#define ohci_cpu_to_le16(x) (x)
#define ohci_cpu_to_le32(x) (x)
#else
gohci.irq = -1;
#if defined(CONFIG_440EP)
gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
-#elif defined(CONFIG_440EPX)
+#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
#endif
ohci_inited = 1;
urb_finished = 1;
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
/* init the device driver */
usb_dev_init();
+#endif
return 0;
}
#else /* !defined(CONFIG_440) */
+#if defined(CONFIG_405EZ)
+#define VECNUM_D0 0 /* DMA channel 0 */
+#define VECNUM_D1 1 /* DMA channel 1 */
+#define VECNUM_D2 2 /* DMA channel 2 */
+#define VECNUM_D3 3 /* DMA channel 3 */
+#define VECNUM_1588 4 /* IEEE 1588 network synchronization */
+#define VECNUM_U0 5 /* UART0 */
+#define VECNUM_U1 6 /* UART1 */
+#define VECNUM_CAN0 7 /* CAN 0 */
+#define VECNUM_CAN1 8 /* CAN 1 */
+#define VECNUM_SPI 9 /* SPI */
+#define VECNUM_IIC0 10 /* I2C */
+#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
+#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
+#define VECNUM_USBH1 13 /* USB Host 1 */
+#define VECNUM_USBH2 14 /* USB Host 2 */
+#define VECNUM_USBDEV 15 /* USB Device */
+#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
+#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
+
+#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
+#define VECNUM_MS 18 /* MAL_SERR_INT */
+#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
+#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
+
+#define VECNUM_MTE 19 /* MAL TXEOB */
+#define VECNUM_MTE1 20 /* MAL TXEOB1 */
+#define VECNUM_MRE 21 /* MAL RXEOB */
+#define VECNUM_NAND 22 /* NAND Flash controller */
+#define VECNUM_ADC 23 /* ADC */
+#define VECNUM_DAC 24 /* DAC */
+#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
+#define VECNUM_RESERVED0 26 /* Reserved */
+#define VECNUM_EIR0 27 /* External interrupt 0 */
+#define VECNUM_EIR1 28 /* External interrupt 1 */
+#define VECNUM_EIR2 29 /* External interrupt 2 */
+#define VECNUM_EIR3 30 /* External interrupt 3 */
+#define VECNUM_EIR4 31 /* External interrupt 4 */
+
+#else /* !CONFIG_405EZ */
+
#define VECNUM_U0 0 /* UART0 */
#define VECNUM_U1 1 /* UART1 */
#define VECNUM_D0 5 /* DMA channel 0 */
#define VECNUM_EIR4 29 /* External interrupt 4 */
#define VECNUM_EIR5 30 /* External interrupt 5 */
#define VECNUM_EIR6 31 /* External interrupt 6 */
+#endif /* defined(CONFIG_405EZ) */
#endif /* defined(CONFIG_440) */
#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
+#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
+#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
+#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
+#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRG1 SPRN_SPRG1
#define SPRG2 SPRN_SPRG2
#define SPRG3 SPRN_SPRG3
+#define SPRG4 SPRN_SPRG4
+#define SPRG5 SPRN_SPRG5
+#define SPRG6 SPRN_SPRG6
+#define SPRG7 SPRN_SPRG7
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
#define SVR SPRN_SVR /* System Version Register */
#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
+#define PVR_405EZ_RA 0x41511460
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
+ defined(CONFIG_405EZ) || \
defined(CONFIG_440)
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
unsigned char bi_enet3addr[6];
#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+ defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
unsigned int bi_opbfreq; /* OPB clock in Hz */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * acadia.h - configuration for AMCC Acadia (405EZ)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ACADIA 1 /* Board is Acadia */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
+#undef CFG_DRAM_TEST /* Disable-takes long time */
+#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
+
+#define CONFIG_NO_SERIAL_EEPROM
+/*#undef CONFIG_NO_SERIAL_EEPROM*/
+
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*----------------------------------------------------------------------------
+ * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+ * assuming a 66MHz input clock to the 405EZ.
+ *---------------------------------------------------------------------------*/
+/* #define PLLMR0_100_100_12 */
+#define PLLMR0_200_133_66
+/* #define PLLMR0_266_160_80 */
+/* #define PLLMR0_333_166_83 */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFE000000
+#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
+
+/*
+ * Define here the location of the environment variables (FLASH).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+ #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#endif
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=acadia\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=acadia/uImage\0" \
+ "kernel_addr=fff10000\0" \
+ "ramdisk_addr=fff20000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 200000 acadia/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b ${fileaddr} fffc0000 ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ "kozio=bootm ffc60000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+#if 0 /* test-only */
+#define TEST_ONLY_NAND
+#endif
+
+#ifdef TEST_ONLY_NAND
+#define CMD_NAND CFG_CMD_NAND
+#else
+#define CMD_NAND 0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DTT | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CMD_NAND | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_USB)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_BAUDRATE 115200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_AD7414 1 /* use AD7414 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+#if 0 /* test-only... */
+/*-----------------------------------------------------------------------
+ * SPI stuff - Define to include SPI control
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SPI
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+#ifdef TEST_ONLY_NAND
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define CFG_NAND 0xd0000000
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+
+/* Memory Bank 0 (Flash) initialization */
+#define CFG_EBC_PB0AP 0x03337200
+#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */
+
+/* Memory Bank 1 (CRAM) initialization */
+#define CFG_EBC_PB1AP 0x030400c0
+#define CFG_EBC_PB1CR 0x000bc000
+
+/* Memory Bank 2 (CRAM) initialization */
+#define CFG_EBC_PB2AP 0x030400c0
+#define CFG_EBC_PB2CR 0x020bc000
+
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000)
+
+/* Memory Bank 4 (CPLD) initialization */
+#define CFG_EBC_PB4AP 0x04006000
+#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */
+
+#define CFG_EBC_CFG 0xf8400000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO_0 setup (PPC405EZ specific)
+ *
+ * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs
+ * GPIO0[4] - External Bus Controller Hold Input
+ * GPIO0[5] - External Bus Controller Priority Input
+ * GPIO0[6] - External Bus Controller HLDA Output
+ * GPIO0[7] - External Bus Controller Bus Request Output
+ * GPIO0[8] - CRAM Clk Output
+ * GPIO0[9] - External Bus Controller Ready Input
+ * GPIO0[10] - CRAM Adv Output
+ * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
+ * GPIO0[25] - External DMA Request Input
+ * GPIO0[26] - External DMA EOT I/O
+ * GPIO0[25] - External DMA Ack_n Output
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[28-30] - Trace Outputs / PWM Inputs
+ * GPIO0[31] - PWM_8 I/O
+ */
+#define CFG_GPIO0_TCR 0xC0000000
+#define CFG_GPIO0_OSRL 0x50000000
+#define CFG_GPIO0_OSRH 0x00000055
+#define CFG_GPIO0_ISR1L 0x00000000
+#define CFG_GPIO0_ISR1H 0x00000055
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TSRH 0x00000055
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO_1 setup (PPC405EZ specific)
+ *
+ * GPIO1[0-6] - PWM_9 to PWM_15 I/O
+ * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
+ * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
+ * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
+ * GPIO1[10-12] - UART0 Control Inputs
+ * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
+ * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
+ * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
+ * GPIO1[16] - SPI_SS_1_N Output
+ * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
+ */
+#define CFG_GPIO1_OSRH 0x55455555
+#define CFG_GPIO1_OSRL 0x40000110
+#define CFG_GPIO1_ISR1H 0x00000000
+#define CFG_GPIO1_ISR1L 0x15555445
+#define CFG_GPIO1_TSRH 0x00000000
+#define CFG_GPIO1_TSRL 0x00000000
+#define CFG_GPIO1_TCR 0xFFFF8014
+
+/*-----------------------------------------------------------------------
+ * EPLD Regs.
+ */
+#define EPLD_BASE 0x80000000
+#define EPLD_ETHRSTBOOT 0x10
+#define EPLD_CTRL 0x14
+#define EPLD_MUXOE 0x16
+
+/*
+ * State definations
+ */
+#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */
+#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */
+#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */
+#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */
+#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */
+#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */
+#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
/*-----------------------------------------------------------------------------+
| Universal interrupt controller interrupts
+-----------------------------------------------------------------------------*/
+#if defined(CONFIG_405EZ)
+#define UIC_DMA0 0x80000000 /* DMA chan. 0 */
+#define UIC_DMA1 0x40000000 /* DMA chan. 1 */
+#define UIC_DMA2 0x20000000 /* DMA chan. 2 */
+#define UIC_DMA3 0x10000000 /* DMA chan. 3 */
+#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
+#define UIC_UART0 0x04000000 /* UART 0 */
+#define UIC_UART1 0x02000000 /* UART 1 */
+#define UIC_CAN0 0x01000000 /* CAN 0 */
+#define UIC_CAN1 0x00800000 /* CAN 1 */
+#define UIC_SPI 0x00400000 /* SPI */
+#define UIC_IIC 0x00200000 /* IIC */
+#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
+#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
+#define UIC_USBH1 0x00040000 /* USB Host 1 */
+#define UIC_USBH2 0x00020000 /* USB Host 2 */
+#define UIC_USBDEV 0x00010000 /* USB Device */
+#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
+#define UIC_ENET1 0x00008000 /* dummy define */
+#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
+
+#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
+#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
+#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
+#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
+
+#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
+#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
+#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
+#define UIC_NAND 0x00000200 /* NAND Flash controller */
+#define UIC_ADC 0x00000100 /* ADC */
+#define UIC_DAC 0x00000080 /* DAC */
+#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
+#define UIC_RESERVED0 0x00000020 /* Reserved */
+#define UIC_EXT0 0x00000010 /* External interrupt 0 */
+#define UIC_EXT1 0x00000008 /* External interrupt 1 */
+#define UIC_EXT2 0x00000004 /* External interrupt 2 */
+#define UIC_EXT3 0x00000002 /* External interrupt 3 */
+#define UIC_EXT4 0x00000001 /* External interrupt 4 */
+
+#else /* !defined(CONFIG_405EZ) */
+
#define UIC_UART0 0x80000000 /* UART 0 */
#define UIC_UART1 0x40000000 /* UART 1 */
#define UIC_IIC 0x20000000 /* IIC */
#define UIC_EXT4 0x00000004 /* External interrupt 4 */
#define UIC_EXT5 0x00000002 /* External interrupt 5 */
#define UIC_EXT6 0x00000001 /* External interrupt 6 */
+#endif /* defined(CONFIG_405EZ) */
/******************************************************************************
* SDRAM Controller
*/
#define VCO_MIN 500
#define VCO_MAX 1000
+#elif defined(CONFIG_405EZ)
+/******************************************************************************
+ * SDR Registers
+ ******************************************************************************/
+#define SDR_DCR_BASE 0x0E
+#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
+#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
+
+#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
+#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+
+#define sdrnand0 0x4000
+#define sdrultra0 0x4040
+#define sdrultra1 0x4050
+#define sdricintstat 0x4510
+
+#define SDR_NAND0_NDEN 0x80000000
+
+#define SDR_ULTRA0_NDGPIOBP 0x80000000
+#define SDR_ULTRA0_CSN_MASK 0x78000000
+#define SDR_ULTRA0_CSNSEL0 0x40000000
+#define SDR_ULTRA0_CSNSEL1 0x20000000
+#define SDR_ULTRA0_CSNSEL2 0x10000000
+#define SDR_ULTRA0_CSNSEL3 0x08000000
+
+#define SDR_ULTRA1_LEDNENABLE 0x40000000
+
+#define SDR_ICRX_STAT 0x80000000
+#define SDR_ICTX0_STAT 0x40000000
+#define SDR_ICTX1_STAT 0x20000000
+
+/******************************************************************************
+ * Control
+ ******************************************************************************/
+#define CNTRL_DCR_BASE 0x0C
+#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */
+#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */
+
+/* CPR Registers */
+#define cprclkupd 0x020 /* CPR_CLKUPD */
+#define cprpllc 0x040 /* CPR_PLLC */
+#define cprplld 0x060 /* CPR_PLLD */
+#define cprprimad 0x080 /* CPR_PRIMAD */
+#define cprperd0 0x0e0 /* CPR_PERD0 */
+#define cprperd1 0x0e1 /* CPR_PERD1 */
+#define cprperc0 0x180 /* CPR_PERC0 */
+#define cprmisc0 0x181 /* CPR_MISC0 */
+#define cprmisc1 0x182 /* CPR_MISC1 */
+
+/*
+ * Macro for accessing the indirect CPR register
+ */
+#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data)
+#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd)
+
+#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
+#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
+#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
+
+#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
+#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
+#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
+
+#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
+#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
+#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
+#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
+
+#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
+#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
+#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
+#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
+
+#if 0 /* Deprecated */
+#define CNTRL_DCR_BASE 0x0f0
+#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
+#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
+#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
+#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
+#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
+#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
+
+#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
+#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
+#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
+#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
+#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
+#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
+#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
+#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
+#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
+#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
+
+/* Bit definitions */
+#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
+#define PLLMR0_CPU_DIV_BYPASS 0x00000000
+#define PLLMR0_CPU_DIV_2 0x00100000
+#define PLLMR0_CPU_DIV_3 0x00200000
+#define PLLMR0_CPU_DIV_4 0x00300000
+
+#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
+#define PLLMR0_CPU_PLB_DIV_1 0x00000000
+#define PLLMR0_CPU_PLB_DIV_2 0x00010000
+#define PLLMR0_CPU_PLB_DIV_3 0x00020000
+#define PLLMR0_CPU_PLB_DIV_4 0x00030000
+
+#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
+#define PLLMR0_OPB_PLB_DIV_1 0x00000000
+#define PLLMR0_OPB_PLB_DIV_2 0x00001000
+#define PLLMR0_OPB_PLB_DIV_3 0x00002000
+#define PLLMR0_OPB_PLB_DIV_4 0x00003000
+
+#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
+#define PLLMR0_EXB_PLB_DIV_2 0x00000000
+#define PLLMR0_EXB_PLB_DIV_3 0x00000100
+#define PLLMR0_EXB_PLB_DIV_4 0x00000200
+#define PLLMR0_EXB_PLB_DIV_5 0x00000300
+
+#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
+#define PLLMR0_MAL_PLB_DIV_1 0x00000000
+#define PLLMR0_MAL_PLB_DIV_2 0x00000010
+#define PLLMR0_MAL_PLB_DIV_3 0x00000020
+#define PLLMR0_MAL_PLB_DIV_4 0x00000030
+
+#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
+#define PLLMR0_PCI_PLB_DIV_1 0x00000000
+#define PLLMR0_PCI_PLB_DIV_2 0x00000001
+#define PLLMR0_PCI_PLB_DIV_3 0x00000002
+#define PLLMR0_PCI_PLB_DIV_4 0x00000003
+
+#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
+#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
+#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
+#define PLLMR1_FBMUL_DIV_16 0x00000000
+#define PLLMR1_FBMUL_DIV_1 0x00100000
+#define PLLMR1_FBMUL_DIV_2 0x00200000
+#define PLLMR1_FBMUL_DIV_3 0x00300000
+#define PLLMR1_FBMUL_DIV_4 0x00400000
+#define PLLMR1_FBMUL_DIV_5 0x00500000
+#define PLLMR1_FBMUL_DIV_6 0x00600000
+#define PLLMR1_FBMUL_DIV_7 0x00700000
+#define PLLMR1_FBMUL_DIV_8 0x00800000
+#define PLLMR1_FBMUL_DIV_9 0x00900000
+#define PLLMR1_FBMUL_DIV_10 0x00A00000
+#define PLLMR1_FBMUL_DIV_11 0x00B00000
+#define PLLMR1_FBMUL_DIV_12 0x00C00000
+#define PLLMR1_FBMUL_DIV_13 0x00D00000
+#define PLLMR1_FBMUL_DIV_14 0x00E00000
+#define PLLMR1_FBMUL_DIV_15 0x00F00000
+
+#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
+#define PLLMR1_FWDVA_DIV_8 0x00000000
+#define PLLMR1_FWDVA_DIV_7 0x00010000
+#define PLLMR1_FWDVA_DIV_6 0x00020000
+#define PLLMR1_FWDVA_DIV_5 0x00030000
+#define PLLMR1_FWDVA_DIV_4 0x00040000
+#define PLLMR1_FWDVA_DIV_3 0x00050000
+#define PLLMR1_FWDVA_DIV_2 0x00060000
+#define PLLMR1_FWDVA_DIV_1 0x00070000
+#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
+#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
+
+/* Defines for CPC0_EPRCSR register */
+#define CPC0_EPRCSR_E0NFE 0x80000000
+#define CPC0_EPRCSR_E1NFE 0x40000000
+#define CPC0_EPRCSR_E1RPP 0x00000080
+#define CPC0_EPRCSR_E0RPP 0x00000040
+#define CPC0_EPRCSR_E1ERP 0x00000020
+#define CPC0_EPRCSR_E0ERP 0x00000010
+#define CPC0_EPRCSR_E1PCI 0x00000002
+#define CPC0_EPRCSR_E0PCI 0x00000001
+
+/* Defines for CPC0_BOOR Register */
+#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE 0x80000000
+#define CPC0_PLLMR1_SSCS 0x80000000
+#define PLL_RESET 0x40000000
+#define CPC0_PLLMR1_PLLR 0x40000000
+ /* Feedback multiplier */
+#define PLL_FBKDIV 0x00F00000
+#define CPC0_PLLMR1_FBDV 0x00F00000
+#define PLL_FBKDIV_16 0x00000000
+#define PLL_FBKDIV_1 0x00100000
+#define PLL_FBKDIV_2 0x00200000
+#define PLL_FBKDIV_3 0x00300000
+#define PLL_FBKDIV_4 0x00400000
+#define PLL_FBKDIV_5 0x00500000
+#define PLL_FBKDIV_6 0x00600000
+#define PLL_FBKDIV_7 0x00700000
+#define PLL_FBKDIV_8 0x00800000
+#define PLL_FBKDIV_9 0x00900000
+#define PLL_FBKDIV_10 0x00A00000
+#define PLL_FBKDIV_11 0x00B00000
+#define PLL_FBKDIV_12 0x00C00000
+#define PLL_FBKDIV_13 0x00D00000
+#define PLL_FBKDIV_14 0x00E00000
+#define PLL_FBKDIV_15 0x00F00000
+ /* Forward A divisor */
+#define PLL_FWDDIVA 0x00070000
+#define CPC0_PLLMR1_FWDVA 0x00070000
+#define PLL_FWDDIVA_8 0x00000000
+#define PLL_FWDDIVA_7 0x00010000
+#define PLL_FWDDIVA_6 0x00020000
+#define PLL_FWDDIVA_5 0x00030000
+#define PLL_FWDDIVA_4 0x00040000
+#define PLL_FWDDIVA_3 0x00050000
+#define PLL_FWDDIVA_2 0x00060000
+#define PLL_FWDDIVA_1 0x00070000
+ /* Forward B divisor */
+#define PLL_FWDDIVB 0x00007000
+#define CPC0_PLLMR1_FWDVB 0x00007000
+#define PLL_FWDDIVB_8 0x00000000
+#define PLL_FWDDIVB_7 0x00001000
+#define PLL_FWDDIVB_6 0x00002000
+#define PLL_FWDDIVB_5 0x00003000
+#define PLL_FWDDIVB_4 0x00004000
+#define PLL_FWDDIVB_3 0x00005000
+#define PLL_FWDDIVB_2 0x00006000
+#define PLL_FWDDIVB_1 0x00007000
+ /* PLL tune bits */
+#define PLL_TUNE_MASK 0x000003FF
+#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
+#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
+#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
+#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
+#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
+#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
+#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
+
+/* Defines for CPC0_PLLMR0 Register fields */
+ /* CPU divisor */
+#define PLL_CPUDIV 0x00300000
+#define CPC0_PLLMR0_CCDV 0x00300000
+#define PLL_CPUDIV_1 0x00000000
+#define PLL_CPUDIV_2 0x00100000
+#define PLL_CPUDIV_3 0x00200000
+#define PLL_CPUDIV_4 0x00300000
+ /* PLB divisor */
+#define PLL_PLBDIV 0x00030000
+#define CPC0_PLLMR0_CBDV 0x00030000
+#define PLL_PLBDIV_1 0x00000000
+#define PLL_PLBDIV_2 0x00010000
+#define PLL_PLBDIV_3 0x00020000
+#define PLL_PLBDIV_4 0x00030000
+ /* OPB divisor */
+#define PLL_OPBDIV 0x00003000
+#define CPC0_PLLMR0_OPDV 0x00003000
+#define PLL_OPBDIV_1 0x00000000
+#define PLL_OPBDIV_2 0x00001000
+#define PLL_OPBDIV_3 0x00002000
+#define PLL_OPBDIV_4 0x00003000
+ /* EBC divisor */
+#define PLL_EXTBUSDIV 0x00000300
+#define CPC0_PLLMR0_EPDV 0x00000300
+#define PLL_EXTBUSDIV_2 0x00000000
+#define PLL_EXTBUSDIV_3 0x00000100
+#define PLL_EXTBUSDIV_4 0x00000200
+#define PLL_EXTBUSDIV_5 0x00000300
+ /* MAL divisor */
+#define PLL_MALDIV 0x00000030
+#define CPC0_PLLMR0_MPDV 0x00000030
+#define PLL_MALDIV_1 0x00000000
+#define PLL_MALDIV_2 0x00000010
+#define PLL_MALDIV_3 0x00000020
+#define PLL_MALDIV_4 0x00000030
+ /* PCI divisor */
+#define PLL_PCIDIV 0x00000003
+#define CPC0_PLLMR0_PPFD 0x00000003
+#define PLL_PCIDIV_1 0x00000000
+#define PLL_PCIDIV_2 0x00000001
+#define PLL_PCIDIV_3 0x00000002
+#define PLL_PCIDIV_4 0x00000003
+
+/*
+ *-------------------------------------------------------------------------------
+ * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+ * assuming a 33.3MHz input clock to the 405EP.
+ *-------------------------------------------------------------------------------
+ */
+#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
+ PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
+ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+/*
+ * PLL Voltage Controlled Oscillator (VCO) definitions
+ * Maximum and minimum values (in MHz) for correct PLL operation.
+ */
+#define VCO_MIN 500
+#define VCO_MAX 1000
+#endif /* #if 0 */
#else /* #ifdef CONFIG_405EP */
/******************************************************************************
* Control
/******************************************************************************
* Memory Access Layer
******************************************************************************/
+#if defined(CONFIG_405EZ)
+#define MAL_DCR_BASE 0x380
+#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
+#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
+#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
+#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
+#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
+#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
+#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
+#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
+/* 0x08-0x0F Reserved */
+#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
+#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
+#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
+#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
+/* 0x14-0x1F Reserved */
+#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
+#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
+#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
+#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
+#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
+#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
+#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
+#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
+#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
+#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
+#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
+#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
+#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
+#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
+#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
+#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
+#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
+#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
+#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
+#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
+#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
+#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
+#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
+#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
+#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
+#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
+#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
+#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
+#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
+#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
+#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
+#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
+#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
+#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
+#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
+#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
+#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
+#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
+#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
+#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
+#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
+#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
+#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
+#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
+#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
+#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
+#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
+#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
+#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
+#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
+#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
+#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
+#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
+#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
+#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
+#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
+#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
+#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
+#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
+#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
+#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
+#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
+#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
+#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
+#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
+#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
+#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
+#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
+#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
+#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
+#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
+#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
+#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
+#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
+#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
+#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
+#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
+#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
+#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
+#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
+#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
+#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
+#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
+#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
+#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
+#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
+#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
+#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
+#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
+#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
+#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
+#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
+#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
+#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
+#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
+#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
+
+#else /* !defined(CONFIG_405EZ) */
+
#define MAL_DCR_BASE 0x180
#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
+#endif /* defined(CONFIG_405EZ) */
/*-----------------------------------------------------------------------------
| IIC Register Offsets
/******************************************************************************
* On Chip Memory
******************************************************************************/
+#if defined(CONFIG_405EZ)
+#define OCM_DCR_BASE 0x020
+#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
+#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
+#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
+#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
+#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
+#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
+#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
+#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
+#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
+#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
+#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
+#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
+#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
+#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
+#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
+#else
#define OCM_DCR_BASE 0x018
#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
+#endif /* CONFIG_405EZ */
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
+#if defined(CONFIG_405EZ)
+/* Only the 405EZ has 2 GPIOs */
+#define GPIO_BASE 0xEF600700
+#define GPIO0_OR (GPIO_BASE+0x0)
+#define GPIO0_TCR (GPIO_BASE+0x4)
+#define GPIO0_OSRL (GPIO_BASE+0x8)
+#define GPIO0_OSRH (GPIO_BASE+0xC)
+#define GPIO0_TSRL (GPIO_BASE+0x10)
+#define GPIO0_TSRH (GPIO_BASE+0x14)
+#define GPIO0_ODR (GPIO_BASE+0x18)
+#define GPIO0_IR (GPIO_BASE+0x1C)
+#define GPIO0_RR1 (GPIO_BASE+0x20)
+#define GPIO0_RR2 (GPIO_BASE+0x24)
+#define GPIO0_RR3 (GPIO_BASE+0x28)
+#define GPIO0_ISR1L (GPIO_BASE+0x30)
+#define GPIO0_ISR1H (GPIO_BASE+0x34)
+#define GPIO0_ISR2L (GPIO_BASE+0x38)
+#define GPIO0_ISR2H (GPIO_BASE+0x3C)
+#define GPIO0_ISR3L (GPIO_BASE+0x40)
+#define GPIO0_ISR3H (GPIO_BASE+0x44)
+
+#define GPIO1_BASE 0xEF600800
+#define GPIO1_OR (GPIO1_BASE+0x0)
+#define GPIO1_TCR (GPIO1_BASE+0x4)
+#define GPIO1_OSRL (GPIO1_BASE+0x8)
+#define GPIO1_OSRH (GPIO1_BASE+0xC)
+#define GPIO1_TSRL (GPIO1_BASE+0x10)
+#define GPIO1_TSRH (GPIO1_BASE+0x14)
+#define GPIO1_ODR (GPIO1_BASE+0x18)
+#define GPIO1_IR (GPIO1_BASE+0x1C)
+#define GPIO1_RR1 (GPIO1_BASE+0x20)
+#define GPIO1_RR2 (GPIO1_BASE+0x24)
+#define GPIO1_RR3 (GPIO1_BASE+0x28)
+#define GPIO1_ISR1L (GPIO1_BASE+0x30)
+#define GPIO1_ISR1H (GPIO1_BASE+0x34)
+#define GPIO1_ISR2L (GPIO1_BASE+0x38)
+#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L (GPIO1_BASE+0x40)
+#define GPIO1_ISR3H (GPIO1_BASE+0x44)
+
+#else /* !405EZ */
+
#define GPIO_BASE 0xEF600700
#define GPIO0_OR (GPIO_BASE+0x0)
#define GPIO0_TCR (GPIO_BASE+0x4)
#define GPIO0_ISR2H (GPIO_BASE+0x38)
#define GPIO0_ISR2L (GPIO_BASE+0x3C)
+#endif /* CONFIG_405EZ */
/*
* Macro for accessing the indirect EBC register
#if defined(CONFIG_440GX)
-#define EMAC_NUM_DEV 4
+#define EMAC_NUM_DEV 4
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
defined(CONFIG_NET_MULTI) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
-#define EMAC_NUM_DEV 2
+#define EMAC_NUM_DEV 2
#else
-#define EMAC_NUM_DEV 1
+#define EMAC_NUM_DEV 1
#endif
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
/*ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
+#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
-#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
+#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
#endif
-#define ZMII_FER (ZMII_BASE)
-#define ZMII_SSR (ZMII_BASE + 4)
-#define ZMII_SMIISR (ZMII_BASE + 8)
+#define ZMII_FER (ZMII_BASE)
+#define ZMII_SSR (ZMII_BASE + 4)
+#define ZMII_SMIISR (ZMII_BASE + 8)
-#define ZMII_RMII 0x22000000
-#define ZMII_MDI0 0x80000000
+#define ZMII_RMII 0x22000000
+#define ZMII_MDI0 0x80000000
/* ZMII FER Register Bit Definitions */
#define ZMII_FER_DIS (0x0)
#if defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
+#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
-#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
+#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#endif
#else
-#define EMAC_BASE 0xEF600800
+#if defined(CONFIG_405EZ)
+#define EMAC_BASE 0xEF600900
+#else
+#define EMAC_BASE 0xEF600800
+#endif
#endif
-#define EMAC_M0 (EMAC_BASE)
-#define EMAC_M1 (EMAC_BASE + 4)
-#define EMAC_TXM0 (EMAC_BASE + 8)
-#define EMAC_TXM1 (EMAC_BASE + 12)
-#define EMAC_RXM (EMAC_BASE + 16)
-#define EMAC_ISR (EMAC_BASE + 20)
-#define EMAC_IER (EMAC_BASE + 24)
-#define EMAC_IAH (EMAC_BASE + 28)
-#define EMAC_IAL (EMAC_BASE + 32)
-#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36)
-#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40)
+#define EMAC_M0 (EMAC_BASE)
+#define EMAC_M1 (EMAC_BASE + 4)
+#define EMAC_TXM0 (EMAC_BASE + 8)
+#define EMAC_TXM1 (EMAC_BASE + 12)
+#define EMAC_RXM (EMAC_BASE + 16)
+#define EMAC_ISR (EMAC_BASE + 20)
+#define EMAC_IER (EMAC_BASE + 24)
+#define EMAC_IAH (EMAC_BASE + 28)
+#define EMAC_IAL (EMAC_BASE + 32)
#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
-#define EMAC_IND_HASH_1 (EMAC_BASE + 48)
-#define EMAC_IND_HASH_2 (EMAC_BASE + 52)
-#define EMAC_IND_HASH_3 (EMAC_BASE + 56)
-#define EMAC_IND_HASH_4 (EMAC_BASE + 60)
-#define EMAC_GRP_HASH_1 (EMAC_BASE + 64)
-#define EMAC_GRP_HASH_2 (EMAC_BASE + 68)
-#define EMAC_GRP_HASH_3 (EMAC_BASE + 72)
-#define EMAC_GRP_HASH_4 (EMAC_BASE + 76)
-#define EMAC_LST_SRC_LOW (EMAC_BASE + 80)
-#define EMAC_LST_SRC_HI (EMAC_BASE + 84)
#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
-#define EMAC_STACR (EMAC_BASE + 92)
-#define EMAC_TRTR (EMAC_BASE + 96)
-#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
+#define EMAC_STACR (EMAC_BASE + 92)
+#define EMAC_TRTR (EMAC_BASE + 96)
+#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
/* bit definitions */
/* MODE REG 0 */
-#define EMAC_M0_RXI (0x80000000)
-#define EMAC_M0_TXI (0x40000000)
-#define EMAC_M0_SRST (0x20000000)
-#define EMAC_M0_TXE (0x10000000)
-#define EMAC_M0_RXE (0x08000000)
-#define EMAC_M0_WKE (0x04000000)
+#define EMAC_M0_RXI (0x80000000)
+#define EMAC_M0_TXI (0x40000000)
+#define EMAC_M0_SRST (0x20000000)
+#define EMAC_M0_TXE (0x10000000)
+#define EMAC_M0_RXE (0x08000000)
+#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX) || \
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
#define EMAC_M1_VLE (0x20000000)
-#define EMAC_M1_EIFC (0x10000000)
-#define EMAC_M1_APP (0x08000000)
-#define EMAC_M1_RSVD (0x06000000)
-#define EMAC_M1_IST (0x01000000)
-#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS (0x00400000)
-#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
-#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
-#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
-#define EMAC_M1_RFS_2K (0x00100000)
-#define EMAC_M1_RFS_1K (0x00080000)
-#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
-#define EMAC_M1_TX_FIFO_8K (0x00040000)
-#define EMAC_M1_TX_FIFO_4K (0x00030000)
+#define EMAC_M1_EIFC (0x10000000)
+#define EMAC_M1_APP (0x08000000)
+#define EMAC_M1_RSVD (0x06000000)
+#define EMAC_M1_IST (0x01000000)
+#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS (0x00400000)
+#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
+#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
+#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K (0x00100000)
+#define EMAC_M1_RFS_1K (0x00080000)
+#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_8K (0x00040000)
+#define EMAC_M1_TX_FIFO_4K (0x00030000)
#define EMAC_M1_TX_FIFO_2K (0x00020000)
-#define EMAC_M1_TX_FIFO_1K (0x00010000)
-#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
+#define EMAC_M1_TX_FIFO_1K (0x00010000)
+#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
#define EMAC_M1_MWSW (0x00007000)
#define EMAC_M1_JUMBO_ENABLE (0x00000800)
#define EMAC_M1_IPPA (0x000007c0)
#define EMAC_M1_RSVD1 (0x00000007)
#else /* defined(CONFIG_440GX) */
/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
-#define EMAC_M1_FDE 0x80000000
-#define EMAC_M1_ILE 0x40000000
-#define EMAC_M1_VLE 0x20000000
-#define EMAC_M1_EIFC 0x10000000
-#define EMAC_M1_APP 0x08000000
-#define EMAC_M1_AEMI 0x02000000
-#define EMAC_M1_IST 0x01000000
-#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS 0x00400000
-#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
-#define EMAC_M1_RFS_2K 0x00200000
-#define EMAC_M1_RFS_1K 0x00100000
-#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
-#define EMAC_M1_TX_FIFO_1K 0x00040000
-#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
-#define EMAC_M1_TR0_MULTI 0x00008000
-#define EMAC_M1_TR1_DEPEND 0x00004000
-#define EMAC_M1_TR1_MULTI 0x00002000
+#define EMAC_M1_FDE 0x80000000
+#define EMAC_M1_ILE 0x40000000
+#define EMAC_M1_VLE 0x20000000
+#define EMAC_M1_EIFC 0x10000000
+#define EMAC_M1_APP 0x08000000
+#define EMAC_M1_AEMI 0x02000000
+#define EMAC_M1_IST 0x01000000
+#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS 0x00400000
+#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K 0x00200000
+#define EMAC_M1_RFS_1K 0x00100000
+#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_1K 0x00040000
+#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
+#define EMAC_M1_TR0_MULTI 0x00008000
+#define EMAC_M1_TR1_DEPEND 0x00004000
+#define EMAC_M1_TR1_MULTI 0x00002000
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define EMAC_M1_JUMBO_ENABLE 0x00001000
+#define EMAC_M1_JUMBO_ENABLE 0x00001000
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#endif /* defined(CONFIG_440GX) */
/* Transmit Mode Register 0 */
-#define EMAC_TXM0_GNP0 (0x80000000)
-#define EMAC_TXM0_GNP1 (0x40000000)
-#define EMAC_TXM0_GNPD (0x20000000)
-#define EMAC_TXM0_FC (0x10000000)
+#define EMAC_TXM0_GNP0 (0x80000000)
+#define EMAC_TXM0_GNP1 (0x40000000)
+#define EMAC_TXM0_GNPD (0x20000000)
+#define EMAC_TXM0_FC (0x10000000)
/* Receive Mode Register */
#define EMAC_RMR_SP (0x80000000)
#define EMAC_ISR_PP (0x01000000)
#define EMAC_ISR_BP (0x00800000)
#define EMAC_ISR_RP (0x00400000)
-#define EMAC_ISR_SE (0x00200000)
-#define EMAC_ISR_SYE (0x00100000)
-#define EMAC_ISR_BFCS (0x00080000)
-#define EMAC_ISR_PTLE (0x00040000)
-#define EMAC_ISR_ORE (0x00020000)
-#define EMAC_ISR_IRE (0x00010000)
-#define EMAC_ISR_DBDM (0x00000200)
-#define EMAC_ISR_DB0 (0x00000100)
-#define EMAC_ISR_SE0 (0x00000080)
-#define EMAC_ISR_TE0 (0x00000040)
-#define EMAC_ISR_DB1 (0x00000020)
-#define EMAC_ISR_SE1 (0x00000010)
-#define EMAC_ISR_TE1 (0x00000008)
-#define EMAC_ISR_MOS (0x00000002)
-#define EMAC_ISR_MOF (0x00000001)
-
+#define EMAC_ISR_SE (0x00200000)
+#define EMAC_ISR_SYE (0x00100000)
+#define EMAC_ISR_BFCS (0x00080000)
+#define EMAC_ISR_PTLE (0x00040000)
+#define EMAC_ISR_ORE (0x00020000)
+#define EMAC_ISR_IRE (0x00010000)
+#define EMAC_ISR_DBDM (0x00000200)
+#define EMAC_ISR_DB0 (0x00000100)
+#define EMAC_ISR_SE0 (0x00000080)
+#define EMAC_ISR_TE0 (0x00000040)
+#define EMAC_ISR_DB1 (0x00000020)
+#define EMAC_ISR_SE1 (0x00000010)
+#define EMAC_ISR_TE1 (0x00000008)
+#define EMAC_ISR_MOS (0x00000002)
+#define EMAC_ISR_MOF (0x00000001)
/* STA CONTROL REG */
-#define EMAC_STACR_OC (0x00008000)
-#define EMAC_STACR_PHYE (0x00004000)
+#define EMAC_STACR_OC (0x00008000)
+#define EMAC_STACR_PHYE (0x00004000)
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
-#define EMAC_STACR_INDIRECT_MODE (0x00002000)
-#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
-#define EMAC_STACR_READ (0x00001000) /* $BUC */
-#define EMAC_STACR_OP_MASK (0x00001800)
-#define EMAC_STACR_MDIO_ADDR (0x00000000)
-#define EMAC_STACR_MDIO_WRITE (0x00000800)
-#define EMAC_STACR_MDIO_READ (0x00001800)
-#define EMAC_STACR_MDIO_READ_INC (0x00001000)
+#define EMAC_STACR_INDIRECT_MODE (0x00002000)
+#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
+#define EMAC_STACR_READ (0x00001000) /* $BUC */
+#define EMAC_STACR_OP_MASK (0x00001800)
+#define EMAC_STACR_MDIO_ADDR (0x00000000)
+#define EMAC_STACR_MDIO_WRITE (0x00000800)
+#define EMAC_STACR_MDIO_READ (0x00001800)
+#define EMAC_STACR_MDIO_READ_INC (0x00001000)
#else
-#define EMAC_STACR_WRITE (0x00002000)
-#define EMAC_STACR_READ (0x00001000)
+#define EMAC_STACR_WRITE (0x00002000)
+#define EMAC_STACR_READ (0x00001000)
#endif
#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
#define EMAC_STACR_CLK_100MHZ (0x00000C00)
/* Transmit Request Threshold Register */
-#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
-#define EMAC_TRTR_192 (0x10000000)
-#define EMAC_TRTR_128 (0x01000000)
+#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
+#define EMAC_TRTR_192 (0x10000000)
+#define EMAC_TRTR_128 (0x01000000)
/* the follwing defines are for the MadMAL status and control registers. */
/* For bits 0..5 look at the mal.h file */
projects / people / ms / u-boot.git / commitdiff
