L: uboot-snps-arc@synopsys.com
F: drivers/gpio/hsdk-creg-gpio.c
+ARC HSDK CGU CLOCK
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Maintained
+L: uboot-snps-arc@synopsys.com
+F: drivers/clk/clk-hsdk-cgu.c
+F: include/dt-bindings/clock/snps,hsdk-cgu.h
+F: doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
+
ARM
M: Albert Aribaud <albert.u.boot@aribaud.net>
S: Maintained
-----------------
All contributions to U-Boot should conform to the Linux kernel
-coding style; see the file "Documentation/CodingStyle" and the script
-"scripts/Lindent" in your Linux kernel source directory.
+coding style; see the kernel coding style guide at
+https://www.kernel.org/doc/html/latest/process/coding-style.html, and the
+script "scripts/Lindent" in your Linux kernel source directory.
Source files originating from a different project (for example the
MTD subsystem) are generally exempt from these guidelines and are not
#define ARC_AUX_IC_PTAG 0x1E
#endif
#define ARC_BCR_IC_BUILD 0x77
+#define AUX_AUX_CACHE_LIMIT 0x5D
+#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
+
+/* ICCM and DCCM auxiliary registers */
+#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
+#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val) \
__builtin_arc_sr((unsigned int)val, reg_immed)
+
+/* ARCNUM [15:8] - field to identify each core in a multi-core system */
+#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARC_ARCREGS_H */
--- /dev/null
+#include <asm-generic/gpio.h>
* relocation but will be used after being zeroed.
*/
int l1_line_sz __section(".data");
-int dcache_exists __section(".data");
-int icache_exists __section(".data");
+bool dcache_exists __section(".data") = false;
+bool icache_exists __section(".data") = false;
#define CACHE_LINE_MASK (~(l1_line_sz - 1))
#ifdef CONFIG_ISA_ARCV2
int slc_line_sz __section(".data");
-int slc_exists __section(".data");
-int ioc_exists __section(".data");
+bool slc_exists __section(".data") = false;
+bool ioc_exists __section(".data") = false;
static unsigned int __before_slc_op(const int op)
{
sbcr.word = read_aux_reg(ARC_BCR_SLC);
if (sbcr.fields.ver) {
slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
- slc_exists = 1;
+ slc_exists = true;
slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
}
cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
if (cbcr.fields.c)
- ioc_exists = 1;
+ ioc_exists = true;
}
#endif
ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
if (ibcr.fields.ver) {
- icache_exists = 1;
+ icache_exists = true;
l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
if (!ic_line_sz)
panic("Instruction exists but line length is 0\n");
dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
if (dbcr.fields.ver){
- dcache_exists = 1;
+ dcache_exists = true;
l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
if (!dc_line_sz)
panic("Data cache exists but line length is 0\n");
select SUPPORT_SPL
select ARCH_MISC_INIT
imply SCSI
+ imply SCSI_AHCI
help
Support for Freescale LS2080AQDS platform
The LS2080A Development System (QDS) is a high-performance
select SUPPORT_SPL
select ARCH_MISC_INIT
imply SCSI
+ imply SCSI_AHCI
help
Support for Freescale LS2080ARDB platform.
The LS2080A Reference design board (RDB) is a high-performance
select ARM64
select BOARD_LATE_INIT
imply SCSI
+ imply SCSI_AHCI
help
Support for Freescale LS1012ARDB platform.
The LS1012A Reference design board (RDB) is a high-performance
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
imply SCSI
+ imply SCSI_AHCI
imply CMD_PCI
menu "LS102xA architecture"
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
+ imply SCSI_AHCI
imply CMD_PCI
config ARCH_LS1046A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
+ imply SCSI_AHCI
config ARCH_LS1088A
bool
reg = <0x10440000 0x1000>;
};
- serial@13800000 {
+ gic: interrupt-controller@10490000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ cpu-offset = <0x4000>;
+ reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
+ };
+
+ serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x3c>;
id = <0>;
};
- serial@13810000 {
+ serail_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x3c>;
id = <1>;
};
- serial@13820000 {
+ serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x3c>;
id = <2>;
};
- serial@13830000 {
+ serial_3: serial@13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x3c>;
id = <3>;
};
- serial@13840000 {
+ serial_4: serial@13840000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13840000 0x3c>;
id = <4>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <0 56 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <1 57 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <2 58 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <3 59 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138a0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <4 60 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138b0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <5 61 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138c0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <6 62 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138d0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <7 63 0>;
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12510000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 75 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12520000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 76 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12530000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 77 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12540000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 78 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 131 0>;
status = "disabled";
};
cpu-offset = <0x8000>;
};
- combiner: interrupt-controller@10440000 {
- samsung,combiner-nr = <16>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
- };
-
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
};
};
};
+
+&combiner {
+ samsung,combiner-nr = <16>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+};
compatible = "samsung,odroid", "samsung,exynos4412";
aliases {
- i2c0 = "/i2c@13860000";
- i2c1 = "/i2c@13870000";
- i2c2 = "/i2c@13880000";
- i2c3 = "/i2c@13890000";
- i2c4 = "/i2c@138a0000";
- i2c5 = "/i2c@138b0000";
- i2c6 = "/i2c@138c0000";
- i2c7 = "/i2c@138d0000";
serial0 = "/serial@13800000";
console = "/serial@13810000";
mmc0 = &mshc_0;
mmc1 = &sdhci2;
};
- i2c@13860000 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- status = "okay";
-
- max77686_pmic@09 {
- compatible = "maxim,max77686";
- interrupts = <7 0>;
- reg = <0x09 0 0>;
- #clock-cells = <1>;
-
- voltage-regulators {
- ldo1_reg: LDO1 {
- regulator-name = "VDD_ALIVE_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "VDDQ_VM1M2_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "VCC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "VDDQ_MMC2_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo5_reg: LDO5 {
- regulator-name = "VDDQ_MMC0/1/3_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "VMPLL_1.0V";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- ldo7_reg: LDO7 {
- regulator-name = "VPLL_1.1V";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- ldo8_reg: LDO8 {
- regulator-name = "VDD_MIPI/HDMI_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo10_reg: LDO10 {
- regulator-name = "VDD_MIPI/HDMI_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo11_reg: LDO11 {
- regulator-name = "VDD_ABB1_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo12_reg: LDO12 {
- regulator-name = "VDD_UOTG_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo13_reg: LDO13 {
- regulator-name = "VDD_C2C_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo14_reg: LDO14 {
- regulator-name = "VDD_ABB02_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo15_reg: LDO15 {
- regulator-name = "VDD_HSIC/OTG_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo16_reg: LDO16 {
- regulator-name = "VDD_HSIC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo17_reg: LDO17 {
- regulator-name = "VDDQ_CAM_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo20_reg: LDO20 {
- regulator-name = "VDDQ_EMMC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo21_reg: LDO21 {
- regulator-name = "TFLASH_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo22_reg: LDO22 {
- regulator-name = "VDDQ_EMMC_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo25_reg: LDO25 {
- regulator-compatible = "LDO25";
- regulator-name = "VDDQ_LCD_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- buck1_reg: BUCK1 {
- regulator-name = "VDD_MIF_1.0V";
- regulator-min-microvolt = <8500000>;
- regulator-max-microvolt = <1100000>;
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "VDD_ARM_1.0V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1500000>;
- };
-
- buck3_reg: BUCK3 {
- regulator-name = "VDD_INT_1.1V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- };
-
- buck4_reg: BUCK4 {
- regulator-name = "VDD_G3D_1.0V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- };
-
- buck5_reg: BUCK5 {
- regulator-name = "VDDQ_AP_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- buck6_reg: BUCK6 {
- regulator-name = "VCC_INL1/7_1.35V";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- };
-
- buck7_reg: BUCK7 {
- regulator-name = "VCC_INL2/3/5_2.0V";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- };
-
- buck8_reg: BUCK8 {
- regulator-name = "VCC_P3V3_2.85V";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
- };
-
serial@13810000 {
status = "okay";
};
};
};
+&i2c_0 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686: max77686_pmic@09 {
+ compatible = "maxim,max77686";
+ interrupt-parent = <&gpx3>;
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "VDDQ_VM1M2_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDDQ_MMC2_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDDQ_MMC0/1/3_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VMPLL_1.0V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VPLL_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD_MIPI/HDMI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDD_MIPI/HDMI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD_ABB1_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD_UOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDD_C2C_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDD_ABB02_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDD_HSIC/OTG_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDD_HSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VDDQ_CAM_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDDQ_EMMC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "TFLASH_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VDDQ_EMMC_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "VDDQ_LCD_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "VDD_MIF_1.0V";
+ regulator-min-microvolt = <8500000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "VDD_ARM_1.0V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "VDD_INT_1.1V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "VDD_G3D_1.0V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "VDDQ_AP_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "VCC_INL1/7_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "VCC_INL2/3/5_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "VCC_P3V3_2.85V";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
&sdhci2 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
};
aliases {
- i2c0 = "/i2c@13860000";
- i2c1 = "/i2c@13870000";
- i2c2 = "/i2c@13880000";
- i2c3 = "/i2c@13890000";
- i2c4 = "/i2c@138a0000";
- i2c5 = "/i2c@138b0000";
- i2c6 = "/i2c@138c0000";
- i2c7 = "/i2c@138d0000";
i2c8 = &i2c_fg;
i2c9 = &i2c_max77693;
serial0 = "/serial@13800000";
status = "okay";
};
- i2c@138d0000 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- status = "okay";
-
- max77686_pmic@09 {
- compatible = "maxim,max77686";
- interrupts = <7 0>;
- reg = <0x09 0 0>;
- #clock-cells = <1>;
-
- voltage-regulators {
- ldo1_reg: LDO1 {
- regulator-compatible = "LDO1";
- regulator-name = "VALIVE_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-compatible = "LDO2";
- regulator-name = "VM1M2_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo3_reg: LDO3 {
- regulator-compatible = "LDO3";
- regulator-name = "VCC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-compatible = "LDO4";
- regulator-name = "VCC_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo5_reg: LDO5 {
- regulator-compatible = "LDO5";
- regulator-name = "VCC_1.8V_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo6_reg: LDO6 {
- regulator-compatible = "LDO6";
- regulator-name = "VMPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo7_reg: LDO7 {
- regulator-compatible = "LDO7";
- regulator-name = "VPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo8_reg: LDO8 {
- regulator-compatible = "LDO8";
- regulator-name = "VMIPI_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-mem-off;
- };
-
- ldo9_reg: LDO9 {
- regulator-compatible = "LDO9";
- regulator-name = "CAM_ISP_MIPI_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-idle;
- };
-
- ldo10_reg: LDO10 {
- regulator-compatible = "LDO10";
- regulator-name = "VMIPI_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-off;
- };
-
- ldo11_reg: LDO11 {
- regulator-compatible = "LDO11";
- regulator-name = "VABB1_1.95V";
- regulator-min-microvolt = <1950000>;
- regulator-max-microvolt = <1950000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo12_reg: LDO12 {
- regulator-compatible = "LDO12";
- regulator-name = "VUOTG_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-mem-off;
- };
-
- ldo13_reg: LDO13 {
- regulator-compatible = "LDO13";
- regulator-name = "NFC_AVDD_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo14_reg: LDO14 {
- regulator-compatible = "LDO14";
- regulator-name = "VABB2_1.95V";
- regulator-min-microvolt = <1950000>;
- regulator-max-microvolt = <1950000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo15_reg: LDO15 {
- regulator-compatible = "LDO15";
- regulator-name = "VHSIC_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-mem-off;
- };
-
- ldo16_reg: LDO16 {
- regulator-compatible = "LDO16";
- regulator-name = "VHSIC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-off;
- };
-
- ldo17_reg: LDO17 {
- regulator-compatible = "LDO17";
- regulator-name = "CAM_SENSOR_CORE_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-idle;
- };
-
- ldo18_reg: LDO18 {
- regulator-compatible = "LDO18";
- regulator-name = "CAM_ISP_SEN_IO_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo19_reg: LDO19 {
- regulator-compatible = "LDO19";
- regulator-name = "VT_CAM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo20_reg: LDO20 {
- regulator-compatible = "LDO20";
- regulator-name = "VDDQ_PRE_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo21_reg: LDO21 {
- regulator-compatible = "LDO21";
- regulator-name = "VTF_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-mem-idle;
- };
-
- ldo22_reg: LDO22 {
- regulator-compatible = "LDO22";
- regulator-name = "VMEM_VDD_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo23_reg: LDO23 {
- regulator-compatible = "LDO23";
- regulator-name = "TSP_AVDD_3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-mem-idle;
- };
-
- ldo24_reg: LDO24 {
- regulator-compatible = "LDO24";
- regulator-name = "TSP_VDD_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo25_reg: LDO25 {
- regulator-compatible = "LDO25";
- regulator-name = "LCD_VCC_3.3V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-mem-idle;
- };
-
- ldo26_reg: LDO26 {
- regulator-compatible = "LDO26";
- regulator-name = "MOTOR_VCC_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-mem-idle;
- };
-
- buck1_reg: BUCK1 {
- regulator-compatible = "BUCK1";
- regulator-name = "vdd_mif";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck2_reg: BUCK2 {
- regulator-compatible = "BUCK2";
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck3_reg: BUCK3 {
- regulator-compatible = "BUCK3";
- regulator-name = "vdd_int";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck4_reg: BUCK4 {
- regulator-compatible = "BUCK4";
- regulator-name = "vdd_g3d";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck5_reg: BUCK5 {
- regulator-compatible = "BUCK5";
- regulator-name = "VMEM_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- regulator-compatible = "BUCK6";
- regulator-name = "VCC_SUB_1.35V";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- };
-
- buck7_reg: BUCK7 {
- regulator-compatible = "BUCK7";
- regulator-name = "VCC_SUB_2.0V";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-always-on;
- };
-
- buck8_reg: BUCK8 {
- regulator-compatible = "BUCK8";
- regulator-name = "VMEM_VDDF_3.0V";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- buck9_reg: BUCK9 {
- regulator-compatible = "BUCK9";
- regulator-name = "CAM_ISP_CORE_1.2V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-off;
- };
- };
- };
- };
-
fimd@11c00000 {
compatible = "samsung,exynos-fimd";
reg = <0x11c00000 0xa4>;
};
};
+&i2c_7 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686: max77686_pmic@09 {
+ compatible = "maxim,max77686";
+ interrupt-parent = <&gpx0>;
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: LDO1 {
+ regulator-compatible = "LDO1";
+ regulator-name = "VALIVE_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "VM1M2_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-compatible = "LDO4";
+ regulator-name = "VCC_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "VCC_1.8V_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "VMPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "VPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-compatible = "LDO8";
+ regulator-name = "VMIPI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-compatible = "LDO9";
+ regulator-name = "CAM_ISP_MIPI_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-compatible = "LDO10";
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-compatible = "LDO11";
+ regulator-name = "VABB1_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-compatible = "LDO12";
+ regulator-name = "VUOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-off;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-compatible = "LDO13";
+ regulator-name = "NFC_AVDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-compatible = "LDO14";
+ regulator-name = "VABB2_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-compatible = "LDO15";
+ regulator-name = "VHSIC_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-compatible = "LDO16";
+ regulator-name = "VHSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-compatible = "LDO17";
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo18_reg: LDO18 {
+ regulator-compatible = "LDO18";
+ regulator-name = "CAM_ISP_SEN_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-compatible = "LDO19";
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-compatible = "LDO20";
+ regulator-name = "VDDQ_PRE_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-compatible = "LDO21";
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-compatible = "LDO22";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-compatible = "LDO23";
+ regulator-name = "TSP_AVDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-mem-idle;
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-compatible = "LDO24";
+ regulator-name = "TSP_VDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "LCD_VCC_3.3V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-compatible = "LDO26";
+ regulator-name = "MOTOR_VCC_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-idle;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-compatible = "BUCK3";
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-compatible = "BUCK4";
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-compatible = "BUCK5";
+ regulator-name = "VMEM_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-compatible = "BUCK6";
+ regulator-name = "VCC_SUB_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-compatible = "BUCK7";
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-compatible = "BUCK8";
+ regulator-name = "VMEM_VDDF_3.0V";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-compatible = "BUCK9";
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-off;
+ };
+ };
+ };
+};
+
&sdhci0 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
/ {
compatible = "samsung,exynos4412";
+};
- gic: interrupt-controller@10490000 {
- cpu-offset = <0x4000>;
- };
-
- interrupt-controller@10440000 {
- samsung,combiner-nr = <20>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
- };
-
+&combiner {
+ samsung,combiner-nr = <20>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+ <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
pinctrl_3: pinctrl@106E0000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 72 0>;
};
g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#endif
-
-/*
- * Implementation specifics
- */
-
-#ifdef CONFIG_ARCH_LUBBOCK
-#include "lubbock.h"
-#endif
-
-#ifdef CONFIG_ARCH_PXA_IDP
-#include "idp.h"
-#endif
-
-#ifdef CONFIG_ARCH_PXA_CERF
-#include "cerf.h"
-#endif
-
-#ifdef CONFIG_ARCH_CSB226
-#include "csb226.h"
-#endif
-
-#ifdef CONFIG_ARCH_INNOKOM
-#include "innokom.h"
-#endif
-
-#ifdef CONFIG_ARCH_PLEB
-#include "pleb.h"
-#endif
-
#endif /* _ASM_ARCH_HARDWARE_H */
*/
#ifdef CONFIG_IDE
#define __io
-#define CONFIG_MVSATA_IDE
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/sizes.h>
#define SC_PLLCTRL_SSC_EN BIT(31)
#define SC_PLLCTRL2_NRSTDS BIT(28)
#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
-#define SC_PLLCTRL3_REGI_SHIFT 16
#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
/* PLL type: VPLL27 */
if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
tmp = readl(base); /* SSCPLLCTRL */
tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
- tmp |= (487 * freq * ssc_rate / divn / 512) &
- SC_PLLCTRL_SSC_DK_MASK;
+ tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK,
+ DIV_ROUND_CLOSEST(487UL * freq * ssc_rate,
+ divn * 512));
writel(tmp, base);
tmp = readl(base + 4);
tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
- tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
+ tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK,
+ DIV_ROUND_CLOSEST(21431887UL * freq,
+ divn * 512));
+ writel(tmp, base + 4);
udelay(50);
}
tmp = readl(base + 8); /* SSCPLLCTRL3 */
tmp &= ~SC_PLLCTRL3_REGI_MASK;
- tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
+ tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
writel(tmp, base + 8);
iounmap(base);
bool "Support MPC837XEMDS"
select BOARD_EARLY_INIT_F
imply CMD_SATA
+ imply FSL_SATA
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
# Use DDR3 controller with DDR2 DIMMs on this board
select SYS_FSL_DDRC_GEN3
imply CMD_SATA
+ imply FSL_SATA
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
select SUPPORT_SPL
select SUPPORT_TPL
imply CMD_SATA
+ imply FSL_SATA
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1025
imply CMD_EEPROM
imply CMD_SATA
+ imply SATA_SIL
config TARGET_P2020RDB
bool "Support P2020RDB-PC"
select ARCH_P2020
imply CMD_EEPROM
imply CMD_SATA
+ imply SATA_SIL
config TARGET_P1_TWR
bool "Support p1_twr"
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
imply CMD_SATA
+ imply FSL_SATA
config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
select PHYS_64BIT
imply CMD_EEPROM
imply CMD_SATA
+ imply FSL_SATA
config TARGET_T1023RDB
bool "Support T1023RDB"
imply CMD_SATA
imply CMD_PCI
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_P1011
bool
imply CMD_SATA
imply CMD_PCI
imply CMD_REGINFO
+ imply SATA_SIL
config ARCH_P1021
bool
imply CMD_NAND
imply CMD_SATA
imply CMD_REGINFO
+ imply SATA_SIL
config ARCH_P1022
bool
imply CMD_SATA
imply CMD_PCI
imply CMD_REGINFO
+ imply SATA_SIL
config ARCH_P1025
bool
imply CMD_NAND
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_P4080
bool
select FSL_ELBC
imply CMD_SATA
imply CMD_REGINFO
+ imply SATA_SIL
config ARCH_P5020
bool
select FSL_ELBC
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_P5040
bool
select FSL_ELBC
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_QEMU_E500
bool
imply CMD_NAND
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_T1042
bool
imply CMD_NAND
imply CMD_SATA
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_T2080
bool
imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_T2081
bool
imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
+ imply FSL_SATA
config ARCH_T4240
bool
imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
+ imply FSL_SATA
config BOOKE
bool
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
imply ICH_SPI
imply INTEL_BROADWELL_GPIO
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply USB
imply USB_EHCI_HCD
imply MMC_PCI
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
+ imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
imply ICH_SPI
imply INTEL_ICH6_GPIO
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply USB
imply USB_EHCI_HCD
select ARCH_EARLY_INIT_R
imply AHCI_PCI
imply E1000
+ imply SCSI_AHCI
imply SYS_NS16550
imply USB
imply USB_EHCI_HCD
imply MMC_SDHCI_SDMA
imply PCH_GBE
imply SCSI
+ imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
make distclean
make omap3_logic_defconfig
+Falcon Mode: FAT SD cards
+=========================
+
+In this case the additional file is written to the filesystem. In this
+example we assume that the uImage and device tree to be used are already on
+the FAT filesystem (only the uImage MUST be for this to function
+afterwards) along with a Falcon Mode aware MLO and the FAT partition has
+already been created and marked bootable:
+
+U-Boot # mmc rescan
+# Load kernel and device tree into memory, perform export
+U-Boot # fatload mmc 0 ${loadaddr} uImage
+U-Boot # run loadfdt
+U-Boot # setenv optargs quiet
+U-Boot # run mmcargs
+U-Boot # run common_bootargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+
+This will print a number of lines and then end with something like:
+ Loading Device Tree to 8dec9000, end 8dee0295 ... OK
+
+So then note the starting address and write the args to mmc/sd:
+
+U-Boot # fatwrite mmc 0:1 0x8dec9000 args 0x20000
+
+The size of 0x20000 matches the CMD_SPL_WRITE_SIZE.
+
+Falcon Mode: NAND
+=================
+
+In this case the additional data is written to another partition of the
+NAND. In this example we assume that the uImage and device tree to be are
+already located on the NAND somewhere (such as filesystem or mtd partition)
+along with a Falcon Mode aware MLO written to the correct locations for
+booting and mtdparts have been configured correctly for the board:
+
+U-Boot # nand read ${loadaddr} kernel
+U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
+U-Boot # run nandargs
+U-Boot # run common_bootargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+U-Boot # nand erase.part u-boot-spl-os
+U-Boot # nand write ${fdtaddr} u-boot-spl-os
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
+
+#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
+#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
+#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
+
+void spl_board_prepare_for_linux(void)
+{
+ /* The Micron NAND starts locked which
+ * prohibits mounting the NAND as RW
+ * The following commands are what unlocks
+ * the NAND to become RW Falcon Mode does not
+ * have as many smarts as U-Boot, but Logic PD
+ * only makes NAND with 512MB so these hard coded
+ * values should work for all current models
+ */
+
+ writeb(0x70, GPMC_NAND_COMMAND_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+ writeb(0x7a, GPMC_NAND_COMMAND_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(-1, GPMC_NAND_COMMAND_0);
+
+ /* Begin address 0 */
+ writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(0x00, GPMC_NAND_ADDRESS_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+
+ /* Ending address at the end of Flash */
+ writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
+ writeb(0xc0, GPMC_NAND_ADDRESS_0);
+ writeb(0xff, GPMC_NAND_ADDRESS_0);
+ writeb(0x03, GPMC_NAND_ADDRESS_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+ writeb(0x79, GPMC_NAND_COMMAND_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+ writeb(-1, GPMC_NAND_DATA_0);
+}
#endif
#ifdef CONFIG_USB_MUSB_OMAP2PLUS
}
#ifdef CONFIG_BOARD_LATE_INIT
+
+static void unlock_nand(void)
+{
+ int dev = nand_curr_device;
+ struct mtd_info *mtd;
+
+ mtd = get_nand_dev_by_index(dev);
+ nand_unlock(mtd, 0, mtd->size, 0);
+}
+
int board_late_init(void)
{
struct board_id *board;
/* restore hsusb0_data5 pin as hsusb0_data5 */
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
+ unlock_nand();
+#endif
return 0;
}
#endif
};
/**
- * Odroix XU3/4 board revisions:
+ * Odroix XU3/XU4/HC1 board revisions (from HC1_MAIN_REV0.1_20170630.pdf):
* Rev ADCmax Board
* 0.1 0 XU3 0.1
- * 0.2 410 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
- * 0.3 1408 XU4 0.1
- * Use +10 % for ADC value tolerance.
+ * 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
+ * 0.3 1280 XU4 0.1
+ * 0.4 739 XU4 0.2
+ * 0.5 1016 XU4+Air0.1 (Passive cooling)
+ * 0.6 1308 XU4S 0.1 (HC1)
+ * Use +1% for ADC value tolerance in the array below, the code loops until
+ * the measured ADC value is lower than then ADCmax from the array.
*/
struct odroid_rev_info odroid_info[] = {
{ EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" },
- { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 410, "xu3" },
- { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1408, "xu4" },
+ { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" },
+ { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" },
+ { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1321, "hc1" },
{ EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" },
};
goto rev_default;
for (i = 0; i < ARRAY_SIZE(odroid_info); i++) {
- /* ADC tolerance: +20 % */
+ /* ADC tolerance: +1% */
if (adcval < odroid_info[i].adc_val)
return odroid_info[i].board_type;
}
return false;
}
+bool board_is_odroidhc1(void)
+{
+ if (gd->board_type == EXYNOS5_BOARD_ODROID_HC1_REV01)
+ return true;
+
+ return false;
+}
+
bool board_is_generic(void)
{
if (gd->board_type == EXYNOS5_BOARD_GENERIC)
{
char *info = "Not supported!";
- if (board_is_odroidxu4())
+ if (board_is_odroidxu4() || board_is_odroidhc1())
return info;
return env_get("dfu_alt_system");
char *alt_boot;
int dev_num;
- if (board_is_odroidxu4())
+ if (board_is_odroidxu4() || board_is_odroidhc1())
return info;
dev_num = simple_strtoul(devstr, NULL, 10);
return 0;
}
+#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
+#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
+#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
+
int board_mmc_init(bd_t *bis)
{
struct dwmci_host *host = NULL;
return 1;
}
+ /*
+ * Switch SDIO external ciu clock divider from default div-by-8 to
+ * minimum possible div-by-2.
+ */
+ writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
+
memset(host, 0, sizeof(struct dwmci_host));
host->name = "Synopsys Mobile storage";
host->ioaddr = (void *)ARC_DWMMC_BASE;
host->buswidth = 4;
host->dev_index = 0;
- host->bus_hz = 100000000;
+ host->bus_hz = 50000000;
add_dwmci(host, host->bus_hz / 2, 400000);
return 0;
}
+/**
+ * Get 'data-position' property from a given image node.
+ *
+ * @fit: pointer to the FIT image header
+ * @noffset: component image node offset
+ * @data_position: holds the data-position property
+ *
+ * returns:
+ * 0, on success
+ * -ENOENT if the property could not be found
+ */
+int fit_image_get_data_position(const void *fit, int noffset,
+ int *data_position)
+{
+ const fdt32_t *val;
+
+ val = fdt_getprop(fit, noffset, FIT_DATA_POSITION_PROP, NULL);
+ if (!val)
+ return -ENOENT;
+
+ *data_position = fdt32_to_cpu(*val);
+
+ return 0;
+}
+
/**
* Get 'data-size' property from a given image node.
*
int align_len = ARCH_DMA_MINALIGN - 1;
uint8_t image_comp = -1, type = -1;
const void *data;
+ bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, &image_comp))
if (fit_image_get_load(fit, node, &load_addr))
load_addr = image_info->load_addr;
- if (!fit_image_get_data_offset(fit, node, &offset)) {
- /* External data */
+ if (!fit_image_get_data_position(fit, node, &offset)) {
+ external_data = true;
+ } else if (!fit_image_get_data_offset(fit, node, &offset)) {
offset += base_offset;
+ external_data = true;
+ }
+
+ if (external_data) {
+ /* External data */
if (fit_image_get_data_size(fit, node, &len))
return -ENOENT;
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_SUN4I_EMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_SCSI_AHCI=y
CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_AXP_ELDO3_VOLT=1200
CONFIG_SCSI=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_SUN4I_EMAC=y
CONFIG_SCSI=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_DM_MMC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=e0600000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
+CONFIG_FSL_SATA=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SATA_SIL3114=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SATA_SIL3114=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_SATA=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_SYS_NS16550=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
+CONFIG_SCSI_AHCI=y
CONFIG_SYS_FSL_DDR2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
+CONFIG_SCSI_AHCI=y
CONFIG_SYS_FSL_DDR2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_BMP=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SCSI=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_SUN4I_EMAC=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_SUN4I_EMAC=y
CONFIG_SCSI=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_SCSI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:256k(vsc7385-firmware),256k(dtb),5632k(kernel),57856k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SATA_SIL3114=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SCSI_AHCI=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SCSI_AHCI=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
+CONFIG_SCSI_AHCI=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_PHYLIB=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_CMD_PCA953X=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(reserved)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SCSI_AHCI=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_FSL_SATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_FSL_SATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI_AHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SATA_MV=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_PXA3XX=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_EXT2=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=5
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_NVRAM=y
+CONFIG_SCSI_AHCI=y
# CONFIG_MMC is not set
CONFIG_SCSI=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_DM_SPI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_DM_SPI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1024k(u-boot),512k(env1),512k(env2),14m(boot),240m(data),-@2048k(UBI)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DWC_AHSATA=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
# CONFIG_MVEBU_GPIO is not set
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SCSI_AHCI=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
-CONFIG_IDENT_STRING=" for ODROID-XU3"
+CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1"
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SCSI_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_TCA642X=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_OF_BOARD=y
+CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MVSATA_IDE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_DM_THERMAL=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SATA_MV=y
CONFIG_FPGA_ALTERA=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI_AHCI=y
CONFIG_MISC=y
CONFIG_ATSHA204A=y
CONFIG_MMC_SDHCI=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_DWC_AHSATA=y
CONFIG_PHYLIB=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
--- /dev/null
+* Synopsys HSDK clock generation unit
+
+The Synopsys HSDK clock controller generates and supplies clock to various
+controllers and peripherals within the SoC.
+
+Required Properties:
+
+- compatible: should be "snps,hsdk-cgu-clock"
+- reg: the pair of physical base address and length of clock generation unit
+ memory mapped region and creg arc core divider memory mapped region.
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
+used in device tree sources.
+
+Example: Clock controller node:
+
+ cgu_clk: cgu-clk@f0000000 {
+ compatible = "snps,hsdk-cgu-clock";
+ reg = <0xf0000000 0x1000>, <0xf00014B8 0x4>;
+ #clock-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+controller:
+
+ uart0: serial0@f0005000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf0005000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cgu_clk CLK_SYS_UART_REF>;
+ };
The 'data-offset' property can be substituted with 'data-position', which
defines an absolute position or address as the offset. This is helpful when
-booting U-Boot proper before performing relocation.
+booting U-Boot proper before performing relocation. Pass '-p [offset]' to
+mkimage to enable 'data-position'.
Normal kernel FIT image has data embedded within FIT structure. U-Boot image
for SPL boot has external data. Existence of 'data-offset' can be used to
See also CMD_SATA which provides command-line support.
+config LIBATA
+ bool
+ help
+ Select this to build and link the libata helper functions.
+
+config SCSI_AHCI
+ bool "Enable SCSI interface to SATA devices"
+ select LIBATA
+ help
+ Enable this to allow interfacing SATA devices via the SCSI layer.
+
menu "SATA/SCSI device support"
config AHCI_PCI
Enable this driver to support Sata devices through
Synopsys DWC AHCI module.
+config DWC_AHSATA
+ bool "Enable DWC AHSATA driver support"
+ select LIBATA
+ help
+ Enable this driver to support the DWC AHSATA SATA controller found
+ in i.MX5 and i.MX6 SoCs.
+
+config FSL_SATA
+ bool "Enable Freescale SATA controller driver support"
+ select LIBATA
+ help
+ Enable this driver to support the SATA controller found in
+ some Freescale PowerPC SoCs.
+
+config MVSATA_IDE
+ bool "Enable Marvell SATA controller driver support via IDE interface"
+ help
+ Enable this driver to support the SATA controller found in
+ some Marvell SoCs, running in IDE compatibility mode using PIO.
+
+config SATA_MV
+ bool "Enable Marvell SATA controller driver support"
+ select LIBATA
+ help
+ Enable this driver to support the SATA controller found in
+ some Marvell SoCs.
+
+config SATA_SIL
+ bool "Enable Silicon Image SIL3131 / SIL3132 / SIL3124 SATA driver support"
+ select LIBATA
+ help
+ Enable this driver to support the SIL3131, SIL3132 and SIL3124
+ SATA controllers.
+
+config SATA_SIL3114
+ bool "Enable Silicon Image SIL3114 SATA driver support"
+ select LIBATA
+ help
+ Enable this driver to support the SIL3114 SATA controllers.
+
endmenu
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
obj-$(CONFIG_LIBATA) += libata.o
obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
-obj-$(CONFIG_MX51_PATA) += mxc_ata.o
obj-$(CONFIG_SATA) += sata.o
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
-obj-$(CONFIG_SATA_DWC) += sata_dwc.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
+++ /dev/null
-/*
- * Freescale iMX51 ATA driver
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on code by:
- * Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
- *
- * Based on code from original FSL ATA driver, which is
- * part of eCos, the Embedded Configurable Operating System.
- * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <ide.h>
-
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-/* MXC ATA register offsets */
-struct mxc_ata_config_regs {
- u8 time_off; /* 0x00 */
- u8 time_on;
- u8 time_1;
- u8 time_2w;
- u8 time_2r;
- u8 time_ax;
- u8 time_pio_rdx;
- u8 time_4;
- u8 time_9;
- u8 time_m;
- u8 time_jn;
- u8 time_d;
- u8 time_k;
- u8 time_ack;
- u8 time_env;
- u8 time_udma_rdx;
- u8 time_zah; /* 0x10 */
- u8 time_mlix;
- u8 time_dvh;
- u8 time_dzfs;
- u8 time_dvs;
- u8 time_cvh;
- u8 time_ss;
- u8 time_cyc;
- u32 fifo_data_32; /* 0x18 */
- u32 fifo_data_16;
- u32 fifo_fill;
- u32 ata_control;
- u32 interrupt_pending;
- u32 interrupt_enable;
- u32 interrupt_clear;
- u32 fifo_alarm;
-};
-
-struct mxc_data_hdd_regs {
- u32 drive_data; /* 0xa0 */
- u32 drive_features;
- u32 drive_sector_count;
- u32 drive_sector_num;
- u32 drive_cyl_low;
- u32 drive_cyl_high;
- u32 drive_dev_head;
- u32 command;
- u32 status;
- u32 alt_status;
-};
-
-/* PIO timing table */
-#define NR_PIO_SPECS 5
-static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 };
-static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 };
-static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 };
-static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 };
-static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 };
-
-#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8)
-static void set_ata_bus_timing(unsigned char mode)
-{
- uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK);
-
- struct mxc_ata_config_regs *ata_regs;
- ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
-
- if (mode >= NR_PIO_SPECS)
- return;
-
- /* Write TIME_OFF/ON/1/2W */
- writeb(3, &ata_regs->time_off);
- writeb(3, &ata_regs->time_on);
- writeb((pio_t1[mode] + T) / T, &ata_regs->time_1);
- writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2w);
-
- /* Write TIME_2R/AX/RDX/4 */
- writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2r);
- writeb((pio_tA[mode] + T) / T + 2, &ata_regs->time_ax);
- writeb(1, &ata_regs->time_pio_rdx);
- writeb((pio_t4[mode] + T) / T, &ata_regs->time_4);
-
- /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
- writeb((pio_t9[mode] + T) / T, &ata_regs->time_9);
-}
-
-int ide_preinit(void)
-{
- struct mxc_ata_config_regs *ata_regs;
- ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
-
- /* 46.3.3.4 @ FSL iMX51 manual */
- /* FIFO normal op., drive reset */
- writel(0x80, &ata_regs->ata_control);
- /* FIFO normal op., drive not reset */
- writel(0xc0, &ata_regs->ata_control);
-
- /* Configure the PIO timing */
- set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE);
-
- /* 46.3.3.4 @ FSL iMX51 manual */
- /* Drive not reset, IORDY handshake */
- writel(0x41, &ata_regs->ata_control);
-
- return 0;
-}
+++ /dev/null
-/*
- * sata_dwc.c
- *
- * Synopsys DesignWare Cores (DWC) SATA host driver
- *
- * Author: Mark Miesfeld <mmiesfeld@amcc.com>
- *
- * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
- * Copyright 2008 DENX Software Engineering
- *
- * Based on versions provided by AMCC and Synopsys which are:
- * Copyright 2006 Applied Micro Circuits Corporation
- * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * SATA support based on the chip canyonlands.
- *
- * 04-17-2009
- * The local version of this driver for the canyonlands board
- * does not use interrupts but polls the chip instead.
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <linux/dma-direction.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <ata.h>
-#include <sata.h>
-#include <linux/ctype.h>
-
-#include "sata_dwc.h"
-
-#define DMA_NUM_CHANS 1
-#define DMA_NUM_CHAN_REGS 8
-
-#define AHB_DMA_BRST_DFLT 16
-
-struct dmareg {
- u32 low;
- u32 high;
-};
-
-struct dma_chan_regs {
- struct dmareg sar;
- struct dmareg dar;
- struct dmareg llp;
- struct dmareg ctl;
- struct dmareg sstat;
- struct dmareg dstat;
- struct dmareg sstatar;
- struct dmareg dstatar;
- struct dmareg cfg;
- struct dmareg sgr;
- struct dmareg dsr;
-};
-
-struct dma_interrupt_regs {
- struct dmareg tfr;
- struct dmareg block;
- struct dmareg srctran;
- struct dmareg dsttran;
- struct dmareg error;
-};
-
-struct ahb_dma_regs {
- struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
- struct dma_interrupt_regs interrupt_raw;
- struct dma_interrupt_regs interrupt_status;
- struct dma_interrupt_regs interrupt_mask;
- struct dma_interrupt_regs interrupt_clear;
- struct dmareg statusInt;
- struct dmareg rq_srcreg;
- struct dmareg rq_dstreg;
- struct dmareg rq_sgl_srcreg;
- struct dmareg rq_sgl_dstreg;
- struct dmareg rq_lst_srcreg;
- struct dmareg rq_lst_dstreg;
- struct dmareg dma_cfg;
- struct dmareg dma_chan_en;
- struct dmareg dma_id;
- struct dmareg dma_test;
- struct dmareg res1;
- struct dmareg res2;
- /* DMA Comp Params
- * Param 6 = dma_param[0], Param 5 = dma_param[1],
- * Param 4 = dma_param[2] ...
- */
- struct dmareg dma_params[6];
-};
-
-#define DMA_EN 0x00000001
-#define DMA_DI 0x00000000
-#define DMA_CHANNEL(ch) (0x00000001 << (ch))
-#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
- ((0x000000001 << (ch)) << 8))
-#define DMA_DISABLE_CHAN(ch) (0x00000000 | \
- ((0x000000001 << (ch)) << 8))
-
-#define SATA_DWC_MAX_PORTS 1
-#define SATA_DWC_SCR_OFFSET 0x24
-#define SATA_DWC_REG_OFFSET 0x64
-
-struct sata_dwc_regs {
- u32 fptagr;
- u32 fpbor;
- u32 fptcr;
- u32 dmacr;
- u32 dbtsr;
- u32 intpr;
- u32 intmr;
- u32 errmr;
- u32 llcr;
- u32 phycr;
- u32 physr;
- u32 rxbistpd;
- u32 rxbistpd1;
- u32 rxbistpd2;
- u32 txbistpd;
- u32 txbistpd1;
- u32 txbistpd2;
- u32 bistcr;
- u32 bistfctr;
- u32 bistsr;
- u32 bistdecr;
- u32 res[15];
- u32 testr;
- u32 versionr;
- u32 idr;
- u32 unimpl[192];
- u32 dmadr[256];
-};
-
-#define SATA_DWC_TXFIFO_DEPTH 0x01FF
-#define SATA_DWC_RXFIFO_DEPTH 0x01FF
-
-#define SATA_DWC_DBTSR_MWR(size) ((size / 4) & SATA_DWC_TXFIFO_DEPTH)
-#define SATA_DWC_DBTSR_MRD(size) (((size / 4) & \
- SATA_DWC_RXFIFO_DEPTH) << 16)
-#define SATA_DWC_INTPR_DMAT 0x00000001
-#define SATA_DWC_INTPR_NEWFP 0x00000002
-#define SATA_DWC_INTPR_PMABRT 0x00000004
-#define SATA_DWC_INTPR_ERR 0x00000008
-#define SATA_DWC_INTPR_NEWBIST 0x00000010
-#define SATA_DWC_INTPR_IPF 0x10000000
-#define SATA_DWC_INTMR_DMATM 0x00000001
-#define SATA_DWC_INTMR_NEWFPM 0x00000002
-#define SATA_DWC_INTMR_PMABRTM 0x00000004
-#define SATA_DWC_INTMR_ERRM 0x00000008
-#define SATA_DWC_INTMR_NEWBISTM 0x00000010
-
-#define SATA_DWC_DMACR_TMOD_TXCHEN 0x00000004
-#define SATA_DWC_DMACR_TXRXCH_CLEAR SATA_DWC_DMACR_TMOD_TXCHEN
-
-#define SATA_DWC_QCMD_MAX 32
-
-#define SATA_DWC_SERROR_ERR_BITS 0x0FFF0F03
-
-#define HSDEVP_FROM_AP(ap) (struct sata_dwc_device_port*) \
- (ap)->private_data
-
-struct sata_dwc_device {
- struct device *dev;
- struct ata_probe_ent *pe;
- struct ata_host *host;
- u8 *reg_base;
- struct sata_dwc_regs *sata_dwc_regs;
- int irq_dma;
-};
-
-struct sata_dwc_device_port {
- struct sata_dwc_device *hsdev;
- int cmd_issued[SATA_DWC_QCMD_MAX];
- u32 dma_chan[SATA_DWC_QCMD_MAX];
- int dma_pending[SATA_DWC_QCMD_MAX];
-};
-
-enum {
- SATA_DWC_CMD_ISSUED_NOT = 0,
- SATA_DWC_CMD_ISSUED_PEND = 1,
- SATA_DWC_CMD_ISSUED_EXEC = 2,
- SATA_DWC_CMD_ISSUED_NODATA = 3,
-
- SATA_DWC_DMA_PENDING_NONE = 0,
- SATA_DWC_DMA_PENDING_TX = 1,
- SATA_DWC_DMA_PENDING_RX = 2,
-};
-
-#define msleep(a) udelay(a * 1000)
-#define ssleep(a) msleep(a * 1000)
-
-static int ata_probe_timeout = (ATA_TMOUT_INTERNAL / 100);
-
-enum sata_dev_state {
- SATA_INIT = 0,
- SATA_READY = 1,
- SATA_NODEVICE = 2,
- SATA_ERROR = 3,
-};
-enum sata_dev_state dev_state = SATA_INIT;
-
-static struct ahb_dma_regs *sata_dma_regs = 0;
-static struct ata_host *phost;
-static struct ata_port ap;
-static struct ata_port *pap = ≈
-static struct ata_device ata_device;
-static struct sata_dwc_device_port dwc_devp;
-
-static void *scr_addr_sstatus;
-static u32 temp_n_block = 0;
-
-static unsigned ata_exec_internal(struct ata_device *dev,
- struct ata_taskfile *tf, const u8 *cdb,
- int dma_dir, unsigned int buflen,
- unsigned long timeout);
-static unsigned int ata_dev_set_feature(struct ata_device *dev,
- u8 enable,u8 feature);
-static unsigned int ata_dev_init_params(struct ata_device *dev,
- u16 heads, u16 sectors);
-static u8 ata_irq_on(struct ata_port *ap);
-static struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
- unsigned int tag);
-static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
- u8 status, int in_wq);
-static void ata_tf_to_host(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static void ata_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc);
-static u8 ata_check_altstatus(struct ata_port *ap);
-static u8 ata_check_status(struct ata_port *ap);
-static void ata_dev_select(struct ata_port *ap, unsigned int device,
- unsigned int wait, unsigned int can_sleep);
-static void ata_qc_issue(struct ata_queued_cmd *qc);
-static void ata_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static int ata_dev_read_sectors(unsigned char* pdata,
- unsigned long datalen, u32 block, u32 n_block);
-static int ata_dev_write_sectors(unsigned char* pdata,
- unsigned long datalen , u32 block, u32 n_block);
-static void ata_std_dev_select(struct ata_port *ap, unsigned int device);
-static void ata_qc_complete(struct ata_queued_cmd *qc);
-static void __ata_qc_complete(struct ata_queued_cmd *qc);
-static void fill_result_tf(struct ata_queued_cmd *qc);
-static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
-static void ata_mmio_data_xfer(struct ata_device *dev,
- unsigned char *buf,
- unsigned int buflen,int do_write);
-static void ata_pio_task(struct ata_port *arg_ap);
-static void __ata_port_freeze(struct ata_port *ap);
-static int ata_port_freeze(struct ata_port *ap);
-static void ata_qc_free(struct ata_queued_cmd *qc);
-static void ata_pio_sectors(struct ata_queued_cmd *qc);
-static void ata_pio_sector(struct ata_queued_cmd *qc);
-static void ata_pio_queue_task(struct ata_port *ap,
- void *data,unsigned long delay);
-static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq);
-static int sata_dwc_softreset(struct ata_port *ap);
-static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
- unsigned int flags, u16 *id);
-static int check_sata_dev_state(void);
-
-static const struct ata_port_info sata_dwc_port_info[] = {
- {
- .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
- ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING |
- ATA_FLAG_SRST | ATA_FLAG_NCQ,
- .pio_mask = 0x1f,
- .mwdma_mask = 0x07,
- .udma_mask = 0x7f,
- },
-};
-
-int init_sata(int dev)
-{
- struct sata_dwc_device hsdev;
- struct ata_host host;
- struct ata_port_info pi = sata_dwc_port_info[0];
- struct ata_link *link;
- struct sata_dwc_device_port hsdevp = dwc_devp;
- u8 *base = 0;
- u8 *sata_dma_regs_addr = 0;
- u8 status;
- unsigned long base_addr = 0;
- int chan = 0;
- int rc;
- int i;
-
- phost = &host;
-
- base = (u8*)SATA_BASE_ADDR;
-
- hsdev.sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
-
- host.n_ports = SATA_DWC_MAX_PORTS;
-
- for (i = 0; i < SATA_DWC_MAX_PORTS; i++) {
- ap.pflags |= ATA_PFLAG_INITIALIZING;
- ap.flags = ATA_FLAG_DISABLED;
- ap.print_id = -1;
- ap.ctl = ATA_DEVCTL_OBS;
- ap.host = &host;
- ap.last_ctl = 0xFF;
-
- link = &ap.link;
- link->ap = ≈
- link->pmp = 0;
- link->active_tag = ATA_TAG_POISON;
- link->hw_sata_spd_limit = 0;
-
- ap.port_no = i;
- host.ports[i] = ≈
- }
-
- ap.pio_mask = pi.pio_mask;
- ap.mwdma_mask = pi.mwdma_mask;
- ap.udma_mask = pi.udma_mask;
- ap.flags |= pi.flags;
- ap.link.flags |= pi.link_flags;
-
- host.ports[0]->ioaddr.cmd_addr = base;
- host.ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
- scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
-
- base_addr = (unsigned long)base;
-
- host.ports[0]->ioaddr.cmd_addr = (void *)base_addr + 0x00;
- host.ports[0]->ioaddr.data_addr = (void *)base_addr + 0x00;
-
- host.ports[0]->ioaddr.error_addr = (void *)base_addr + 0x04;
- host.ports[0]->ioaddr.feature_addr = (void *)base_addr + 0x04;
-
- host.ports[0]->ioaddr.nsect_addr = (void *)base_addr + 0x08;
-
- host.ports[0]->ioaddr.lbal_addr = (void *)base_addr + 0x0c;
- host.ports[0]->ioaddr.lbam_addr = (void *)base_addr + 0x10;
- host.ports[0]->ioaddr.lbah_addr = (void *)base_addr + 0x14;
-
- host.ports[0]->ioaddr.device_addr = (void *)base_addr + 0x18;
- host.ports[0]->ioaddr.command_addr = (void *)base_addr + 0x1c;
- host.ports[0]->ioaddr.status_addr = (void *)base_addr + 0x1c;
-
- host.ports[0]->ioaddr.altstatus_addr = (void *)base_addr + 0x20;
- host.ports[0]->ioaddr.ctl_addr = (void *)base_addr + 0x20;
-
- sata_dma_regs_addr = (u8*)SATA_DMA_REG_ADDR;
- sata_dma_regs = (void *__iomem)sata_dma_regs_addr;
-
- status = ata_check_altstatus(&ap);
-
- if (status == 0x7f) {
- printf("Hard Disk not found.\n");
- dev_state = SATA_NODEVICE;
- rc = false;
- return rc;
- }
-
- printf("Waiting for device...");
- i = 0;
- while (1) {
- udelay(10000);
-
- status = ata_check_altstatus(&ap);
-
- if ((status & ATA_BUSY) == 0) {
- printf("\n");
- break;
- }
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
-
- dev_state = SATA_NODEVICE;
- rc = false;
- return rc;
- }
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- rc = sata_dwc_softreset(&ap);
-
- if (rc) {
- printf("sata_dwc : error. soft reset failed\n");
- return rc;
- }
-
- for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
- out_le32(&(sata_dma_regs->interrupt_mask.error.low),
- DMA_DISABLE_CHAN(chan));
-
- out_le32(&(sata_dma_regs->interrupt_mask.tfr.low),
- DMA_DISABLE_CHAN(chan));
- }
-
- out_le32(&(sata_dma_regs->dma_cfg.low), DMA_DI);
-
- out_le32(&hsdev.sata_dwc_regs->intmr,
- SATA_DWC_INTMR_ERRM |
- SATA_DWC_INTMR_PMABRTM);
-
- /* Unmask the error bits that should trigger
- * an error interrupt by setting the error mask register.
- */
- out_le32(&hsdev.sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
-
- hsdev.host = ap.host;
- memset(&hsdevp, 0, sizeof(hsdevp));
- hsdevp.hsdev = &hsdev;
-
- for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
- hsdevp.cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
-
- out_le32((void __iomem *)scr_addr_sstatus + 4,
- in_le32((void __iomem *)scr_addr_sstatus + 4));
-
- rc = 0;
- return rc;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-static u8 ata_check_altstatus(struct ata_port *ap)
-{
- u8 val = 0;
- val = readb(ap->ioaddr.altstatus_addr);
- return val;
-}
-
-static int sata_dwc_softreset(struct ata_port *ap)
-{
- u8 nsect,lbal = 0;
- u8 tmp = 0;
- struct ata_ioports *ioaddr = &ap->ioaddr;
-
- in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4));
-
- writeb(0x55, ioaddr->nsect_addr);
- writeb(0xaa, ioaddr->lbal_addr);
- writeb(0xaa, ioaddr->nsect_addr);
- writeb(0x55, ioaddr->lbal_addr);
- writeb(0x55, ioaddr->nsect_addr);
- writeb(0xaa, ioaddr->lbal_addr);
-
- nsect = readb(ioaddr->nsect_addr);
- lbal = readb(ioaddr->lbal_addr);
-
- if ((nsect == 0x55) && (lbal == 0xaa)) {
- printf("Device found\n");
- } else {
- printf("No device found\n");
- dev_state = SATA_NODEVICE;
- return false;
- }
-
- tmp = ATA_DEVICE_OBS;
- writeb(tmp, ioaddr->device_addr);
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- udelay(200);
-
- writeb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
-
- udelay(200);
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- msleep(150);
- ata_check_status(ap);
-
- msleep(50);
- ata_check_status(ap);
-
- while (1) {
- u8 status = ata_check_status(ap);
-
- if (!(status & ATA_BUSY))
- break;
-
- printf("Hard Disk status is BUSY.\n");
- msleep(50);
- }
-
- tmp = ATA_DEVICE_OBS;
- writeb(tmp, ioaddr->device_addr);
-
- nsect = readb(ioaddr->nsect_addr);
- lbal = readb(ioaddr->lbal_addr);
-
- return 0;
-}
-
-static u8 ata_check_status(struct ata_port *ap)
-{
- u8 val = 0;
- val = readb(ap->ioaddr.status_addr);
- return val;
-}
-
-static int ata_id_has_hipm(const u16 *id)
-{
- u16 val = id[76];
-
- if (val == 0 || val == 0xffff)
- return -1;
-
- return val & (1 << 9);
-}
-
-static int ata_id_has_dipm(const u16 *id)
-{
- u16 val = id[78];
-
- if (val == 0 || val == 0xffff)
- return -1;
-
- return val & (1 << 3);
-}
-
-int scan_sata(int dev)
-{
- int i;
- int rc;
- u8 status;
- const u16 *id;
- struct ata_device *ata_dev = &ata_device;
- unsigned long pio_mask, mwdma_mask;
- char revbuf[7];
- u16 iobuf[ATA_SECTOR_WORDS];
-
- memset(iobuf, 0, sizeof(iobuf));
-
- if (dev_state == SATA_NODEVICE)
- return 1;
-
- printf("Waiting for device...");
- i = 0;
- while (1) {
- udelay(10000);
-
- status = ata_check_altstatus(&ap);
-
- if ((status & ATA_BUSY) == 0) {
- printf("\n");
- break;
- }
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
-
- dev_state = SATA_NODEVICE;
- return 1;
- }
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- udelay(1000);
-
- rc = ata_dev_read_id(ata_dev, &ata_dev->class,
- ATA_READID_POSTRESET,ata_dev->id);
- if (rc) {
- printf("sata_dwc : error. failed sata scan\n");
- return 1;
- }
-
- /* SATA drives indicate we have a bridge. We don't know which
- * end of the link the bridge is which is a problem
- */
- if (ata_id_is_sata(ata_dev->id))
- ap.cbl = ATA_CBL_SATA;
-
- id = ata_dev->id;
-
- ata_dev->flags &= ~ATA_DFLAG_CFG_MASK;
- ata_dev->max_sectors = 0;
- ata_dev->cdb_len = 0;
- ata_dev->n_sectors = 0;
- ata_dev->cylinders = 0;
- ata_dev->heads = 0;
- ata_dev->sectors = 0;
-
- if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
- pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
- pio_mask <<= 3;
- pio_mask |= 0x7;
- } else {
- /* If word 64 isn't valid then Word 51 high byte holds
- * the PIO timing number for the maximum. Turn it into
- * a mask.
- */
- u8 mode = (id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF;
- if (mode < 5) {
- pio_mask = (2 << mode) - 1;
- } else {
- pio_mask = 1;
- }
- }
-
- mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
-
- if (ata_id_is_cfa(id)) {
- int pio = id[163] & 0x7;
- int dma = (id[163] >> 3) & 7;
-
- if (pio)
- pio_mask |= (1 << 5);
- if (pio > 1)
- pio_mask |= (1 << 6);
- if (dma)
- mwdma_mask |= (1 << 3);
- if (dma > 1)
- mwdma_mask |= (1 << 4);
- }
-
- if (ata_dev->class == ATA_DEV_ATA) {
- if (ata_id_is_cfa(id)) {
- if (id[162] & 1)
- printf("supports DRM functions and may "
- "not be fully accessable.\n");
- strcpy(revbuf, "CFA");
- } else {
- if (ata_id_has_tpm(id))
- printf("supports DRM functions and may "
- "not be fully accessable.\n");
- }
-
- ata_dev->n_sectors = ata_id_n_sectors((u16*)id);
-
- if (ata_dev->id[59] & 0x100)
- ata_dev->multi_count = ata_dev->id[59] & 0xff;
-
- if (ata_id_has_lba(id)) {
- char ncq_desc[20];
-
- ata_dev->flags |= ATA_DFLAG_LBA;
- if (ata_id_has_lba48(id)) {
- ata_dev->flags |= ATA_DFLAG_LBA48;
-
- if (ata_dev->n_sectors >= (1UL << 28) &&
- ata_id_has_flush_ext(id))
- ata_dev->flags |= ATA_DFLAG_FLUSH_EXT;
- }
- if (!ata_id_has_ncq(ata_dev->id))
- ncq_desc[0] = '\0';
-
- if (ata_dev->horkage & ATA_HORKAGE_NONCQ)
- strcpy(ncq_desc, "NCQ (not used)");
-
- if (ap.flags & ATA_FLAG_NCQ)
- ata_dev->flags |= ATA_DFLAG_NCQ;
- }
- ata_dev->cdb_len = 16;
- }
- ata_dev->max_sectors = ATA_MAX_SECTORS;
- if (ata_dev->flags & ATA_DFLAG_LBA48)
- ata_dev->max_sectors = ATA_MAX_SECTORS_LBA48;
-
- if (!(ata_dev->horkage & ATA_HORKAGE_IPM)) {
- if (ata_id_has_hipm(ata_dev->id))
- ata_dev->flags |= ATA_DFLAG_HIPM;
- if (ata_id_has_dipm(ata_dev->id))
- ata_dev->flags |= ATA_DFLAG_DIPM;
- }
-
- if ((ap.cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ata_dev->id))) {
- ata_dev->udma_mask &= ATA_UDMA5;
- ata_dev->max_sectors = ATA_MAX_SECTORS;
- }
-
- if (ata_dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
- printf("Drive reports diagnostics failure."
- "This may indicate a drive\n");
- printf("fault or invalid emulation."
- "Contact drive vendor for information.\n");
- }
-
- rc = check_sata_dev_state();
-
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].revision,
- ATA_ID_FW_REV, sizeof(sata_dev_desc[dev].revision));
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].vendor,
- ATA_ID_PROD, sizeof(sata_dev_desc[dev].vendor));
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].product,
- ATA_ID_SERNO, sizeof(sata_dev_desc[dev].product));
-
- sata_dev_desc[dev].lba = (u32) ata_dev->n_sectors;
-
-#ifdef CONFIG_LBA48
- if (ata_dev->id[83] & (1 << 10)) {
- sata_dev_desc[dev].lba48 = 1;
- } else {
- sata_dev_desc[dev].lba48 = 0;
- }
-#endif
-
- return 0;
-}
-
-static u8 ata_busy_wait(struct ata_port *ap,
- unsigned int bits,unsigned int max)
-{
- u8 status;
-
- do {
- udelay(10);
- status = ata_check_status(ap);
- max--;
- } while (status != 0xff && (status & bits) && (max > 0));
-
- return status;
-}
-
-static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
- unsigned int flags, u16 *id)
-{
- struct ata_port *ap = pap;
- unsigned int class = *p_class;
- struct ata_taskfile tf;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1, tried_spinup = 0;
- u8 status;
- int rc;
-
- status = ata_busy_wait(ap, ATA_BUSY, 30000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- rc = false;
- return rc;
- }
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
- tf.ctl = ap->ctl;
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_ID_ATA;
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
-
- /* Device presence detection is unreliable on some
- * controllers. Always poll IDENTIFY if available.
- */
- tf.flags |= ATA_TFLAG_POLLING;
-
- temp_n_block = 1;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
- sizeof(id[0]) * ATA_ID_WORDS, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
- rc = -EIO;
- reason = "I/O error";
- goto err_out;
- }
-
- /* Falling back doesn't make sense if ID data was read
- * successfully at least once.
- */
- may_fallback = 0;
-
- unsigned int id_cnt;
-
- for (id_cnt = 0; id_cnt < ATA_ID_WORDS; id_cnt++)
- id[id_cnt] = le16_to_cpu(id[id_cnt]);
-
-
- rc = -EINVAL;
- reason = "device reports invalid type";
-
- if (class == ATA_DEV_ATA) {
- if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
- goto err_out;
- } else {
- if (ata_id_is_ata(id))
- goto err_out;
- }
- if (!tried_spinup && (id[2] == 0x37c8 || id[2] == 0x738c)) {
- tried_spinup = 1;
- /*
- * Drive powered-up in standby mode, and requires a specific
- * SET_FEATURES spin-up subcommand before it will accept
- * anything other than the original IDENTIFY command.
- */
- err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP, 0);
- if (err_mask && id[2] != 0x738c) {
- rc = -EIO;
- reason = "SPINUP failed";
- goto err_out;
- }
- /*
- * If the drive initially returned incomplete IDENTIFY info,
- * we now must reissue the IDENTIFY command.
- */
- if (id[2] == 0x37c8)
- goto retry;
- }
-
- if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) {
- /*
- * The exact sequence expected by certain pre-ATA4 drives is:
- * SRST RESET
- * IDENTIFY (optional in early ATA)
- * INITIALIZE DEVICE PARAMETERS (later IDE and ATA)
- * anything else..
- * Some drives were very specific about that exact sequence.
- *
- * Note that ATA4 says lba is mandatory so the second check
- * shoud never trigger.
- */
- if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
- err_mask = ata_dev_init_params(dev, id[3], id[6]);
- if (err_mask) {
- rc = -EIO;
- reason = "INIT_DEV_PARAMS failed";
- goto err_out;
- }
-
- /* current CHS translation info (id[53-58]) might be
- * changed. reread the identify device info.
- */
- flags &= ~ATA_READID_POSTRESET;
- goto retry;
- }
- }
-
- *p_class = class;
- return 0;
-
-err_out:
- printf("failed to READ ID (%s, err_mask=0x%x)\n", reason, err_mask);
- return rc;
-}
-
-static u8 ata_wait_idle(struct ata_port *ap)
-{
- u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
- return status;
-}
-
-static void ata_dev_select(struct ata_port *ap, unsigned int device,
- unsigned int wait, unsigned int can_sleep)
-{
- if (wait)
- ata_wait_idle(ap);
-
- ata_std_dev_select(ap, device);
-
- if (wait)
- ata_wait_idle(ap);
-}
-
-static void ata_std_dev_select(struct ata_port *ap, unsigned int device)
-{
- u8 tmp;
-
- if (device == 0) {
- tmp = ATA_DEVICE_OBS;
- } else {
- tmp = ATA_DEVICE_OBS | ATA_DEV1;
- }
-
- writeb(tmp, ap->ioaddr.device_addr);
-
- readb(ap->ioaddr.altstatus_addr);
-
- udelay(1);
-}
-
-static int waiting_for_reg_state(volatile u8 *offset,
- int timeout_msec,
- u32 sign)
-{
- int i;
- u32 status;
-
- for (i = 0; i < timeout_msec; i++) {
- status = readl(offset);
- if ((status & sign) != 0)
- break;
- msleep(1);
- }
-
- return (i < timeout_msec) ? 0 : -1;
-}
-
-static void ata_qc_reinit(struct ata_queued_cmd *qc)
-{
- qc->dma_dir = DMA_NONE;
- qc->flags = 0;
- qc->nbytes = qc->extrabytes = qc->curbytes = 0;
- qc->n_elem = 0;
- qc->err_mask = 0;
- qc->sect_size = ATA_SECT_SIZE;
- qc->nbytes = ATA_SECT_SIZE * temp_n_block;
-
- memset(&qc->tf, 0, sizeof(qc->tf));
- qc->tf.ctl = 0;
- qc->tf.device = ATA_DEVICE_OBS;
-
- qc->result_tf.command = ATA_DRDY;
- qc->result_tf.feature = 0;
-}
-
-struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
- unsigned int tag)
-{
- if (tag < ATA_MAX_QUEUE)
- return &ap->qcmd[tag];
- return NULL;
-}
-
-static void __ata_port_freeze(struct ata_port *ap)
-{
- printf("set port freeze.\n");
- ap->pflags |= ATA_PFLAG_FROZEN;
-}
-
-static int ata_port_freeze(struct ata_port *ap)
-{
- __ata_port_freeze(ap);
- return 0;
-}
-
-unsigned ata_exec_internal(struct ata_device *dev,
- struct ata_taskfile *tf, const u8 *cdb,
- int dma_dir, unsigned int buflen,
- unsigned long timeout)
-{
- struct ata_link *link = dev->link;
- struct ata_port *ap = pap;
- struct ata_queued_cmd *qc;
- unsigned int tag, preempted_tag;
- u32 preempted_sactive, preempted_qc_active;
- int preempted_nr_active_links;
- unsigned int err_mask;
- int rc = 0;
- u8 status;
-
- status = ata_busy_wait(ap, ATA_BUSY, 300000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- rc = false;
- return rc;
- }
-
- if (ap->pflags & ATA_PFLAG_FROZEN)
- return AC_ERR_SYSTEM;
-
- tag = ATA_TAG_INTERNAL;
-
- if (test_and_set_bit(tag, &ap->qc_allocated)) {
- rc = false;
- return rc;
- }
-
- qc = __ata_qc_from_tag(ap, tag);
- qc->tag = tag;
- qc->ap = ap;
- qc->dev = dev;
-
- ata_qc_reinit(qc);
-
- preempted_tag = link->active_tag;
- preempted_sactive = link->sactive;
- preempted_qc_active = ap->qc_active;
- preempted_nr_active_links = ap->nr_active_links;
- link->active_tag = ATA_TAG_POISON;
- link->sactive = 0;
- ap->qc_active = 0;
- ap->nr_active_links = 0;
-
- qc->tf = *tf;
- if (cdb)
- memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
- qc->flags |= ATA_QCFLAG_RESULT_TF;
- qc->dma_dir = dma_dir;
- qc->private_data = 0;
-
- ata_qc_issue(qc);
-
- if (!timeout)
- timeout = ata_probe_timeout * 1000 / HZ;
-
- status = ata_busy_wait(ap, ATA_BUSY, 30000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- printf("altstatus = 0x%x.\n", status);
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- if (waiting_for_reg_state(ap->ioaddr.altstatus_addr, 1000, 0x8)) {
- u8 status = 0;
- u8 errorStatus = 0;
-
- status = readb(ap->ioaddr.altstatus_addr);
- if ((status & 0x01) != 0) {
- errorStatus = readb(ap->ioaddr.feature_addr);
- if (errorStatus == 0x04 &&
- qc->tf.command == ATA_CMD_PIO_READ_EXT){
- printf("Hard Disk doesn't support LBA48\n");
- dev_state = SATA_ERROR;
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
- }
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- status = ata_busy_wait(ap, ATA_BUSY, 10);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- ata_pio_task(ap);
-
- if (!rc) {
- if (qc->flags & ATA_QCFLAG_ACTIVE) {
- qc->err_mask |= AC_ERR_TIMEOUT;
- ata_port_freeze(ap);
- }
- }
-
- if (qc->flags & ATA_QCFLAG_FAILED) {
- if (qc->result_tf.command & (ATA_ERR | ATA_DF))
- qc->err_mask |= AC_ERR_DEV;
-
- if (!qc->err_mask)
- qc->err_mask |= AC_ERR_OTHER;
-
- if (qc->err_mask & ~AC_ERR_OTHER)
- qc->err_mask &= ~AC_ERR_OTHER;
- }
-
- *tf = qc->result_tf;
- err_mask = qc->err_mask;
- ata_qc_free(qc);
- link->active_tag = preempted_tag;
- link->sactive = preempted_sactive;
- ap->qc_active = preempted_qc_active;
- ap->nr_active_links = preempted_nr_active_links;
-
- if (ap->flags & ATA_FLAG_DISABLED) {
- err_mask |= AC_ERR_SYSTEM;
- ap->flags &= ~ATA_FLAG_DISABLED;
- }
-
- return err_mask;
-}
-
-static void ata_qc_issue(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- struct ata_link *link = qc->dev->link;
- u8 prot = qc->tf.protocol;
-
- if (ata_is_ncq(prot)) {
- if (!link->sactive)
- ap->nr_active_links++;
- link->sactive |= 1 << qc->tag;
- } else {
- ap->nr_active_links++;
- link->active_tag = qc->tag;
- }
-
- qc->flags |= ATA_QCFLAG_ACTIVE;
- ap->qc_active |= 1 << qc->tag;
-
- if (qc->dev->flags & ATA_DFLAG_SLEEPING) {
- msleep(1);
- return;
- }
-
- qc->err_mask |= ata_qc_issue_prot(qc);
- if (qc->err_mask)
- goto err;
-
- return;
-err:
- ata_qc_complete(qc);
-}
-
-static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
-
- if (ap->flags & ATA_FLAG_PIO_POLLING) {
- switch (qc->tf.protocol) {
- case ATA_PROT_PIO:
- case ATA_PROT_NODATA:
- case ATAPI_PROT_PIO:
- case ATAPI_PROT_NODATA:
- qc->tf.flags |= ATA_TFLAG_POLLING;
- break;
- default:
- break;
- }
- }
-
- ata_dev_select(ap, qc->dev->devno, 1, 0);
-
- switch (qc->tf.protocol) {
- case ATA_PROT_PIO:
- if (qc->tf.flags & ATA_TFLAG_POLLING)
- qc->tf.ctl |= ATA_NIEN;
-
- ata_tf_to_host(ap, &qc->tf);
-
- ap->hsm_task_state = HSM_ST;
-
- if (qc->tf.flags & ATA_TFLAG_POLLING)
- ata_pio_queue_task(ap, qc, 0);
-
- break;
-
- default:
- return AC_ERR_SYSTEM;
- }
-
- return 0;
-}
-
-static void ata_tf_to_host(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- ata_tf_load(ap, tf);
- ata_exec_command(ap, tf);
-}
-
-static void ata_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
- unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
-
- if (tf->ctl != ap->last_ctl) {
- if (ioaddr->ctl_addr)
- writeb(tf->ctl, ioaddr->ctl_addr);
- ap->last_ctl = tf->ctl;
- ata_wait_idle(ap);
- }
-
- if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
- writeb(tf->hob_feature, ioaddr->feature_addr);
- writeb(tf->hob_nsect, ioaddr->nsect_addr);
- writeb(tf->hob_lbal, ioaddr->lbal_addr);
- writeb(tf->hob_lbam, ioaddr->lbam_addr);
- writeb(tf->hob_lbah, ioaddr->lbah_addr);
- }
-
- if (is_addr) {
- writeb(tf->feature, ioaddr->feature_addr);
- writeb(tf->nsect, ioaddr->nsect_addr);
- writeb(tf->lbal, ioaddr->lbal_addr);
- writeb(tf->lbam, ioaddr->lbam_addr);
- writeb(tf->lbah, ioaddr->lbah_addr);
- }
-
- if (tf->flags & ATA_TFLAG_DEVICE)
- writeb(tf->device, ioaddr->device_addr);
-
- ata_wait_idle(ap);
-}
-
-static void ata_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- writeb(tf->command, ap->ioaddr.command_addr);
-
- readb(ap->ioaddr.altstatus_addr);
-
- udelay(1);
-}
-
-static void ata_pio_queue_task(struct ata_port *ap,
- void *data,unsigned long delay)
-{
- ap->port_task_data = data;
-}
-
-static unsigned int ac_err_mask(u8 status)
-{
- if (status & (ATA_BUSY | ATA_DRQ))
- return AC_ERR_HSM;
- if (status & (ATA_ERR | ATA_DF))
- return AC_ERR_DEV;
- return 0;
-}
-
-static unsigned int __ac_err_mask(u8 status)
-{
- unsigned int mask = ac_err_mask(status);
- if (mask == 0)
- return AC_ERR_OTHER;
- return mask;
-}
-
-static void ata_pio_task(struct ata_port *arg_ap)
-{
- struct ata_port *ap = arg_ap;
- struct ata_queued_cmd *qc = ap->port_task_data;
- u8 status;
- int poll_next;
-
-fsm_start:
- /*
- * This is purely heuristic. This is a fast path.
- * Sometimes when we enter, BSY will be cleared in
- * a chk-status or two. If not, the drive is probably seeking
- * or something. Snooze for a couple msecs, then
- * chk-status again. If still busy, queue delayed work.
- */
- status = ata_busy_wait(ap, ATA_BUSY, 5);
- if (status & ATA_BUSY) {
- msleep(2);
- status = ata_busy_wait(ap, ATA_BUSY, 10);
- if (status & ATA_BUSY) {
- ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
- return;
- }
- }
-
- poll_next = ata_hsm_move(ap, qc, status, 1);
-
- /* another command or interrupt handler
- * may be running at this point.
- */
- if (poll_next)
- goto fsm_start;
-}
-
-static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
- u8 status, int in_wq)
-{
- int poll_next;
-
-fsm_start:
- switch (ap->hsm_task_state) {
- case HSM_ST_FIRST:
- poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
-
- if ((status & ATA_DRQ) == 0) {
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
- } else {
- qc->err_mask |= AC_ERR_HSM;
- }
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- /* Device should not ask for data transfer (DRQ=1)
- * when it finds something wrong.
- * We ignore DRQ here and stop the HSM by
- * changing hsm_task_state to HSM_ST_ERR and
- * let the EH abort the command or reset the device.
- */
- if (status & (ATA_ERR | ATA_DF)) {
- if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
- printf("DRQ=1 with device error, "
- "dev_stat 0x%X\n", status);
- qc->err_mask |= AC_ERR_HSM;
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
- }
-
- if (qc->tf.protocol == ATA_PROT_PIO) {
- /* PIO data out protocol.
- * send first data block.
- */
- /* ata_pio_sectors() might change the state
- * to HSM_ST_LAST. so, the state is changed here
- * before ata_pio_sectors().
- */
- ap->hsm_task_state = HSM_ST;
- ata_pio_sectors(qc);
- } else {
- printf("protocol is not ATA_PROT_PIO \n");
- }
- break;
-
- case HSM_ST:
- if ((status & ATA_DRQ) == 0) {
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
- } else {
- /* HSM violation. Let EH handle this.
- * Phantom devices also trigger this
- * condition. Mark hint.
- */
- qc->err_mask |= AC_ERR_HSM | AC_ERR_NODEV_HINT;
- }
-
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
- /* For PIO reads, some devices may ask for
- * data transfer (DRQ=1) alone with ERR=1.
- * We respect DRQ here and transfer one
- * block of junk data before changing the
- * hsm_task_state to HSM_ST_ERR.
- *
- * For PIO writes, ERR=1 DRQ=1 doesn't make
- * sense since the data block has been
- * transferred to the device.
- */
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
-
- if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
- ata_pio_sectors(qc);
- status = ata_wait_idle(ap);
- }
-
- if (status & (ATA_BUSY | ATA_DRQ))
- qc->err_mask |= AC_ERR_HSM;
-
- /* ata_pio_sectors() might change the
- * state to HSM_ST_LAST. so, the state
- * is changed after ata_pio_sectors().
- */
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- ata_pio_sectors(qc);
- if (ap->hsm_task_state == HSM_ST_LAST &&
- (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
- status = ata_wait_idle(ap);
- goto fsm_start;
- }
-
- poll_next = 1;
- break;
-
- case HSM_ST_LAST:
- if (!ata_ok(status)) {
- qc->err_mask |= __ac_err_mask(status);
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- ap->hsm_task_state = HSM_ST_IDLE;
-
- ata_hsm_qc_complete(qc, in_wq);
-
- poll_next = 0;
- break;
-
- case HSM_ST_ERR:
- /* make sure qc->err_mask is available to
- * know what's wrong and recover
- */
- ap->hsm_task_state = HSM_ST_IDLE;
-
- ata_hsm_qc_complete(qc, in_wq);
-
- poll_next = 0;
- break;
- default:
- poll_next = 0;
- }
-
- return poll_next;
-}
-
-static void ata_pio_sectors(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap;
- ap = pap;
- qc->pdata = ap->pdata;
-
- ata_pio_sector(qc);
-
- readb(qc->ap->ioaddr.altstatus_addr);
- udelay(1);
-}
-
-static void ata_pio_sector(struct ata_queued_cmd *qc)
-{
- int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
- struct ata_port *ap = qc->ap;
- unsigned int offset;
- unsigned char *buf;
- char temp_data_buf[512];
-
- if (qc->curbytes == qc->nbytes - qc->sect_size)
- ap->hsm_task_state = HSM_ST_LAST;
-
- offset = qc->curbytes;
-
- switch (qc->tf.command) {
- case ATA_CMD_ID_ATA:
- buf = (unsigned char *)&ata_device.id[0];
- break;
- case ATA_CMD_PIO_READ_EXT:
- case ATA_CMD_PIO_READ:
- case ATA_CMD_PIO_WRITE_EXT:
- case ATA_CMD_PIO_WRITE:
- buf = qc->pdata + offset;
- break;
- default:
- buf = (unsigned char *)&temp_data_buf[0];
- }
-
- ata_mmio_data_xfer(qc->dev, buf, qc->sect_size, do_write);
-
- qc->curbytes += qc->sect_size;
-
-}
-
-static void ata_mmio_data_xfer(struct ata_device *dev, unsigned char *buf,
- unsigned int buflen, int do_write)
-{
- struct ata_port *ap = pap;
- void __iomem *data_addr = ap->ioaddr.data_addr;
- unsigned int words = buflen >> 1;
- u16 *buf16 = (u16 *)buf;
- unsigned int i = 0;
-
- udelay(100);
- if (do_write) {
- for (i = 0; i < words; i++)
- writew(le16_to_cpu(buf16[i]), data_addr);
- } else {
- for (i = 0; i < words; i++)
- buf16[i] = cpu_to_le16(readw(data_addr));
- }
-
- if (buflen & 0x01) {
- __le16 align_buf[1] = { 0 };
- unsigned char *trailing_buf = buf + buflen - 1;
-
- if (do_write) {
- memcpy(align_buf, trailing_buf, 1);
- writew(le16_to_cpu(align_buf[0]), data_addr);
- } else {
- align_buf[0] = cpu_to_le16(readw(data_addr));
- memcpy(trailing_buf, align_buf, 1);
- }
- }
-}
-
-static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
-{
- struct ata_port *ap = qc->ap;
-
- if (in_wq) {
- /* EH might have kicked in while host lock is
- * released.
- */
- qc = &ap->qcmd[qc->tag];
- if (qc) {
- if (!(qc->err_mask & AC_ERR_HSM)) {
- ata_irq_on(ap);
- ata_qc_complete(qc);
- } else {
- ata_port_freeze(ap);
- }
- }
- } else {
- if (!(qc->err_mask & AC_ERR_HSM)) {
- ata_qc_complete(qc);
- } else {
- ata_port_freeze(ap);
- }
- }
-}
-
-static u8 ata_irq_on(struct ata_port *ap)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
- u8 tmp;
-
- ap->ctl &= ~ATA_NIEN;
- ap->last_ctl = ap->ctl;
-
- if (ioaddr->ctl_addr)
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- tmp = ata_wait_idle(ap);
-
- return tmp;
-}
-
-static unsigned int ata_tag_internal(unsigned int tag)
-{
- return tag == ATA_MAX_QUEUE - 1;
-}
-
-static void ata_qc_complete(struct ata_queued_cmd *qc)
-{
- struct ata_device *dev = qc->dev;
- if (qc->err_mask)
- qc->flags |= ATA_QCFLAG_FAILED;
-
- if (qc->flags & ATA_QCFLAG_FAILED) {
- if (!ata_tag_internal(qc->tag)) {
- fill_result_tf(qc);
- return;
- }
- }
- if (qc->flags & ATA_QCFLAG_RESULT_TF)
- fill_result_tf(qc);
-
- /* Some commands need post-processing after successful
- * completion.
- */
- switch (qc->tf.command) {
- case ATA_CMD_SET_FEATURES:
- if (qc->tf.feature != SETFEATURES_WC_ON &&
- qc->tf.feature != SETFEATURES_WC_OFF)
- break;
- case ATA_CMD_INIT_DEV_PARAMS:
- case ATA_CMD_SET_MULTI:
- break;
-
- case ATA_CMD_SLEEP:
- dev->flags |= ATA_DFLAG_SLEEPING;
- break;
- }
-
- __ata_qc_complete(qc);
-}
-
-static void fill_result_tf(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
-
- qc->result_tf.flags = qc->tf.flags;
- ata_tf_read(ap, &qc->result_tf);
-}
-
-static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
-
- tf->command = ata_check_status(ap);
- tf->feature = readb(ioaddr->error_addr);
- tf->nsect = readb(ioaddr->nsect_addr);
- tf->lbal = readb(ioaddr->lbal_addr);
- tf->lbam = readb(ioaddr->lbam_addr);
- tf->lbah = readb(ioaddr->lbah_addr);
- tf->device = readb(ioaddr->device_addr);
-
- if (tf->flags & ATA_TFLAG_LBA48) {
- if (ioaddr->ctl_addr) {
- writeb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
-
- tf->hob_feature = readb(ioaddr->error_addr);
- tf->hob_nsect = readb(ioaddr->nsect_addr);
- tf->hob_lbal = readb(ioaddr->lbal_addr);
- tf->hob_lbam = readb(ioaddr->lbam_addr);
- tf->hob_lbah = readb(ioaddr->lbah_addr);
-
- writeb(tf->ctl, ioaddr->ctl_addr);
- ap->last_ctl = tf->ctl;
- } else {
- printf("sata_dwc warnning register read.\n");
- }
- }
-}
-
-static void __ata_qc_complete(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- struct ata_link *link = qc->dev->link;
-
- link->active_tag = ATA_TAG_POISON;
- ap->nr_active_links--;
-
- if (qc->flags & ATA_QCFLAG_CLEAR_EXCL && ap->excl_link == link)
- ap->excl_link = NULL;
-
- qc->flags &= ~ATA_QCFLAG_ACTIVE;
- ap->qc_active &= ~(1 << qc->tag);
-}
-
-static void ata_qc_free(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- unsigned int tag;
- qc->flags = 0;
- tag = qc->tag;
- if (tag < ATA_MAX_QUEUE) {
- qc->tag = ATA_TAG_POISON;
- clear_bit(tag, &ap->qc_allocated);
- }
-}
-
-static int check_sata_dev_state(void)
-{
- unsigned long datalen;
- unsigned char *pdata;
- int ret = 0;
- int i = 0;
- char temp_data_buf[512];
-
- while (1) {
- udelay(10000);
-
- pdata = (unsigned char*)&temp_data_buf[0];
- datalen = 512;
-
- ret = ata_dev_read_sectors(pdata, datalen, 0, 1);
-
- if (ret == true)
- break;
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
- dev_state = SATA_NODEVICE;
- return false;
- }
-
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- dev_state = SATA_READY;
-
- return true;
-}
-
-static unsigned int ata_dev_set_feature(struct ata_device *dev,
- u8 enable, u8 feature)
-{
- struct ata_taskfile tf;
- struct ata_port *ap;
- ap = pap;
- unsigned int err_mask;
-
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
-
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_SET_FEATURES;
- tf.feature = enable;
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.protocol = ATA_PROT_NODATA;
- tf.nsect = feature;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
-
- return err_mask;
-}
-
-static unsigned int ata_dev_init_params(struct ata_device *dev,
- u16 heads, u16 sectors)
-{
- struct ata_taskfile tf;
- struct ata_port *ap;
- ap = pap;
- unsigned int err_mask;
-
- if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
- return AC_ERR_INVALID;
-
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_INIT_DEV_PARAMS;
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.protocol = ATA_PROT_NODATA;
- tf.nsect = sectors;
- tf.device |= (heads - 1) & 0x0f;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
-
- if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
- err_mask = 0;
-
- return err_mask;
-}
-
-#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
-#define SATA_MAX_READ_BLK 0xFF
-#else
-#define SATA_MAX_READ_BLK 0xFFFF
-#endif
-
-ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
- ulong start,blks, buf_addr;
- unsigned short smallblks;
- unsigned long datalen;
- unsigned char *pdata;
- device &= 0xff;
-
- u32 block = 0;
- u32 n_block = 0;
-
- if (dev_state != SATA_READY)
- return 0;
-
- buf_addr = (unsigned long)buffer;
- start = blknr;
- blks = blkcnt;
- do {
- pdata = (unsigned char *)buf_addr;
- if (blks > SATA_MAX_READ_BLK) {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
- smallblks = SATA_MAX_READ_BLK;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += SATA_MAX_READ_BLK;
- blks -= SATA_MAX_READ_BLK;
- } else {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
- datalen = sata_dev_desc[device].blksz * blks;
- smallblks = (unsigned short)blks;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += blks;
- blks = 0;
- }
-
- if (ata_dev_read_sectors(pdata, datalen, block, n_block) != true) {
- printf("sata_dwc : Hard disk read error.\n");
- blkcnt -= blks;
- break;
- }
- buf_addr += datalen;
- } while (blks != 0);
-
- return (blkcnt);
-}
-
-static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen,
- u32 block, u32 n_block)
-{
- struct ata_port *ap = pap;
- struct ata_device *dev = &ata_device;
- struct ata_taskfile tf;
- unsigned int class = ATA_DEV_ATA;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1;
-
- if (dev_state == SATA_ERROR)
- return false;
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
-
- ap->pdata = pdata;
-
- tf.device = ATA_DEVICE_OBS;
-
- temp_n_block = n_block;
-
-#ifdef CONFIG_LBA48
- tf.command = ATA_CMD_PIO_READ_EXT;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
-
- tf.hob_feature = 31;
- tf.feature = 31;
- tf.hob_nsect = (n_block >> 8) & 0xff;
- tf.nsect = n_block & 0xff;
-
- tf.hob_lbah = 0x0;
- tf.hob_lbam = 0x0;
- tf.hob_lbal = (block >> 24) & 0xff;
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-#else
- tf.command = ATA_CMD_PIO_READ;
- tf.flags |= ATA_TFLAG_LBA ;
-
- tf.feature = 31;
- tf.nsect = n_block & 0xff;
-
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = (block >> 24) & 0xf;
-
- tf.device |= 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-
-#endif
-
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.flags |= ATA_TFLAG_POLLING;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("READ_SECTORS NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
-
- reason = "I/O error";
- goto err_out;
- }
-
- return true;
-
-err_out:
- printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
- return false;
-}
-
-#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
-#define SATA_MAX_WRITE_BLK 0xFF
-#else
-#define SATA_MAX_WRITE_BLK 0xFFFF
-#endif
-
-ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
-{
- ulong start,blks, buf_addr;
- unsigned short smallblks;
- unsigned long datalen;
- unsigned char *pdata;
- device &= 0xff;
-
-
- u32 block = 0;
- u32 n_block = 0;
-
- if (dev_state != SATA_READY)
- return 0;
-
- buf_addr = (unsigned long)buffer;
- start = blknr;
- blks = blkcnt;
- do {
- pdata = (unsigned char *)buf_addr;
- if (blks > SATA_MAX_WRITE_BLK) {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_WRITE_BLK;
- smallblks = SATA_MAX_WRITE_BLK;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += SATA_MAX_WRITE_BLK;
- blks -= SATA_MAX_WRITE_BLK;
- } else {
- datalen = sata_dev_desc[device].blksz * blks;
- smallblks = (unsigned short)blks;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += blks;
- blks = 0;
- }
-
- if (ata_dev_write_sectors(pdata, datalen, block, n_block) != true) {
- printf("sata_dwc : Hard disk read error.\n");
- blkcnt -= blks;
- break;
- }
- buf_addr += datalen;
- } while (blks != 0);
-
- return (blkcnt);
-}
-
-static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen,
- u32 block, u32 n_block)
-{
- struct ata_port *ap = pap;
- struct ata_device *dev = &ata_device;
- struct ata_taskfile tf;
- unsigned int class = ATA_DEV_ATA;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1;
-
- if (dev_state == SATA_ERROR)
- return false;
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
-
- ap->pdata = pdata;
-
- tf.device = ATA_DEVICE_OBS;
-
- temp_n_block = n_block;
-
-
-#ifdef CONFIG_LBA48
- tf.command = ATA_CMD_PIO_WRITE_EXT;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48 | ATA_TFLAG_WRITE;
-
- tf.hob_feature = 31;
- tf.feature = 31;
- tf.hob_nsect = (n_block >> 8) & 0xff;
- tf.nsect = n_block & 0xff;
-
- tf.hob_lbah = 0x0;
- tf.hob_lbam = 0x0;
- tf.hob_lbal = (block >> 24) & 0xff;
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-#else
- tf.command = ATA_CMD_PIO_WRITE;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_WRITE;
-
- tf.feature = 31;
- tf.nsect = n_block & 0xff;
-
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = (block >> 24) & 0xf;
-
- tf.device |= 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-
-#endif
-
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.flags |= ATA_TFLAG_POLLING;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("READ_SECTORS NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
-
- reason = "I/O error";
- goto err_out;
- }
-
- return true;
-
-err_out:
- printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
- return false;
-}
+++ /dev/null
-/*
- * sata_dwc.h
- *
- * Synopsys DesignWare Cores (DWC) SATA host driver
- *
- * Author: Mark Miesfeld <mmiesfeld@amcc.com>
- *
- * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
- * Copyright 2008 DENX Software Engineering
- *
- * Based on versions provided by AMCC and Synopsys which are:
- * Copyright 2006 Applied Micro Circuits Corporation
- * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * SATA support based on the chip canyonlands.
- *
- * 04-17-2009
- * The local version of this driver for the canyonlands board
- * does not use interrupts but polls the chip instead.
- */
-
-
-#ifndef _SATA_DWC_H_
-#define _SATA_DWC_H_
-
-#define __U_BOOT__
-
-#define HZ 100
-#define READ 0
-#define WRITE 1
-
-enum {
- ATA_READID_POSTRESET = (1 << 0),
-
- ATA_DNXFER_PIO = 0,
- ATA_DNXFER_DMA = 1,
- ATA_DNXFER_40C = 2,
- ATA_DNXFER_FORCE_PIO = 3,
- ATA_DNXFER_FORCE_PIO0 = 4,
-
- ATA_DNXFER_QUIET = (1 << 31),
-};
-
-enum hsm_task_states {
- HSM_ST_IDLE,
- HSM_ST_FIRST,
- HSM_ST,
- HSM_ST_LAST,
- HSM_ST_ERR,
-};
-
-#define ATA_SHORT_PAUSE ((HZ >> 6) + 1)
-
-struct ata_queued_cmd {
- struct ata_port *ap;
- struct ata_device *dev;
-
- struct ata_taskfile tf;
- u8 cdb[ATAPI_CDB_LEN];
- unsigned long flags;
- unsigned int tag;
- unsigned int n_elem;
-
- int dma_dir;
- unsigned int sect_size;
-
- unsigned int nbytes;
- unsigned int extrabytes;
- unsigned int curbytes;
-
- unsigned int err_mask;
- struct ata_taskfile result_tf;
-
- void *private_data;
-#ifndef __U_BOOT__
- void *lldd_task;
-#endif
- unsigned char *pdata;
-};
-
-typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc);
-
-#define ATA_TAG_POISON 0xfafbfcfdU
-
-enum {
- LIBATA_MAX_PRD = ATA_MAX_PRD / 2,
- LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4,
- ATA_MAX_PORTS = 8,
- ATA_DEF_QUEUE = 1,
- ATA_MAX_QUEUE = 32,
- ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1,
- ATA_MAX_BUS = 2,
- ATA_DEF_BUSY_WAIT = 10000,
-
- ATAPI_MAX_DRAIN = 16 << 10,
-
- ATA_SHT_EMULATED = 1,
- ATA_SHT_CMD_PER_LUN = 1,
- ATA_SHT_THIS_ID = -1,
- ATA_SHT_USE_CLUSTERING = 1,
-
- ATA_DFLAG_LBA = (1 << 0),
- ATA_DFLAG_LBA48 = (1 << 1),
- ATA_DFLAG_CDB_INTR = (1 << 2),
- ATA_DFLAG_NCQ = (1 << 3),
- ATA_DFLAG_FLUSH_EXT = (1 << 4),
- ATA_DFLAG_ACPI_PENDING = (1 << 5),
- ATA_DFLAG_ACPI_FAILED = (1 << 6),
- ATA_DFLAG_AN = (1 << 7),
- ATA_DFLAG_HIPM = (1 << 8),
- ATA_DFLAG_DIPM = (1 << 9),
- ATA_DFLAG_DMADIR = (1 << 10),
- ATA_DFLAG_CFG_MASK = (1 << 12) - 1,
-
- ATA_DFLAG_PIO = (1 << 12),
- ATA_DFLAG_NCQ_OFF = (1 << 13),
- ATA_DFLAG_SPUNDOWN = (1 << 14),
- ATA_DFLAG_SLEEPING = (1 << 15),
- ATA_DFLAG_DUBIOUS_XFER = (1 << 16),
- ATA_DFLAG_INIT_MASK = (1 << 24) - 1,
-
- ATA_DFLAG_DETACH = (1 << 24),
- ATA_DFLAG_DETACHED = (1 << 25),
-
- ATA_LFLAG_HRST_TO_RESUME = (1 << 0),
- ATA_LFLAG_SKIP_D2H_BSY = (1 << 1),
- ATA_LFLAG_NO_SRST = (1 << 2),
- ATA_LFLAG_ASSUME_ATA = (1 << 3),
- ATA_LFLAG_ASSUME_SEMB = (1 << 4),
- ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB,
- ATA_LFLAG_NO_RETRY = (1 << 5),
- ATA_LFLAG_DISABLED = (1 << 6),
-
- ATA_FLAG_SLAVE_POSS = (1 << 0),
- ATA_FLAG_SATA = (1 << 1),
- ATA_FLAG_NO_LEGACY = (1 << 2),
- ATA_FLAG_MMIO = (1 << 3),
- ATA_FLAG_SRST = (1 << 4),
- ATA_FLAG_SATA_RESET = (1 << 5),
- ATA_FLAG_NO_ATAPI = (1 << 6),
- ATA_FLAG_PIO_DMA = (1 << 7),
- ATA_FLAG_PIO_LBA48 = (1 << 8),
- ATA_FLAG_PIO_POLLING = (1 << 9),
- ATA_FLAG_NCQ = (1 << 10),
- ATA_FLAG_DEBUGMSG = (1 << 13),
- ATA_FLAG_IGN_SIMPLEX = (1 << 15),
- ATA_FLAG_NO_IORDY = (1 << 16),
- ATA_FLAG_ACPI_SATA = (1 << 17),
- ATA_FLAG_AN = (1 << 18),
- ATA_FLAG_PMP = (1 << 19),
- ATA_FLAG_IPM = (1 << 20),
-
- ATA_FLAG_DISABLED = (1 << 23),
-
- ATA_PFLAG_EH_PENDING = (1 << 0),
- ATA_PFLAG_EH_IN_PROGRESS = (1 << 1),
- ATA_PFLAG_FROZEN = (1 << 2),
- ATA_PFLAG_RECOVERED = (1 << 3),
- ATA_PFLAG_LOADING = (1 << 4),
- ATA_PFLAG_UNLOADING = (1 << 5),
- ATA_PFLAG_SCSI_HOTPLUG = (1 << 6),
- ATA_PFLAG_INITIALIZING = (1 << 7),
- ATA_PFLAG_RESETTING = (1 << 8),
- ATA_PFLAG_SUSPENDED = (1 << 17),
- ATA_PFLAG_PM_PENDING = (1 << 18),
-
- ATA_QCFLAG_ACTIVE = (1 << 0),
- ATA_QCFLAG_DMAMAP = (1 << 1),
- ATA_QCFLAG_IO = (1 << 3),
- ATA_QCFLAG_RESULT_TF = (1 << 4),
- ATA_QCFLAG_CLEAR_EXCL = (1 << 5),
- ATA_QCFLAG_QUIET = (1 << 6),
-
- ATA_QCFLAG_FAILED = (1 << 16),
- ATA_QCFLAG_SENSE_VALID = (1 << 17),
- ATA_QCFLAG_EH_SCHEDULED = (1 << 18),
-
- ATA_HOST_SIMPLEX = (1 << 0),
- ATA_HOST_STARTED = (1 << 1),
-
- ATA_TMOUT_BOOT = 30 * 100,
- ATA_TMOUT_BOOT_QUICK = 7 * 100,
- ATA_TMOUT_INTERNAL = 30 * 100,
- ATA_TMOUT_INTERNAL_QUICK = 5 * 100,
-
- /* FIXME: GoVault needs 2s but we can't afford that without
- * parallel probing. 800ms is enough for iVDR disk
- * HHD424020F7SV00. Increase to 2secs when parallel probing
- * is in place.
- */
- ATA_TMOUT_FF_WAIT = 4 * 100 / 5,
-
- BUS_UNKNOWN = 0,
- BUS_DMA = 1,
- BUS_IDLE = 2,
- BUS_NOINTR = 3,
- BUS_NODATA = 4,
- BUS_TIMER = 5,
- BUS_PIO = 6,
- BUS_EDD = 7,
- BUS_IDENTIFY = 8,
- BUS_PACKET = 9,
-
- PORT_UNKNOWN = 0,
- PORT_ENABLED = 1,
- PORT_DISABLED = 2,
-
- /* encoding various smaller bitmaps into a single
- * unsigned long bitmap
- */
- ATA_NR_PIO_MODES = 7,
- ATA_NR_MWDMA_MODES = 5,
- ATA_NR_UDMA_MODES = 8,
-
- ATA_SHIFT_PIO = 0,
- ATA_SHIFT_MWDMA = ATA_SHIFT_PIO + ATA_NR_PIO_MODES,
- ATA_SHIFT_UDMA = ATA_SHIFT_MWDMA + ATA_NR_MWDMA_MODES,
-
- ATA_DMA_PAD_SZ = 4,
-
- ATA_ERING_SIZE = 32,
-
- ATA_DEFER_LINK = 1,
- ATA_DEFER_PORT = 2,
-
- ATA_EH_DESC_LEN = 80,
-
- ATA_EH_REVALIDATE = (1 << 0),
- ATA_EH_SOFTRESET = (1 << 1),
- ATA_EH_HARDRESET = (1 << 2),
- ATA_EH_ENABLE_LINK = (1 << 3),
- ATA_EH_LPM = (1 << 4),
-
- ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET,
- ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE,
-
- ATA_EHI_HOTPLUGGED = (1 << 0),
- ATA_EHI_RESUME_LINK = (1 << 1),
- ATA_EHI_NO_AUTOPSY = (1 << 2),
- ATA_EHI_QUIET = (1 << 3),
-
- ATA_EHI_DID_SOFTRESET = (1 << 16),
- ATA_EHI_DID_HARDRESET = (1 << 17),
- ATA_EHI_PRINTINFO = (1 << 18),
- ATA_EHI_SETMODE = (1 << 19),
- ATA_EHI_POST_SETMODE = (1 << 20),
-
- ATA_EHI_DID_RESET = ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET,
- ATA_EHI_RESET_MODIFIER_MASK = ATA_EHI_RESUME_LINK,
-
- ATA_EH_MAX_TRIES = 5,
-
- ATA_PROBE_MAX_TRIES = 3,
- ATA_EH_DEV_TRIES = 3,
- ATA_EH_PMP_TRIES = 5,
- ATA_EH_PMP_LINK_TRIES = 3,
-
- SATA_PMP_SCR_TIMEOUT = 250,
-
- /* Horkage types. May be set by libata or controller on drives
- (some horkage may be drive/controller pair dependant */
-
- ATA_HORKAGE_DIAGNOSTIC = (1 << 0),
- ATA_HORKAGE_NODMA = (1 << 1),
- ATA_HORKAGE_NONCQ = (1 << 2),
- ATA_HORKAGE_MAX_SEC_128 = (1 << 3),
- ATA_HORKAGE_BROKEN_HPA = (1 << 4),
- ATA_HORKAGE_SKIP_PM = (1 << 5),
- ATA_HORKAGE_HPA_SIZE = (1 << 6),
- ATA_HORKAGE_IPM = (1 << 7),
- ATA_HORKAGE_IVB = (1 << 8),
- ATA_HORKAGE_STUCK_ERR = (1 << 9),
-
- ATA_DMA_MASK_ATA = (1 << 0),
- ATA_DMA_MASK_ATAPI = (1 << 1),
- ATA_DMA_MASK_CFA = (1 << 2),
-
- ATAPI_READ = 0,
- ATAPI_WRITE = 1,
- ATAPI_READ_CD = 2,
- ATAPI_PASS_THRU = 3,
- ATAPI_MISC = 4,
-};
-
-enum ata_completion_errors {
- AC_ERR_DEV = (1 << 0),
- AC_ERR_HSM = (1 << 1),
- AC_ERR_TIMEOUT = (1 << 2),
- AC_ERR_MEDIA = (1 << 3),
- AC_ERR_ATA_BUS = (1 << 4),
- AC_ERR_HOST_BUS = (1 << 5),
- AC_ERR_SYSTEM = (1 << 6),
- AC_ERR_INVALID = (1 << 7),
- AC_ERR_OTHER = (1 << 8),
- AC_ERR_NODEV_HINT = (1 << 9),
- AC_ERR_NCQ = (1 << 10),
-};
-
-enum ata_xfer_mask {
- ATA_MASK_PIO = ((1LU << ATA_NR_PIO_MODES) - 1) << ATA_SHIFT_PIO,
- ATA_MASK_MWDMA = ((1LU << ATA_NR_MWDMA_MODES) - 1) << ATA_SHIFT_MWDMA,
- ATA_MASK_UDMA = ((1LU << ATA_NR_UDMA_MODES) - 1) << ATA_SHIFT_UDMA,
-};
-
-struct ata_port_info {
-#ifndef __U_BOOT__
- struct scsi_host_template *sht;
-#endif
- unsigned long flags;
- unsigned long link_flags;
- unsigned long pio_mask;
- unsigned long mwdma_mask;
- unsigned long udma_mask;
-#ifndef __U_BOOT__
- const struct ata_port_operations *port_ops;
- void *private_data;
-#endif
-};
-
-struct ata_ioports {
- void __iomem *cmd_addr;
- void __iomem *data_addr;
- void __iomem *error_addr;
- void __iomem *feature_addr;
- void __iomem *nsect_addr;
- void __iomem *lbal_addr;
- void __iomem *lbam_addr;
- void __iomem *lbah_addr;
- void __iomem *device_addr;
- void __iomem *status_addr;
- void __iomem *command_addr;
- void __iomem *altstatus_addr;
- void __iomem *ctl_addr;
-#ifndef __U_BOOT__
- void __iomem *bmdma_addr;
-#endif
- void __iomem *scr_addr;
-};
-
-struct ata_host {
-#ifndef __U_BOOT__
- void __iomem * const *iomap;
- void *private_data;
- const struct ata_port_operations *ops;
- unsigned long flags;
- struct ata_port *simplex_claimed;
-#endif
- unsigned int n_ports;
- struct ata_port *ports[0];
-};
-
-#ifndef __U_BOOT__
-struct ata_port_stats {
- unsigned long unhandled_irq;
- unsigned long idle_irq;
- unsigned long rw_reqbuf;
-};
-#endif
-
-struct ata_device {
- struct ata_link *link;
- unsigned int devno;
- unsigned long flags;
- unsigned int horkage;
-#ifndef __U_BOOT__
- struct scsi_device *sdev;
-#ifdef CONFIG_ATA_ACPI
- acpi_handle acpi_handle;
- union acpi_object *gtf_cache;
-#endif
-#endif
- u64 n_sectors;
- unsigned int class;
-
- union {
- u16 id[ATA_ID_WORDS];
- u32 gscr[SATA_PMP_GSCR_DWORDS];
- };
-#ifndef __U_BOOT__
- u8 pio_mode;
- u8 dma_mode;
- u8 xfer_mode;
- unsigned int xfer_shift;
-#endif
- unsigned int multi_count;
- unsigned int max_sectors;
- unsigned int cdb_len;
-#ifndef __U_BOOT__
- unsigned long pio_mask;
- unsigned long mwdma_mask;
-#endif
- unsigned long udma_mask;
- u16 cylinders;
- u16 heads;
- u16 sectors;
-#ifndef __U_BOOT__
- int spdn_cnt;
-#endif
-};
-
-struct ata_link {
- struct ata_port *ap;
- int pmp;
- unsigned int active_tag;
- u32 sactive;
- unsigned int flags;
- unsigned int hw_sata_spd_limit;
-#ifndef __U_BOOT__
- unsigned int sata_spd_limit;
- unsigned int sata_spd;
- struct ata_device device[2];
-#endif
-};
-
-struct ata_port {
- unsigned long flags;
- unsigned int pflags;
- unsigned int print_id;
- unsigned int port_no;
-
- struct ata_ioports ioaddr;
-
- u8 ctl;
- u8 last_ctl;
- unsigned int pio_mask;
- unsigned int mwdma_mask;
- unsigned int udma_mask;
- unsigned int cbl;
-
- struct ata_queued_cmd qcmd[ATA_MAX_QUEUE];
- unsigned long qc_allocated;
- unsigned int qc_active;
- int nr_active_links;
-
- struct ata_link link;
-#ifndef __U_BOOT__
- int nr_pmp_links;
- struct ata_link *pmp_link;
-#endif
- struct ata_link *excl_link;
- int nr_pmp_links;
-#ifndef __U_BOOT__
- struct ata_port_stats stats;
- struct device *dev;
- u32 msg_enable;
-#endif
- struct ata_host *host;
- void *port_task_data;
-
- unsigned int hsm_task_state;
- void *private_data;
- unsigned char *pdata;
-};
-
-#endif
This clock driver adds support for RCC clock management
for STM32F4 and STM32F7 SoCs.
+config CLK_HSDK
+ bool "Enable cgu clock driver for HSDK"
+ depends on CLK
+ help
+ Enable this to support the cgu clocks on Synopsys ARC HSDK
+
config CLK_ZYNQ
bool "Enable clock driver support for Zynq"
depends on CLK && ARCH_ZYNQ
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
+obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
--- /dev/null
+/*
+ * Synopsys HSDK SDP CGU clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <linux/io.h>
+
+/*
+ * Synopsys ARC HSDK clock tree.
+ *
+ * ------------------
+ * | 33.33 MHz xtal |
+ * ------------------
+ * |
+ * | -----------
+ * |-->| ARC PLL |
+ * | -----------
+ * | |
+ * | |-->|CGU_ARC_IDIV|----------->
+ * | |-->|CREG_CORE_IF_DIV|------->
+ * |
+ * | --------------
+ * |-->| SYSTEM PLL |
+ * | --------------
+ * | |
+ * | |-->|CGU_SYS_IDIV_APB|------->
+ * | |-->|CGU_SYS_IDIV_AXI|------->
+ * | |-->|CGU_SYS_IDIV_*|--------->
+ * | |-->|CGU_SYS_IDIV_EBI_REF|--->
+ * |
+ * | --------------
+ * |-->| TUNNEL PLL |
+ * | --------------
+ * | |
+ * | |-->|CGU_TUN_IDIV|----------->
+ * |
+ * | ------------
+ * |-->| HDMI PLL |
+ * | ------------
+ * | |
+ * | |-->|CGU_HDMI_IDIV_APB|------>
+ * |
+ * | -----------
+ * |-->| DDR PLL |
+ * -----------
+ * |
+ * |---------------------------->
+ */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CGU_ARC_IDIV 0x080
+#define CGU_TUN_IDIV 0x380
+#define CGU_HDMI_IDIV_APB 0x480
+#define CGU_SYS_IDIV_APB 0x180
+#define CGU_SYS_IDIV_AXI 0x190
+#define CGU_SYS_IDIV_ETH 0x1A0
+#define CGU_SYS_IDIV_USB 0x1B0
+#define CGU_SYS_IDIV_SDIO 0x1C0
+#define CGU_SYS_IDIV_HDMI 0x1D0
+#define CGU_SYS_IDIV_GFX_CORE 0x1E0
+#define CGU_SYS_IDIV_GFX_DMA 0x1F0
+#define CGU_SYS_IDIV_GFX_CFG 0x200
+#define CGU_SYS_IDIV_DMAC_CORE 0x210
+#define CGU_SYS_IDIV_DMAC_CFG 0x220
+#define CGU_SYS_IDIV_SDIO_REF 0x230
+#define CGU_SYS_IDIV_SPI_REF 0x240
+#define CGU_SYS_IDIV_I2C_REF 0x250
+#define CGU_SYS_IDIV_UART_REF 0x260
+#define CGU_SYS_IDIV_EBI_REF 0x270
+
+#define CGU_IDIV_MASK 0xFF /* All idiv have 8 significant bits */
+
+#define CGU_ARC_PLL 0x0
+#define CGU_SYS_PLL 0x10
+#define CGU_DDR_PLL 0x20
+#define CGU_TUN_PLL 0x30
+#define CGU_HDMI_PLL 0x40
+
+#define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
+#define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
+#define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
+#define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
+
+#define CGU_PLL_CTRL_ODIV_SHIFT 2
+#define CGU_PLL_CTRL_IDIV_SHIFT 4
+#define CGU_PLL_CTRL_FBDIV_SHIFT 9
+#define CGU_PLL_CTRL_BAND_SHIFT 20
+
+#define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
+#define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
+#define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
+
+#define CGU_PLL_CTRL_PD BIT(0)
+#define CGU_PLL_CTRL_BYPASS BIT(1)
+
+#define CGU_PLL_STATUS_LOCK BIT(0)
+#define CGU_PLL_STATUS_ERR BIT(1)
+
+#define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
+
+#define CREG_CORE_IF_DIV 0x000 /* ARC CORE interface divider */
+#define CORE_IF_CLK_THRESHOLD_HZ 500000000
+#define CREG_CORE_IF_CLK_DIV_1 0x0
+#define CREG_CORE_IF_CLK_DIV_2 0x1
+
+#define PARENT_RATE 33333333 /* fixed clock - xtal */
+#define CGU_MAX_CLOCKS 24
+
+struct hsdk_pll_cfg {
+ u32 rate;
+ u32 idiv;
+ u32 fbdiv;
+ u32 odiv;
+ u32 band;
+};
+
+static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
+ { 100000000, 0, 11, 3, 0 },
+ { 125000000, 0, 14, 3, 0 },
+ { 133000000, 0, 15, 3, 0 },
+ { 150000000, 0, 17, 3, 0 },
+ { 200000000, 1, 47, 3, 0 },
+ { 233000000, 1, 27, 2, 0 },
+ { 300000000, 1, 35, 2, 0 },
+ { 333000000, 1, 39, 2, 0 },
+ { 400000000, 1, 47, 2, 0 },
+ { 500000000, 0, 14, 1, 0 },
+ { 600000000, 0, 17, 1, 0 },
+ { 700000000, 0, 20, 1, 0 },
+ { 800000000, 0, 23, 1, 0 },
+ { 900000000, 1, 26, 0, 0 },
+ { 1000000000, 1, 29, 0, 0 },
+ { 1100000000, 1, 32, 0, 0 },
+ { 1200000000, 1, 35, 0, 0 },
+ { 1300000000, 1, 38, 0, 0 },
+ { 1400000000, 1, 41, 0, 0 },
+ { 1500000000, 1, 44, 0, 0 },
+ { 1600000000, 1, 47, 0, 0 },
+ {}
+};
+
+static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
+ { 297000000, 0, 21, 2, 0 },
+ { 540000000, 0, 19, 1, 0 },
+ { 594000000, 0, 21, 1, 0 },
+ {}
+};
+
+struct hsdk_cgu_clk {
+ /* CGU block register */
+ void __iomem *cgu_regs;
+ /* CREG block register */
+ void __iomem *creg_regs;
+
+ /* PLLs registers */
+ void __iomem *regs;
+ /* PLLs special registers */
+ void __iomem *spec_regs;
+ /* PLLs devdata */
+ const struct hsdk_pll_devdata *pll_devdata;
+
+ /* Dividers registers */
+ void __iomem *idiv_regs;
+};
+
+struct hsdk_pll_devdata {
+ const struct hsdk_pll_cfg *pll_cfg;
+ int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
+ const struct hsdk_pll_cfg *cfg);
+};
+
+static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
+ const struct hsdk_pll_cfg *);
+static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
+ const struct hsdk_pll_cfg *);
+
+static const struct hsdk_pll_devdata core_pll_dat = {
+ .pll_cfg = asdt_pll_cfg,
+ .update_rate = hsdk_pll_core_update_rate,
+};
+
+static const struct hsdk_pll_devdata sdt_pll_dat = {
+ .pll_cfg = asdt_pll_cfg,
+ .update_rate = hsdk_pll_comm_update_rate,
+};
+
+static const struct hsdk_pll_devdata hdmi_pll_dat = {
+ .pll_cfg = hdmi_pll_cfg,
+ .update_rate = hsdk_pll_comm_update_rate,
+};
+
+static ulong idiv_set(struct clk *, ulong);
+static ulong idiv_get(struct clk *);
+static int idiv_off(struct clk *);
+static ulong pll_set(struct clk *, ulong);
+static ulong pll_get(struct clk *);
+
+struct hsdk_cgu_clock_map {
+ u32 cgu_pll_oft;
+ u32 creg_div_oft;
+ u32 cgu_div_oft;
+ const struct hsdk_pll_devdata *pll_devdata;
+ ulong (*get_rate)(struct clk *clk);
+ ulong (*set_rate)(struct clk *clk, ulong rate);
+ int (*disable)(struct clk *clk);
+};
+
+static const struct hsdk_cgu_clock_map clock_map[] = {
+ { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
+ { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
+ { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
+ { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
+ { CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
+};
+
+static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
+{
+ iowrite32(val, clk->idiv_regs);
+}
+
+static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
+{
+ return ioread32(clk->idiv_regs);
+}
+
+static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
+{
+ iowrite32(val, clk->regs + reg);
+}
+
+static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
+{
+ return ioread32(clk->regs + reg);
+}
+
+static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
+{
+ iowrite32(val, clk->spec_regs + reg);
+}
+
+static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
+{
+ return ioread32(clk->spec_regs + reg);
+}
+
+static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
+ const struct hsdk_pll_cfg *cfg)
+{
+ u32 val = 0;
+
+ /* Powerdown and Bypass bits should be cleared */
+ val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
+ val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
+ val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
+ val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
+
+ pr_debug("write configurarion: %#x\n", val);
+
+ hsdk_pll_write(clk, CGU_PLL_CTRL, val);
+}
+
+static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
+{
+ return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
+}
+
+static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
+{
+ return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
+}
+
+static ulong pll_get(struct clk *sclk)
+{
+ u32 val;
+ u64 rate;
+ u32 idiv, fbdiv, odiv;
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
+ val = hsdk_pll_read(clk, CGU_PLL_CTRL);
+
+ pr_debug("current configurarion: %#x\n", val);
+
+ /* Check if PLL is disabled */
+ if (val & CGU_PLL_CTRL_PD)
+ return 0;
+
+ /* Check if PLL is bypassed */
+ if (val & CGU_PLL_CTRL_BYPASS)
+ return PARENT_RATE;
+
+ /* input divider = reg.idiv + 1 */
+ idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
+ /* fb divider = 2*(reg.fbdiv + 1) */
+ fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
+ /* output divider = 2^(reg.odiv) */
+ odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
+
+ rate = (u64)PARENT_RATE * fbdiv;
+ do_div(rate, idiv * odiv);
+
+ return rate;
+}
+
+static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
+{
+ int i;
+ unsigned long best_rate;
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
+
+ if (pll_cfg[0].rate == 0)
+ return -EINVAL;
+
+ best_rate = pll_cfg[0].rate;
+
+ for (i = 1; pll_cfg[i].rate != 0; i++) {
+ if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
+ best_rate = pll_cfg[i].rate;
+ }
+
+ pr_debug("chosen best rate: %lu\n", best_rate);
+
+ return best_rate;
+}
+
+static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
+ unsigned long rate,
+ const struct hsdk_pll_cfg *cfg)
+{
+ hsdk_pll_set_cfg(clk, cfg);
+
+ /*
+ * Wait until CGU relocks and check error status.
+ * If after timeout CGU is unlocked yet return error.
+ */
+ udelay(HSDK_PLL_MAX_LOCK_TIME);
+ if (!hsdk_pll_is_locked(clk))
+ return -ETIMEDOUT;
+
+ if (hsdk_pll_is_err(clk))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
+ unsigned long rate,
+ const struct hsdk_pll_cfg *cfg)
+{
+ /*
+ * When core clock exceeds 500MHz, the divider for the interface
+ * clock must be programmed to div-by-2.
+ */
+ if (rate > CORE_IF_CLK_THRESHOLD_HZ)
+ hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
+
+ hsdk_pll_set_cfg(clk, cfg);
+
+ /*
+ * Wait until CGU relocks and check error status.
+ * If after timeout CGU is unlocked yet return error.
+ */
+ udelay(HSDK_PLL_MAX_LOCK_TIME);
+ if (!hsdk_pll_is_locked(clk))
+ return -ETIMEDOUT;
+
+ if (hsdk_pll_is_err(clk))
+ return -EINVAL;
+
+ /*
+ * Program divider to div-by-1 if we succesfuly set core clock below
+ * 500MHz threshold.
+ */
+ if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
+ hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
+
+ return 0;
+}
+
+static ulong pll_set(struct clk *sclk, ulong rate)
+{
+ int i;
+ unsigned long best_rate;
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
+
+ best_rate = hsdk_pll_round_rate(sclk, rate);
+
+ for (i = 0; pll_cfg[i].rate != 0; i++) {
+ if (pll_cfg[i].rate == best_rate) {
+ return clk->pll_devdata->update_rate(clk, best_rate,
+ &pll_cfg[i]);
+ }
+ }
+
+ pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
+
+ return -EINVAL;
+}
+
+static int idiv_off(struct clk *sclk)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
+ hsdk_idiv_write(clk, 0);
+
+ return 0;
+}
+
+static ulong idiv_get(struct clk *sclk)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong parent_rate = pll_get(sclk);
+ u32 div_factor = hsdk_idiv_read(clk);
+
+ div_factor &= CGU_IDIV_MASK;
+
+ pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
+
+ if (div_factor == 0)
+ return 0;
+
+ return parent_rate / div_factor;
+}
+
+static ulong idiv_set(struct clk *sclk, ulong rate)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ ulong parent_rate = pll_get(sclk);
+ u32 div_factor;
+
+ div_factor = parent_rate / rate;
+ if (abs(rate - parent_rate / (div_factor + 1)) <=
+ abs(rate - parent_rate / div_factor)) {
+ div_factor += 1;
+ }
+
+ if (div_factor & ~CGU_IDIV_MASK) {
+ pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
+ rate, parent_rate, div_factor, CGU_IDIV_MASK);
+
+ div_factor = CGU_IDIV_MASK;
+ }
+
+ if (div_factor == 0) {
+ pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
+ rate, parent_rate, div_factor);
+
+ div_factor = 1;
+ }
+
+ hsdk_idiv_write(clk, div_factor);
+
+ return 0;
+}
+
+static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
+{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
+ if (sclk->id >= CGU_MAX_CLOCKS)
+ return -EINVAL;
+
+ clk->pll_devdata = clock_map[sclk->id].pll_devdata;
+ clk->regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
+ clk->spec_regs = clk->creg_regs + clock_map[sclk->id].creg_div_oft;
+ clk->idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
+
+ return 0;
+}
+
+static ulong hsdk_cgu_get_rate(struct clk *sclk)
+{
+ if (hsdk_prepare_clock_tree_branch(sclk))
+ return -EINVAL;
+
+ return clock_map[sclk->id].get_rate(sclk);
+}
+
+static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
+{
+ if (hsdk_prepare_clock_tree_branch(sclk))
+ return -EINVAL;
+
+ return clock_map[sclk->id].set_rate(sclk, rate);
+}
+
+static int hsdk_cgu_disable(struct clk *sclk)
+{
+ if (hsdk_prepare_clock_tree_branch(sclk))
+ return -EINVAL;
+
+ if (clock_map[sclk->id].disable)
+ return clock_map[sclk->id].disable(sclk);
+
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops hsdk_cgu_ops = {
+ .set_rate = hsdk_cgu_set_rate,
+ .get_rate = hsdk_cgu_get_rate,
+ .disable = hsdk_cgu_disable,
+};
+
+static int hsdk_cgu_clk_probe(struct udevice *dev)
+{
+ struct hsdk_cgu_clk *pll_clk = dev_get_priv(dev);
+
+ BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
+
+ pll_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
+ if (!pll_clk->cgu_regs)
+ return -EINVAL;
+
+ pll_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
+ if (!pll_clk->creg_regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id hsdk_cgu_clk_id[] = {
+ { .compatible = "snps,hsdk-cgu-clock" },
+ { }
+};
+
+U_BOOT_DRIVER(hsdk_cgu_clk) = {
+ .name = "hsdk-cgu-clk",
+ .id = UCLASS_CLK,
+ .of_match = hsdk_cgu_clk_id,
+ .probe = hsdk_cgu_clk_probe,
+ .platdata_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
+ .ops = &hsdk_cgu_ops,
+};
config HSDK_CREG_GPIO
bool "HSDK CREG GPIO griver"
- depends on DM
+ depends on DM_GPIO
default n
help
This driver supports CREG GPIOs on Synopsys HSDK SOC.
NAND initialization process.
config NAND_DENALI
- bool "Support Denali NAND controller"
+ bool
select SYS_NAND_SELF_INIT
imply CMD_NAND
- help
- Enable support for the Denali NAND controller.
config NAND_DENALI_DT
bool "Support Denali NAND controller as a DT device"
- depends on NAND_DENALI && OF_CONTROL && DM
+ select NAND_DENALI
+ depends on OF_CONTROL && DM
help
Enable the driver for NAND flash on platforms using a Denali NAND
controller as a DT device.
return -EINVAL;
/* Scan peripherals connected to each SPMI channel */
- for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
+ for (i = 0; i < SPMI_MAX_PERIPH ; i++) {
uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
uint8_t slave_id = (periph & 0xf0000) >> 16;
uint8_t pid = (periph & 0xff00) >> 8;
/*
* SATA
*/
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
-#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
#endif
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE 4
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#endif
/*
* SATA
*/
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
/*
* SATA
*/
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
#endif /* CONFIG_PCI */
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
-#define CONFIG_SCSI_AHCI
-
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SCSI_AHCI
-
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#endif /* CONFIG_TSEC_ENET */
/* SATA */
-#define CONFIG_FSL_SATA
#define CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
#ifdef CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_FSL_SATA
-#define CONFIG_LIBATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_PCIE3
-#define CONFIG_SATA_SIL
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_SRIO
*/
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
* SATA
*/
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
* SATA
*/
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SATA_SIL
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_MXC_OCOTP
/* SATA Configs */
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_OMAP_USB3PHY1_HOST
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* Network */
#define CONFIG_IMX_HDMI
/* SATA */
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
/* Ethernet */
#define CONFIG_FEC_MXC
#ifndef CONFIG_SPL_BUILD
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
/* SATA */
#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_LIBATA
#define CONFIG_LBA48
-#define CONFIG_DWC_AHSATA
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
/*
* SATA
*/
-#define CONFIG_LIBATA
#define CONFIG_LBA48
-#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA_MV
-#define CONFIG_LIBATA
#define CONFIG_LBA48
/* Additional FS support/configuration */
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* SPI Flash Configs */
#define CONFIG_OMAP_USB2PHY2_HOST
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define __io
#define CONFIG_IDE_PREINIT
/* ED Mini V has an IDE-compatible SATA connector for port 1 */
-#define CONFIG_MVSATA_IDE
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
#undef CONFIG_TPM_TIS_BASE_ADDRESS
-#undef CONFIG_SCSI_AHCI
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
"stdout=serial\0" \
"stderr=serial\0"
-/* SATA is not supported in Quark SoC */
-#undef CONFIG_SCSI_AHCI
-
/* 10/100M Ethernet support */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_ALTDESCRIPTOR
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* MMC Configs */
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
- #define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
- #define CONFIG_LIBATA
#endif
/*
#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c
#define CONFIG_MISC_INIT_R
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
#define CONFIG_SYS_SCSI_MAX_LUN 1
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#define CONFIG_FSL_ESDHC
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
/* EEPROM */
/* SATA */
#ifndef SPL_NO_SATA
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#ifndef CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT2
#endif
#endif
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
/* EEPROM */
/* SATA */
#ifndef SPL_NO_SATA
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
/* SATA */
#ifdef CONFIG_SCSI
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
* SATA
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/*
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_SYS_MMC_ENV_DEV 0
#ifdef CONFIG_CMD_SATA
- #define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
#define CONFIG_LBA48
- #define CONFIG_LIBATA
#endif
/* Framebuffer and LCD */
/* SATA Configuration */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* Ethernet Configuration */
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
#define CONFIG_FEC_MXC
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* UART */
#define CONFIG_PREBOOT \
"setenv preboot;" \
- "nand unlock;" \
"saveenv;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"tftpboot $loadaddr zImage;" \
"bootz $loadaddr\0" \
"nandbootcommon=echo 'Booting kernel from NAND...';" \
- "nand unlock;" \
"run nandargs;" \
"run common_bootargs;" \
"run dump_bootargs;" \
#define CONSOLEDEV "ttyO2"
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* SPL */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SATA_SIL
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#if defined(CONFIG_TARGET_P2020RDB)
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#ifndef __ASSEMBLY__
/* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 6
-#define CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
/* Environment options */
#define CONFIG_ENV_SIZE SZ_64K
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#undef CONFIG_SCSI_AHCI
-
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
#ifdef CONFIG_AHCI
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SUNXI_AHCI
#define CONFIG_SYS_64BIT_LBA
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
/* SATA */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* USB */
/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_SATA_MV
-#define CONFIG_LIBATA
#define CONFIG_LBA48
/* Additional FS support/configuration */
/*
* SATA/SCSI/AHCI configuration
*/
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
/* Network support */
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
-#define CONFIG_LIBATA
#endif
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/* SATA AHCI storage */
-
-#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#endif
#ifdef CONFIG_SATA_CEVA
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
--- /dev/null
+/*
+ * Synopsys HSDK SDP CGU clock driver dts bindings
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_
+#define __DT_BINDINGS_CLK_HSDK_CGU_H_
+
+#define CLK_ARC_PLL 0
+#define CLK_ARC 1
+#define CLK_DDR_PLL 2
+#define CLK_SYS_PLL 3
+#define CLK_SYS_APB 4
+#define CLK_SYS_AXI 5
+#define CLK_SYS_ETH 6
+#define CLK_SYS_USB 7
+#define CLK_SYS_SDIO 8
+#define CLK_SYS_HDMI 9
+#define CLK_SYS_GFX_CORE 10
+#define CLK_SYS_GFX_DMA 11
+#define CLK_SYS_GFX_CFG 12
+#define CLK_SYS_DMAC_CORE 13
+#define CLK_SYS_DMAC_CFG 14
+#define CLK_SYS_SDIO_REF 15
+#define CLK_SYS_SPI_REF 16
+#define CLK_SYS_I2C_REF 17
+#define CLK_SYS_UART_REF 18
+#define CLK_SYS_EBI_REF 19
+#define CLK_TUN_PLL 20
+#define CLK_TUN 21
+#define CLK_HDMI_PLL 22
+#define CLK_HDMI 23
+
+#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
/* image node */
#define FIT_DATA_PROP "data"
+#define FIT_DATA_POSITION_PROP "data-position"
#define FIT_DATA_OFFSET_PROP "data-offset"
#define FIT_DATA_SIZE_PROP "data-size"
#define FIT_TIMESTAMP_PROP "timestamp"
int fit_image_get_data(const void *fit, int noffset,
const void **data, size_t *size);
int fit_image_get_data_offset(const void *fit, int noffset, int *data_offset);
+int fit_image_get_data_position(const void *fit, int noffset,
+ int *data_position);
int fit_image_get_data_size(const void *fit, int noffset, int *data_size);
int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
EXYNOS5_BOARD_ODROID_XU3_REV01,
EXYNOS5_BOARD_ODROID_XU3_REV02,
EXYNOS5_BOARD_ODROID_XU4_REV01,
+ EXYNOS5_BOARD_ODROID_HC1_REV01,
EXYNOS5_BOARD_ODROID_UNKNOWN,
EXYNOS5_BOARD_COUNT,
bool board_is_generic(void);
bool board_is_odroidxu3(void);
bool board_is_odroidxu4(void);
+bool board_is_odroidhc1(void);
#endif
CONFIG_AP_SH4A_4A
CONFIG_ARCH_ADPAG101P
CONFIG_ARCH_CPU_INIT
-CONFIG_ARCH_CSB226
CONFIG_ARCH_HAS_ILOG2_U32
CONFIG_ARCH_HAS_ILOG2_U64
-CONFIG_ARCH_INNOKOM
CONFIG_ARCH_KIRKWOOD
-CONFIG_ARCH_LUBBOCK
CONFIG_ARCH_MAP_SYSMEM
CONFIG_ARCH_OMAP4
CONFIG_ARCH_ORION5X
-CONFIG_ARCH_PLEB
-CONFIG_ARCH_PXA_CERF
-CONFIG_ARCH_PXA_IDP
CONFIG_ARCH_RMOBILE_BOARD_STRING
CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
CONFIG_ARCH_TEGRA
CONFIG_DWC2_UTMI_WIDTH
CONFIG_DWCDDR21MCTL
CONFIG_DWCDDR21MCTL_BASE
-CONFIG_DWC_AHSATA
CONFIG_DWC_AHSATA_BASE_ADDR
CONFIG_DWC_AHSATA_PORT_ID
CONFIG_DW_ALTDESCRIPTOR
CONFIG_FSL_QIXIS
CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
CONFIG_FSL_QIXIS_V2
-CONFIG_FSL_SATA
CONFIG_FSL_SATA_V2
CONFIG_FSL_SDHC_V2_3
CONFIG_FSL_SDRAM_TYPE
CONFIG_LG4573
CONFIG_LG4573_BUS
CONFIG_LG4573_CS
-CONFIG_LIBATA
CONFIG_LIB_HW_RAND
CONFIG_LIB_UUID
CONFIG_LINUX
CONFIG_MVGBE_PORTS
CONFIG_MVMFP_V2
CONFIG_MVS
-CONFIG_MVSATA_IDE
CONFIG_MVSATA_IDE_USE_PORT0
CONFIG_MVSATA_IDE_USE_PORT1
CONFIG_MV_ETH_RXQ
CONFIG_SAR_REG
CONFIG_SATA1
CONFIG_SATA2
-CONFIG_SATA_MV
-CONFIG_SATA_SIL
-CONFIG_SATA_SIL3114
CONFIG_SATA_ULI5288
CONFIG_SBC8349
CONFIG_SBC8548
CONFIG_SCIF_A
CONFIG_SCIF_EXT_CLOCK
CONFIG_SCIF_USE_EXT_CLK
-CONFIG_SCSI_AHCI
CONFIG_SCSI_AHCI_PLAT
CONFIG_SCSI_DEV_LIST
CONFIG_SC_TIMER_CLK
cmd = ('sgdisk', '-U', '375a56f7-d6c9-4e81-b5f0-09d41ca89efe',
persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
- cmd = ('sgdisk', '--new=1:2048:2560', '-c 1:part1', persistent)
+ # part1 offset 1MB size 1MB
+ cmd = ('sgdisk', '--new=1:2048:4095', '-c 1:part1', persistent)
+ # part2 offset 2MB size 1.5MB
u_boot_utils.run_and_log(u_boot_console, cmd)
- cmd = ('sgdisk', '--new=2:4096:4608', '-c 2:part2', persistent)
+ cmd = ('sgdisk', '--new=2:4096:7167', '-c 2:part2', persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
cmd = ('sgdisk', '-l', persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
output = u_boot_console.run_command('gpt read host 0')
- assert 'Start 1MiB, size 0MiB' in output
+ assert 'Start 1MiB, size 1MiB' in output
assert 'Block size 512, name part1' in output
- assert 'Start 2MiB, size 0MiB' in output
+ assert 'Start 2MiB, size 1MiB' in output
assert 'Block size 512, name part2' in output
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "part1"' in output
- assert '0x00001000 0x00001200 "part2"' in output
+ assert '0x00000800 0x00000fff "part1"' in output
+ assert '0x00001000 0x00001bff "part2"' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
output = u_boot_console.run_command('gpt read host 0')
assert 'name second' in output
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "first"' in output
- assert '0x00001000 0x00001200 "second"' in output
+ assert '0x00000800 0x00000fff "first"' in output
+ assert '0x00001000 0x00001bff "second"' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "first"' in output
- assert '0x00001000 0x00001200 "second"' in output
+ assert '0x00000800 0x00000fff "first"' in output
+ assert '0x00001000 0x00001bff "second"' in output
u_boot_console.run_command('gpt swap host 0 first second')
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "second"' in output
- assert '0x00001000 0x00001200 "first"' in output
+ assert '0x00000800 0x00000fff "second"' in output
+ assert '0x00001000 0x00001bff "first"' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
assert 'Writing GPT: success!' in output
output = u_boot_console.run_command('part list host 0')
assert '0x00000022 0x00001fde "all"' in output
- output = u_boot_console.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=0x100000,size=0x40200;name=second,start=0x200000,size=0x40200;"')
+ output = u_boot_console.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=1M,size=1M;name=second,start=0x200000,size=0x180000;"')
assert 'Writing GPT: success!' in output
output = u_boot_console.run_command('part list host 0')
- assert '0x00000800 0x00000a00 "first"' in output
- assert '0x00001000 0x00001200 "second"' in output
+ assert '0x00000800 0x00000fff "first"' in output
+ assert '0x00001000 0x00001bff "second"' in output
output = u_boot_console.run_command('gpt guid host 0')
assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
import pytest
import time
+"""
+Note: This test doesn't rely on boardenv_* configuration values but they can
+change test behavior.
+
+# Setup env__sleep_accurate to False if time is not accurate on your platform
+env__sleep_accurate = False
+
+"""
+
def test_sleep(u_boot_console):
"""Test the sleep command, and validate that it sleeps for approximately
the correct amount of time."""
+ sleep_skip = u_boot_console.config.env.get('env__sleep_accurate', True)
+ if not sleep_skip:
+ pytest.skip('sleep is not accurate')
+
if u_boot_console.config.buildconfig.get('config_cmd_misc', 'n') != 'y':
pytest.skip('sleep command not supported')
# 3s isn't too long, but is enough to cross a few second boundaries.
projects / people / ms / u-boot.git / commitdiff
