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00e5a55c BS |
1 | Subject: atl2: add atl2 network driver |
2 | From: Chris Snook <csnook@redhat.com> | |
3 | Patch-mainline: 2.6.28 | |
4 | ||
5 | Driver for Atheros L2 10/100 network device. Includes necessary | |
6 | changes for Kconfig, Makefile, and pci_ids.h. | |
7 | ||
8 | Signed-off-by: Chris Snook <csnook@redhat.com> | |
9 | Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net> | |
10 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
11 | --- | |
12 | ||
13 | --- | |
14 | drivers/net/Kconfig | 11 | |
15 | drivers/net/Makefile | 1 | |
16 | drivers/net/atlx/Makefile | 2 | |
17 | drivers/net/atlx/atl2.c | 3127 ++++++++++++++++++++++++++++++++++++++++++++++ | |
18 | drivers/net/atlx/atl2.h | 530 +++++++ | |
19 | include/linux/pci_ids.h | 1 | |
20 | 6 files changed, 3672 insertions(+) | |
21 | ||
22 | --- /dev/null | |
23 | +++ b/drivers/net/atlx/atl2.c | |
24 | @@ -0,0 +1,3127 @@ | |
25 | +/* | |
26 | + * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. | |
27 | + * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> | |
28 | + * | |
29 | + * Derived from Intel e1000 driver | |
30 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
31 | + * | |
32 | + * This program is free software; you can redistribute it and/or modify it | |
33 | + * under the terms of the GNU General Public License as published by the Free | |
34 | + * Software Foundation; either version 2 of the License, or (at your option) | |
35 | + * any later version. | |
36 | + * | |
37 | + * This program is distributed in the hope that it will be useful, but WITHOUT | |
38 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
39 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
40 | + * more details. | |
41 | + * | |
42 | + * You should have received a copy of the GNU General Public License along with | |
43 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | |
44 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
45 | + */ | |
46 | + | |
47 | +#include <asm/atomic.h> | |
48 | +#include <linux/crc32.h> | |
49 | +#include <linux/dma-mapping.h> | |
50 | +#include <linux/etherdevice.h> | |
51 | +#include <linux/ethtool.h> | |
52 | +#include <linux/hardirq.h> | |
53 | +#include <linux/if_vlan.h> | |
54 | +#include <linux/in.h> | |
55 | +#include <linux/interrupt.h> | |
56 | +#include <linux/ip.h> | |
57 | +#include <linux/irqflags.h> | |
58 | +#include <linux/irqreturn.h> | |
59 | +#include <linux/mii.h> | |
60 | +#include <linux/net.h> | |
61 | +#include <linux/netdevice.h> | |
62 | +#include <linux/pci.h> | |
63 | +#include <linux/pci_ids.h> | |
64 | +#include <linux/pm.h> | |
65 | +#include <linux/skbuff.h> | |
66 | +#include <linux/spinlock.h> | |
67 | +#include <linux/string.h> | |
68 | +#include <linux/tcp.h> | |
69 | +#include <linux/timer.h> | |
70 | +#include <linux/types.h> | |
71 | +#include <linux/workqueue.h> | |
72 | + | |
73 | +#include "atl2.h" | |
74 | + | |
75 | +#define ATL2_DRV_VERSION "2.2.3" | |
76 | + | |
77 | +static char atl2_driver_name[] = "atl2"; | |
78 | +static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; | |
79 | +static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; | |
80 | +static char atl2_driver_version[] = ATL2_DRV_VERSION; | |
81 | + | |
82 | +MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); | |
83 | +MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); | |
84 | +MODULE_LICENSE("GPL"); | |
85 | +MODULE_VERSION(ATL2_DRV_VERSION); | |
86 | + | |
87 | +/* | |
88 | + * atl2_pci_tbl - PCI Device ID Table | |
89 | + */ | |
90 | +static struct pci_device_id atl2_pci_tbl[] = { | |
91 | + {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, | |
92 | + /* required last entry */ | |
93 | + {0,} | |
94 | +}; | |
95 | +MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); | |
96 | + | |
97 | +static void atl2_set_ethtool_ops(struct net_device *netdev); | |
98 | + | |
99 | +static void atl2_check_options(struct atl2_adapter *adapter); | |
100 | + | |
101 | +/* | |
102 | + * atl2_sw_init - Initialize general software structures (struct atl2_adapter) | |
103 | + * @adapter: board private structure to initialize | |
104 | + * | |
105 | + * atl2_sw_init initializes the Adapter private data structure. | |
106 | + * Fields are initialized based on PCI device information and | |
107 | + * OS network device settings (MTU size). | |
108 | + */ | |
109 | +static int __devinit atl2_sw_init(struct atl2_adapter *adapter) | |
110 | +{ | |
111 | + struct atl2_hw *hw = &adapter->hw; | |
112 | + struct pci_dev *pdev = adapter->pdev; | |
113 | + | |
114 | + /* PCI config space info */ | |
115 | + hw->vendor_id = pdev->vendor; | |
116 | + hw->device_id = pdev->device; | |
117 | + hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
118 | + hw->subsystem_id = pdev->subsystem_device; | |
119 | + | |
120 | + pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); | |
121 | + pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); | |
122 | + | |
123 | + adapter->wol = 0; | |
124 | + adapter->ict = 50000; /* ~100ms */ | |
125 | + adapter->link_speed = SPEED_0; /* hardware init */ | |
126 | + adapter->link_duplex = FULL_DUPLEX; | |
127 | + | |
128 | + hw->phy_configured = false; | |
129 | + hw->preamble_len = 7; | |
130 | + hw->ipgt = 0x60; | |
131 | + hw->min_ifg = 0x50; | |
132 | + hw->ipgr1 = 0x40; | |
133 | + hw->ipgr2 = 0x60; | |
134 | + hw->retry_buf = 2; | |
135 | + hw->max_retry = 0xf; | |
136 | + hw->lcol = 0x37; | |
137 | + hw->jam_ipg = 7; | |
138 | + hw->fc_rxd_hi = 0; | |
139 | + hw->fc_rxd_lo = 0; | |
140 | + hw->max_frame_size = adapter->netdev->mtu; | |
141 | + | |
142 | + spin_lock_init(&adapter->stats_lock); | |
143 | + spin_lock_init(&adapter->tx_lock); | |
144 | + | |
145 | + set_bit(__ATL2_DOWN, &adapter->flags); | |
146 | + | |
147 | + return 0; | |
148 | +} | |
149 | + | |
150 | +/* | |
151 | + * atl2_set_multi - Multicast and Promiscuous mode set | |
152 | + * @netdev: network interface device structure | |
153 | + * | |
154 | + * The set_multi entry point is called whenever the multicast address | |
155 | + * list or the network interface flags are updated. This routine is | |
156 | + * responsible for configuring the hardware for proper multicast, | |
157 | + * promiscuous mode, and all-multi behavior. | |
158 | + */ | |
159 | +static void atl2_set_multi(struct net_device *netdev) | |
160 | +{ | |
161 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
162 | + struct atl2_hw *hw = &adapter->hw; | |
163 | + struct dev_mc_list *mc_ptr; | |
164 | + u32 rctl; | |
165 | + u32 hash_value; | |
166 | + | |
167 | + /* Check for Promiscuous and All Multicast modes */ | |
168 | + rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); | |
169 | + | |
170 | + if (netdev->flags & IFF_PROMISC) { | |
171 | + rctl |= MAC_CTRL_PROMIS_EN; | |
172 | + } else if (netdev->flags & IFF_ALLMULTI) { | |
173 | + rctl |= MAC_CTRL_MC_ALL_EN; | |
174 | + rctl &= ~MAC_CTRL_PROMIS_EN; | |
175 | + } else | |
176 | + rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); | |
177 | + | |
178 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); | |
179 | + | |
180 | + /* clear the old settings from the multicast hash table */ | |
181 | + ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); | |
182 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); | |
183 | + | |
184 | + /* comoute mc addresses' hash value ,and put it into hash table */ | |
185 | + for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | |
186 | + hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr); | |
187 | + atl2_hash_set(hw, hash_value); | |
188 | + } | |
189 | +} | |
190 | + | |
191 | +static void init_ring_ptrs(struct atl2_adapter *adapter) | |
192 | +{ | |
193 | + /* Read / Write Ptr Initialize: */ | |
194 | + adapter->txd_write_ptr = 0; | |
195 | + atomic_set(&adapter->txd_read_ptr, 0); | |
196 | + | |
197 | + adapter->rxd_read_ptr = 0; | |
198 | + adapter->rxd_write_ptr = 0; | |
199 | + | |
200 | + atomic_set(&adapter->txs_write_ptr, 0); | |
201 | + adapter->txs_next_clear = 0; | |
202 | +} | |
203 | + | |
204 | +/* | |
205 | + * atl2_configure - Configure Transmit&Receive Unit after Reset | |
206 | + * @adapter: board private structure | |
207 | + * | |
208 | + * Configure the Tx /Rx unit of the MAC after a reset. | |
209 | + */ | |
210 | +static int atl2_configure(struct atl2_adapter *adapter) | |
211 | +{ | |
212 | + struct atl2_hw *hw = &adapter->hw; | |
213 | + u32 value; | |
214 | + | |
215 | + /* clear interrupt status */ | |
216 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); | |
217 | + | |
218 | + /* set MAC Address */ | |
219 | + value = (((u32)hw->mac_addr[2]) << 24) | | |
220 | + (((u32)hw->mac_addr[3]) << 16) | | |
221 | + (((u32)hw->mac_addr[4]) << 8) | | |
222 | + (((u32)hw->mac_addr[5])); | |
223 | + ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); | |
224 | + value = (((u32)hw->mac_addr[0]) << 8) | | |
225 | + (((u32)hw->mac_addr[1])); | |
226 | + ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); | |
227 | + | |
228 | + /* HI base address */ | |
229 | + ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, | |
230 | + (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); | |
231 | + | |
232 | + /* LO base address */ | |
233 | + ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, | |
234 | + (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); | |
235 | + ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, | |
236 | + (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); | |
237 | + ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, | |
238 | + (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); | |
239 | + | |
240 | + /* element count */ | |
241 | + ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); | |
242 | + ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); | |
243 | + ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); | |
244 | + | |
245 | + /* config Internal SRAM */ | |
246 | +/* | |
247 | + ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); | |
248 | + ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); | |
249 | +*/ | |
250 | + | |
251 | + /* config IPG/IFG */ | |
252 | + value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << | |
253 | + MAC_IPG_IFG_IPGT_SHIFT) | | |
254 | + (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << | |
255 | + MAC_IPG_IFG_MIFG_SHIFT) | | |
256 | + (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << | |
257 | + MAC_IPG_IFG_IPGR1_SHIFT)| | |
258 | + (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << | |
259 | + MAC_IPG_IFG_IPGR2_SHIFT); | |
260 | + ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); | |
261 | + | |
262 | + /* config Half-Duplex Control */ | |
263 | + value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | | |
264 | + (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << | |
265 | + MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | | |
266 | + MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | | |
267 | + (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | | |
268 | + (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << | |
269 | + MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); | |
270 | + ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); | |
271 | + | |
272 | + /* set Interrupt Moderator Timer */ | |
273 | + ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); | |
274 | + ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); | |
275 | + | |
276 | + /* set Interrupt Clear Timer */ | |
277 | + ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); | |
278 | + | |
279 | + /* set MTU */ | |
280 | + ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + | |
281 | + ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); | |
282 | + | |
283 | + /* 1590 */ | |
284 | + ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); | |
285 | + | |
286 | + /* flow control */ | |
287 | + ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); | |
288 | + ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); | |
289 | + | |
290 | + /* Init mailbox */ | |
291 | + ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); | |
292 | + ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); | |
293 | + | |
294 | + /* enable DMA read/write */ | |
295 | + ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); | |
296 | + ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); | |
297 | + | |
298 | + value = ATL2_READ_REG(&adapter->hw, REG_ISR); | |
299 | + if ((value & ISR_PHY_LINKDOWN) != 0) | |
300 | + value = 1; /* config failed */ | |
301 | + else | |
302 | + value = 0; | |
303 | + | |
304 | + /* clear all interrupt status */ | |
305 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); | |
306 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); | |
307 | + return value; | |
308 | +} | |
309 | + | |
310 | +/* | |
311 | + * atl2_setup_ring_resources - allocate Tx / RX descriptor resources | |
312 | + * @adapter: board private structure | |
313 | + * | |
314 | + * Return 0 on success, negative on failure | |
315 | + */ | |
316 | +static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) | |
317 | +{ | |
318 | + struct pci_dev *pdev = adapter->pdev; | |
319 | + int size; | |
320 | + u8 offset = 0; | |
321 | + | |
322 | + /* real ring DMA buffer */ | |
323 | + adapter->ring_size = size = | |
324 | + adapter->txd_ring_size * 1 + 7 + /* dword align */ | |
325 | + adapter->txs_ring_size * 4 + 7 + /* dword align */ | |
326 | + adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ | |
327 | + | |
328 | + adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, | |
329 | + &adapter->ring_dma); | |
330 | + if (!adapter->ring_vir_addr) | |
331 | + return -ENOMEM; | |
332 | + memset(adapter->ring_vir_addr, 0, adapter->ring_size); | |
333 | + | |
334 | + /* Init TXD Ring */ | |
335 | + adapter->txd_dma = adapter->ring_dma ; | |
336 | + offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; | |
337 | + adapter->txd_dma += offset; | |
338 | + adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr + | |
339 | + offset); | |
340 | + | |
341 | + /* Init TXS Ring */ | |
342 | + adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; | |
343 | + offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; | |
344 | + adapter->txs_dma += offset; | |
345 | + adapter->txs_ring = (struct tx_pkt_status *) | |
346 | + (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); | |
347 | + | |
348 | + /* Init RXD Ring */ | |
349 | + adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; | |
350 | + offset = (adapter->rxd_dma & 127) ? | |
351 | + (128 - (adapter->rxd_dma & 127)) : 0; | |
352 | + if (offset > 7) | |
353 | + offset -= 8; | |
354 | + else | |
355 | + offset += (128 - 8); | |
356 | + | |
357 | + adapter->rxd_dma += offset; | |
358 | + adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + | |
359 | + (adapter->txs_ring_size * 4 + offset)); | |
360 | + | |
361 | +/* | |
362 | + * Read / Write Ptr Initialize: | |
363 | + * init_ring_ptrs(adapter); | |
364 | + */ | |
365 | + return 0; | |
366 | +} | |
367 | + | |
368 | +/* | |
369 | + * atl2_irq_enable - Enable default interrupt generation settings | |
370 | + * @adapter: board private structure | |
371 | + */ | |
372 | +static inline void atl2_irq_enable(struct atl2_adapter *adapter) | |
373 | +{ | |
374 | + ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); | |
375 | + ATL2_WRITE_FLUSH(&adapter->hw); | |
376 | +} | |
377 | + | |
378 | +/* | |
379 | + * atl2_irq_disable - Mask off interrupt generation on the NIC | |
380 | + * @adapter: board private structure | |
381 | + */ | |
382 | +static inline void atl2_irq_disable(struct atl2_adapter *adapter) | |
383 | +{ | |
384 | + ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); | |
385 | + ATL2_WRITE_FLUSH(&adapter->hw); | |
386 | + synchronize_irq(adapter->pdev->irq); | |
387 | +} | |
388 | + | |
389 | +#ifdef NETIF_F_HW_VLAN_TX | |
390 | +static void atl2_vlan_rx_register(struct net_device *netdev, | |
391 | + struct vlan_group *grp) | |
392 | +{ | |
393 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
394 | + u32 ctrl; | |
395 | + | |
396 | + atl2_irq_disable(adapter); | |
397 | + adapter->vlgrp = grp; | |
398 | + | |
399 | + if (grp) { | |
400 | + /* enable VLAN tag insert/strip */ | |
401 | + ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); | |
402 | + ctrl |= MAC_CTRL_RMV_VLAN; | |
403 | + ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); | |
404 | + } else { | |
405 | + /* disable VLAN tag insert/strip */ | |
406 | + ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); | |
407 | + ctrl &= ~MAC_CTRL_RMV_VLAN; | |
408 | + ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); | |
409 | + } | |
410 | + | |
411 | + atl2_irq_enable(adapter); | |
412 | +} | |
413 | + | |
414 | +static void atl2_restore_vlan(struct atl2_adapter *adapter) | |
415 | +{ | |
416 | + atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
417 | +} | |
418 | +#endif | |
419 | + | |
420 | +static void atl2_intr_rx(struct atl2_adapter *adapter) | |
421 | +{ | |
422 | + struct net_device *netdev = adapter->netdev; | |
423 | + struct rx_desc *rxd; | |
424 | + struct sk_buff *skb; | |
425 | + | |
426 | + do { | |
427 | + rxd = adapter->rxd_ring+adapter->rxd_write_ptr; | |
428 | + if (!rxd->status.update) | |
429 | + break; /* end of tx */ | |
430 | + | |
431 | + /* clear this flag at once */ | |
432 | + rxd->status.update = 0; | |
433 | + | |
434 | + if (rxd->status.ok && rxd->status.pkt_size >= 60) { | |
435 | + int rx_size = (int)(rxd->status.pkt_size - 4); | |
436 | + /* alloc new buffer */ | |
437 | + skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN); | |
438 | + if (NULL == skb) { | |
439 | + printk(KERN_WARNING | |
440 | + "%s: Mem squeeze, deferring packet.\n", | |
441 | + netdev->name); | |
442 | + /* | |
443 | + * Check that some rx space is free. If not, | |
444 | + * free one and mark stats->rx_dropped++. | |
445 | + */ | |
446 | + adapter->net_stats.rx_dropped++; | |
447 | + break; | |
448 | + } | |
449 | + skb_reserve(skb, NET_IP_ALIGN); | |
450 | + skb->dev = netdev; | |
451 | + memcpy(skb->data, rxd->packet, rx_size); | |
452 | + skb_put(skb, rx_size); | |
453 | + skb->protocol = eth_type_trans(skb, netdev); | |
454 | +#ifdef NETIF_F_HW_VLAN_TX | |
455 | + if (adapter->vlgrp && (rxd->status.vlan)) { | |
456 | + u16 vlan_tag = (rxd->status.vtag>>4) | | |
457 | + ((rxd->status.vtag&7) << 13) | | |
458 | + ((rxd->status.vtag&8) << 9); | |
459 | + vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag); | |
460 | + } else | |
461 | +#endif | |
462 | + netif_rx(skb); | |
463 | + adapter->net_stats.rx_bytes += rx_size; | |
464 | + adapter->net_stats.rx_packets++; | |
465 | + netdev->last_rx = jiffies; | |
466 | + } else { | |
467 | + adapter->net_stats.rx_errors++; | |
468 | + | |
469 | + if (rxd->status.ok && rxd->status.pkt_size <= 60) | |
470 | + adapter->net_stats.rx_length_errors++; | |
471 | + if (rxd->status.mcast) | |
472 | + adapter->net_stats.multicast++; | |
473 | + if (rxd->status.crc) | |
474 | + adapter->net_stats.rx_crc_errors++; | |
475 | + if (rxd->status.align) | |
476 | + adapter->net_stats.rx_frame_errors++; | |
477 | + } | |
478 | + | |
479 | + /* advance write ptr */ | |
480 | + if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) | |
481 | + adapter->rxd_write_ptr = 0; | |
482 | + } while (1); | |
483 | + | |
484 | + /* update mailbox? */ | |
485 | + adapter->rxd_read_ptr = adapter->rxd_write_ptr; | |
486 | + ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); | |
487 | +} | |
488 | + | |
489 | +static void atl2_intr_tx(struct atl2_adapter *adapter) | |
490 | +{ | |
491 | + u32 txd_read_ptr; | |
492 | + u32 txs_write_ptr; | |
493 | + struct tx_pkt_status *txs; | |
494 | + struct tx_pkt_header *txph; | |
495 | + int free_hole = 0; | |
496 | + | |
497 | + do { | |
498 | + txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); | |
499 | + txs = adapter->txs_ring + txs_write_ptr; | |
500 | + if (!txs->update) | |
501 | + break; /* tx stop here */ | |
502 | + | |
503 | + free_hole = 1; | |
504 | + txs->update = 0; | |
505 | + | |
506 | + if (++txs_write_ptr == adapter->txs_ring_size) | |
507 | + txs_write_ptr = 0; | |
508 | + atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); | |
509 | + | |
510 | + txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); | |
511 | + txph = (struct tx_pkt_header *) | |
512 | + (((u8 *)adapter->txd_ring) + txd_read_ptr); | |
513 | + | |
514 | + if (txph->pkt_size != txs->pkt_size) { | |
515 | + struct tx_pkt_status *old_txs = txs; | |
516 | + printk(KERN_WARNING | |
517 | + "%s: txs packet size not consistent with txd" | |
518 | + " txd_:0x%08x, txs_:0x%08x!\n", | |
519 | + adapter->netdev->name, | |
520 | + *(u32 *)txph, *(u32 *)txs); | |
521 | + printk(KERN_WARNING | |
522 | + "txd read ptr: 0x%x\n", | |
523 | + txd_read_ptr); | |
524 | + txs = adapter->txs_ring + txs_write_ptr; | |
525 | + printk(KERN_WARNING | |
526 | + "txs-behind:0x%08x\n", | |
527 | + *(u32 *)txs); | |
528 | + if (txs_write_ptr < 2) { | |
529 | + txs = adapter->txs_ring + | |
530 | + (adapter->txs_ring_size + | |
531 | + txs_write_ptr - 2); | |
532 | + } else { | |
533 | + txs = adapter->txs_ring + (txs_write_ptr - 2); | |
534 | + } | |
535 | + printk(KERN_WARNING | |
536 | + "txs-before:0x%08x\n", | |
537 | + *(u32 *)txs); | |
538 | + txs = old_txs; | |
539 | + } | |
540 | + | |
541 | + /* 4for TPH */ | |
542 | + txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); | |
543 | + if (txd_read_ptr >= adapter->txd_ring_size) | |
544 | + txd_read_ptr -= adapter->txd_ring_size; | |
545 | + | |
546 | + atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); | |
547 | + | |
548 | + /* tx statistics: */ | |
549 | + if (txs->ok) | |
550 | + adapter->net_stats.tx_packets++; | |
551 | + else | |
552 | + adapter->net_stats.tx_errors++; | |
553 | + | |
554 | + if (txs->defer) | |
555 | + adapter->net_stats.collisions++; | |
556 | + if (txs->abort_col) | |
557 | + adapter->net_stats.tx_aborted_errors++; | |
558 | + if (txs->late_col) | |
559 | + adapter->net_stats.tx_window_errors++; | |
560 | + if (txs->underun) | |
561 | + adapter->net_stats.tx_fifo_errors++; | |
562 | + } while (1); | |
563 | + | |
564 | + if (free_hole) { | |
565 | + if (netif_queue_stopped(adapter->netdev) && | |
566 | + netif_carrier_ok(adapter->netdev)) | |
567 | + netif_wake_queue(adapter->netdev); | |
568 | + } | |
569 | +} | |
570 | + | |
571 | +static void atl2_check_for_link(struct atl2_adapter *adapter) | |
572 | +{ | |
573 | + struct net_device *netdev = adapter->netdev; | |
574 | + u16 phy_data = 0; | |
575 | + | |
576 | + spin_lock(&adapter->stats_lock); | |
577 | + atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); | |
578 | + atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); | |
579 | + spin_unlock(&adapter->stats_lock); | |
580 | + | |
581 | + /* notify upper layer link down ASAP */ | |
582 | + if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ | |
583 | + if (netif_carrier_ok(netdev)) { /* old link state: Up */ | |
584 | + printk(KERN_INFO "%s: %s NIC Link is Down\n", | |
585 | + atl2_driver_name, netdev->name); | |
586 | + adapter->link_speed = SPEED_0; | |
587 | + netif_carrier_off(netdev); | |
588 | + netif_stop_queue(netdev); | |
589 | + } | |
590 | + } | |
591 | + schedule_work(&adapter->link_chg_task); | |
592 | +} | |
593 | + | |
594 | +static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) | |
595 | +{ | |
596 | + u16 phy_data; | |
597 | + spin_lock(&adapter->stats_lock); | |
598 | + atl2_read_phy_reg(&adapter->hw, 19, &phy_data); | |
599 | + spin_unlock(&adapter->stats_lock); | |
600 | +} | |
601 | + | |
602 | +/* | |
603 | + * atl2_intr - Interrupt Handler | |
604 | + * @irq: interrupt number | |
605 | + * @data: pointer to a network interface device structure | |
606 | + * @pt_regs: CPU registers structure | |
607 | + */ | |
608 | +static irqreturn_t atl2_intr(int irq, void *data) | |
609 | +{ | |
610 | + struct atl2_adapter *adapter = netdev_priv(data); | |
611 | + struct atl2_hw *hw = &adapter->hw; | |
612 | + u32 status; | |
613 | + | |
614 | + status = ATL2_READ_REG(hw, REG_ISR); | |
615 | + if (0 == status) | |
616 | + return IRQ_NONE; | |
617 | + | |
618 | + /* link event */ | |
619 | + if (status & ISR_PHY) | |
620 | + atl2_clear_phy_int(adapter); | |
621 | + | |
622 | + /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ | |
623 | + ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); | |
624 | + | |
625 | + /* check if PCIE PHY Link down */ | |
626 | + if (status & ISR_PHY_LINKDOWN) { | |
627 | + if (netif_running(adapter->netdev)) { /* reset MAC */ | |
628 | + ATL2_WRITE_REG(hw, REG_ISR, 0); | |
629 | + ATL2_WRITE_REG(hw, REG_IMR, 0); | |
630 | + ATL2_WRITE_FLUSH(hw); | |
631 | + schedule_work(&adapter->reset_task); | |
632 | + return IRQ_HANDLED; | |
633 | + } | |
634 | + } | |
635 | + | |
636 | + /* check if DMA read/write error? */ | |
637 | + if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { | |
638 | + ATL2_WRITE_REG(hw, REG_ISR, 0); | |
639 | + ATL2_WRITE_REG(hw, REG_IMR, 0); | |
640 | + ATL2_WRITE_FLUSH(hw); | |
641 | + schedule_work(&adapter->reset_task); | |
642 | + return IRQ_HANDLED; | |
643 | + } | |
644 | + | |
645 | + /* link event */ | |
646 | + if (status & (ISR_PHY | ISR_MANUAL)) { | |
647 | + adapter->net_stats.tx_carrier_errors++; | |
648 | + atl2_check_for_link(adapter); | |
649 | + } | |
650 | + | |
651 | + /* transmit event */ | |
652 | + if (status & ISR_TX_EVENT) | |
653 | + atl2_intr_tx(adapter); | |
654 | + | |
655 | + /* rx exception */ | |
656 | + if (status & ISR_RX_EVENT) | |
657 | + atl2_intr_rx(adapter); | |
658 | + | |
659 | + /* re-enable Interrupt */ | |
660 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); | |
661 | + return IRQ_HANDLED; | |
662 | +} | |
663 | + | |
664 | +static int atl2_request_irq(struct atl2_adapter *adapter) | |
665 | +{ | |
666 | + struct net_device *netdev = adapter->netdev; | |
667 | + int flags, err = 0; | |
668 | + | |
669 | + flags = IRQF_SHARED; | |
670 | +#ifdef CONFIG_PCI_MSI | |
671 | + adapter->have_msi = true; | |
672 | + err = pci_enable_msi(adapter->pdev); | |
673 | + if (err) | |
674 | + adapter->have_msi = false; | |
675 | + | |
676 | + if (adapter->have_msi) | |
677 | + flags &= ~IRQF_SHARED; | |
678 | +#endif | |
679 | + | |
680 | + return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name, | |
681 | + netdev); | |
682 | +} | |
683 | + | |
684 | +/* | |
685 | + * atl2_free_ring_resources - Free Tx / RX descriptor Resources | |
686 | + * @adapter: board private structure | |
687 | + * | |
688 | + * Free all transmit software resources | |
689 | + */ | |
690 | +static void atl2_free_ring_resources(struct atl2_adapter *adapter) | |
691 | +{ | |
692 | + struct pci_dev *pdev = adapter->pdev; | |
693 | + pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, | |
694 | + adapter->ring_dma); | |
695 | +} | |
696 | + | |
697 | +/* | |
698 | + * atl2_open - Called when a network interface is made active | |
699 | + * @netdev: network interface device structure | |
700 | + * | |
701 | + * Returns 0 on success, negative value on failure | |
702 | + * | |
703 | + * The open entry point is called when a network interface is made | |
704 | + * active by the system (IFF_UP). At this point all resources needed | |
705 | + * for transmit and receive operations are allocated, the interrupt | |
706 | + * handler is registered with the OS, the watchdog timer is started, | |
707 | + * and the stack is notified that the interface is ready. | |
708 | + */ | |
709 | +static int atl2_open(struct net_device *netdev) | |
710 | +{ | |
711 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
712 | + int err; | |
713 | + u32 val; | |
714 | + | |
715 | + /* disallow open during test */ | |
716 | + if (test_bit(__ATL2_TESTING, &adapter->flags)) | |
717 | + return -EBUSY; | |
718 | + | |
719 | + /* allocate transmit descriptors */ | |
720 | + err = atl2_setup_ring_resources(adapter); | |
721 | + if (err) | |
722 | + return err; | |
723 | + | |
724 | + err = atl2_init_hw(&adapter->hw); | |
725 | + if (err) { | |
726 | + err = -EIO; | |
727 | + goto err_init_hw; | |
728 | + } | |
729 | + | |
730 | + /* hardware has been reset, we need to reload some things */ | |
731 | + atl2_set_multi(netdev); | |
732 | + init_ring_ptrs(adapter); | |
733 | + | |
734 | +#ifdef NETIF_F_HW_VLAN_TX | |
735 | + atl2_restore_vlan(adapter); | |
736 | +#endif | |
737 | + | |
738 | + if (atl2_configure(adapter)) { | |
739 | + err = -EIO; | |
740 | + goto err_config; | |
741 | + } | |
742 | + | |
743 | + err = atl2_request_irq(adapter); | |
744 | + if (err) | |
745 | + goto err_req_irq; | |
746 | + | |
747 | + clear_bit(__ATL2_DOWN, &adapter->flags); | |
748 | + | |
749 | + mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ); | |
750 | + | |
751 | + val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); | |
752 | + ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, | |
753 | + val | MASTER_CTRL_MANUAL_INT); | |
754 | + | |
755 | + atl2_irq_enable(adapter); | |
756 | + | |
757 | + return 0; | |
758 | + | |
759 | +err_init_hw: | |
760 | +err_req_irq: | |
761 | +err_config: | |
762 | + atl2_free_ring_resources(adapter); | |
763 | + atl2_reset_hw(&adapter->hw); | |
764 | + | |
765 | + return err; | |
766 | +} | |
767 | + | |
768 | +static void atl2_down(struct atl2_adapter *adapter) | |
769 | +{ | |
770 | + struct net_device *netdev = adapter->netdev; | |
771 | + | |
772 | + /* signal that we're down so the interrupt handler does not | |
773 | + * reschedule our watchdog timer */ | |
774 | + set_bit(__ATL2_DOWN, &adapter->flags); | |
775 | + | |
776 | +#ifdef NETIF_F_LLTX | |
777 | + netif_stop_queue(netdev); | |
778 | +#else | |
779 | + netif_tx_disable(netdev); | |
780 | +#endif | |
781 | + | |
782 | + /* reset MAC to disable all RX/TX */ | |
783 | + atl2_reset_hw(&adapter->hw); | |
784 | + msleep(1); | |
785 | + | |
786 | + atl2_irq_disable(adapter); | |
787 | + | |
788 | + del_timer_sync(&adapter->watchdog_timer); | |
789 | + del_timer_sync(&adapter->phy_config_timer); | |
790 | + clear_bit(0, &adapter->cfg_phy); | |
791 | + | |
792 | + netif_carrier_off(netdev); | |
793 | + adapter->link_speed = SPEED_0; | |
794 | + adapter->link_duplex = -1; | |
795 | +} | |
796 | + | |
797 | +static void atl2_free_irq(struct atl2_adapter *adapter) | |
798 | +{ | |
799 | + struct net_device *netdev = adapter->netdev; | |
800 | + | |
801 | + free_irq(adapter->pdev->irq, netdev); | |
802 | + | |
803 | +#ifdef CONFIG_PCI_MSI | |
804 | + if (adapter->have_msi) | |
805 | + pci_disable_msi(adapter->pdev); | |
806 | +#endif | |
807 | +} | |
808 | + | |
809 | +/* | |
810 | + * atl2_close - Disables a network interface | |
811 | + * @netdev: network interface device structure | |
812 | + * | |
813 | + * Returns 0, this is not allowed to fail | |
814 | + * | |
815 | + * The close entry point is called when an interface is de-activated | |
816 | + * by the OS. The hardware is still under the drivers control, but | |
817 | + * needs to be disabled. A global MAC reset is issued to stop the | |
818 | + * hardware, and all transmit and receive resources are freed. | |
819 | + */ | |
820 | +static int atl2_close(struct net_device *netdev) | |
821 | +{ | |
822 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
823 | + | |
824 | + WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); | |
825 | + | |
826 | + atl2_down(adapter); | |
827 | + atl2_free_irq(adapter); | |
828 | + atl2_free_ring_resources(adapter); | |
829 | + | |
830 | + return 0; | |
831 | +} | |
832 | + | |
833 | +static inline int TxsFreeUnit(struct atl2_adapter *adapter) | |
834 | +{ | |
835 | + u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); | |
836 | + | |
837 | + return (adapter->txs_next_clear >= txs_write_ptr) ? | |
838 | + (int) (adapter->txs_ring_size - adapter->txs_next_clear + | |
839 | + txs_write_ptr - 1) : | |
840 | + (int) (txs_write_ptr - adapter->txs_next_clear - 1); | |
841 | +} | |
842 | + | |
843 | +static inline int TxdFreeBytes(struct atl2_adapter *adapter) | |
844 | +{ | |
845 | + u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); | |
846 | + | |
847 | + return (adapter->txd_write_ptr >= txd_read_ptr) ? | |
848 | + (int) (adapter->txd_ring_size - adapter->txd_write_ptr + | |
849 | + txd_read_ptr - 1) : | |
850 | + (int) (txd_read_ptr - adapter->txd_write_ptr - 1); | |
851 | +} | |
852 | + | |
853 | +static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
854 | +{ | |
855 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
856 | + unsigned long flags; | |
857 | + struct tx_pkt_header *txph; | |
858 | + u32 offset, copy_len; | |
859 | + int txs_unused; | |
860 | + int txbuf_unused; | |
861 | + | |
862 | + if (test_bit(__ATL2_DOWN, &adapter->flags)) { | |
863 | + dev_kfree_skb_any(skb); | |
864 | + return NETDEV_TX_OK; | |
865 | + } | |
866 | + | |
867 | + if (unlikely(skb->len <= 0)) { | |
868 | + dev_kfree_skb_any(skb); | |
869 | + return NETDEV_TX_OK; | |
870 | + } | |
871 | + | |
872 | +#ifdef NETIF_F_LLTX | |
873 | + local_irq_save(flags); | |
874 | + if (!spin_trylock(&adapter->tx_lock)) { | |
875 | + /* Collision - tell upper layer to requeue */ | |
876 | + local_irq_restore(flags); | |
877 | + return NETDEV_TX_LOCKED; | |
878 | + } | |
879 | +#else | |
880 | + spin_lock_irqsave(&adapter->tx_lock, flags); | |
881 | +#endif | |
882 | + txs_unused = TxsFreeUnit(adapter); | |
883 | + txbuf_unused = TxdFreeBytes(adapter); | |
884 | + | |
885 | + if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || | |
886 | + txs_unused < 1) { | |
887 | + /* not enough resources */ | |
888 | + netif_stop_queue(netdev); | |
889 | + spin_unlock_irqrestore(&adapter->tx_lock, flags); | |
890 | + return NETDEV_TX_BUSY; | |
891 | + } | |
892 | + | |
893 | + offset = adapter->txd_write_ptr; | |
894 | + | |
895 | + txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); | |
896 | + | |
897 | + *(u32 *)txph = 0; | |
898 | + txph->pkt_size = skb->len; | |
899 | + | |
900 | + offset += 4; | |
901 | + if (offset >= adapter->txd_ring_size) | |
902 | + offset -= adapter->txd_ring_size; | |
903 | + copy_len = adapter->txd_ring_size - offset; | |
904 | + if (copy_len >= skb->len) { | |
905 | + memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); | |
906 | + offset += ((u32)(skb->len + 3) & ~3); | |
907 | + } else { | |
908 | + memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); | |
909 | + memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, | |
910 | + skb->len-copy_len); | |
911 | + offset = ((u32)(skb->len-copy_len + 3) & ~3); | |
912 | + } | |
913 | +#ifdef NETIF_F_HW_VLAN_TX | |
914 | + if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | |
915 | + u16 vlan_tag = vlan_tx_tag_get(skb); | |
916 | + vlan_tag = (vlan_tag << 4) | | |
917 | + (vlan_tag >> 13) | | |
918 | + ((vlan_tag >> 9) & 0x8); | |
919 | + txph->ins_vlan = 1; | |
920 | + txph->vlan = vlan_tag; | |
921 | + } | |
922 | +#endif | |
923 | + if (offset >= adapter->txd_ring_size) | |
924 | + offset -= adapter->txd_ring_size; | |
925 | + adapter->txd_write_ptr = offset; | |
926 | + | |
927 | + /* clear txs before send */ | |
928 | + adapter->txs_ring[adapter->txs_next_clear].update = 0; | |
929 | + if (++adapter->txs_next_clear == adapter->txs_ring_size) | |
930 | + adapter->txs_next_clear = 0; | |
931 | + | |
932 | + ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, | |
933 | + (adapter->txd_write_ptr >> 2)); | |
934 | + | |
935 | + spin_unlock_irqrestore(&adapter->tx_lock, flags); | |
936 | + | |
937 | + netdev->trans_start = jiffies; | |
938 | + dev_kfree_skb_any(skb); | |
939 | + return NETDEV_TX_OK; | |
940 | +} | |
941 | + | |
942 | +/* | |
943 | + * atl2_get_stats - Get System Network Statistics | |
944 | + * @netdev: network interface device structure | |
945 | + * | |
946 | + * Returns the address of the device statistics structure. | |
947 | + * The statistics are actually updated from the timer callback. | |
948 | + */ | |
949 | +static struct net_device_stats *atl2_get_stats(struct net_device *netdev) | |
950 | +{ | |
951 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
952 | + return &adapter->net_stats; | |
953 | +} | |
954 | + | |
955 | +/* | |
956 | + * atl2_change_mtu - Change the Maximum Transfer Unit | |
957 | + * @netdev: network interface device structure | |
958 | + * @new_mtu: new value for maximum frame size | |
959 | + * | |
960 | + * Returns 0 on success, negative on failure | |
961 | + */ | |
962 | +static int atl2_change_mtu(struct net_device *netdev, int new_mtu) | |
963 | +{ | |
964 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
965 | + struct atl2_hw *hw = &adapter->hw; | |
966 | + | |
967 | + if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) | |
968 | + return -EINVAL; | |
969 | + | |
970 | + /* set MTU */ | |
971 | + if (hw->max_frame_size != new_mtu) { | |
972 | + netdev->mtu = new_mtu; | |
973 | + ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + | |
974 | + VLAN_SIZE + ETHERNET_FCS_SIZE); | |
975 | + } | |
976 | + | |
977 | + return 0; | |
978 | +} | |
979 | + | |
980 | +/* | |
981 | + * atl2_set_mac - Change the Ethernet Address of the NIC | |
982 | + * @netdev: network interface device structure | |
983 | + * @p: pointer to an address structure | |
984 | + * | |
985 | + * Returns 0 on success, negative on failure | |
986 | + */ | |
987 | +static int atl2_set_mac(struct net_device *netdev, void *p) | |
988 | +{ | |
989 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
990 | + struct sockaddr *addr = p; | |
991 | + | |
992 | + if (!is_valid_ether_addr(addr->sa_data)) | |
993 | + return -EADDRNOTAVAIL; | |
994 | + | |
995 | + if (netif_running(netdev)) | |
996 | + return -EBUSY; | |
997 | + | |
998 | + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
999 | + memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); | |
1000 | + | |
1001 | + atl2_set_mac_addr(&adapter->hw); | |
1002 | + | |
1003 | + return 0; | |
1004 | +} | |
1005 | + | |
1006 | +/* | |
1007 | + * atl2_mii_ioctl - | |
1008 | + * @netdev: | |
1009 | + * @ifreq: | |
1010 | + * @cmd: | |
1011 | + */ | |
1012 | +static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
1013 | +{ | |
1014 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1015 | + struct mii_ioctl_data *data = if_mii(ifr); | |
1016 | + unsigned long flags; | |
1017 | + | |
1018 | + switch (cmd) { | |
1019 | + case SIOCGMIIPHY: | |
1020 | + data->phy_id = 0; | |
1021 | + break; | |
1022 | + case SIOCGMIIREG: | |
1023 | + if (!capable(CAP_NET_ADMIN)) | |
1024 | + return -EPERM; | |
1025 | + spin_lock_irqsave(&adapter->stats_lock, flags); | |
1026 | + if (atl2_read_phy_reg(&adapter->hw, | |
1027 | + data->reg_num & 0x1F, &data->val_out)) { | |
1028 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1029 | + return -EIO; | |
1030 | + } | |
1031 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1032 | + break; | |
1033 | + case SIOCSMIIREG: | |
1034 | + if (!capable(CAP_NET_ADMIN)) | |
1035 | + return -EPERM; | |
1036 | + if (data->reg_num & ~(0x1F)) | |
1037 | + return -EFAULT; | |
1038 | + spin_lock_irqsave(&adapter->stats_lock, flags); | |
1039 | + if (atl2_write_phy_reg(&adapter->hw, data->reg_num, | |
1040 | + data->val_in)) { | |
1041 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1042 | + return -EIO; | |
1043 | + } | |
1044 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1045 | + break; | |
1046 | + default: | |
1047 | + return -EOPNOTSUPP; | |
1048 | + } | |
1049 | + return 0; | |
1050 | +} | |
1051 | + | |
1052 | +/* | |
1053 | + * atl2_ioctl - | |
1054 | + * @netdev: | |
1055 | + * @ifreq: | |
1056 | + * @cmd: | |
1057 | + */ | |
1058 | +static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
1059 | +{ | |
1060 | + switch (cmd) { | |
1061 | + case SIOCGMIIPHY: | |
1062 | + case SIOCGMIIREG: | |
1063 | + case SIOCSMIIREG: | |
1064 | + return atl2_mii_ioctl(netdev, ifr, cmd); | |
1065 | +#ifdef ETHTOOL_OPS_COMPAT | |
1066 | + case SIOCETHTOOL: | |
1067 | + return ethtool_ioctl(ifr); | |
1068 | +#endif | |
1069 | + default: | |
1070 | + return -EOPNOTSUPP; | |
1071 | + } | |
1072 | +} | |
1073 | + | |
1074 | +/* | |
1075 | + * atl2_tx_timeout - Respond to a Tx Hang | |
1076 | + * @netdev: network interface device structure | |
1077 | + */ | |
1078 | +static void atl2_tx_timeout(struct net_device *netdev) | |
1079 | +{ | |
1080 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1081 | + | |
1082 | + /* Do the reset outside of interrupt context */ | |
1083 | + schedule_work(&adapter->reset_task); | |
1084 | +} | |
1085 | + | |
1086 | +/* | |
1087 | + * atl2_watchdog - Timer Call-back | |
1088 | + * @data: pointer to netdev cast into an unsigned long | |
1089 | + */ | |
1090 | +static void atl2_watchdog(unsigned long data) | |
1091 | +{ | |
1092 | + struct atl2_adapter *adapter = (struct atl2_adapter *) data; | |
1093 | + u32 drop_rxd, drop_rxs; | |
1094 | + unsigned long flags; | |
1095 | + | |
1096 | + if (!test_bit(__ATL2_DOWN, &adapter->flags)) { | |
1097 | + spin_lock_irqsave(&adapter->stats_lock, flags); | |
1098 | + drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); | |
1099 | + drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); | |
1100 | + adapter->net_stats.rx_over_errors += (drop_rxd+drop_rxs); | |
1101 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1102 | + | |
1103 | + /* Reset the timer */ | |
1104 | + mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ); | |
1105 | + } | |
1106 | +} | |
1107 | + | |
1108 | +/* | |
1109 | + * atl2_phy_config - Timer Call-back | |
1110 | + * @data: pointer to netdev cast into an unsigned long | |
1111 | + */ | |
1112 | +static void atl2_phy_config(unsigned long data) | |
1113 | +{ | |
1114 | + struct atl2_adapter *adapter = (struct atl2_adapter *) data; | |
1115 | + struct atl2_hw *hw = &adapter->hw; | |
1116 | + unsigned long flags; | |
1117 | + | |
1118 | + spin_lock_irqsave(&adapter->stats_lock, flags); | |
1119 | + atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); | |
1120 | + atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | | |
1121 | + MII_CR_RESTART_AUTO_NEG); | |
1122 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1123 | + clear_bit(0, &adapter->cfg_phy); | |
1124 | +} | |
1125 | + | |
1126 | +static int atl2_up(struct atl2_adapter *adapter) | |
1127 | +{ | |
1128 | + struct net_device *netdev = adapter->netdev; | |
1129 | + int err = 0; | |
1130 | + u32 val; | |
1131 | + | |
1132 | + /* hardware has been reset, we need to reload some things */ | |
1133 | + | |
1134 | + err = atl2_init_hw(&adapter->hw); | |
1135 | + if (err) { | |
1136 | + err = -EIO; | |
1137 | + return err; | |
1138 | + } | |
1139 | + | |
1140 | + atl2_set_multi(netdev); | |
1141 | + init_ring_ptrs(adapter); | |
1142 | + | |
1143 | +#ifdef NETIF_F_HW_VLAN_TX | |
1144 | + atl2_restore_vlan(adapter); | |
1145 | +#endif | |
1146 | + | |
1147 | + if (atl2_configure(adapter)) { | |
1148 | + err = -EIO; | |
1149 | + goto err_up; | |
1150 | + } | |
1151 | + | |
1152 | + clear_bit(__ATL2_DOWN, &adapter->flags); | |
1153 | + | |
1154 | + val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); | |
1155 | + ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | | |
1156 | + MASTER_CTRL_MANUAL_INT); | |
1157 | + | |
1158 | + atl2_irq_enable(adapter); | |
1159 | + | |
1160 | +err_up: | |
1161 | + return err; | |
1162 | +} | |
1163 | + | |
1164 | +static void atl2_reinit_locked(struct atl2_adapter *adapter) | |
1165 | +{ | |
1166 | + WARN_ON(in_interrupt()); | |
1167 | + while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) | |
1168 | + msleep(1); | |
1169 | + atl2_down(adapter); | |
1170 | + atl2_up(adapter); | |
1171 | + clear_bit(__ATL2_RESETTING, &adapter->flags); | |
1172 | +} | |
1173 | + | |
1174 | +static void atl2_reset_task(struct work_struct *work) | |
1175 | +{ | |
1176 | + struct atl2_adapter *adapter; | |
1177 | + adapter = container_of(work, struct atl2_adapter, reset_task); | |
1178 | + | |
1179 | + atl2_reinit_locked(adapter); | |
1180 | +} | |
1181 | + | |
1182 | +static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) | |
1183 | +{ | |
1184 | + u32 value; | |
1185 | + struct atl2_hw *hw = &adapter->hw; | |
1186 | + struct net_device *netdev = adapter->netdev; | |
1187 | + | |
1188 | + /* Config MAC CTRL Register */ | |
1189 | + value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; | |
1190 | + | |
1191 | + /* duplex */ | |
1192 | + if (FULL_DUPLEX == adapter->link_duplex) | |
1193 | + value |= MAC_CTRL_DUPLX; | |
1194 | + | |
1195 | + /* flow control */ | |
1196 | + value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); | |
1197 | + | |
1198 | + /* PAD & CRC */ | |
1199 | + value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | |
1200 | + | |
1201 | + /* preamble length */ | |
1202 | + value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << | |
1203 | + MAC_CTRL_PRMLEN_SHIFT); | |
1204 | + | |
1205 | + /* vlan */ | |
1206 | + if (adapter->vlgrp) | |
1207 | + value |= MAC_CTRL_RMV_VLAN; | |
1208 | + | |
1209 | + /* filter mode */ | |
1210 | + value |= MAC_CTRL_BC_EN; | |
1211 | + if (netdev->flags & IFF_PROMISC) | |
1212 | + value |= MAC_CTRL_PROMIS_EN; | |
1213 | + else if (netdev->flags & IFF_ALLMULTI) | |
1214 | + value |= MAC_CTRL_MC_ALL_EN; | |
1215 | + | |
1216 | + /* half retry buffer */ | |
1217 | + value |= (((u32)(adapter->hw.retry_buf & | |
1218 | + MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); | |
1219 | + | |
1220 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | |
1221 | +} | |
1222 | + | |
1223 | +static int atl2_check_link(struct atl2_adapter *adapter) | |
1224 | +{ | |
1225 | + struct atl2_hw *hw = &adapter->hw; | |
1226 | + struct net_device *netdev = adapter->netdev; | |
1227 | + int ret_val; | |
1228 | + u16 speed, duplex, phy_data; | |
1229 | + int reconfig = 0; | |
1230 | + | |
1231 | + /* MII_BMSR must read twise */ | |
1232 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | |
1233 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | |
1234 | + if (!(phy_data&BMSR_LSTATUS)) { /* link down */ | |
1235 | + if (netif_carrier_ok(netdev)) { /* old link state: Up */ | |
1236 | + u32 value; | |
1237 | + /* disable rx */ | |
1238 | + value = ATL2_READ_REG(hw, REG_MAC_CTRL); | |
1239 | + value &= ~MAC_CTRL_RX_EN; | |
1240 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | |
1241 | + adapter->link_speed = SPEED_0; | |
1242 | + netif_carrier_off(netdev); | |
1243 | + netif_stop_queue(netdev); | |
1244 | + } | |
1245 | + return 0; | |
1246 | + } | |
1247 | + | |
1248 | + /* Link Up */ | |
1249 | + ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); | |
1250 | + if (ret_val) | |
1251 | + return ret_val; | |
1252 | + switch (hw->MediaType) { | |
1253 | + case MEDIA_TYPE_100M_FULL: | |
1254 | + if (speed != SPEED_100 || duplex != FULL_DUPLEX) | |
1255 | + reconfig = 1; | |
1256 | + break; | |
1257 | + case MEDIA_TYPE_100M_HALF: | |
1258 | + if (speed != SPEED_100 || duplex != HALF_DUPLEX) | |
1259 | + reconfig = 1; | |
1260 | + break; | |
1261 | + case MEDIA_TYPE_10M_FULL: | |
1262 | + if (speed != SPEED_10 || duplex != FULL_DUPLEX) | |
1263 | + reconfig = 1; | |
1264 | + break; | |
1265 | + case MEDIA_TYPE_10M_HALF: | |
1266 | + if (speed != SPEED_10 || duplex != HALF_DUPLEX) | |
1267 | + reconfig = 1; | |
1268 | + break; | |
1269 | + } | |
1270 | + /* link result is our setting */ | |
1271 | + if (reconfig == 0) { | |
1272 | + if (adapter->link_speed != speed || | |
1273 | + adapter->link_duplex != duplex) { | |
1274 | + adapter->link_speed = speed; | |
1275 | + adapter->link_duplex = duplex; | |
1276 | + atl2_setup_mac_ctrl(adapter); | |
1277 | + printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", | |
1278 | + atl2_driver_name, netdev->name, | |
1279 | + adapter->link_speed, | |
1280 | + adapter->link_duplex == FULL_DUPLEX ? | |
1281 | + "Full Duplex" : "Half Duplex"); | |
1282 | + } | |
1283 | + | |
1284 | + if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ | |
1285 | + netif_carrier_on(netdev); | |
1286 | + netif_wake_queue(netdev); | |
1287 | + } | |
1288 | + return 0; | |
1289 | + } | |
1290 | + | |
1291 | + /* change original link status */ | |
1292 | + if (netif_carrier_ok(netdev)) { | |
1293 | + u32 value; | |
1294 | + /* disable rx */ | |
1295 | + value = ATL2_READ_REG(hw, REG_MAC_CTRL); | |
1296 | + value &= ~MAC_CTRL_RX_EN; | |
1297 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | |
1298 | + | |
1299 | + adapter->link_speed = SPEED_0; | |
1300 | + netif_carrier_off(netdev); | |
1301 | + netif_stop_queue(netdev); | |
1302 | + } | |
1303 | + | |
1304 | + /* auto-neg, insert timer to re-config phy | |
1305 | + * (if interval smaller than 5 seconds, something strange) */ | |
1306 | + if (!test_bit(__ATL2_DOWN, &adapter->flags)) { | |
1307 | + if (!test_and_set_bit(0, &adapter->cfg_phy)) | |
1308 | + mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ); | |
1309 | + } | |
1310 | + | |
1311 | + return 0; | |
1312 | +} | |
1313 | + | |
1314 | +/* | |
1315 | + * atl2_link_chg_task - deal with link change event Out of interrupt context | |
1316 | + * @netdev: network interface device structure | |
1317 | + */ | |
1318 | +static void atl2_link_chg_task(struct work_struct *work) | |
1319 | +{ | |
1320 | + struct atl2_adapter *adapter; | |
1321 | + unsigned long flags; | |
1322 | + | |
1323 | + adapter = container_of(work, struct atl2_adapter, link_chg_task); | |
1324 | + | |
1325 | + spin_lock_irqsave(&adapter->stats_lock, flags); | |
1326 | + atl2_check_link(adapter); | |
1327 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1328 | +} | |
1329 | + | |
1330 | +static void atl2_setup_pcicmd(struct pci_dev *pdev) | |
1331 | +{ | |
1332 | + u16 cmd; | |
1333 | + | |
1334 | + pci_read_config_word(pdev, PCI_COMMAND, &cmd); | |
1335 | + | |
1336 | + if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1337 | + cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1338 | + if (cmd & PCI_COMMAND_IO) | |
1339 | + cmd &= ~PCI_COMMAND_IO; | |
1340 | + if (0 == (cmd & PCI_COMMAND_MEMORY)) | |
1341 | + cmd |= PCI_COMMAND_MEMORY; | |
1342 | + if (0 == (cmd & PCI_COMMAND_MASTER)) | |
1343 | + cmd |= PCI_COMMAND_MASTER; | |
1344 | + pci_write_config_word(pdev, PCI_COMMAND, cmd); | |
1345 | + | |
1346 | + /* | |
1347 | + * some motherboards BIOS(PXE/EFI) driver may set PME | |
1348 | + * while they transfer control to OS (Windows/Linux) | |
1349 | + * so we should clear this bit before NIC work normally | |
1350 | + */ | |
1351 | + pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); | |
1352 | +} | |
1353 | + | |
1354 | +/* | |
1355 | + * atl2_probe - Device Initialization Routine | |
1356 | + * @pdev: PCI device information struct | |
1357 | + * @ent: entry in atl2_pci_tbl | |
1358 | + * | |
1359 | + * Returns 0 on success, negative on failure | |
1360 | + * | |
1361 | + * atl2_probe initializes an adapter identified by a pci_dev structure. | |
1362 | + * The OS initialization, configuring of the adapter private structure, | |
1363 | + * and a hardware reset occur. | |
1364 | + */ | |
1365 | +static int __devinit atl2_probe(struct pci_dev *pdev, | |
1366 | + const struct pci_device_id *ent) | |
1367 | +{ | |
1368 | + struct net_device *netdev; | |
1369 | + struct atl2_adapter *adapter; | |
1370 | + static int cards_found; | |
1371 | + unsigned long mmio_start; | |
1372 | + int mmio_len; | |
1373 | + int err; | |
1374 | + | |
1375 | + cards_found = 0; | |
1376 | + | |
1377 | + err = pci_enable_device(pdev); | |
1378 | + if (err) | |
1379 | + return err; | |
1380 | + | |
1381 | + /* | |
1382 | + * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA | |
1383 | + * until the kernel has the proper infrastructure to support 64-bit DMA | |
1384 | + * on these devices. | |
1385 | + */ | |
1386 | + if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) && | |
1387 | + pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { | |
1388 | + printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); | |
1389 | + goto err_dma; | |
1390 | + } | |
1391 | + | |
1392 | + /* Mark all PCI regions associated with PCI device | |
1393 | + * pdev as being reserved by owner atl2_driver_name */ | |
1394 | + err = pci_request_regions(pdev, atl2_driver_name); | |
1395 | + if (err) | |
1396 | + goto err_pci_reg; | |
1397 | + | |
1398 | + /* Enables bus-mastering on the device and calls | |
1399 | + * pcibios_set_master to do the needed arch specific settings */ | |
1400 | + pci_set_master(pdev); | |
1401 | + | |
1402 | + err = -ENOMEM; | |
1403 | + netdev = alloc_etherdev(sizeof(struct atl2_adapter)); | |
1404 | + if (!netdev) | |
1405 | + goto err_alloc_etherdev; | |
1406 | + | |
1407 | + SET_NETDEV_DEV(netdev, &pdev->dev); | |
1408 | + | |
1409 | + pci_set_drvdata(pdev, netdev); | |
1410 | + adapter = netdev_priv(netdev); | |
1411 | + adapter->netdev = netdev; | |
1412 | + adapter->pdev = pdev; | |
1413 | + adapter->hw.back = adapter; | |
1414 | + | |
1415 | + mmio_start = pci_resource_start(pdev, 0x0); | |
1416 | + mmio_len = pci_resource_len(pdev, 0x0); | |
1417 | + | |
1418 | + adapter->hw.mem_rang = (u32)mmio_len; | |
1419 | + adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); | |
1420 | + if (!adapter->hw.hw_addr) { | |
1421 | + err = -EIO; | |
1422 | + goto err_ioremap; | |
1423 | + } | |
1424 | + | |
1425 | + atl2_setup_pcicmd(pdev); | |
1426 | + | |
1427 | + netdev->open = &atl2_open; | |
1428 | + netdev->stop = &atl2_close; | |
1429 | + netdev->hard_start_xmit = &atl2_xmit_frame; | |
1430 | + netdev->get_stats = &atl2_get_stats; | |
1431 | + netdev->set_multicast_list = &atl2_set_multi; | |
1432 | + netdev->set_mac_address = &atl2_set_mac; | |
1433 | + netdev->change_mtu = &atl2_change_mtu; | |
1434 | + netdev->do_ioctl = &atl2_ioctl; | |
1435 | + atl2_set_ethtool_ops(netdev); | |
1436 | + | |
1437 | +#ifdef HAVE_TX_TIMEOUT | |
1438 | + netdev->tx_timeout = &atl2_tx_timeout; | |
1439 | + netdev->watchdog_timeo = 5 * HZ; | |
1440 | +#endif | |
1441 | +#ifdef NETIF_F_HW_VLAN_TX | |
1442 | + netdev->vlan_rx_register = atl2_vlan_rx_register; | |
1443 | +#endif | |
1444 | + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1445 | + | |
1446 | + netdev->mem_start = mmio_start; | |
1447 | + netdev->mem_end = mmio_start + mmio_len; | |
1448 | + adapter->bd_number = cards_found; | |
1449 | + adapter->pci_using_64 = false; | |
1450 | + | |
1451 | + /* setup the private structure */ | |
1452 | + err = atl2_sw_init(adapter); | |
1453 | + if (err) | |
1454 | + goto err_sw_init; | |
1455 | + | |
1456 | + err = -EIO; | |
1457 | + | |
1458 | +#ifdef NETIF_F_HW_VLAN_TX | |
1459 | + netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); | |
1460 | +#endif | |
1461 | + | |
1462 | +#ifdef NETIF_F_LLTX | |
1463 | + netdev->features |= NETIF_F_LLTX; | |
1464 | +#endif | |
1465 | + | |
1466 | + /* Init PHY as early as possible due to power saving issue */ | |
1467 | + atl2_phy_init(&adapter->hw); | |
1468 | + | |
1469 | + /* reset the controller to | |
1470 | + * put the device in a known good starting state */ | |
1471 | + | |
1472 | + if (atl2_reset_hw(&adapter->hw)) { | |
1473 | + err = -EIO; | |
1474 | + goto err_reset; | |
1475 | + } | |
1476 | + | |
1477 | + /* copy the MAC address out of the EEPROM */ | |
1478 | + atl2_read_mac_addr(&adapter->hw); | |
1479 | + memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); | |
1480 | +/* FIXME: do we still need this? */ | |
1481 | +#ifdef ETHTOOL_GPERMADDR | |
1482 | + memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len); | |
1483 | + | |
1484 | + if (!is_valid_ether_addr(netdev->perm_addr)) { | |
1485 | +#else | |
1486 | + if (!is_valid_ether_addr(netdev->dev_addr)) { | |
1487 | +#endif | |
1488 | + err = -EIO; | |
1489 | + goto err_eeprom; | |
1490 | + } | |
1491 | + | |
1492 | + atl2_check_options(adapter); | |
1493 | + | |
1494 | + init_timer(&adapter->watchdog_timer); | |
1495 | + adapter->watchdog_timer.function = &atl2_watchdog; | |
1496 | + adapter->watchdog_timer.data = (unsigned long) adapter; | |
1497 | + | |
1498 | + init_timer(&adapter->phy_config_timer); | |
1499 | + adapter->phy_config_timer.function = &atl2_phy_config; | |
1500 | + adapter->phy_config_timer.data = (unsigned long) adapter; | |
1501 | + | |
1502 | + INIT_WORK(&adapter->reset_task, atl2_reset_task); | |
1503 | + INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); | |
1504 | + | |
1505 | + strcpy(netdev->name, "eth%d"); /* ?? */ | |
1506 | + err = register_netdev(netdev); | |
1507 | + if (err) | |
1508 | + goto err_register; | |
1509 | + | |
1510 | + /* assume we have no link for now */ | |
1511 | + netif_carrier_off(netdev); | |
1512 | + netif_stop_queue(netdev); | |
1513 | + | |
1514 | + cards_found++; | |
1515 | + | |
1516 | + return 0; | |
1517 | + | |
1518 | +err_reset: | |
1519 | +err_register: | |
1520 | +err_sw_init: | |
1521 | +err_eeprom: | |
1522 | + iounmap(adapter->hw.hw_addr); | |
1523 | +err_ioremap: | |
1524 | + free_netdev(netdev); | |
1525 | +err_alloc_etherdev: | |
1526 | + pci_release_regions(pdev); | |
1527 | +err_pci_reg: | |
1528 | +err_dma: | |
1529 | + pci_disable_device(pdev); | |
1530 | + return err; | |
1531 | +} | |
1532 | + | |
1533 | +/* | |
1534 | + * atl2_remove - Device Removal Routine | |
1535 | + * @pdev: PCI device information struct | |
1536 | + * | |
1537 | + * atl2_remove is called by the PCI subsystem to alert the driver | |
1538 | + * that it should release a PCI device. The could be caused by a | |
1539 | + * Hot-Plug event, or because the driver is going to be removed from | |
1540 | + * memory. | |
1541 | + */ | |
1542 | +/* FIXME: write the original MAC address back in case it was changed from a | |
1543 | + * BIOS-set value, as in atl1 -- CHS */ | |
1544 | +static void __devexit atl2_remove(struct pci_dev *pdev) | |
1545 | +{ | |
1546 | + struct net_device *netdev = pci_get_drvdata(pdev); | |
1547 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1548 | + | |
1549 | + /* flush_scheduled work may reschedule our watchdog task, so | |
1550 | + * explicitly disable watchdog tasks from being rescheduled */ | |
1551 | + set_bit(__ATL2_DOWN, &adapter->flags); | |
1552 | + | |
1553 | + del_timer_sync(&adapter->watchdog_timer); | |
1554 | + del_timer_sync(&adapter->phy_config_timer); | |
1555 | + | |
1556 | + flush_scheduled_work(); | |
1557 | + | |
1558 | + unregister_netdev(netdev); | |
1559 | + | |
1560 | + atl2_force_ps(&adapter->hw); | |
1561 | + | |
1562 | + iounmap(adapter->hw.hw_addr); | |
1563 | + pci_release_regions(pdev); | |
1564 | + | |
1565 | + free_netdev(netdev); | |
1566 | + | |
1567 | + pci_disable_device(pdev); | |
1568 | +} | |
1569 | + | |
1570 | +static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) | |
1571 | +{ | |
1572 | + struct net_device *netdev = pci_get_drvdata(pdev); | |
1573 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1574 | + struct atl2_hw *hw = &adapter->hw; | |
1575 | + u16 speed, duplex; | |
1576 | + u32 ctrl = 0; | |
1577 | + u32 wufc = adapter->wol; | |
1578 | + | |
1579 | +#ifdef CONFIG_PM | |
1580 | + int retval = 0; | |
1581 | +#endif | |
1582 | + | |
1583 | + netif_device_detach(netdev); | |
1584 | + | |
1585 | + if (netif_running(netdev)) { | |
1586 | + WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); | |
1587 | + atl2_down(adapter); | |
1588 | + } | |
1589 | + | |
1590 | +#ifdef CONFIG_PM | |
1591 | + retval = pci_save_state(pdev); | |
1592 | + if (retval) | |
1593 | + return retval; | |
1594 | +#endif | |
1595 | + | |
1596 | + atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); | |
1597 | + atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); | |
1598 | + if (ctrl & BMSR_LSTATUS) | |
1599 | + wufc &= ~ATLX_WUFC_LNKC; | |
1600 | + | |
1601 | + if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { | |
1602 | + u32 ret_val; | |
1603 | + /* get current link speed & duplex */ | |
1604 | + ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); | |
1605 | + if (ret_val) { | |
1606 | + printk(KERN_DEBUG | |
1607 | + "%s: get speed&duplex error while suspend\n", | |
1608 | + atl2_driver_name); | |
1609 | + goto wol_dis; | |
1610 | + } | |
1611 | + | |
1612 | + ctrl = 0; | |
1613 | + | |
1614 | + /* turn on magic packet wol */ | |
1615 | + if (wufc & ATLX_WUFC_MAG) | |
1616 | + ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); | |
1617 | + | |
1618 | + /* ignore Link Chg event when Link is up */ | |
1619 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); | |
1620 | + | |
1621 | + /* Config MAC CTRL Register */ | |
1622 | + ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; | |
1623 | + if (FULL_DUPLEX == adapter->link_duplex) | |
1624 | + ctrl |= MAC_CTRL_DUPLX; | |
1625 | + ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | |
1626 | + ctrl |= (((u32)adapter->hw.preamble_len & | |
1627 | + MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); | |
1628 | + ctrl |= (((u32)(adapter->hw.retry_buf & | |
1629 | + MAC_CTRL_HALF_LEFT_BUF_MASK)) << | |
1630 | + MAC_CTRL_HALF_LEFT_BUF_SHIFT); | |
1631 | + if (wufc & ATLX_WUFC_MAG) { | |
1632 | + /* magic packet maybe Broadcast&multicast&Unicast */ | |
1633 | + ctrl |= MAC_CTRL_BC_EN; | |
1634 | + } | |
1635 | + | |
1636 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); | |
1637 | + | |
1638 | + /* pcie patch */ | |
1639 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | |
1640 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
1641 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | |
1642 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | |
1643 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | |
1644 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | |
1645 | + | |
1646 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | |
1647 | + goto suspend_exit; | |
1648 | + } | |
1649 | + | |
1650 | + if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { | |
1651 | + /* link is down, so only LINK CHG WOL event enable */ | |
1652 | + ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); | |
1653 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); | |
1654 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); | |
1655 | + | |
1656 | + /* pcie patch */ | |
1657 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | |
1658 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
1659 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | |
1660 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | |
1661 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | |
1662 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | |
1663 | + | |
1664 | + hw->phy_configured = false; /* re-init PHY when resume */ | |
1665 | + | |
1666 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | |
1667 | + | |
1668 | + goto suspend_exit; | |
1669 | + } | |
1670 | + | |
1671 | +wol_dis: | |
1672 | + /* WOL disabled */ | |
1673 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); | |
1674 | + | |
1675 | + /* pcie patch */ | |
1676 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | |
1677 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
1678 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | |
1679 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | |
1680 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | |
1681 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | |
1682 | + | |
1683 | + atl2_force_ps(hw); | |
1684 | + hw->phy_configured = false; /* re-init PHY when resume */ | |
1685 | + | |
1686 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
1687 | + | |
1688 | +suspend_exit: | |
1689 | + if (netif_running(netdev)) | |
1690 | + atl2_free_irq(adapter); | |
1691 | + | |
1692 | + pci_disable_device(pdev); | |
1693 | + | |
1694 | + pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1695 | + | |
1696 | + return 0; | |
1697 | +} | |
1698 | + | |
1699 | +#ifdef CONFIG_PM | |
1700 | +static int atl2_resume(struct pci_dev *pdev) | |
1701 | +{ | |
1702 | + struct net_device *netdev = pci_get_drvdata(pdev); | |
1703 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1704 | + u32 err; | |
1705 | + | |
1706 | + pci_set_power_state(pdev, PCI_D0); | |
1707 | + pci_restore_state(pdev); | |
1708 | + | |
1709 | + err = pci_enable_device(pdev); | |
1710 | + if (err) { | |
1711 | + printk(KERN_ERR | |
1712 | + "atl2: Cannot enable PCI device from suspend\n"); | |
1713 | + return err; | |
1714 | + } | |
1715 | + | |
1716 | + pci_set_master(pdev); | |
1717 | + | |
1718 | + ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ | |
1719 | + | |
1720 | + pci_enable_wake(pdev, PCI_D3hot, 0); | |
1721 | + pci_enable_wake(pdev, PCI_D3cold, 0); | |
1722 | + | |
1723 | + ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); | |
1724 | + | |
1725 | + err = atl2_request_irq(adapter); | |
1726 | + if (netif_running(netdev) && err) | |
1727 | + return err; | |
1728 | + | |
1729 | + atl2_reset_hw(&adapter->hw); | |
1730 | + | |
1731 | + if (netif_running(netdev)) | |
1732 | + atl2_up(adapter); | |
1733 | + | |
1734 | + netif_device_attach(netdev); | |
1735 | + | |
1736 | + return 0; | |
1737 | +} | |
1738 | +#endif | |
1739 | + | |
1740 | +static void atl2_shutdown(struct pci_dev *pdev) | |
1741 | +{ | |
1742 | + atl2_suspend(pdev, PMSG_SUSPEND); | |
1743 | +} | |
1744 | + | |
1745 | +static struct pci_driver atl2_driver = { | |
1746 | + .name = atl2_driver_name, | |
1747 | + .id_table = atl2_pci_tbl, | |
1748 | + .probe = atl2_probe, | |
1749 | + .remove = __devexit_p(atl2_remove), | |
1750 | + /* Power Managment Hooks */ | |
1751 | + .suspend = atl2_suspend, | |
1752 | +#ifdef CONFIG_PM | |
1753 | + .resume = atl2_resume, | |
1754 | +#endif | |
1755 | + .shutdown = atl2_shutdown, | |
1756 | +}; | |
1757 | + | |
1758 | +/* | |
1759 | + * atl2_init_module - Driver Registration Routine | |
1760 | + * | |
1761 | + * atl2_init_module is the first routine called when the driver is | |
1762 | + * loaded. All it does is register with the PCI subsystem. | |
1763 | + */ | |
1764 | +static int __init atl2_init_module(void) | |
1765 | +{ | |
1766 | + printk(KERN_INFO "%s - version %s\n", atl2_driver_string, | |
1767 | + atl2_driver_version); | |
1768 | + printk(KERN_INFO "%s\n", atl2_copyright); | |
1769 | + return pci_register_driver(&atl2_driver); | |
1770 | +} | |
1771 | +module_init(atl2_init_module); | |
1772 | + | |
1773 | +/* | |
1774 | + * atl2_exit_module - Driver Exit Cleanup Routine | |
1775 | + * | |
1776 | + * atl2_exit_module is called just before the driver is removed | |
1777 | + * from memory. | |
1778 | + */ | |
1779 | +static void __exit atl2_exit_module(void) | |
1780 | +{ | |
1781 | + pci_unregister_driver(&atl2_driver); | |
1782 | +} | |
1783 | +module_exit(atl2_exit_module); | |
1784 | + | |
1785 | +static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) | |
1786 | +{ | |
1787 | + struct atl2_adapter *adapter = hw->back; | |
1788 | + pci_read_config_word(adapter->pdev, reg, value); | |
1789 | +} | |
1790 | + | |
1791 | +static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) | |
1792 | +{ | |
1793 | + struct atl2_adapter *adapter = hw->back; | |
1794 | + pci_write_config_word(adapter->pdev, reg, *value); | |
1795 | +} | |
1796 | + | |
1797 | +static int atl2_get_settings(struct net_device *netdev, | |
1798 | + struct ethtool_cmd *ecmd) | |
1799 | +{ | |
1800 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1801 | + struct atl2_hw *hw = &adapter->hw; | |
1802 | + | |
1803 | + ecmd->supported = (SUPPORTED_10baseT_Half | | |
1804 | + SUPPORTED_10baseT_Full | | |
1805 | + SUPPORTED_100baseT_Half | | |
1806 | + SUPPORTED_100baseT_Full | | |
1807 | + SUPPORTED_Autoneg | | |
1808 | + SUPPORTED_TP); | |
1809 | + ecmd->advertising = ADVERTISED_TP; | |
1810 | + | |
1811 | + ecmd->advertising |= ADVERTISED_Autoneg; | |
1812 | + ecmd->advertising |= hw->autoneg_advertised; | |
1813 | + | |
1814 | + ecmd->port = PORT_TP; | |
1815 | + ecmd->phy_address = 0; | |
1816 | + ecmd->transceiver = XCVR_INTERNAL; | |
1817 | + | |
1818 | + if (adapter->link_speed != SPEED_0) { | |
1819 | + ecmd->speed = adapter->link_speed; | |
1820 | + if (adapter->link_duplex == FULL_DUPLEX) | |
1821 | + ecmd->duplex = DUPLEX_FULL; | |
1822 | + else | |
1823 | + ecmd->duplex = DUPLEX_HALF; | |
1824 | + } else { | |
1825 | + ecmd->speed = -1; | |
1826 | + ecmd->duplex = -1; | |
1827 | + } | |
1828 | + | |
1829 | + ecmd->autoneg = AUTONEG_ENABLE; | |
1830 | + return 0; | |
1831 | +} | |
1832 | + | |
1833 | +static int atl2_set_settings(struct net_device *netdev, | |
1834 | + struct ethtool_cmd *ecmd) | |
1835 | +{ | |
1836 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1837 | + struct atl2_hw *hw = &adapter->hw; | |
1838 | + | |
1839 | + while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) | |
1840 | + msleep(1); | |
1841 | + | |
1842 | + if (ecmd->autoneg == AUTONEG_ENABLE) { | |
1843 | +#define MY_ADV_MASK (ADVERTISE_10_HALF | \ | |
1844 | + ADVERTISE_10_FULL | \ | |
1845 | + ADVERTISE_100_HALF| \ | |
1846 | + ADVERTISE_100_FULL) | |
1847 | + | |
1848 | + if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) { | |
1849 | + hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; | |
1850 | + hw->autoneg_advertised = MY_ADV_MASK; | |
1851 | + } else if ((ecmd->advertising & MY_ADV_MASK) == | |
1852 | + ADVERTISE_100_FULL) { | |
1853 | + hw->MediaType = MEDIA_TYPE_100M_FULL; | |
1854 | + hw->autoneg_advertised = ADVERTISE_100_FULL; | |
1855 | + } else if ((ecmd->advertising & MY_ADV_MASK) == | |
1856 | + ADVERTISE_100_HALF) { | |
1857 | + hw->MediaType = MEDIA_TYPE_100M_HALF; | |
1858 | + hw->autoneg_advertised = ADVERTISE_100_HALF; | |
1859 | + } else if ((ecmd->advertising & MY_ADV_MASK) == | |
1860 | + ADVERTISE_10_FULL) { | |
1861 | + hw->MediaType = MEDIA_TYPE_10M_FULL; | |
1862 | + hw->autoneg_advertised = ADVERTISE_10_FULL; | |
1863 | + } else if ((ecmd->advertising & MY_ADV_MASK) == | |
1864 | + ADVERTISE_10_HALF) { | |
1865 | + hw->MediaType = MEDIA_TYPE_10M_HALF; | |
1866 | + hw->autoneg_advertised = ADVERTISE_10_HALF; | |
1867 | + } else { | |
1868 | + clear_bit(__ATL2_RESETTING, &adapter->flags); | |
1869 | + return -EINVAL; | |
1870 | + } | |
1871 | + ecmd->advertising = hw->autoneg_advertised | | |
1872 | + ADVERTISED_TP | ADVERTISED_Autoneg; | |
1873 | + } else { | |
1874 | + clear_bit(__ATL2_RESETTING, &adapter->flags); | |
1875 | + return -EINVAL; | |
1876 | + } | |
1877 | + | |
1878 | + /* reset the link */ | |
1879 | + if (netif_running(adapter->netdev)) { | |
1880 | + atl2_down(adapter); | |
1881 | + atl2_up(adapter); | |
1882 | + } else | |
1883 | + atl2_reset_hw(&adapter->hw); | |
1884 | + | |
1885 | + clear_bit(__ATL2_RESETTING, &adapter->flags); | |
1886 | + return 0; | |
1887 | +} | |
1888 | + | |
1889 | +static u32 atl2_get_tx_csum(struct net_device *netdev) | |
1890 | +{ | |
1891 | + return (netdev->features & NETIF_F_HW_CSUM) != 0; | |
1892 | +} | |
1893 | + | |
1894 | +static u32 atl2_get_msglevel(struct net_device *netdev) | |
1895 | +{ | |
1896 | + return 0; | |
1897 | +} | |
1898 | + | |
1899 | +/* | |
1900 | + * It's sane for this to be empty, but we might want to take advantage of this. | |
1901 | + */ | |
1902 | +static void atl2_set_msglevel(struct net_device *netdev, u32 data) | |
1903 | +{ | |
1904 | +} | |
1905 | + | |
1906 | +static int atl2_get_regs_len(struct net_device *netdev) | |
1907 | +{ | |
1908 | +#define ATL2_REGS_LEN 42 | |
1909 | + return sizeof(u32) * ATL2_REGS_LEN; | |
1910 | +} | |
1911 | + | |
1912 | +static void atl2_get_regs(struct net_device *netdev, | |
1913 | + struct ethtool_regs *regs, void *p) | |
1914 | +{ | |
1915 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1916 | + struct atl2_hw *hw = &adapter->hw; | |
1917 | + u32 *regs_buff = p; | |
1918 | + u16 phy_data; | |
1919 | + | |
1920 | + memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); | |
1921 | + | |
1922 | + regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; | |
1923 | + | |
1924 | + regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); | |
1925 | + regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | |
1926 | + regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); | |
1927 | + regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); | |
1928 | + regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); | |
1929 | + regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); | |
1930 | + regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); | |
1931 | + regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); | |
1932 | + regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); | |
1933 | + regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); | |
1934 | + regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); | |
1935 | + regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); | |
1936 | + regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); | |
1937 | + regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); | |
1938 | + regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); | |
1939 | + regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); | |
1940 | + regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); | |
1941 | + regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); | |
1942 | + regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); | |
1943 | + regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); | |
1944 | + regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); | |
1945 | + regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); | |
1946 | + regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); | |
1947 | + regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); | |
1948 | + regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); | |
1949 | + regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); | |
1950 | + regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); | |
1951 | + regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); | |
1952 | + regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); | |
1953 | + regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); | |
1954 | + regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); | |
1955 | + regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); | |
1956 | + regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); | |
1957 | + regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); | |
1958 | + regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); | |
1959 | + regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); | |
1960 | + regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); | |
1961 | + regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); | |
1962 | + regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); | |
1963 | + | |
1964 | + atl2_read_phy_reg(hw, MII_BMCR, &phy_data); | |
1965 | + regs_buff[40] = (u32)phy_data; | |
1966 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | |
1967 | + regs_buff[41] = (u32)phy_data; | |
1968 | +} | |
1969 | + | |
1970 | +static int atl2_get_eeprom_len(struct net_device *netdev) | |
1971 | +{ | |
1972 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1973 | + | |
1974 | + if (!atl2_check_eeprom_exist(&adapter->hw)) | |
1975 | + return 512; | |
1976 | + else | |
1977 | + return 0; | |
1978 | +} | |
1979 | + | |
1980 | +static int atl2_get_eeprom(struct net_device *netdev, | |
1981 | + struct ethtool_eeprom *eeprom, u8 *bytes) | |
1982 | +{ | |
1983 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
1984 | + struct atl2_hw *hw = &adapter->hw; | |
1985 | + u32 *eeprom_buff; | |
1986 | + int first_dword, last_dword; | |
1987 | + int ret_val = 0; | |
1988 | + int i; | |
1989 | + | |
1990 | + if (eeprom->len == 0) | |
1991 | + return -EINVAL; | |
1992 | + | |
1993 | + if (atl2_check_eeprom_exist(hw)) | |
1994 | + return -EINVAL; | |
1995 | + | |
1996 | + eeprom->magic = hw->vendor_id | (hw->device_id << 16); | |
1997 | + | |
1998 | + first_dword = eeprom->offset >> 2; | |
1999 | + last_dword = (eeprom->offset + eeprom->len - 1) >> 2; | |
2000 | + | |
2001 | + eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), | |
2002 | + GFP_KERNEL); | |
2003 | + if (!eeprom_buff) | |
2004 | + return -ENOMEM; | |
2005 | + | |
2006 | + for (i = first_dword; i < last_dword; i++) { | |
2007 | + if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) | |
2008 | + return -EIO; | |
2009 | + } | |
2010 | + | |
2011 | + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), | |
2012 | + eeprom->len); | |
2013 | + kfree(eeprom_buff); | |
2014 | + | |
2015 | + return ret_val; | |
2016 | +} | |
2017 | + | |
2018 | +static int atl2_set_eeprom(struct net_device *netdev, | |
2019 | + struct ethtool_eeprom *eeprom, u8 *bytes) | |
2020 | +{ | |
2021 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
2022 | + struct atl2_hw *hw = &adapter->hw; | |
2023 | + u32 *eeprom_buff; | |
2024 | + u32 *ptr; | |
2025 | + int max_len, first_dword, last_dword, ret_val = 0; | |
2026 | + int i; | |
2027 | + | |
2028 | + if (eeprom->len == 0) | |
2029 | + return -EOPNOTSUPP; | |
2030 | + | |
2031 | + if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) | |
2032 | + return -EFAULT; | |
2033 | + | |
2034 | + max_len = 512; | |
2035 | + | |
2036 | + first_dword = eeprom->offset >> 2; | |
2037 | + last_dword = (eeprom->offset + eeprom->len - 1) >> 2; | |
2038 | + eeprom_buff = kmalloc(max_len, GFP_KERNEL); | |
2039 | + if (!eeprom_buff) | |
2040 | + return -ENOMEM; | |
2041 | + | |
2042 | + ptr = (u32 *)eeprom_buff; | |
2043 | + | |
2044 | + if (eeprom->offset & 3) { | |
2045 | + /* need read/modify/write of first changed EEPROM word */ | |
2046 | + /* only the second byte of the word is being modified */ | |
2047 | + if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) | |
2048 | + return -EIO; | |
2049 | + ptr++; | |
2050 | + } | |
2051 | + if (((eeprom->offset + eeprom->len) & 3)) { | |
2052 | + /* | |
2053 | + * need read/modify/write of last changed EEPROM word | |
2054 | + * only the first byte of the word is being modified | |
2055 | + */ | |
2056 | + if (!atl2_read_eeprom(hw, last_dword * 4, | |
2057 | + &(eeprom_buff[last_dword - first_dword]))) | |
2058 | + return -EIO; | |
2059 | + } | |
2060 | + | |
2061 | + /* Device's eeprom is always little-endian, word addressable */ | |
2062 | + memcpy(ptr, bytes, eeprom->len); | |
2063 | + | |
2064 | + for (i = 0; i < last_dword - first_dword + 1; i++) { | |
2065 | + if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) | |
2066 | + return -EIO; | |
2067 | + } | |
2068 | + | |
2069 | + kfree(eeprom_buff); | |
2070 | + return ret_val; | |
2071 | +} | |
2072 | + | |
2073 | +static void atl2_get_drvinfo(struct net_device *netdev, | |
2074 | + struct ethtool_drvinfo *drvinfo) | |
2075 | +{ | |
2076 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
2077 | + | |
2078 | + strncpy(drvinfo->driver, atl2_driver_name, 32); | |
2079 | + strncpy(drvinfo->version, atl2_driver_version, 32); | |
2080 | + strncpy(drvinfo->fw_version, "L2", 32); | |
2081 | + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); | |
2082 | + drvinfo->n_stats = 0; | |
2083 | + drvinfo->testinfo_len = 0; | |
2084 | + drvinfo->regdump_len = atl2_get_regs_len(netdev); | |
2085 | + drvinfo->eedump_len = atl2_get_eeprom_len(netdev); | |
2086 | +} | |
2087 | + | |
2088 | +static void atl2_get_wol(struct net_device *netdev, | |
2089 | + struct ethtool_wolinfo *wol) | |
2090 | +{ | |
2091 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
2092 | + | |
2093 | + wol->supported = WAKE_MAGIC; | |
2094 | + wol->wolopts = 0; | |
2095 | + | |
2096 | + if (adapter->wol & ATLX_WUFC_EX) | |
2097 | + wol->wolopts |= WAKE_UCAST; | |
2098 | + if (adapter->wol & ATLX_WUFC_MC) | |
2099 | + wol->wolopts |= WAKE_MCAST; | |
2100 | + if (adapter->wol & ATLX_WUFC_BC) | |
2101 | + wol->wolopts |= WAKE_BCAST; | |
2102 | + if (adapter->wol & ATLX_WUFC_MAG) | |
2103 | + wol->wolopts |= WAKE_MAGIC; | |
2104 | + if (adapter->wol & ATLX_WUFC_LNKC) | |
2105 | + wol->wolopts |= WAKE_PHY; | |
2106 | +} | |
2107 | + | |
2108 | +static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
2109 | +{ | |
2110 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
2111 | + | |
2112 | + if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) | |
2113 | + return -EOPNOTSUPP; | |
2114 | + | |
2115 | + if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST)) | |
2116 | + return -EOPNOTSUPP; | |
2117 | + | |
2118 | + /* these settings will always override what we currently have */ | |
2119 | + adapter->wol = 0; | |
2120 | + | |
2121 | + if (wol->wolopts & WAKE_MAGIC) | |
2122 | + adapter->wol |= ATLX_WUFC_MAG; | |
2123 | + if (wol->wolopts & WAKE_PHY) | |
2124 | + adapter->wol |= ATLX_WUFC_LNKC; | |
2125 | + | |
2126 | + return 0; | |
2127 | +} | |
2128 | + | |
2129 | +static int atl2_nway_reset(struct net_device *netdev) | |
2130 | +{ | |
2131 | + struct atl2_adapter *adapter = netdev_priv(netdev); | |
2132 | + if (netif_running(netdev)) | |
2133 | + atl2_reinit_locked(adapter); | |
2134 | + return 0; | |
2135 | +} | |
2136 | + | |
2137 | +static struct ethtool_ops atl2_ethtool_ops = { | |
2138 | + .get_settings = atl2_get_settings, | |
2139 | + .set_settings = atl2_set_settings, | |
2140 | + .get_drvinfo = atl2_get_drvinfo, | |
2141 | + .get_regs_len = atl2_get_regs_len, | |
2142 | + .get_regs = atl2_get_regs, | |
2143 | + .get_wol = atl2_get_wol, | |
2144 | + .set_wol = atl2_set_wol, | |
2145 | + .get_msglevel = atl2_get_msglevel, | |
2146 | + .set_msglevel = atl2_set_msglevel, | |
2147 | + .nway_reset = atl2_nway_reset, | |
2148 | + .get_link = ethtool_op_get_link, | |
2149 | + .get_eeprom_len = atl2_get_eeprom_len, | |
2150 | + .get_eeprom = atl2_get_eeprom, | |
2151 | + .set_eeprom = atl2_set_eeprom, | |
2152 | + .get_tx_csum = atl2_get_tx_csum, | |
2153 | + .get_sg = ethtool_op_get_sg, | |
2154 | + .set_sg = ethtool_op_set_sg, | |
2155 | +#ifdef NETIF_F_TSO | |
2156 | + .get_tso = ethtool_op_get_tso, | |
2157 | +#endif | |
2158 | +}; | |
2159 | + | |
2160 | +static void atl2_set_ethtool_ops(struct net_device *netdev) | |
2161 | +{ | |
2162 | + SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops); | |
2163 | +} | |
2164 | + | |
2165 | +#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ | |
2166 | + (((a) & 0xff00ff00) >> 8)) | |
2167 | +#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) | |
2168 | +#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) | |
2169 | + | |
2170 | +/* | |
2171 | + * Reset the transmit and receive units; mask and clear all interrupts. | |
2172 | + * | |
2173 | + * hw - Struct containing variables accessed by shared code | |
2174 | + * return : 0 or idle status (if error) | |
2175 | + */ | |
2176 | +static s32 atl2_reset_hw(struct atl2_hw *hw) | |
2177 | +{ | |
2178 | + u32 icr; | |
2179 | + u16 pci_cfg_cmd_word; | |
2180 | + int i; | |
2181 | + | |
2182 | + /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ | |
2183 | + atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); | |
2184 | + if ((pci_cfg_cmd_word & | |
2185 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != | |
2186 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { | |
2187 | + pci_cfg_cmd_word |= | |
2188 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); | |
2189 | + atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); | |
2190 | + } | |
2191 | + | |
2192 | + /* Clear Interrupt mask to stop board from generating | |
2193 | + * interrupts & Clear any pending interrupt events | |
2194 | + */ | |
2195 | + /* FIXME */ | |
2196 | + /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ | |
2197 | + /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ | |
2198 | + | |
2199 | + /* Issue Soft Reset to the MAC. This will reset the chip's | |
2200 | + * transmit, receive, DMA. It will not effect | |
2201 | + * the current PCI configuration. The global reset bit is self- | |
2202 | + * clearing, and should clear within a microsecond. | |
2203 | + */ | |
2204 | + ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); | |
2205 | + wmb(); | |
2206 | + msleep(1); /* delay about 1ms */ | |
2207 | + | |
2208 | + /* Wait at least 10ms for All module to be Idle */ | |
2209 | + for (i = 0; i < 10; i++) { | |
2210 | + icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); | |
2211 | + if (!icr) | |
2212 | + break; | |
2213 | + msleep(1); /* delay 1 ms */ | |
2214 | + cpu_relax(); | |
2215 | + } | |
2216 | + | |
2217 | + if (icr) | |
2218 | + return icr; | |
2219 | + | |
2220 | + return 0; | |
2221 | +} | |
2222 | + | |
2223 | +#define CUSTOM_SPI_CS_SETUP 2 | |
2224 | +#define CUSTOM_SPI_CLK_HI 2 | |
2225 | +#define CUSTOM_SPI_CLK_LO 2 | |
2226 | +#define CUSTOM_SPI_CS_HOLD 2 | |
2227 | +#define CUSTOM_SPI_CS_HI 3 | |
2228 | + | |
2229 | +static struct atl2_spi_flash_dev flash_table[] = | |
2230 | +{ | |
2231 | +/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ | |
2232 | +{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, | |
2233 | +{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, | |
2234 | +{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, | |
2235 | +}; | |
2236 | + | |
2237 | +static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) | |
2238 | +{ | |
2239 | + int i; | |
2240 | + u32 value; | |
2241 | + | |
2242 | + ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); | |
2243 | + ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); | |
2244 | + | |
2245 | + value = SPI_FLASH_CTRL_WAIT_READY | | |
2246 | + (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << | |
2247 | + SPI_FLASH_CTRL_CS_SETUP_SHIFT | | |
2248 | + (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << | |
2249 | + SPI_FLASH_CTRL_CLK_HI_SHIFT | | |
2250 | + (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << | |
2251 | + SPI_FLASH_CTRL_CLK_LO_SHIFT | | |
2252 | + (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << | |
2253 | + SPI_FLASH_CTRL_CS_HOLD_SHIFT | | |
2254 | + (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << | |
2255 | + SPI_FLASH_CTRL_CS_HI_SHIFT | | |
2256 | + (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; | |
2257 | + | |
2258 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | |
2259 | + | |
2260 | + value |= SPI_FLASH_CTRL_START; | |
2261 | + | |
2262 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | |
2263 | + | |
2264 | + for (i = 0; i < 10; i++) { | |
2265 | + msleep(1); | |
2266 | + value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | |
2267 | + if (!(value & SPI_FLASH_CTRL_START)) | |
2268 | + break; | |
2269 | + } | |
2270 | + | |
2271 | + if (value & SPI_FLASH_CTRL_START) | |
2272 | + return false; | |
2273 | + | |
2274 | + *buf = ATL2_READ_REG(hw, REG_SPI_DATA); | |
2275 | + | |
2276 | + return true; | |
2277 | +} | |
2278 | + | |
2279 | +/* | |
2280 | + * get_permanent_address | |
2281 | + * return 0 if get valid mac address, | |
2282 | + */ | |
2283 | +static int get_permanent_address(struct atl2_hw *hw) | |
2284 | +{ | |
2285 | + u32 Addr[2]; | |
2286 | + u32 i, Control; | |
2287 | + u16 Register; | |
2288 | + u8 EthAddr[NODE_ADDRESS_SIZE]; | |
2289 | + bool KeyValid; | |
2290 | + | |
2291 | + if (is_valid_ether_addr(hw->perm_mac_addr)) | |
2292 | + return 0; | |
2293 | + | |
2294 | + Addr[0] = 0; | |
2295 | + Addr[1] = 0; | |
2296 | + | |
2297 | + if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ | |
2298 | + Register = 0; | |
2299 | + KeyValid = false; | |
2300 | + | |
2301 | + /* Read out all EEPROM content */ | |
2302 | + i = 0; | |
2303 | + while (1) { | |
2304 | + if (atl2_read_eeprom(hw, i + 0x100, &Control)) { | |
2305 | + if (KeyValid) { | |
2306 | + if (Register == REG_MAC_STA_ADDR) | |
2307 | + Addr[0] = Control; | |
2308 | + else if (Register == | |
2309 | + (REG_MAC_STA_ADDR + 4)) | |
2310 | + Addr[1] = Control; | |
2311 | + KeyValid = false; | |
2312 | + } else if ((Control & 0xff) == 0x5A) { | |
2313 | + KeyValid = true; | |
2314 | + Register = (u16) (Control >> 16); | |
2315 | + } else { | |
2316 | + /* assume data end while encount an invalid KEYWORD */ | |
2317 | + break; | |
2318 | + } | |
2319 | + } else { | |
2320 | + break; /* read error */ | |
2321 | + } | |
2322 | + i += 4; | |
2323 | + } | |
2324 | + | |
2325 | + *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); | |
2326 | + *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); | |
2327 | + | |
2328 | + if (is_valid_ether_addr(EthAddr)) { | |
2329 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); | |
2330 | + return 0; | |
2331 | + } | |
2332 | + return 1; | |
2333 | + } | |
2334 | + | |
2335 | + /* see if SPI flash exists? */ | |
2336 | + Addr[0] = 0; | |
2337 | + Addr[1] = 0; | |
2338 | + Register = 0; | |
2339 | + KeyValid = false; | |
2340 | + i = 0; | |
2341 | + while (1) { | |
2342 | + if (atl2_spi_read(hw, i + 0x1f000, &Control)) { | |
2343 | + if (KeyValid) { | |
2344 | + if (Register == REG_MAC_STA_ADDR) | |
2345 | + Addr[0] = Control; | |
2346 | + else if (Register == (REG_MAC_STA_ADDR + 4)) | |
2347 | + Addr[1] = Control; | |
2348 | + KeyValid = false; | |
2349 | + } else if ((Control & 0xff) == 0x5A) { | |
2350 | + KeyValid = true; | |
2351 | + Register = (u16) (Control >> 16); | |
2352 | + } else { | |
2353 | + break; /* data end */ | |
2354 | + } | |
2355 | + } else { | |
2356 | + break; /* read error */ | |
2357 | + } | |
2358 | + i += 4; | |
2359 | + } | |
2360 | + | |
2361 | + *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); | |
2362 | + *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); | |
2363 | + if (is_valid_ether_addr(EthAddr)) { | |
2364 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); | |
2365 | + return 0; | |
2366 | + } | |
2367 | + /* maybe MAC-address is from BIOS */ | |
2368 | + Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); | |
2369 | + Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); | |
2370 | + *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); | |
2371 | + *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); | |
2372 | + | |
2373 | + if (is_valid_ether_addr(EthAddr)) { | |
2374 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); | |
2375 | + return 0; | |
2376 | + } | |
2377 | + | |
2378 | + return 1; | |
2379 | +} | |
2380 | + | |
2381 | +/* | |
2382 | + * Reads the adapter's MAC address from the EEPROM | |
2383 | + * | |
2384 | + * hw - Struct containing variables accessed by shared code | |
2385 | + */ | |
2386 | +static s32 atl2_read_mac_addr(struct atl2_hw *hw) | |
2387 | +{ | |
2388 | + u16 i; | |
2389 | + | |
2390 | + if (get_permanent_address(hw)) { | |
2391 | + /* for test */ | |
2392 | + /* FIXME: shouldn't we use random_ether_addr() here? */ | |
2393 | + hw->perm_mac_addr[0] = 0x00; | |
2394 | + hw->perm_mac_addr[1] = 0x13; | |
2395 | + hw->perm_mac_addr[2] = 0x74; | |
2396 | + hw->perm_mac_addr[3] = 0x00; | |
2397 | + hw->perm_mac_addr[4] = 0x5c; | |
2398 | + hw->perm_mac_addr[5] = 0x38; | |
2399 | + } | |
2400 | + | |
2401 | + for (i = 0; i < NODE_ADDRESS_SIZE; i++) | |
2402 | + hw->mac_addr[i] = hw->perm_mac_addr[i]; | |
2403 | + | |
2404 | + return 0; | |
2405 | +} | |
2406 | + | |
2407 | +/* | |
2408 | + * Hashes an address to determine its location in the multicast table | |
2409 | + * | |
2410 | + * hw - Struct containing variables accessed by shared code | |
2411 | + * mc_addr - the multicast address to hash | |
2412 | + * | |
2413 | + * atl2_hash_mc_addr | |
2414 | + * purpose | |
2415 | + * set hash value for a multicast address | |
2416 | + * hash calcu processing : | |
2417 | + * 1. calcu 32bit CRC for multicast address | |
2418 | + * 2. reverse crc with MSB to LSB | |
2419 | + */ | |
2420 | +static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) | |
2421 | +{ | |
2422 | + u32 crc32, value; | |
2423 | + int i; | |
2424 | + | |
2425 | + value = 0; | |
2426 | + crc32 = ether_crc_le(6, mc_addr); | |
2427 | + | |
2428 | + for (i = 0; i < 32; i++) | |
2429 | + value |= (((crc32 >> i) & 1) << (31 - i)); | |
2430 | + | |
2431 | + return value; | |
2432 | +} | |
2433 | + | |
2434 | +/* | |
2435 | + * Sets the bit in the multicast table corresponding to the hash value. | |
2436 | + * | |
2437 | + * hw - Struct containing variables accessed by shared code | |
2438 | + * hash_value - Multicast address hash value | |
2439 | + */ | |
2440 | +static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) | |
2441 | +{ | |
2442 | + u32 hash_bit, hash_reg; | |
2443 | + u32 mta; | |
2444 | + | |
2445 | + /* The HASH Table is a register array of 2 32-bit registers. | |
2446 | + * It is treated like an array of 64 bits. We want to set | |
2447 | + * bit BitArray[hash_value]. So we figure out what register | |
2448 | + * the bit is in, read it, OR in the new bit, then write | |
2449 | + * back the new value. The register is determined by the | |
2450 | + * upper 7 bits of the hash value and the bit within that | |
2451 | + * register are determined by the lower 5 bits of the value. | |
2452 | + */ | |
2453 | + hash_reg = (hash_value >> 31) & 0x1; | |
2454 | + hash_bit = (hash_value >> 26) & 0x1F; | |
2455 | + | |
2456 | + mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); | |
2457 | + | |
2458 | + mta |= (1 << hash_bit); | |
2459 | + | |
2460 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); | |
2461 | +} | |
2462 | + | |
2463 | +/* | |
2464 | + * atl2_init_pcie - init PCIE module | |
2465 | + */ | |
2466 | +static void atl2_init_pcie(struct atl2_hw *hw) | |
2467 | +{ | |
2468 | + u32 value; | |
2469 | + value = LTSSM_TEST_MODE_DEF; | |
2470 | + ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); | |
2471 | + | |
2472 | + value = PCIE_DLL_TX_CTRL1_DEF; | |
2473 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); | |
2474 | +} | |
2475 | + | |
2476 | +static void atl2_init_flash_opcode(struct atl2_hw *hw) | |
2477 | +{ | |
2478 | + if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) | |
2479 | + hw->flash_vendor = 0; /* ATMEL */ | |
2480 | + | |
2481 | + /* Init OP table */ | |
2482 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, | |
2483 | + flash_table[hw->flash_vendor].cmdPROGRAM); | |
2484 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, | |
2485 | + flash_table[hw->flash_vendor].cmdSECTOR_ERASE); | |
2486 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, | |
2487 | + flash_table[hw->flash_vendor].cmdCHIP_ERASE); | |
2488 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, | |
2489 | + flash_table[hw->flash_vendor].cmdRDID); | |
2490 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, | |
2491 | + flash_table[hw->flash_vendor].cmdWREN); | |
2492 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, | |
2493 | + flash_table[hw->flash_vendor].cmdRDSR); | |
2494 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, | |
2495 | + flash_table[hw->flash_vendor].cmdWRSR); | |
2496 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, | |
2497 | + flash_table[hw->flash_vendor].cmdREAD); | |
2498 | +} | |
2499 | + | |
2500 | +/******************************************************************** | |
2501 | +* Performs basic configuration of the adapter. | |
2502 | +* | |
2503 | +* hw - Struct containing variables accessed by shared code | |
2504 | +* Assumes that the controller has previously been reset and is in a | |
2505 | +* post-reset uninitialized state. Initializes multicast table, | |
2506 | +* and Calls routines to setup link | |
2507 | +* Leaves the transmit and receive units disabled and uninitialized. | |
2508 | +********************************************************************/ | |
2509 | +static s32 atl2_init_hw(struct atl2_hw *hw) | |
2510 | +{ | |
2511 | + u32 ret_val = 0; | |
2512 | + | |
2513 | + atl2_init_pcie(hw); | |
2514 | + | |
2515 | + /* Zero out the Multicast HASH table */ | |
2516 | + /* clear the old settings from the multicast hash table */ | |
2517 | + ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); | |
2518 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); | |
2519 | + | |
2520 | + atl2_init_flash_opcode(hw); | |
2521 | + | |
2522 | + ret_val = atl2_phy_init(hw); | |
2523 | + | |
2524 | + return ret_val; | |
2525 | +} | |
2526 | + | |
2527 | +/* | |
2528 | + * Detects the current speed and duplex settings of the hardware. | |
2529 | + * | |
2530 | + * hw - Struct containing variables accessed by shared code | |
2531 | + * speed - Speed of the connection | |
2532 | + * duplex - Duplex setting of the connection | |
2533 | + */ | |
2534 | +static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, | |
2535 | + u16 *duplex) | |
2536 | +{ | |
2537 | + s32 ret_val; | |
2538 | + u16 phy_data; | |
2539 | + | |
2540 | + /* Read PHY Specific Status Register (17) */ | |
2541 | + ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); | |
2542 | + if (ret_val) | |
2543 | + return ret_val; | |
2544 | + | |
2545 | + if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) | |
2546 | + return ATLX_ERR_PHY_RES; | |
2547 | + | |
2548 | + switch (phy_data & MII_ATLX_PSSR_SPEED) { | |
2549 | + case MII_ATLX_PSSR_100MBS: | |
2550 | + *speed = SPEED_100; | |
2551 | + break; | |
2552 | + case MII_ATLX_PSSR_10MBS: | |
2553 | + *speed = SPEED_10; | |
2554 | + break; | |
2555 | + default: | |
2556 | + return ATLX_ERR_PHY_SPEED; | |
2557 | + break; | |
2558 | + } | |
2559 | + | |
2560 | + if (phy_data & MII_ATLX_PSSR_DPLX) | |
2561 | + *duplex = FULL_DUPLEX; | |
2562 | + else | |
2563 | + *duplex = HALF_DUPLEX; | |
2564 | + | |
2565 | + return 0; | |
2566 | +} | |
2567 | + | |
2568 | +/* | |
2569 | + * Reads the value from a PHY register | |
2570 | + * hw - Struct containing variables accessed by shared code | |
2571 | + * reg_addr - address of the PHY register to read | |
2572 | + */ | |
2573 | +static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) | |
2574 | +{ | |
2575 | + u32 val; | |
2576 | + int i; | |
2577 | + | |
2578 | + val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | | |
2579 | + MDIO_START | | |
2580 | + MDIO_SUP_PREAMBLE | | |
2581 | + MDIO_RW | | |
2582 | + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | |
2583 | + ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); | |
2584 | + | |
2585 | + wmb(); | |
2586 | + | |
2587 | + for (i = 0; i < MDIO_WAIT_TIMES; i++) { | |
2588 | + udelay(2); | |
2589 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | |
2590 | + if (!(val & (MDIO_START | MDIO_BUSY))) | |
2591 | + break; | |
2592 | + wmb(); | |
2593 | + } | |
2594 | + if (!(val & (MDIO_START | MDIO_BUSY))) { | |
2595 | + *phy_data = (u16)val; | |
2596 | + return 0; | |
2597 | + } | |
2598 | + | |
2599 | + return ATLX_ERR_PHY; | |
2600 | +} | |
2601 | + | |
2602 | +/* | |
2603 | + * Writes a value to a PHY register | |
2604 | + * hw - Struct containing variables accessed by shared code | |
2605 | + * reg_addr - address of the PHY register to write | |
2606 | + * data - data to write to the PHY | |
2607 | + */ | |
2608 | +static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) | |
2609 | +{ | |
2610 | + int i; | |
2611 | + u32 val; | |
2612 | + | |
2613 | + val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | | |
2614 | + (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | | |
2615 | + MDIO_SUP_PREAMBLE | | |
2616 | + MDIO_START | | |
2617 | + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | |
2618 | + ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); | |
2619 | + | |
2620 | + wmb(); | |
2621 | + | |
2622 | + for (i = 0; i < MDIO_WAIT_TIMES; i++) { | |
2623 | + udelay(2); | |
2624 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | |
2625 | + if (!(val & (MDIO_START | MDIO_BUSY))) | |
2626 | + break; | |
2627 | + | |
2628 | + wmb(); | |
2629 | + } | |
2630 | + | |
2631 | + if (!(val & (MDIO_START | MDIO_BUSY))) | |
2632 | + return 0; | |
2633 | + | |
2634 | + return ATLX_ERR_PHY; | |
2635 | +} | |
2636 | + | |
2637 | +/* | |
2638 | + * Configures PHY autoneg and flow control advertisement settings | |
2639 | + * | |
2640 | + * hw - Struct containing variables accessed by shared code | |
2641 | + */ | |
2642 | +static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) | |
2643 | +{ | |
2644 | + s32 ret_val; | |
2645 | + s16 mii_autoneg_adv_reg; | |
2646 | + | |
2647 | + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
2648 | + mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; | |
2649 | + | |
2650 | + /* Need to parse autoneg_advertised and set up | |
2651 | + * the appropriate PHY registers. First we will parse for | |
2652 | + * autoneg_advertised software override. Since we can advertise | |
2653 | + * a plethora of combinations, we need to check each bit | |
2654 | + * individually. | |
2655 | + */ | |
2656 | + | |
2657 | + /* First we clear all the 10/100 mb speed bits in the Auto-Neg | |
2658 | + * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
2659 | + * the 1000Base-T Control Register (Address 9). */ | |
2660 | + mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; | |
2661 | + | |
2662 | + /* Need to parse MediaType and setup the | |
2663 | + * appropriate PHY registers. */ | |
2664 | + switch (hw->MediaType) { | |
2665 | + case MEDIA_TYPE_AUTO_SENSOR: | |
2666 | + mii_autoneg_adv_reg |= | |
2667 | + (MII_AR_10T_HD_CAPS | | |
2668 | + MII_AR_10T_FD_CAPS | | |
2669 | + MII_AR_100TX_HD_CAPS| | |
2670 | + MII_AR_100TX_FD_CAPS); | |
2671 | + hw->autoneg_advertised = | |
2672 | + ADVERTISE_10_HALF | | |
2673 | + ADVERTISE_10_FULL | | |
2674 | + ADVERTISE_100_HALF| | |
2675 | + ADVERTISE_100_FULL; | |
2676 | + break; | |
2677 | + case MEDIA_TYPE_100M_FULL: | |
2678 | + mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; | |
2679 | + hw->autoneg_advertised = ADVERTISE_100_FULL; | |
2680 | + break; | |
2681 | + case MEDIA_TYPE_100M_HALF: | |
2682 | + mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; | |
2683 | + hw->autoneg_advertised = ADVERTISE_100_HALF; | |
2684 | + break; | |
2685 | + case MEDIA_TYPE_10M_FULL: | |
2686 | + mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; | |
2687 | + hw->autoneg_advertised = ADVERTISE_10_FULL; | |
2688 | + break; | |
2689 | + default: | |
2690 | + mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; | |
2691 | + hw->autoneg_advertised = ADVERTISE_10_HALF; | |
2692 | + break; | |
2693 | + } | |
2694 | + | |
2695 | + /* flow control fixed to enable all */ | |
2696 | + mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); | |
2697 | + | |
2698 | + hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; | |
2699 | + | |
2700 | + ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); | |
2701 | + | |
2702 | + if (ret_val) | |
2703 | + return ret_val; | |
2704 | + | |
2705 | + return 0; | |
2706 | +} | |
2707 | + | |
2708 | +/* | |
2709 | + * Resets the PHY and make all config validate | |
2710 | + * | |
2711 | + * hw - Struct containing variables accessed by shared code | |
2712 | + * | |
2713 | + * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) | |
2714 | + */ | |
2715 | +static s32 atl2_phy_commit(struct atl2_hw *hw) | |
2716 | +{ | |
2717 | + s32 ret_val; | |
2718 | + u16 phy_data; | |
2719 | + | |
2720 | + phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; | |
2721 | + ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); | |
2722 | + if (ret_val) { | |
2723 | + u32 val; | |
2724 | + int i; | |
2725 | + /* pcie serdes link may be down ! */ | |
2726 | + for (i = 0; i < 25; i++) { | |
2727 | + msleep(1); | |
2728 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | |
2729 | + if (!(val & (MDIO_START | MDIO_BUSY))) | |
2730 | + break; | |
2731 | + } | |
2732 | + | |
2733 | + if (0 != (val & (MDIO_START | MDIO_BUSY))) { | |
2734 | + printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); | |
2735 | + return ret_val; | |
2736 | + } | |
2737 | + } | |
2738 | + return 0; | |
2739 | +} | |
2740 | + | |
2741 | +static s32 atl2_phy_init(struct atl2_hw *hw) | |
2742 | +{ | |
2743 | + s32 ret_val; | |
2744 | + u16 phy_val; | |
2745 | + | |
2746 | + if (hw->phy_configured) | |
2747 | + return 0; | |
2748 | + | |
2749 | + /* Enable PHY */ | |
2750 | + ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); | |
2751 | + ATL2_WRITE_FLUSH(hw); | |
2752 | + msleep(1); | |
2753 | + | |
2754 | + /* check if the PHY is in powersaving mode */ | |
2755 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); | |
2756 | + atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); | |
2757 | + | |
2758 | + /* 024E / 124E 0r 0274 / 1274 ? */ | |
2759 | + if (phy_val & 0x1000) { | |
2760 | + phy_val &= ~0x1000; | |
2761 | + atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); | |
2762 | + } | |
2763 | + | |
2764 | + msleep(1); | |
2765 | + | |
2766 | + /*Enable PHY LinkChange Interrupt */ | |
2767 | + ret_val = atl2_write_phy_reg(hw, 18, 0xC00); | |
2768 | + if (ret_val) | |
2769 | + return ret_val; | |
2770 | + | |
2771 | + /* setup AutoNeg parameters */ | |
2772 | + ret_val = atl2_phy_setup_autoneg_adv(hw); | |
2773 | + if (ret_val) | |
2774 | + return ret_val; | |
2775 | + | |
2776 | + /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ | |
2777 | + ret_val = atl2_phy_commit(hw); | |
2778 | + if (ret_val) | |
2779 | + return ret_val; | |
2780 | + | |
2781 | + hw->phy_configured = true; | |
2782 | + | |
2783 | + return ret_val; | |
2784 | +} | |
2785 | + | |
2786 | +static void atl2_set_mac_addr(struct atl2_hw *hw) | |
2787 | +{ | |
2788 | + u32 value; | |
2789 | + /* 00-0B-6A-F6-00-DC | |
2790 | + * 0: 6AF600DC 1: 000B | |
2791 | + * low dword */ | |
2792 | + value = (((u32)hw->mac_addr[2]) << 24) | | |
2793 | + (((u32)hw->mac_addr[3]) << 16) | | |
2794 | + (((u32)hw->mac_addr[4]) << 8) | | |
2795 | + (((u32)hw->mac_addr[5])); | |
2796 | + ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); | |
2797 | + /* hight dword */ | |
2798 | + value = (((u32)hw->mac_addr[0]) << 8) | | |
2799 | + (((u32)hw->mac_addr[1])); | |
2800 | + ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); | |
2801 | +} | |
2802 | + | |
2803 | +/* | |
2804 | + * check_eeprom_exist | |
2805 | + * return 0 if eeprom exist | |
2806 | + */ | |
2807 | +static int atl2_check_eeprom_exist(struct atl2_hw *hw) | |
2808 | +{ | |
2809 | + u32 value; | |
2810 | + | |
2811 | + value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | |
2812 | + if (value & SPI_FLASH_CTRL_EN_VPD) { | |
2813 | + value &= ~SPI_FLASH_CTRL_EN_VPD; | |
2814 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | |
2815 | + } | |
2816 | + value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); | |
2817 | + return ((value & 0xFF00) == 0x6C00) ? 0 : 1; | |
2818 | +} | |
2819 | + | |
2820 | +/* FIXME: This doesn't look right. -- CHS */ | |
2821 | +static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) | |
2822 | +{ | |
2823 | + return true; | |
2824 | +} | |
2825 | + | |
2826 | +static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) | |
2827 | +{ | |
2828 | + int i; | |
2829 | + u32 Control; | |
2830 | + | |
2831 | + if (Offset & 0x3) | |
2832 | + return false; /* address do not align */ | |
2833 | + | |
2834 | + ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); | |
2835 | + Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; | |
2836 | + ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); | |
2837 | + | |
2838 | + for (i = 0; i < 10; i++) { | |
2839 | + msleep(2); | |
2840 | + Control = ATL2_READ_REG(hw, REG_VPD_CAP); | |
2841 | + if (Control & VPD_CAP_VPD_FLAG) | |
2842 | + break; | |
2843 | + } | |
2844 | + | |
2845 | + if (Control & VPD_CAP_VPD_FLAG) { | |
2846 | + *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); | |
2847 | + return true; | |
2848 | + } | |
2849 | + return false; /* timeout */ | |
2850 | +} | |
2851 | + | |
2852 | +static void atl2_force_ps(struct atl2_hw *hw) | |
2853 | +{ | |
2854 | + u16 phy_val; | |
2855 | + | |
2856 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); | |
2857 | + atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); | |
2858 | + atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); | |
2859 | + | |
2860 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); | |
2861 | + atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); | |
2862 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); | |
2863 | + atl2_write_phy_reg(hw, MII_DBG_DATA, 0); | |
2864 | +} | |
2865 | + | |
2866 | +/* This is the only thing that needs to be changed to adjust the | |
2867 | + * maximum number of ports that the driver can manage. | |
2868 | + */ | |
2869 | +#define ATL2_MAX_NIC 4 | |
2870 | + | |
2871 | +#define OPTION_UNSET -1 | |
2872 | +#define OPTION_DISABLED 0 | |
2873 | +#define OPTION_ENABLED 1 | |
2874 | + | |
2875 | +/* All parameters are treated the same, as an integer array of values. | |
2876 | + * This macro just reduces the need to repeat the same declaration code | |
2877 | + * over and over (plus this helps to avoid typo bugs). | |
2878 | + */ | |
2879 | +#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} | |
2880 | +#ifndef module_param_array | |
2881 | +/* Module Parameters are always initialized to -1, so that the driver | |
2882 | + * can tell the difference between no user specified value or the | |
2883 | + * user asking for the default value. | |
2884 | + * The true default values are loaded in when atl2_check_options is called. | |
2885 | + * | |
2886 | + * This is a GCC extension to ANSI C. | |
2887 | + * See the item "Labeled Elements in Initializers" in the section | |
2888 | + * "Extensions to the C Language Family" of the GCC documentation. | |
2889 | + */ | |
2890 | + | |
2891 | +#define ATL2_PARAM(X, desc) \ | |
2892 | + static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ | |
2893 | + MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ | |
2894 | + MODULE_PARM_DESC(X, desc); | |
2895 | +#else | |
2896 | +#define ATL2_PARAM(X, desc) \ | |
2897 | + static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ | |
2898 | + static int num_##X = 0; \ | |
2899 | + module_param_array_named(X, X, int, &num_##X, 0); \ | |
2900 | + MODULE_PARM_DESC(X, desc); | |
2901 | +#endif | |
2902 | + | |
2903 | +/* | |
2904 | + * Transmit Memory Size | |
2905 | + * Valid Range: 64-2048 | |
2906 | + * Default Value: 128 | |
2907 | + */ | |
2908 | +#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ | |
2909 | +#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ | |
2910 | +#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ | |
2911 | +ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); | |
2912 | + | |
2913 | +/* | |
2914 | + * Receive Memory Block Count | |
2915 | + * Valid Range: 16-512 | |
2916 | + * Default Value: 128 | |
2917 | + */ | |
2918 | +#define ATL2_MIN_RXD_COUNT 16 | |
2919 | +#define ATL2_MAX_RXD_COUNT 512 | |
2920 | +#define ATL2_DEFAULT_RXD_COUNT 64 | |
2921 | +ATL2_PARAM(RxMemBlock, "Number of receive memory block"); | |
2922 | + | |
2923 | +/* | |
2924 | + * User Specified MediaType Override | |
2925 | + * | |
2926 | + * Valid Range: 0-5 | |
2927 | + * - 0 - auto-negotiate at all supported speeds | |
2928 | + * - 1 - only link at 1000Mbps Full Duplex | |
2929 | + * - 2 - only link at 100Mbps Full Duplex | |
2930 | + * - 3 - only link at 100Mbps Half Duplex | |
2931 | + * - 4 - only link at 10Mbps Full Duplex | |
2932 | + * - 5 - only link at 10Mbps Half Duplex | |
2933 | + * Default Value: 0 | |
2934 | + */ | |
2935 | +ATL2_PARAM(MediaType, "MediaType Select"); | |
2936 | + | |
2937 | +/* | |
2938 | + * Interrupt Moderate Timer in units of 2048 ns (~2 us) | |
2939 | + * Valid Range: 10-65535 | |
2940 | + * Default Value: 45000(90ms) | |
2941 | + */ | |
2942 | +#define INT_MOD_DEFAULT_CNT 100 /* 200us */ | |
2943 | +#define INT_MOD_MAX_CNT 65000 | |
2944 | +#define INT_MOD_MIN_CNT 50 | |
2945 | +ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); | |
2946 | + | |
2947 | +/* | |
2948 | + * FlashVendor | |
2949 | + * Valid Range: 0-2 | |
2950 | + * 0 - Atmel | |
2951 | + * 1 - SST | |
2952 | + * 2 - ST | |
2953 | + */ | |
2954 | +ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); | |
2955 | + | |
2956 | +#define AUTONEG_ADV_DEFAULT 0x2F | |
2957 | +#define AUTONEG_ADV_MASK 0x2F | |
2958 | +#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL | |
2959 | + | |
2960 | +#define FLASH_VENDOR_DEFAULT 0 | |
2961 | +#define FLASH_VENDOR_MIN 0 | |
2962 | +#define FLASH_VENDOR_MAX 2 | |
2963 | + | |
2964 | +struct atl2_option { | |
2965 | + enum { enable_option, range_option, list_option } type; | |
2966 | + char *name; | |
2967 | + char *err; | |
2968 | + int def; | |
2969 | + union { | |
2970 | + struct { /* range_option info */ | |
2971 | + int min; | |
2972 | + int max; | |
2973 | + } r; | |
2974 | + struct { /* list_option info */ | |
2975 | + int nr; | |
2976 | + struct atl2_opt_list { int i; char *str; } *p; | |
2977 | + } l; | |
2978 | + } arg; | |
2979 | +}; | |
2980 | + | |
2981 | +static int __devinit atl2_validate_option(int *value, struct atl2_option *opt) | |
2982 | +{ | |
2983 | + int i; | |
2984 | + struct atl2_opt_list *ent; | |
2985 | + | |
2986 | + if (*value == OPTION_UNSET) { | |
2987 | + *value = opt->def; | |
2988 | + return 0; | |
2989 | + } | |
2990 | + | |
2991 | + switch (opt->type) { | |
2992 | + case enable_option: | |
2993 | + switch (*value) { | |
2994 | + case OPTION_ENABLED: | |
2995 | + printk(KERN_INFO "%s Enabled\n", opt->name); | |
2996 | + return 0; | |
2997 | + break; | |
2998 | + case OPTION_DISABLED: | |
2999 | + printk(KERN_INFO "%s Disabled\n", opt->name); | |
3000 | + return 0; | |
3001 | + break; | |
3002 | + } | |
3003 | + break; | |
3004 | + case range_option: | |
3005 | + if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { | |
3006 | + printk(KERN_INFO "%s set to %i\n", opt->name, *value); | |
3007 | + return 0; | |
3008 | + } | |
3009 | + break; | |
3010 | + case list_option: | |
3011 | + for (i = 0; i < opt->arg.l.nr; i++) { | |
3012 | + ent = &opt->arg.l.p[i]; | |
3013 | + if (*value == ent->i) { | |
3014 | + if (ent->str[0] != '\0') | |
3015 | + printk(KERN_INFO "%s\n", ent->str); | |
3016 | + return 0; | |
3017 | + } | |
3018 | + } | |
3019 | + break; | |
3020 | + default: | |
3021 | + BUG(); | |
3022 | + } | |
3023 | + | |
3024 | + printk(KERN_INFO "Invalid %s specified (%i) %s\n", | |
3025 | + opt->name, *value, opt->err); | |
3026 | + *value = opt->def; | |
3027 | + return -1; | |
3028 | +} | |
3029 | + | |
3030 | +/* | |
3031 | + * atl2_check_options - Range Checking for Command Line Parameters | |
3032 | + * @adapter: board private structure | |
3033 | + * | |
3034 | + * This routine checks all command line parameters for valid user | |
3035 | + * input. If an invalid value is given, or if no user specified | |
3036 | + * value exists, a default value is used. The final value is stored | |
3037 | + * in a variable in the adapter structure. | |
3038 | + */ | |
3039 | +static void __devinit atl2_check_options(struct atl2_adapter *adapter) | |
3040 | +{ | |
3041 | + int val; | |
3042 | + struct atl2_option opt; | |
3043 | + int bd = adapter->bd_number; | |
3044 | + if (bd >= ATL2_MAX_NIC) { | |
3045 | + printk(KERN_NOTICE "Warning: no configuration for board #%i\n", | |
3046 | + bd); | |
3047 | + printk(KERN_NOTICE "Using defaults for all values\n"); | |
3048 | +#ifndef module_param_array | |
3049 | + bd = ATL2_MAX_NIC; | |
3050 | +#endif | |
3051 | + } | |
3052 | + | |
3053 | + /* Bytes of Transmit Memory */ | |
3054 | + opt.type = range_option; | |
3055 | + opt.name = "Bytes of Transmit Memory"; | |
3056 | + opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); | |
3057 | + opt.def = ATL2_DEFAULT_TX_MEMSIZE; | |
3058 | + opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; | |
3059 | + opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; | |
3060 | +#ifdef module_param_array | |
3061 | + if (num_TxMemSize > bd) { | |
3062 | +#endif | |
3063 | + val = TxMemSize[bd]; | |
3064 | + atl2_validate_option(&val, &opt); | |
3065 | + adapter->txd_ring_size = ((u32) val) * 1024; | |
3066 | +#ifdef module_param_array | |
3067 | + } else | |
3068 | + adapter->txd_ring_size = ((u32)opt.def) * 1024; | |
3069 | +#endif | |
3070 | + /* txs ring size: */ | |
3071 | + adapter->txs_ring_size = adapter->txd_ring_size / 128; | |
3072 | + if (adapter->txs_ring_size > 160) | |
3073 | + adapter->txs_ring_size = 160; | |
3074 | + | |
3075 | + /* Receive Memory Block Count */ | |
3076 | + opt.type = range_option; | |
3077 | + opt.name = "Number of receive memory block"; | |
3078 | + opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); | |
3079 | + opt.def = ATL2_DEFAULT_RXD_COUNT; | |
3080 | + opt.arg.r.min = ATL2_MIN_RXD_COUNT; | |
3081 | + opt.arg.r.max = ATL2_MAX_RXD_COUNT; | |
3082 | +#ifdef module_param_array | |
3083 | + if (num_RxMemBlock > bd) { | |
3084 | +#endif | |
3085 | + val = RxMemBlock[bd]; | |
3086 | + atl2_validate_option(&val, &opt); | |
3087 | + adapter->rxd_ring_size = (u32)val; | |
3088 | + /* FIXME */ | |
3089 | + /* ((u16)val)&~1; */ /* even number */ | |
3090 | +#ifdef module_param_array | |
3091 | + } else | |
3092 | + adapter->rxd_ring_size = (u32)opt.def; | |
3093 | +#endif | |
3094 | + /* init RXD Flow control value */ | |
3095 | + adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; | |
3096 | + adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > | |
3097 | + (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : | |
3098 | + (adapter->rxd_ring_size / 12); | |
3099 | + | |
3100 | + /* Interrupt Moderate Timer */ | |
3101 | + opt.type = range_option; | |
3102 | + opt.name = "Interrupt Moderate Timer"; | |
3103 | + opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); | |
3104 | + opt.def = INT_MOD_DEFAULT_CNT; | |
3105 | + opt.arg.r.min = INT_MOD_MIN_CNT; | |
3106 | + opt.arg.r.max = INT_MOD_MAX_CNT; | |
3107 | +#ifdef module_param_array | |
3108 | + if (num_IntModTimer > bd) { | |
3109 | +#endif | |
3110 | + val = IntModTimer[bd]; | |
3111 | + atl2_validate_option(&val, &opt); | |
3112 | + adapter->imt = (u16) val; | |
3113 | +#ifdef module_param_array | |
3114 | + } else | |
3115 | + adapter->imt = (u16)(opt.def); | |
3116 | +#endif | |
3117 | + /* Flash Vendor */ | |
3118 | + opt.type = range_option; | |
3119 | + opt.name = "SPI Flash Vendor"; | |
3120 | + opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); | |
3121 | + opt.def = FLASH_VENDOR_DEFAULT; | |
3122 | + opt.arg.r.min = FLASH_VENDOR_MIN; | |
3123 | + opt.arg.r.max = FLASH_VENDOR_MAX; | |
3124 | +#ifdef module_param_array | |
3125 | + if (num_FlashVendor > bd) { | |
3126 | +#endif | |
3127 | + val = FlashVendor[bd]; | |
3128 | + atl2_validate_option(&val, &opt); | |
3129 | + adapter->hw.flash_vendor = (u8) val; | |
3130 | +#ifdef module_param_array | |
3131 | + } else | |
3132 | + adapter->hw.flash_vendor = (u8)(opt.def); | |
3133 | +#endif | |
3134 | + /* MediaType */ | |
3135 | + opt.type = range_option; | |
3136 | + opt.name = "Speed/Duplex Selection"; | |
3137 | + opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); | |
3138 | + opt.def = MEDIA_TYPE_AUTO_SENSOR; | |
3139 | + opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; | |
3140 | + opt.arg.r.max = MEDIA_TYPE_10M_HALF; | |
3141 | +#ifdef module_param_array | |
3142 | + if (num_MediaType > bd) { | |
3143 | +#endif | |
3144 | + val = MediaType[bd]; | |
3145 | + atl2_validate_option(&val, &opt); | |
3146 | + adapter->hw.MediaType = (u16) val; | |
3147 | +#ifdef module_param_array | |
3148 | + } else | |
3149 | + adapter->hw.MediaType = (u16)(opt.def); | |
3150 | +#endif | |
3151 | +} | |
3152 | --- /dev/null | |
3153 | +++ b/drivers/net/atlx/atl2.h | |
3154 | @@ -0,0 +1,530 @@ | |
3155 | +/* atl2.h -- atl2 driver definitions | |
3156 | + * | |
3157 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. | |
3158 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> | |
3159 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> | |
3160 | + * | |
3161 | + * Derived from Intel e1000 driver | |
3162 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
3163 | + * | |
3164 | + * This program is free software; you can redistribute it and/or modify it | |
3165 | + * under the terms of the GNU General Public License as published by the Free | |
3166 | + * Software Foundation; either version 2 of the License, or (at your option) | |
3167 | + * any later version. | |
3168 | + * | |
3169 | + * This program is distributed in the hope that it will be useful, but WITHOUT | |
3170 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
3171 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
3172 | + * more details. | |
3173 | + * | |
3174 | + * You should have received a copy of the GNU General Public License along with | |
3175 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | |
3176 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
3177 | + */ | |
3178 | + | |
3179 | +#ifndef _ATL2_H_ | |
3180 | +#define _ATL2_H_ | |
3181 | + | |
3182 | +#include <asm/atomic.h> | |
3183 | +#include <linux/netdevice.h> | |
3184 | + | |
3185 | +#ifndef _ATL2_HW_H_ | |
3186 | +#define _ATL2_HW_H_ | |
3187 | + | |
3188 | +#ifndef _ATL2_OSDEP_H_ | |
3189 | +#define _ATL2_OSDEP_H_ | |
3190 | + | |
3191 | +#include <linux/pci.h> | |
3192 | +#include <linux/delay.h> | |
3193 | +#include <linux/interrupt.h> | |
3194 | +#include <linux/if_ether.h> | |
3195 | + | |
3196 | +#include "atlx.h" | |
3197 | + | |
3198 | +#ifdef ETHTOOL_OPS_COMPAT | |
3199 | +extern int ethtool_ioctl(struct ifreq *ifr); | |
3200 | +#endif | |
3201 | + | |
3202 | +#define PCI_COMMAND_REGISTER PCI_COMMAND | |
3203 | +#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE | |
3204 | +#define ETH_ADDR_LEN ETH_ALEN | |
3205 | + | |
3206 | +#define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \ | |
3207 | + ((a)->hw_addr + (reg)))) | |
3208 | + | |
3209 | +#define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr)) | |
3210 | + | |
3211 | +#define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg))) | |
3212 | + | |
3213 | +#define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \ | |
3214 | + ((a)->hw_addr + (reg)))) | |
3215 | + | |
3216 | +#define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg))) | |
3217 | + | |
3218 | +#define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \ | |
3219 | + ((a)->hw_addr + (reg)))) | |
3220 | + | |
3221 | +#define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg))) | |
3222 | + | |
3223 | +#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \ | |
3224 | + (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2)))) | |
3225 | + | |
3226 | +#define ATL2_READ_REG_ARRAY(a, reg, offset) \ | |
3227 | + (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2))) | |
3228 | + | |
3229 | +#endif /* _ATL2_OSDEP_H_ */ | |
3230 | + | |
3231 | +struct atl2_adapter; | |
3232 | +struct atl2_hw; | |
3233 | + | |
3234 | +/* function prototype */ | |
3235 | +static s32 atl2_reset_hw(struct atl2_hw *hw); | |
3236 | +static s32 atl2_read_mac_addr(struct atl2_hw *hw); | |
3237 | +static s32 atl2_init_hw(struct atl2_hw *hw); | |
3238 | +static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, | |
3239 | + u16 *duplex); | |
3240 | +static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr); | |
3241 | +static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value); | |
3242 | +static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data); | |
3243 | +static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data); | |
3244 | +static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); | |
3245 | +static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); | |
3246 | +static void atl2_set_mac_addr(struct atl2_hw *hw); | |
3247 | +static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue); | |
3248 | +static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value); | |
3249 | +static s32 atl2_phy_init(struct atl2_hw *hw); | |
3250 | +static int atl2_check_eeprom_exist(struct atl2_hw *hw); | |
3251 | +static void atl2_force_ps(struct atl2_hw *hw); | |
3252 | + | |
3253 | +/* register definition */ | |
3254 | + | |
3255 | +/* Block IDLE Status Register */ | |
3256 | +#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC is non-IDLE */ | |
3257 | +#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC is non-IDLE */ | |
3258 | +#define IDLE_STATUS_DMAR 8 /* 1: DMAR is non-IDLE */ | |
3259 | +#define IDLE_STATUS_DMAW 4 /* 1: DMAW is non-IDLE */ | |
3260 | + | |
3261 | +/* MDIO Control Register */ | |
3262 | +#define MDIO_WAIT_TIMES 10 | |
3263 | + | |
3264 | +/* MAC Control Register */ | |
3265 | +#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: TX max backoff */ | |
3266 | +#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: 25MHz from phy */ | |
3267 | +#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28 | |
3268 | +#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* MAC retry buf x32B */ | |
3269 | + | |
3270 | +/* Internal SRAM Partition Register */ | |
3271 | +#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM | |
3272 | + * default: 2byte*1024 */ | |
3273 | +#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM | |
3274 | + * default: 2byte*1024 */ | |
3275 | + | |
3276 | +/* Descriptor Control register */ | |
3277 | +#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit | |
3278 | + * Data Mem low 32-bit(dword align) */ | |
3279 | +#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by | |
3280 | + * double word , max 256KB) */ | |
3281 | +#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit | |
3282 | + * Status Memory low 32-bit(dword word | |
3283 | + * align) */ | |
3284 | +#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047 | |
3285 | + * bytes. */ | |
3286 | +#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit | |
3287 | + * Status Memory low 32-bit(unit 8 | |
3288 | + * bytes) */ | |
3289 | +#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer | |
3290 | + * number (unit 1536bytes, max | |
3291 | + * 1536*2047) */ | |
3292 | + | |
3293 | +/* DMAR Control Register */ | |
3294 | +#define REG_DMAR 0x1580 | |
3295 | +#define DMAR_EN 0x1 /* 1: Enable DMAR */ | |
3296 | + | |
3297 | +/* TX Cur-Through (early tx threshold) Control Register */ | |
3298 | +#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet | |
3299 | + * threshold(unit word) */ | |
3300 | + | |
3301 | +/* DMAW Control Register */ | |
3302 | +#define REG_DMAW 0x15A0 | |
3303 | +#define DMAW_EN 0x1 | |
3304 | + | |
3305 | +/* Flow control register */ | |
3306 | +#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow | |
3307 | + * threshold configuration register */ | |
3308 | +#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow | |
3309 | + * threshold configuration register */ | |
3310 | + | |
3311 | +/* Mailbox Register */ | |
3312 | +#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */ | |
3313 | +#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */ | |
3314 | + | |
3315 | +/* Interrupt Status Register */ | |
3316 | +#define ISR_TIMER 1 /* Interrupt when Timer counts down to zero */ | |
3317 | +#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set | |
3318 | + * when SW_MAN_INT_EN is set in Table 51 | |
3319 | + * Selene Master Control Register | |
3320 | + * (Offset 0x1400). */ | |
3321 | +#define ISR_RXF_OV 4 /* RXF overflow interrupt */ | |
3322 | +#define ISR_TXF_UR 8 /* TXF underrun interrupt */ | |
3323 | +#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full | |
3324 | + * interrupt */ | |
3325 | +#define ISR_RXS_OV 0x20 /* Internal receive status buffer full | |
3326 | + * interrupt */ | |
3327 | +#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */ | |
3328 | +#define ISR_HOST_TXD_UR 0x80 | |
3329 | +#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */ | |
3330 | +#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should | |
3331 | + * do Reset */ | |
3332 | +#define ISR_DMAW_TO_RST 0x400 | |
3333 | +#define ISR_PHY 0x800 /* phy interrupt */ | |
3334 | +#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written | |
3335 | + * to host */ | |
3336 | +#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written | |
3337 | + * to host. */ | |
3338 | +#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one | |
3339 | + * packet */ | |
3340 | + | |
3341 | +#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\ | |
3342 | + ISR_TS_UPDATE | ISR_TX_EARLY) | |
3343 | +#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\ | |
3344 | + ISR_RS_UPDATE) | |
3345 | + | |
3346 | +#define IMR_NORMAL_MASK (\ | |
3347 | + /*ISR_LINK_CHG |*/\ | |
3348 | + ISR_MANUAL |\ | |
3349 | + ISR_DMAR_TO_RST |\ | |
3350 | + ISR_DMAW_TO_RST |\ | |
3351 | + ISR_PHY |\ | |
3352 | + ISR_PHY_LINKDOWN |\ | |
3353 | + ISR_TS_UPDATE |\ | |
3354 | + ISR_RS_UPDATE) | |
3355 | + | |
3356 | +/* Receive MAC Statistics Registers */ | |
3357 | +#define REG_STS_RX_PAUSE 0x1700 /* Num pause packets received */ | |
3358 | +#define REG_STS_RXD_OV 0x1704 /* Num frames dropped due to RX | |
3359 | + * FIFO overflow */ | |
3360 | +#define REG_STS_RXS_OV 0x1708 /* Num frames dropped due to RX | |
3361 | + * Status Buffer Overflow */ | |
3362 | +#define REG_STS_RX_FILTER 0x170C /* Num packets dropped due to | |
3363 | + * address filtering */ | |
3364 | + | |
3365 | +/* MII definitions */ | |
3366 | + | |
3367 | +/* PHY Common Register */ | |
3368 | +#define MII_SMARTSPEED 0x14 | |
3369 | +#define MII_DBG_ADDR 0x1D | |
3370 | +#define MII_DBG_DATA 0x1E | |
3371 | + | |
3372 | +/* PCI Command Register Bit Definitions */ | |
3373 | +#define PCI_REG_COMMAND 0x04 | |
3374 | +#define CMD_IO_SPACE 0x0001 | |
3375 | +#define CMD_MEMORY_SPACE 0x0002 | |
3376 | +#define CMD_BUS_MASTER 0x0004 | |
3377 | + | |
3378 | +#define MEDIA_TYPE_100M_FULL 1 | |
3379 | +#define MEDIA_TYPE_100M_HALF 2 | |
3380 | +#define MEDIA_TYPE_10M_FULL 3 | |
3381 | +#define MEDIA_TYPE_10M_HALF 4 | |
3382 | + | |
3383 | +#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */ | |
3384 | + | |
3385 | +/* The size (in bytes) of a ethernet packet */ | |
3386 | +#define ENET_HEADER_SIZE 14 | |
3387 | +#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */ | |
3388 | +#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */ | |
3389 | +#define ETHERNET_FCS_SIZE 4 | |
3390 | +#define MAX_JUMBO_FRAME_SIZE 0x2000 | |
3391 | +#define VLAN_SIZE 4 | |
3392 | + | |
3393 | +struct tx_pkt_header { | |
3394 | + unsigned pkt_size:11; | |
3395 | + unsigned:4; /* reserved */ | |
3396 | + unsigned ins_vlan:1; /* txmac should insert vlan */ | |
3397 | + unsigned short vlan; /* vlan tag */ | |
3398 | +}; | |
3399 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ | |
3400 | +#define TX_PKT_HEADER_SIZE_MASK 0x7FF | |
3401 | +#define TX_PKT_HEADER_SIZE_SHIFT 0 | |
3402 | +#define TX_PKT_HEADER_INS_VLAN_MASK 0x1 | |
3403 | +#define TX_PKT_HEADER_INS_VLAN_SHIFT 15 | |
3404 | +#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF | |
3405 | +#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16 | |
3406 | + | |
3407 | +struct tx_pkt_status { | |
3408 | + unsigned pkt_size:11; | |
3409 | + unsigned:5; /* reserved */ | |
3410 | + unsigned ok:1; /* current packet transmitted without error */ | |
3411 | + unsigned bcast:1; /* broadcast packet */ | |
3412 | + unsigned mcast:1; /* multicast packet */ | |
3413 | + unsigned pause:1; /* transmiited a pause frame */ | |
3414 | + unsigned ctrl:1; | |
3415 | + unsigned defer:1; /* current packet is xmitted with defer */ | |
3416 | + unsigned exc_defer:1; | |
3417 | + unsigned single_col:1; | |
3418 | + unsigned multi_col:1; | |
3419 | + unsigned late_col:1; | |
3420 | + unsigned abort_col:1; | |
3421 | + unsigned underun:1; /* current packet is aborted | |
3422 | + * due to txram underrun */ | |
3423 | + unsigned:3; /* reserved */ | |
3424 | + unsigned update:1; /* always 1'b1 in tx_status_buf */ | |
3425 | +}; | |
3426 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ | |
3427 | +#define TX_PKT_STATUS_SIZE_MASK 0x7FF | |
3428 | +#define TX_PKT_STATUS_SIZE_SHIFT 0 | |
3429 | +#define TX_PKT_STATUS_OK_MASK 0x1 | |
3430 | +#define TX_PKT_STATUS_OK_SHIFT 16 | |
3431 | +#define TX_PKT_STATUS_BCAST_MASK 0x1 | |
3432 | +#define TX_PKT_STATUS_BCAST_SHIFT 17 | |
3433 | +#define TX_PKT_STATUS_MCAST_MASK 0x1 | |
3434 | +#define TX_PKT_STATUS_MCAST_SHIFT 18 | |
3435 | +#define TX_PKT_STATUS_PAUSE_MASK 0x1 | |
3436 | +#define TX_PKT_STATUS_PAUSE_SHIFT 19 | |
3437 | +#define TX_PKT_STATUS_CTRL_MASK 0x1 | |
3438 | +#define TX_PKT_STATUS_CTRL_SHIFT 20 | |
3439 | +#define TX_PKT_STATUS_DEFER_MASK 0x1 | |
3440 | +#define TX_PKT_STATUS_DEFER_SHIFT 21 | |
3441 | +#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1 | |
3442 | +#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22 | |
3443 | +#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1 | |
3444 | +#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23 | |
3445 | +#define TX_PKT_STATUS_MULTI_COL_MASK 0x1 | |
3446 | +#define TX_PKT_STATUS_MULTI_COL_SHIFT 24 | |
3447 | +#define TX_PKT_STATUS_LATE_COL_MASK 0x1 | |
3448 | +#define TX_PKT_STATUS_LATE_COL_SHIFT 25 | |
3449 | +#define TX_PKT_STATUS_ABORT_COL_MASK 0x1 | |
3450 | +#define TX_PKT_STATUS_ABORT_COL_SHIFT 26 | |
3451 | +#define TX_PKT_STATUS_UNDERRUN_MASK 0x1 | |
3452 | +#define TX_PKT_STATUS_UNDERRUN_SHIFT 27 | |
3453 | +#define TX_PKT_STATUS_UPDATE_MASK 0x1 | |
3454 | +#define TX_PKT_STATUS_UPDATE_SHIFT 31 | |
3455 | + | |
3456 | +struct rx_pkt_status { | |
3457 | + unsigned pkt_size:11; /* packet size, max 2047 bytes */ | |
3458 | + unsigned:5; /* reserved */ | |
3459 | + unsigned ok:1; /* current packet received ok without error */ | |
3460 | + unsigned bcast:1; /* current packet is broadcast */ | |
3461 | + unsigned mcast:1; /* current packet is multicast */ | |
3462 | + unsigned pause:1; | |
3463 | + unsigned ctrl:1; | |
3464 | + unsigned crc:1; /* received a packet with crc error */ | |
3465 | + unsigned code:1; /* received a packet with code error */ | |
3466 | + unsigned runt:1; /* received a packet less than 64 bytes | |
3467 | + * with good crc */ | |
3468 | + unsigned frag:1; /* received a packet less than 64 bytes | |
3469 | + * with bad crc */ | |
3470 | + unsigned trunc:1; /* current frame truncated due to rxram full */ | |
3471 | + unsigned align:1; /* this packet is alignment error */ | |
3472 | + unsigned vlan:1; /* this packet has vlan */ | |
3473 | + unsigned:3; /* reserved */ | |
3474 | + unsigned update:1; | |
3475 | + unsigned short vtag; /* vlan tag */ | |
3476 | + unsigned:16; | |
3477 | +}; | |
3478 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ | |
3479 | +#define RX_PKT_STATUS_SIZE_MASK 0x7FF | |
3480 | +#define RX_PKT_STATUS_SIZE_SHIFT 0 | |
3481 | +#define RX_PKT_STATUS_OK_MASK 0x1 | |
3482 | +#define RX_PKT_STATUS_OK_SHIFT 16 | |
3483 | +#define RX_PKT_STATUS_BCAST_MASK 0x1 | |
3484 | +#define RX_PKT_STATUS_BCAST_SHIFT 17 | |
3485 | +#define RX_PKT_STATUS_MCAST_MASK 0x1 | |
3486 | +#define RX_PKT_STATUS_MCAST_SHIFT 18 | |
3487 | +#define RX_PKT_STATUS_PAUSE_MASK 0x1 | |
3488 | +#define RX_PKT_STATUS_PAUSE_SHIFT 19 | |
3489 | +#define RX_PKT_STATUS_CTRL_MASK 0x1 | |
3490 | +#define RX_PKT_STATUS_CTRL_SHIFT 20 | |
3491 | +#define RX_PKT_STATUS_CRC_MASK 0x1 | |
3492 | +#define RX_PKT_STATUS_CRC_SHIFT 21 | |
3493 | +#define RX_PKT_STATUS_CODE_MASK 0x1 | |
3494 | +#define RX_PKT_STATUS_CODE_SHIFT 22 | |
3495 | +#define RX_PKT_STATUS_RUNT_MASK 0x1 | |
3496 | +#define RX_PKT_STATUS_RUNT_SHIFT 23 | |
3497 | +#define RX_PKT_STATUS_FRAG_MASK 0x1 | |
3498 | +#define RX_PKT_STATUS_FRAG_SHIFT 24 | |
3499 | +#define RX_PKT_STATUS_TRUNK_MASK 0x1 | |
3500 | +#define RX_PKT_STATUS_TRUNK_SHIFT 25 | |
3501 | +#define RX_PKT_STATUS_ALIGN_MASK 0x1 | |
3502 | +#define RX_PKT_STATUS_ALIGN_SHIFT 26 | |
3503 | +#define RX_PKT_STATUS_VLAN_MASK 0x1 | |
3504 | +#define RX_PKT_STATUS_VLAN_SHIFT 27 | |
3505 | +#define RX_PKT_STATUS_UPDATE_MASK 0x1 | |
3506 | +#define RX_PKT_STATUS_UPDATE_SHIFT 31 | |
3507 | +#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF | |
3508 | +#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32 | |
3509 | + | |
3510 | +struct rx_desc { | |
3511 | + struct rx_pkt_status status; | |
3512 | + unsigned char packet[1536-sizeof(struct rx_pkt_status)]; | |
3513 | +}; | |
3514 | + | |
3515 | +enum atl2_speed_duplex { | |
3516 | + atl2_10_half = 0, | |
3517 | + atl2_10_full = 1, | |
3518 | + atl2_100_half = 2, | |
3519 | + atl2_100_full = 3 | |
3520 | +}; | |
3521 | + | |
3522 | +struct atl2_spi_flash_dev { | |
3523 | + const char *manu_name; /* manufacturer id */ | |
3524 | + /* op-code */ | |
3525 | + u8 cmdWRSR; | |
3526 | + u8 cmdREAD; | |
3527 | + u8 cmdPROGRAM; | |
3528 | + u8 cmdWREN; | |
3529 | + u8 cmdWRDI; | |
3530 | + u8 cmdRDSR; | |
3531 | + u8 cmdRDID; | |
3532 | + u8 cmdSECTOR_ERASE; | |
3533 | + u8 cmdCHIP_ERASE; | |
3534 | +}; | |
3535 | + | |
3536 | +/* Structure containing variables used by the shared code (atl2_hw.c) */ | |
3537 | +struct atl2_hw { | |
3538 | + u8 __iomem *hw_addr; | |
3539 | + void *back; | |
3540 | + | |
3541 | + u8 preamble_len; | |
3542 | + u8 max_retry; /* Retransmission maximum, afterwards the | |
3543 | + * packet will be discarded. */ | |
3544 | + u8 jam_ipg; /* IPG to start JAM for collision based flow | |
3545 | + * control in half-duplex mode. In unit of | |
3546 | + * 8-bit time. */ | |
3547 | + u8 ipgt; /* Desired back to back inter-packet gap. The | |
3548 | + * default is 96-bit time. */ | |
3549 | + u8 min_ifg; /* Minimum number of IFG to enforce in between | |
3550 | + * RX frames. Frame gap below such IFP is | |
3551 | + * dropped. */ | |
3552 | + u8 ipgr1; /* 64bit Carrier-Sense window */ | |
3553 | + u8 ipgr2; /* 96-bit IPG window */ | |
3554 | + u8 retry_buf; /* When half-duplex mode, should hold some | |
3555 | + * bytes for mac retry . (8*4bytes unit) */ | |
3556 | + | |
3557 | + u16 fc_rxd_hi; | |
3558 | + u16 fc_rxd_lo; | |
3559 | + u16 lcol; /* Collision Window */ | |
3560 | + u16 max_frame_size; | |
3561 | + | |
3562 | + u16 MediaType; | |
3563 | + u16 autoneg_advertised; | |
3564 | + u16 pci_cmd_word; | |
3565 | + | |
3566 | + u16 mii_autoneg_adv_reg; | |
3567 | + | |
3568 | + u32 mem_rang; | |
3569 | + u32 txcw; | |
3570 | + u32 mc_filter_type; | |
3571 | + u32 num_mc_addrs; | |
3572 | + u32 collision_delta; | |
3573 | + u32 tx_packet_delta; | |
3574 | + u16 phy_spd_default; | |
3575 | + | |
3576 | + u16 device_id; | |
3577 | + u16 vendor_id; | |
3578 | + u16 subsystem_id; | |
3579 | + u16 subsystem_vendor_id; | |
3580 | + u8 revision_id; | |
3581 | + | |
3582 | + /* spi flash */ | |
3583 | + u8 flash_vendor; | |
3584 | + | |
3585 | + u8 dma_fairness; | |
3586 | + u8 mac_addr[NODE_ADDRESS_SIZE]; | |
3587 | + u8 perm_mac_addr[NODE_ADDRESS_SIZE]; | |
3588 | + | |
3589 | + /* FIXME */ | |
3590 | + /* bool phy_preamble_sup; */ | |
3591 | + bool phy_configured; | |
3592 | +}; | |
3593 | + | |
3594 | +#endif /* _ATL2_HW_H_ */ | |
3595 | + | |
3596 | +struct atl2_ring_header { | |
3597 | + /* pointer to the descriptor ring memory */ | |
3598 | + void *desc; | |
3599 | + /* physical adress of the descriptor ring */ | |
3600 | + dma_addr_t dma; | |
3601 | + /* length of descriptor ring in bytes */ | |
3602 | + unsigned int size; | |
3603 | +}; | |
3604 | + | |
3605 | +/* board specific private data structure */ | |
3606 | +struct atl2_adapter { | |
3607 | + /* OS defined structs */ | |
3608 | + struct net_device *netdev; | |
3609 | + struct pci_dev *pdev; | |
3610 | + struct net_device_stats net_stats; | |
3611 | +#ifdef NETIF_F_HW_VLAN_TX | |
3612 | + struct vlan_group *vlgrp; | |
3613 | +#endif | |
3614 | + u32 wol; | |
3615 | + u16 link_speed; | |
3616 | + u16 link_duplex; | |
3617 | + | |
3618 | + spinlock_t stats_lock; | |
3619 | + spinlock_t tx_lock; | |
3620 | + | |
3621 | + struct work_struct reset_task; | |
3622 | + struct work_struct link_chg_task; | |
3623 | + struct timer_list watchdog_timer; | |
3624 | + struct timer_list phy_config_timer; | |
3625 | + | |
3626 | + unsigned long cfg_phy; | |
3627 | + bool mac_disabled; | |
3628 | + | |
3629 | + /* All Descriptor memory */ | |
3630 | + dma_addr_t ring_dma; | |
3631 | + void *ring_vir_addr; | |
3632 | + int ring_size; | |
3633 | + | |
3634 | + struct tx_pkt_header *txd_ring; | |
3635 | + dma_addr_t txd_dma; | |
3636 | + | |
3637 | + struct tx_pkt_status *txs_ring; | |
3638 | + dma_addr_t txs_dma; | |
3639 | + | |
3640 | + struct rx_desc *rxd_ring; | |
3641 | + dma_addr_t rxd_dma; | |
3642 | + | |
3643 | + u32 txd_ring_size; /* bytes per unit */ | |
3644 | + u32 txs_ring_size; /* dwords per unit */ | |
3645 | + u32 rxd_ring_size; /* 1536 bytes per unit */ | |
3646 | + | |
3647 | + /* read /write ptr: */ | |
3648 | + /* host */ | |
3649 | + u32 txd_write_ptr; | |
3650 | + u32 txs_next_clear; | |
3651 | + u32 rxd_read_ptr; | |
3652 | + | |
3653 | + /* nic */ | |
3654 | + atomic_t txd_read_ptr; | |
3655 | + atomic_t txs_write_ptr; | |
3656 | + u32 rxd_write_ptr; | |
3657 | + | |
3658 | + /* Interrupt Moderator timer ( 2us resolution) */ | |
3659 | + u16 imt; | |
3660 | + /* Interrupt Clear timer (2us resolution) */ | |
3661 | + u16 ict; | |
3662 | + | |
3663 | + unsigned long flags; | |
3664 | + /* structs defined in atl2_hw.h */ | |
3665 | + u32 bd_number; /* board number */ | |
3666 | + bool pci_using_64; | |
3667 | + bool have_msi; | |
3668 | + struct atl2_hw hw; | |
3669 | + | |
3670 | + u32 usr_cmd; | |
3671 | + /* FIXME */ | |
3672 | + /* u32 regs_buff[ATL2_REGS_LEN]; */ | |
3673 | + u32 pci_state[16]; | |
3674 | + | |
3675 | + u32 *config_space; | |
3676 | +}; | |
3677 | + | |
3678 | +enum atl2_state_t { | |
3679 | + __ATL2_TESTING, | |
3680 | + __ATL2_RESETTING, | |
3681 | + __ATL2_DOWN | |
3682 | +}; | |
3683 | + | |
3684 | +#endif /* _ATL2_H_ */ | |
3685 | --- a/drivers/net/atlx/Makefile | |
3686 | +++ b/drivers/net/atlx/Makefile | |
3687 | @@ -1 +1,3 @@ | |
3688 | obj-$(CONFIG_ATL1) += atl1.o | |
3689 | +obj-$(CONFIG_ATL2) += atl2.o | |
3690 | + | |
3691 | --- a/drivers/net/Kconfig | |
3692 | +++ b/drivers/net/Kconfig | |
3693 | @@ -1840,6 +1840,17 @@ config NE_H8300 | |
3694 | Say Y here if you want to use the NE2000 compatible | |
3695 | controller on the Renesas H8/300 processor. | |
3696 | ||
3697 | +config ATL2 | |
3698 | + tristate "Atheros L2 Fast Ethernet support" | |
3699 | + depends on PCI | |
3700 | + select CRC32 | |
3701 | + select MII | |
3702 | + help | |
3703 | + This driver supports the Atheros L2 fast ethernet adapter. | |
3704 | + | |
3705 | + To compile this driver as a module, choose M here. The module | |
3706 | + will be called atl2. | |
3707 | + | |
3708 | source "drivers/net/fs_enet/Kconfig" | |
3709 | ||
3710 | endif # NET_ETHERNET | |
3711 | --- a/drivers/net/Makefile | |
3712 | +++ b/drivers/net/Makefile | |
3713 | @@ -15,6 +15,7 @@ obj-$(CONFIG_EHEA) += ehea/ | |
3714 | obj-$(CONFIG_CAN) += can/ | |
3715 | obj-$(CONFIG_BONDING) += bonding/ | |
3716 | obj-$(CONFIG_ATL1) += atlx/ | |
3717 | +obj-$(CONFIG_ATL2) += atlx/ | |
3718 | obj-$(CONFIG_ATL1E) += atl1e/ | |
3719 | obj-$(CONFIG_GIANFAR) += gianfar_driver.o | |
3720 | obj-$(CONFIG_TEHUTI) += tehuti.o | |
3721 | --- a/include/linux/pci_ids.h | |
3722 | +++ b/include/linux/pci_ids.h | |
3723 | @@ -2222,6 +2222,7 @@ | |
3724 | ||
3725 | #define PCI_VENDOR_ID_ATTANSIC 0x1969 | |
3726 | #define PCI_DEVICE_ID_ATTANSIC_L1 0x1048 | |
3727 | +#define PCI_DEVICE_ID_ATTANSIC_L2 0x2048 | |
3728 | ||
3729 | #define PCI_VENDOR_ID_JMICRON 0x197B | |
3730 | #define PCI_DEVICE_ID_JMICRON_JMB360 0x2360 |