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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b AM |
2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
3 | 2004, 2005 | |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2, or (at your option) | |
16 | any later version. | |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
b99bd4ef | 28 | #include <string.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
b99bd4ef | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
b99bd4ef NC |
32 | |
33 | /* Need TARGET_CPU. */ | |
34 | #include "config.h" | |
35 | #include "subsegs.h" | |
36 | #include "obstack.h" | |
37 | #include "symbols.h" | |
38 | #include "listing.h" | |
39 | ||
f263249b RE |
40 | #include "opcode/arm.h" |
41 | ||
b99bd4ef NC |
42 | #ifdef OBJ_ELF |
43 | #include "elf/arm.h" | |
44 | #include "dwarf2dbg.h" | |
a394c00f | 45 | #include "dw2gencfi.h" |
b99bd4ef NC |
46 | #endif |
47 | ||
7ed4c4c5 | 48 | /* XXX Set this to 1 after the next binutils release. */ |
03b1477f RE |
49 | #define WARN_DEPRECATED 0 |
50 | ||
7ed4c4c5 NC |
51 | #ifdef OBJ_ELF |
52 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
53 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
54 | ||
55 | /* This structure holds the unwinding state. */ | |
56 | ||
57 | static struct | |
58 | { | |
c19d1205 ZW |
59 | symbolS * proc_start; |
60 | symbolS * table_entry; | |
61 | symbolS * personality_routine; | |
62 | int personality_index; | |
7ed4c4c5 | 63 | /* The segment containing the function. */ |
c19d1205 ZW |
64 | segT saved_seg; |
65 | subsegT saved_subseg; | |
7ed4c4c5 NC |
66 | /* Opcodes generated from this function. */ |
67 | unsigned char * opcodes; | |
c19d1205 ZW |
68 | int opcode_count; |
69 | int opcode_alloc; | |
7ed4c4c5 | 70 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 71 | offsetT frame_size; |
7ed4c4c5 NC |
72 | /* We don't add stack adjustment opcodes immediately so that we can merge |
73 | multiple adjustments. We can also omit the final adjustment | |
74 | when using a frame pointer. */ | |
c19d1205 | 75 | offsetT pending_offset; |
7ed4c4c5 | 76 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
77 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
78 | offsetT fp_offset; | |
79 | int fp_reg; | |
7ed4c4c5 | 80 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 81 | unsigned fp_used:1; |
7ed4c4c5 | 82 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 83 | unsigned sp_restored:1; |
7ed4c4c5 NC |
84 | } unwind; |
85 | ||
84798bd6 JB |
86 | /* Bit N indicates that an R_ARM_NONE relocation has been output for |
87 | __aeabi_unwind_cpp_prN already if set. This enables dependencies to be | |
88 | emitted only once per section, to save unnecessary bloat. */ | |
89 | static unsigned int marked_pr_dependency = 0; | |
90 | ||
7ed4c4c5 NC |
91 | #endif /* OBJ_ELF */ |
92 | ||
33a392fb PB |
93 | enum arm_float_abi |
94 | { | |
95 | ARM_FLOAT_ABI_HARD, | |
96 | ARM_FLOAT_ABI_SOFTFP, | |
97 | ARM_FLOAT_ABI_SOFT | |
98 | }; | |
99 | ||
c19d1205 | 100 | /* Types of processor to assemble for. */ |
b99bd4ef NC |
101 | #ifndef CPU_DEFAULT |
102 | #if defined __XSCALE__ | |
e74cfd16 | 103 | #define CPU_DEFAULT ARM_ARCH_XSCALE |
b99bd4ef NC |
104 | #else |
105 | #if defined __thumb__ | |
e74cfd16 | 106 | #define CPU_DEFAULT ARM_ARCH_V5T |
b99bd4ef NC |
107 | #endif |
108 | #endif | |
109 | #endif | |
110 | ||
111 | #ifndef FPU_DEFAULT | |
c820d418 MM |
112 | # ifdef TE_LINUX |
113 | # define FPU_DEFAULT FPU_ARCH_FPA | |
114 | # elif defined (TE_NetBSD) | |
115 | # ifdef OBJ_ELF | |
116 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
117 | # else | |
118 | /* Legacy a.out format. */ | |
119 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
120 | # endif | |
4e7fd91e PB |
121 | # elif defined (TE_VXWORKS) |
122 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
123 | # else |
124 | /* For backwards compatibility, default to FPA. */ | |
125 | # define FPU_DEFAULT FPU_ARCH_FPA | |
126 | # endif | |
127 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 128 | |
c19d1205 | 129 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 130 | |
e74cfd16 PB |
131 | static arm_feature_set cpu_variant; |
132 | static arm_feature_set arm_arch_used; | |
133 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 134 | |
b99bd4ef | 135 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
136 | static int uses_apcs_26 = FALSE; |
137 | static int atpcs = FALSE; | |
b34976b6 AM |
138 | static int support_interwork = FALSE; |
139 | static int uses_apcs_float = FALSE; | |
c19d1205 | 140 | static int pic_code = FALSE; |
03b1477f RE |
141 | |
142 | /* Variables that we set while parsing command-line options. Once all | |
143 | options have been read we re-process these values to set the real | |
144 | assembly flags. */ | |
e74cfd16 PB |
145 | static const arm_feature_set *legacy_cpu = NULL; |
146 | static const arm_feature_set *legacy_fpu = NULL; | |
147 | ||
148 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
149 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
150 | static const arm_feature_set *march_cpu_opt = NULL; | |
151 | static const arm_feature_set *march_fpu_opt = NULL; | |
152 | static const arm_feature_set *mfpu_opt = NULL; | |
153 | ||
154 | /* Constants for known architecture features. */ | |
155 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
156 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
157 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
158 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; | |
159 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
160 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
161 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
162 | ||
163 | #ifdef CPU_DEFAULT | |
164 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
165 | #endif | |
166 | ||
167 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
168 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
169 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
170 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
171 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
172 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
173 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
174 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
175 | static const arm_feature_set arm_ext_v4t_5 = | |
176 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
177 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
178 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
179 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
180 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
181 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
182 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
183 | static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); | |
184 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); | |
62b3e311 PB |
185 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
186 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); | |
187 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
188 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
189 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
190 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); | |
e74cfd16 PB |
191 | |
192 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
193 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
194 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
195 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
196 | ||
197 | static const arm_feature_set arm_cext_iwmmxt = | |
198 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
199 | static const arm_feature_set arm_cext_xscale = | |
200 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
201 | static const arm_feature_set arm_cext_maverick = | |
202 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
203 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
204 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
205 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
206 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
207 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
208 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
209 | ||
33a392fb | 210 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
211 | /* Record user cpu selection for object attributes. */ |
212 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
213 | /* Must be long enough to hold any of the names in arm_cpus. */ |
214 | static char selected_cpu_name[16]; | |
7cc69913 | 215 | #ifdef OBJ_ELF |
deeaaff8 DJ |
216 | # ifdef EABI_DEFAULT |
217 | static int meabi_flags = EABI_DEFAULT; | |
218 | # else | |
d507cf36 | 219 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 220 | # endif |
7cc69913 | 221 | #endif |
b99bd4ef | 222 | |
b99bd4ef | 223 | #ifdef OBJ_ELF |
c19d1205 | 224 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
225 | symbolS * GOT_symbol; |
226 | #endif | |
227 | ||
b99bd4ef NC |
228 | /* 0: assemble for ARM, |
229 | 1: assemble for Thumb, | |
230 | 2: assemble for Thumb even though target CPU does not support thumb | |
231 | instructions. */ | |
232 | static int thumb_mode = 0; | |
233 | ||
c19d1205 ZW |
234 | /* If unified_syntax is true, we are processing the new unified |
235 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
236 | ||
237 | - Immediate operands do not require a # prefix. | |
238 | - Conditional affixes always appear at the end of the | |
239 | instruction. (For backward compatibility, those instructions | |
240 | that formerly had them in the middle, continue to accept them | |
241 | there.) | |
242 | - The IT instruction may appear, and if it does is validated | |
243 | against subsequent conditional affixes. It does not generate | |
244 | machine code. | |
245 | ||
246 | Important differences from the old Thumb mode: | |
247 | ||
248 | - Immediate operands do not require a # prefix. | |
249 | - Most of the V6T2 instructions are only available in unified mode. | |
250 | - The .N and .W suffixes are recognized and honored (it is an error | |
251 | if they cannot be honored). | |
252 | - All instructions set the flags if and only if they have an 's' affix. | |
253 | - Conditional affixes may be used. They are validated against | |
254 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
255 | conditional affix except in the scope of an IT instruction. */ | |
256 | ||
257 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef NC |
258 | |
259 | struct arm_it | |
260 | { | |
c19d1205 | 261 | const char * error; |
b99bd4ef | 262 | unsigned long instruction; |
c19d1205 ZW |
263 | int size; |
264 | int size_req; | |
265 | int cond; | |
0110f2b8 PB |
266 | /* Set to the opcode if the instruction needs relaxation. |
267 | Zero if the instruction is not relaxed. */ | |
268 | unsigned long relax; | |
b99bd4ef NC |
269 | struct |
270 | { | |
271 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
272 | expressionS exp; |
273 | int pc_rel; | |
b99bd4ef | 274 | } reloc; |
b99bd4ef | 275 | |
c19d1205 ZW |
276 | struct |
277 | { | |
278 | unsigned reg; | |
ca3f61f7 NC |
279 | signed int imm; |
280 | unsigned present : 1; /* Operand present. */ | |
281 | unsigned isreg : 1; /* Operand was a register. */ | |
282 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
283 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ | |
284 | unsigned writeback : 1; /* Operand has trailing ! */ | |
285 | unsigned preind : 1; /* Preindexed address. */ | |
286 | unsigned postind : 1; /* Postindexed address. */ | |
287 | unsigned negative : 1; /* Index register was negated. */ | |
288 | unsigned shifted : 1; /* Shift applied to operation. */ | |
289 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 290 | } operands[6]; |
b99bd4ef NC |
291 | }; |
292 | ||
c19d1205 | 293 | static struct arm_it inst; |
b99bd4ef NC |
294 | |
295 | #define NUM_FLOAT_VALS 8 | |
296 | ||
05d2d07e | 297 | const char * fp_const[] = |
b99bd4ef NC |
298 | { |
299 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
300 | }; | |
301 | ||
c19d1205 | 302 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
303 | #define MAX_LITTLENUMS 6 |
304 | ||
305 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
306 | ||
307 | #define FAIL (-1) | |
308 | #define SUCCESS (0) | |
309 | ||
310 | #define SUFF_S 1 | |
311 | #define SUFF_D 2 | |
312 | #define SUFF_E 3 | |
313 | #define SUFF_P 4 | |
314 | ||
c19d1205 ZW |
315 | #define CP_T_X 0x00008000 |
316 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 317 | |
c19d1205 ZW |
318 | #define CONDS_BIT 0x00100000 |
319 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
320 | |
321 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
322 | ||
323 | struct asm_cond | |
324 | { | |
c19d1205 | 325 | const char * template; |
b99bd4ef NC |
326 | unsigned long value; |
327 | }; | |
328 | ||
c19d1205 | 329 | #define COND_ALWAYS 0xE |
b99bd4ef | 330 | |
b99bd4ef NC |
331 | struct asm_psr |
332 | { | |
b34976b6 | 333 | const char *template; |
b99bd4ef NC |
334 | unsigned long field; |
335 | }; | |
336 | ||
62b3e311 PB |
337 | struct asm_barrier_opt |
338 | { | |
339 | const char *template; | |
340 | unsigned long value; | |
341 | }; | |
342 | ||
2d2255b5 | 343 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
344 | #define SPSR_BIT (1 << 22) |
345 | ||
c19d1205 ZW |
346 | /* The individual PSR flag bits. */ |
347 | #define PSR_c (1 << 16) | |
348 | #define PSR_x (1 << 17) | |
349 | #define PSR_s (1 << 18) | |
350 | #define PSR_f (1 << 19) | |
b99bd4ef | 351 | |
c19d1205 | 352 | struct reloc_entry |
bfae80f2 | 353 | { |
c19d1205 ZW |
354 | char *name; |
355 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
356 | }; |
357 | ||
358 | enum vfp_sp_reg_pos | |
359 | { | |
360 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn | |
361 | }; | |
362 | ||
363 | enum vfp_ldstm_type | |
364 | { | |
365 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
366 | }; | |
367 | ||
c19d1205 ZW |
368 | /* ARM register categories. This includes coprocessor numbers and various |
369 | architecture extensions' registers. */ | |
370 | enum arm_reg_type | |
bfae80f2 | 371 | { |
c19d1205 ZW |
372 | REG_TYPE_RN, |
373 | REG_TYPE_CP, | |
374 | REG_TYPE_CN, | |
375 | REG_TYPE_FN, | |
376 | REG_TYPE_VFS, | |
377 | REG_TYPE_VFD, | |
378 | REG_TYPE_VFC, | |
379 | REG_TYPE_MVF, | |
380 | REG_TYPE_MVD, | |
381 | REG_TYPE_MVFX, | |
382 | REG_TYPE_MVDX, | |
383 | REG_TYPE_MVAX, | |
384 | REG_TYPE_DSPSC, | |
385 | REG_TYPE_MMXWR, | |
386 | REG_TYPE_MMXWC, | |
387 | REG_TYPE_MMXWCG, | |
388 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
389 | }; |
390 | ||
6c43fab6 RE |
391 | /* Structure for a hash table entry for a register. */ |
392 | struct reg_entry | |
393 | { | |
c19d1205 ZW |
394 | const char *name; |
395 | unsigned char number; | |
396 | unsigned char type; | |
397 | unsigned char builtin; | |
6c43fab6 RE |
398 | }; |
399 | ||
c19d1205 ZW |
400 | /* Diagnostics used when we don't get a register of the expected type. */ |
401 | const char *const reg_expected_msgs[] = | |
402 | { | |
403 | N_("ARM register expected"), | |
404 | N_("bad or missing co-processor number"), | |
405 | N_("co-processor register expected"), | |
406 | N_("FPA register expected"), | |
407 | N_("VFP single precision register expected"), | |
408 | N_("VFP double precision register expected"), | |
409 | N_("VFP system register expected"), | |
410 | N_("Maverick MVF register expected"), | |
411 | N_("Maverick MVD register expected"), | |
412 | N_("Maverick MVFX register expected"), | |
413 | N_("Maverick MVDX register expected"), | |
414 | N_("Maverick MVAX register expected"), | |
415 | N_("Maverick DSPSC register expected"), | |
416 | N_("iWMMXt data register expected"), | |
417 | N_("iWMMXt control register expected"), | |
418 | N_("iWMMXt scalar register expected"), | |
419 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
420 | }; |
421 | ||
c19d1205 ZW |
422 | /* Some well known registers that we refer to directly elsewhere. */ |
423 | #define REG_SP 13 | |
424 | #define REG_LR 14 | |
425 | #define REG_PC 15 | |
404ff6b5 | 426 | |
b99bd4ef NC |
427 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
428 | take 2: */ | |
c19d1205 | 429 | #define INSN_SIZE 4 |
b99bd4ef NC |
430 | |
431 | struct asm_opcode | |
432 | { | |
433 | /* Basic string to match. */ | |
c19d1205 ZW |
434 | const char *template; |
435 | ||
436 | /* Parameters to instruction. */ | |
437 | unsigned char operands[8]; | |
438 | ||
439 | /* Conditional tag - see opcode_lookup. */ | |
440 | unsigned int tag : 4; | |
b99bd4ef NC |
441 | |
442 | /* Basic instruction code. */ | |
c19d1205 | 443 | unsigned int avalue : 28; |
b99bd4ef | 444 | |
c19d1205 ZW |
445 | /* Thumb-format instruction code. */ |
446 | unsigned int tvalue; | |
b99bd4ef | 447 | |
90e4755a | 448 | /* Which architecture variant provides this instruction. */ |
e74cfd16 PB |
449 | const arm_feature_set *avariant; |
450 | const arm_feature_set *tvariant; | |
c19d1205 ZW |
451 | |
452 | /* Function to call to encode instruction in ARM format. */ | |
453 | void (* aencode) (void); | |
b99bd4ef | 454 | |
c19d1205 ZW |
455 | /* Function to call to encode instruction in Thumb format. */ |
456 | void (* tencode) (void); | |
b99bd4ef NC |
457 | }; |
458 | ||
a737bd4d NC |
459 | /* Defines for various bits that we will want to toggle. */ |
460 | #define INST_IMMEDIATE 0x02000000 | |
461 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 462 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
463 | #define SHIFT_BY_REG 0x00000010 |
464 | #define PRE_INDEX 0x01000000 | |
465 | #define INDEX_UP 0x00800000 | |
466 | #define WRITE_BACK 0x00200000 | |
467 | #define LDM_TYPE_2_OR_3 0x00400000 | |
90e4755a | 468 | |
a737bd4d NC |
469 | #define LITERAL_MASK 0xf000f000 |
470 | #define OPCODE_MASK 0xfe1fffff | |
471 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 472 | |
a737bd4d | 473 | #define DATA_OP_SHIFT 21 |
90e4755a | 474 | |
ef8d22e6 PB |
475 | #define T2_OPCODE_MASK 0xfe1fffff |
476 | #define T2_DATA_OP_SHIFT 21 | |
477 | ||
a737bd4d NC |
478 | /* Codes to distinguish the arithmetic instructions. */ |
479 | #define OPCODE_AND 0 | |
480 | #define OPCODE_EOR 1 | |
481 | #define OPCODE_SUB 2 | |
482 | #define OPCODE_RSB 3 | |
483 | #define OPCODE_ADD 4 | |
484 | #define OPCODE_ADC 5 | |
485 | #define OPCODE_SBC 6 | |
486 | #define OPCODE_RSC 7 | |
487 | #define OPCODE_TST 8 | |
488 | #define OPCODE_TEQ 9 | |
489 | #define OPCODE_CMP 10 | |
490 | #define OPCODE_CMN 11 | |
491 | #define OPCODE_ORR 12 | |
492 | #define OPCODE_MOV 13 | |
493 | #define OPCODE_BIC 14 | |
494 | #define OPCODE_MVN 15 | |
90e4755a | 495 | |
ef8d22e6 PB |
496 | #define T2_OPCODE_AND 0 |
497 | #define T2_OPCODE_BIC 1 | |
498 | #define T2_OPCODE_ORR 2 | |
499 | #define T2_OPCODE_ORN 3 | |
500 | #define T2_OPCODE_EOR 4 | |
501 | #define T2_OPCODE_ADD 8 | |
502 | #define T2_OPCODE_ADC 10 | |
503 | #define T2_OPCODE_SBC 11 | |
504 | #define T2_OPCODE_SUB 13 | |
505 | #define T2_OPCODE_RSB 14 | |
506 | ||
a737bd4d NC |
507 | #define T_OPCODE_MUL 0x4340 |
508 | #define T_OPCODE_TST 0x4200 | |
509 | #define T_OPCODE_CMN 0x42c0 | |
510 | #define T_OPCODE_NEG 0x4240 | |
511 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 512 | |
a737bd4d NC |
513 | #define T_OPCODE_ADD_R3 0x1800 |
514 | #define T_OPCODE_SUB_R3 0x1a00 | |
515 | #define T_OPCODE_ADD_HI 0x4400 | |
516 | #define T_OPCODE_ADD_ST 0xb000 | |
517 | #define T_OPCODE_SUB_ST 0xb080 | |
518 | #define T_OPCODE_ADD_SP 0xa800 | |
519 | #define T_OPCODE_ADD_PC 0xa000 | |
520 | #define T_OPCODE_ADD_I8 0x3000 | |
521 | #define T_OPCODE_SUB_I8 0x3800 | |
522 | #define T_OPCODE_ADD_I3 0x1c00 | |
523 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 524 | |
a737bd4d NC |
525 | #define T_OPCODE_ASR_R 0x4100 |
526 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
527 | #define T_OPCODE_LSR_R 0x40c0 |
528 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
529 | #define T_OPCODE_ASR_I 0x1000 |
530 | #define T_OPCODE_LSL_I 0x0000 | |
531 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 532 | |
a737bd4d NC |
533 | #define T_OPCODE_MOV_I8 0x2000 |
534 | #define T_OPCODE_CMP_I8 0x2800 | |
535 | #define T_OPCODE_CMP_LR 0x4280 | |
536 | #define T_OPCODE_MOV_HR 0x4600 | |
537 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 538 | |
a737bd4d NC |
539 | #define T_OPCODE_LDR_PC 0x4800 |
540 | #define T_OPCODE_LDR_SP 0x9800 | |
541 | #define T_OPCODE_STR_SP 0x9000 | |
542 | #define T_OPCODE_LDR_IW 0x6800 | |
543 | #define T_OPCODE_STR_IW 0x6000 | |
544 | #define T_OPCODE_LDR_IH 0x8800 | |
545 | #define T_OPCODE_STR_IH 0x8000 | |
546 | #define T_OPCODE_LDR_IB 0x7800 | |
547 | #define T_OPCODE_STR_IB 0x7000 | |
548 | #define T_OPCODE_LDR_RW 0x5800 | |
549 | #define T_OPCODE_STR_RW 0x5000 | |
550 | #define T_OPCODE_LDR_RH 0x5a00 | |
551 | #define T_OPCODE_STR_RH 0x5200 | |
552 | #define T_OPCODE_LDR_RB 0x5c00 | |
553 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 554 | |
a737bd4d NC |
555 | #define T_OPCODE_PUSH 0xb400 |
556 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 557 | |
2fc8bdac | 558 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 559 | |
a737bd4d | 560 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 561 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 562 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 563 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
564 | |
565 | #define BAD_ARGS _("bad arguments to instruction") | |
566 | #define BAD_PC _("r15 not allowed here") | |
567 | #define BAD_COND _("instruction cannot be conditional") | |
568 | #define BAD_OVERLAP _("registers may not be the same") | |
569 | #define BAD_HIREG _("lo register required") | |
570 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 571 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
572 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
573 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
c19d1205 ZW |
574 | |
575 | static struct hash_control *arm_ops_hsh; | |
576 | static struct hash_control *arm_cond_hsh; | |
577 | static struct hash_control *arm_shift_hsh; | |
578 | static struct hash_control *arm_psr_hsh; | |
62b3e311 | 579 | static struct hash_control *arm_v7m_psr_hsh; |
c19d1205 ZW |
580 | static struct hash_control *arm_reg_hsh; |
581 | static struct hash_control *arm_reloc_hsh; | |
62b3e311 | 582 | static struct hash_control *arm_barrier_opt_hsh; |
b99bd4ef | 583 | |
b99bd4ef NC |
584 | /* Stuff needed to resolve the label ambiguity |
585 | As: | |
586 | ... | |
587 | label: <insn> | |
588 | may differ from: | |
589 | ... | |
590 | label: | |
c19d1205 | 591 | <insn> |
b99bd4ef NC |
592 | */ |
593 | ||
594 | symbolS * last_label_seen; | |
b34976b6 | 595 | static int label_is_thumb_function_name = FALSE; |
a737bd4d | 596 | \f |
3d0c9500 NC |
597 | /* Literal pool structure. Held on a per-section |
598 | and per-sub-section basis. */ | |
a737bd4d | 599 | |
c19d1205 | 600 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 601 | typedef struct literal_pool |
b99bd4ef | 602 | { |
c19d1205 ZW |
603 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
604 | unsigned int next_free_entry; | |
605 | unsigned int id; | |
606 | symbolS * symbol; | |
607 | segT section; | |
608 | subsegT sub_section; | |
61b5f74b | 609 | struct literal_pool * next; |
3d0c9500 | 610 | } literal_pool; |
b99bd4ef | 611 | |
3d0c9500 NC |
612 | /* Pointer to a linked list of literal pools. */ |
613 | literal_pool * list_of_pools = NULL; | |
e27ec89e PB |
614 | |
615 | /* State variables for IT block handling. */ | |
616 | static bfd_boolean current_it_mask = 0; | |
617 | static int current_cc; | |
618 | ||
c19d1205 ZW |
619 | \f |
620 | /* Pure syntax. */ | |
b99bd4ef | 621 | |
c19d1205 ZW |
622 | /* This array holds the chars that always start a comment. If the |
623 | pre-processor is disabled, these aren't very useful. */ | |
624 | const char comment_chars[] = "@"; | |
3d0c9500 | 625 | |
c19d1205 ZW |
626 | /* This array holds the chars that only start a comment at the beginning of |
627 | a line. If the line seems to have the form '# 123 filename' | |
628 | .line and .file directives will appear in the pre-processed output. */ | |
629 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
630 | first line of the input file. This is because the compiler outputs | |
631 | #NO_APP at the beginning of its output. */ | |
632 | /* Also note that comments like this one will always work. */ | |
633 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 634 | |
c19d1205 | 635 | const char line_separator_chars[] = ";"; |
b99bd4ef | 636 | |
c19d1205 ZW |
637 | /* Chars that can be used to separate mant |
638 | from exp in floating point numbers. */ | |
639 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 640 | |
c19d1205 ZW |
641 | /* Chars that mean this number is a floating point constant. */ |
642 | /* As in 0f12.456 */ | |
643 | /* or 0d1.2345e12 */ | |
b99bd4ef | 644 | |
c19d1205 | 645 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 646 | |
c19d1205 ZW |
647 | /* Prefix characters that indicate the start of an immediate |
648 | value. */ | |
649 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 650 | |
c19d1205 ZW |
651 | /* Separator character handling. */ |
652 | ||
653 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
654 | ||
655 | static inline int | |
656 | skip_past_char (char ** str, char c) | |
657 | { | |
658 | if (**str == c) | |
659 | { | |
660 | (*str)++; | |
661 | return SUCCESS; | |
3d0c9500 | 662 | } |
c19d1205 ZW |
663 | else |
664 | return FAIL; | |
665 | } | |
666 | #define skip_past_comma(str) skip_past_char (str, ',') | |
3d0c9500 | 667 | |
c19d1205 ZW |
668 | /* Arithmetic expressions (possibly involving symbols). */ |
669 | ||
670 | /* Return TRUE if anything in the expression is a bignum. */ | |
671 | ||
672 | static int | |
673 | walk_no_bignums (symbolS * sp) | |
674 | { | |
675 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
676 | return 1; | |
677 | ||
678 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 679 | { |
c19d1205 ZW |
680 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
681 | || (symbol_get_value_expression (sp)->X_op_symbol | |
682 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
683 | } |
684 | ||
c19d1205 | 685 | return 0; |
3d0c9500 NC |
686 | } |
687 | ||
c19d1205 ZW |
688 | static int in_my_get_expression = 0; |
689 | ||
690 | /* Third argument to my_get_expression. */ | |
691 | #define GE_NO_PREFIX 0 | |
692 | #define GE_IMM_PREFIX 1 | |
693 | #define GE_OPT_PREFIX 2 | |
a737bd4d | 694 | |
b99bd4ef | 695 | static int |
c19d1205 | 696 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 697 | { |
c19d1205 ZW |
698 | char * save_in; |
699 | segT seg; | |
b99bd4ef | 700 | |
c19d1205 ZW |
701 | /* In unified syntax, all prefixes are optional. */ |
702 | if (unified_syntax) | |
703 | prefix_mode = GE_OPT_PREFIX; | |
b99bd4ef | 704 | |
c19d1205 | 705 | switch (prefix_mode) |
b99bd4ef | 706 | { |
c19d1205 ZW |
707 | case GE_NO_PREFIX: break; |
708 | case GE_IMM_PREFIX: | |
709 | if (!is_immediate_prefix (**str)) | |
710 | { | |
711 | inst.error = _("immediate expression requires a # prefix"); | |
712 | return FAIL; | |
713 | } | |
714 | (*str)++; | |
715 | break; | |
716 | case GE_OPT_PREFIX: | |
717 | if (is_immediate_prefix (**str)) | |
718 | (*str)++; | |
719 | break; | |
720 | default: abort (); | |
721 | } | |
b99bd4ef | 722 | |
c19d1205 | 723 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 724 | |
c19d1205 ZW |
725 | save_in = input_line_pointer; |
726 | input_line_pointer = *str; | |
727 | in_my_get_expression = 1; | |
728 | seg = expression (ep); | |
729 | in_my_get_expression = 0; | |
730 | ||
731 | if (ep->X_op == O_illegal) | |
b99bd4ef | 732 | { |
c19d1205 ZW |
733 | /* We found a bad expression in md_operand(). */ |
734 | *str = input_line_pointer; | |
735 | input_line_pointer = save_in; | |
736 | if (inst.error == NULL) | |
737 | inst.error = _("bad expression"); | |
738 | return 1; | |
739 | } | |
b99bd4ef | 740 | |
c19d1205 ZW |
741 | #ifdef OBJ_AOUT |
742 | if (seg != absolute_section | |
743 | && seg != text_section | |
744 | && seg != data_section | |
745 | && seg != bss_section | |
746 | && seg != undefined_section) | |
747 | { | |
748 | inst.error = _("bad segment"); | |
749 | *str = input_line_pointer; | |
750 | input_line_pointer = save_in; | |
751 | return 1; | |
b99bd4ef | 752 | } |
c19d1205 | 753 | #endif |
b99bd4ef | 754 | |
c19d1205 ZW |
755 | /* Get rid of any bignums now, so that we don't generate an error for which |
756 | we can't establish a line number later on. Big numbers are never valid | |
757 | in instructions, which is where this routine is always called. */ | |
758 | if (ep->X_op == O_big | |
759 | || (ep->X_add_symbol | |
760 | && (walk_no_bignums (ep->X_add_symbol) | |
761 | || (ep->X_op_symbol | |
762 | && walk_no_bignums (ep->X_op_symbol))))) | |
763 | { | |
764 | inst.error = _("invalid constant"); | |
765 | *str = input_line_pointer; | |
766 | input_line_pointer = save_in; | |
767 | return 1; | |
768 | } | |
b99bd4ef | 769 | |
c19d1205 ZW |
770 | *str = input_line_pointer; |
771 | input_line_pointer = save_in; | |
772 | return 0; | |
b99bd4ef NC |
773 | } |
774 | ||
c19d1205 ZW |
775 | /* Turn a string in input_line_pointer into a floating point constant |
776 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
777 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
778 | returned, or NULL on OK. | |
b99bd4ef | 779 | |
c19d1205 ZW |
780 | Note that fp constants aren't represent in the normal way on the ARM. |
781 | In big endian mode, things are as expected. However, in little endian | |
782 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
783 | within the words. For example, (double) 1.1 in big endian mode is | |
784 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
785 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 786 | |
c19d1205 | 787 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 788 | |
c19d1205 ZW |
789 | char * |
790 | md_atof (int type, char * litP, int * sizeP) | |
791 | { | |
792 | int prec; | |
793 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
794 | char *t; | |
795 | int i; | |
b99bd4ef | 796 | |
c19d1205 ZW |
797 | switch (type) |
798 | { | |
799 | case 'f': | |
800 | case 'F': | |
801 | case 's': | |
802 | case 'S': | |
803 | prec = 2; | |
804 | break; | |
b99bd4ef | 805 | |
c19d1205 ZW |
806 | case 'd': |
807 | case 'D': | |
808 | case 'r': | |
809 | case 'R': | |
810 | prec = 4; | |
811 | break; | |
b99bd4ef | 812 | |
c19d1205 ZW |
813 | case 'x': |
814 | case 'X': | |
815 | prec = 6; | |
816 | break; | |
b99bd4ef | 817 | |
c19d1205 ZW |
818 | case 'p': |
819 | case 'P': | |
820 | prec = 6; | |
821 | break; | |
a737bd4d | 822 | |
c19d1205 ZW |
823 | default: |
824 | *sizeP = 0; | |
825 | return _("bad call to MD_ATOF()"); | |
826 | } | |
b99bd4ef | 827 | |
c19d1205 ZW |
828 | t = atof_ieee (input_line_pointer, type, words); |
829 | if (t) | |
830 | input_line_pointer = t; | |
831 | *sizeP = prec * 2; | |
b99bd4ef | 832 | |
c19d1205 ZW |
833 | if (target_big_endian) |
834 | { | |
835 | for (i = 0; i < prec; i++) | |
836 | { | |
837 | md_number_to_chars (litP, (valueT) words[i], 2); | |
838 | litP += 2; | |
839 | } | |
840 | } | |
841 | else | |
842 | { | |
e74cfd16 | 843 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
844 | for (i = prec - 1; i >= 0; i--) |
845 | { | |
846 | md_number_to_chars (litP, (valueT) words[i], 2); | |
847 | litP += 2; | |
848 | } | |
849 | else | |
850 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
851 | For an 8 byte float the order is 1 0 3 2. */ | |
852 | for (i = 0; i < prec; i += 2) | |
853 | { | |
854 | md_number_to_chars (litP, (valueT) words[i + 1], 2); | |
855 | md_number_to_chars (litP + 2, (valueT) words[i], 2); | |
856 | litP += 4; | |
857 | } | |
858 | } | |
b99bd4ef | 859 | |
c19d1205 ZW |
860 | return 0; |
861 | } | |
b99bd4ef | 862 | |
c19d1205 ZW |
863 | /* We handle all bad expressions here, so that we can report the faulty |
864 | instruction in the error message. */ | |
865 | void | |
866 | md_operand (expressionS * expr) | |
867 | { | |
868 | if (in_my_get_expression) | |
869 | expr->X_op = O_illegal; | |
b99bd4ef NC |
870 | } |
871 | ||
c19d1205 | 872 | /* Immediate values. */ |
b99bd4ef | 873 | |
c19d1205 ZW |
874 | /* Generic immediate-value read function for use in directives. |
875 | Accepts anything that 'expression' can fold to a constant. | |
876 | *val receives the number. */ | |
877 | #ifdef OBJ_ELF | |
878 | static int | |
879 | immediate_for_directive (int *val) | |
b99bd4ef | 880 | { |
c19d1205 ZW |
881 | expressionS exp; |
882 | exp.X_op = O_illegal; | |
b99bd4ef | 883 | |
c19d1205 ZW |
884 | if (is_immediate_prefix (*input_line_pointer)) |
885 | { | |
886 | input_line_pointer++; | |
887 | expression (&exp); | |
888 | } | |
b99bd4ef | 889 | |
c19d1205 ZW |
890 | if (exp.X_op != O_constant) |
891 | { | |
892 | as_bad (_("expected #constant")); | |
893 | ignore_rest_of_line (); | |
894 | return FAIL; | |
895 | } | |
896 | *val = exp.X_add_number; | |
897 | return SUCCESS; | |
b99bd4ef | 898 | } |
c19d1205 | 899 | #endif |
b99bd4ef | 900 | |
c19d1205 | 901 | /* Register parsing. */ |
b99bd4ef | 902 | |
c19d1205 ZW |
903 | /* Generic register parser. CCP points to what should be the |
904 | beginning of a register name. If it is indeed a valid register | |
905 | name, advance CCP over it and return the reg_entry structure; | |
906 | otherwise return NULL. Does not issue diagnostics. */ | |
907 | ||
908 | static struct reg_entry * | |
909 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 910 | { |
c19d1205 ZW |
911 | char *start = *ccp; |
912 | char *p; | |
913 | struct reg_entry *reg; | |
b99bd4ef | 914 | |
c19d1205 ZW |
915 | #ifdef REGISTER_PREFIX |
916 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 917 | return NULL; |
c19d1205 ZW |
918 | start++; |
919 | #endif | |
920 | #ifdef OPTIONAL_REGISTER_PREFIX | |
921 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
922 | start++; | |
923 | #endif | |
b99bd4ef | 924 | |
c19d1205 ZW |
925 | p = start; |
926 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
927 | return NULL; | |
b99bd4ef | 928 | |
c19d1205 ZW |
929 | do |
930 | p++; | |
931 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
932 | ||
933 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
934 | ||
935 | if (!reg) | |
936 | return NULL; | |
937 | ||
938 | *ccp = p; | |
939 | return reg; | |
b99bd4ef NC |
940 | } |
941 | ||
c19d1205 | 942 | /* As above, but the register must be of type TYPE, and the return |
01cfc07f | 943 | value is the register number or FAIL. */ |
c19d1205 | 944 | |
b99bd4ef | 945 | static int |
c19d1205 | 946 | arm_reg_parse (char **ccp, enum arm_reg_type type) |
b99bd4ef | 947 | { |
c19d1205 ZW |
948 | char *start = *ccp; |
949 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
b99bd4ef | 950 | |
c19d1205 ZW |
951 | if (reg && reg->type == type) |
952 | return reg->number; | |
6057a28f | 953 | |
c19d1205 ZW |
954 | /* Alternative syntaxes are accepted for a few register classes. */ |
955 | switch (type) | |
956 | { | |
957 | case REG_TYPE_MVF: | |
958 | case REG_TYPE_MVD: | |
959 | case REG_TYPE_MVFX: | |
960 | case REG_TYPE_MVDX: | |
961 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 962 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
963 | return reg->number; |
964 | break; | |
69b97547 | 965 | |
c19d1205 ZW |
966 | case REG_TYPE_CP: |
967 | /* For backward compatibility, a bare number is valid here. */ | |
968 | { | |
969 | unsigned long processor = strtoul (start, ccp, 10); | |
970 | if (*ccp != start && processor <= 15) | |
971 | return processor; | |
972 | } | |
6057a28f | 973 | |
c19d1205 ZW |
974 | case REG_TYPE_MMXWC: |
975 | /* WC includes WCG. ??? I'm not sure this is true for all | |
976 | instructions that take WC registers. */ | |
79134647 | 977 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 978 | return reg->number; |
6057a28f | 979 | break; |
c19d1205 | 980 | |
6057a28f | 981 | default: |
c19d1205 | 982 | break; |
6057a28f NC |
983 | } |
984 | ||
c19d1205 ZW |
985 | *ccp = start; |
986 | return FAIL; | |
987 | } | |
69b97547 | 988 | |
c19d1205 ZW |
989 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
990 | static long | |
991 | parse_reg_list (char ** strp) | |
992 | { | |
993 | char * str = * strp; | |
994 | long range = 0; | |
995 | int another_range; | |
a737bd4d | 996 | |
c19d1205 ZW |
997 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
998 | do | |
6057a28f | 999 | { |
c19d1205 | 1000 | another_range = 0; |
a737bd4d | 1001 | |
c19d1205 ZW |
1002 | if (*str == '{') |
1003 | { | |
1004 | int in_range = 0; | |
1005 | int cur_reg = -1; | |
a737bd4d | 1006 | |
c19d1205 ZW |
1007 | str++; |
1008 | do | |
1009 | { | |
1010 | int reg; | |
6057a28f | 1011 | |
c19d1205 ZW |
1012 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
1013 | { | |
1014 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
1015 | return FAIL; | |
1016 | } | |
a737bd4d | 1017 | |
c19d1205 ZW |
1018 | if (in_range) |
1019 | { | |
1020 | int i; | |
a737bd4d | 1021 | |
c19d1205 ZW |
1022 | if (reg <= cur_reg) |
1023 | { | |
1024 | inst.error = _("bad range in register list"); | |
1025 | return FAIL; | |
1026 | } | |
40a18ebd | 1027 | |
c19d1205 ZW |
1028 | for (i = cur_reg + 1; i < reg; i++) |
1029 | { | |
1030 | if (range & (1 << i)) | |
1031 | as_tsktsk | |
1032 | (_("Warning: duplicated register (r%d) in register list"), | |
1033 | i); | |
1034 | else | |
1035 | range |= 1 << i; | |
1036 | } | |
1037 | in_range = 0; | |
1038 | } | |
a737bd4d | 1039 | |
c19d1205 ZW |
1040 | if (range & (1 << reg)) |
1041 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1042 | reg); | |
1043 | else if (reg <= cur_reg) | |
1044 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1045 | |
c19d1205 ZW |
1046 | range |= 1 << reg; |
1047 | cur_reg = reg; | |
1048 | } | |
1049 | while (skip_past_comma (&str) != FAIL | |
1050 | || (in_range = 1, *str++ == '-')); | |
1051 | str--; | |
a737bd4d | 1052 | |
c19d1205 ZW |
1053 | if (*str++ != '}') |
1054 | { | |
1055 | inst.error = _("missing `}'"); | |
1056 | return FAIL; | |
1057 | } | |
1058 | } | |
1059 | else | |
1060 | { | |
1061 | expressionS expr; | |
40a18ebd | 1062 | |
c19d1205 ZW |
1063 | if (my_get_expression (&expr, &str, GE_NO_PREFIX)) |
1064 | return FAIL; | |
40a18ebd | 1065 | |
c19d1205 ZW |
1066 | if (expr.X_op == O_constant) |
1067 | { | |
1068 | if (expr.X_add_number | |
1069 | != (expr.X_add_number & 0x0000ffff)) | |
1070 | { | |
1071 | inst.error = _("invalid register mask"); | |
1072 | return FAIL; | |
1073 | } | |
a737bd4d | 1074 | |
c19d1205 ZW |
1075 | if ((range & expr.X_add_number) != 0) |
1076 | { | |
1077 | int regno = range & expr.X_add_number; | |
a737bd4d | 1078 | |
c19d1205 ZW |
1079 | regno &= -regno; |
1080 | regno = (1 << regno) - 1; | |
1081 | as_tsktsk | |
1082 | (_("Warning: duplicated register (r%d) in register list"), | |
1083 | regno); | |
1084 | } | |
a737bd4d | 1085 | |
c19d1205 ZW |
1086 | range |= expr.X_add_number; |
1087 | } | |
1088 | else | |
1089 | { | |
1090 | if (inst.reloc.type != 0) | |
1091 | { | |
1092 | inst.error = _("expression too complex"); | |
1093 | return FAIL; | |
1094 | } | |
a737bd4d | 1095 | |
c19d1205 ZW |
1096 | memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); |
1097 | inst.reloc.type = BFD_RELOC_ARM_MULTI; | |
1098 | inst.reloc.pc_rel = 0; | |
1099 | } | |
1100 | } | |
a737bd4d | 1101 | |
c19d1205 ZW |
1102 | if (*str == '|' || *str == '+') |
1103 | { | |
1104 | str++; | |
1105 | another_range = 1; | |
1106 | } | |
a737bd4d | 1107 | } |
c19d1205 | 1108 | while (another_range); |
a737bd4d | 1109 | |
c19d1205 ZW |
1110 | *strp = str; |
1111 | return range; | |
a737bd4d NC |
1112 | } |
1113 | ||
c19d1205 ZW |
1114 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1115 | Otherwise return the number of registers, and set PBASE to the first | |
1116 | register. Double precision registers are matched if DP is nonzero. */ | |
6057a28f | 1117 | |
c19d1205 | 1118 | static int |
ca3f61f7 | 1119 | parse_vfp_reg_list (char **str, unsigned int *pbase, int dp) |
6057a28f | 1120 | { |
c19d1205 ZW |
1121 | int base_reg; |
1122 | int new_base; | |
1123 | int regtype; | |
1124 | int max_regs; | |
1125 | int count = 0; | |
1126 | int warned = 0; | |
1127 | unsigned long mask = 0; | |
a737bd4d | 1128 | int i; |
6057a28f | 1129 | |
c19d1205 ZW |
1130 | if (**str != '{') |
1131 | return FAIL; | |
6057a28f | 1132 | |
c19d1205 | 1133 | (*str)++; |
6057a28f | 1134 | |
c19d1205 | 1135 | if (dp) |
a737bd4d | 1136 | { |
c19d1205 ZW |
1137 | regtype = REG_TYPE_VFD; |
1138 | max_regs = 16; | |
1139 | } | |
1140 | else | |
1141 | { | |
1142 | regtype = REG_TYPE_VFS; | |
1143 | max_regs = 32; | |
1144 | } | |
6057a28f | 1145 | |
c19d1205 | 1146 | base_reg = max_regs; |
a737bd4d | 1147 | |
c19d1205 ZW |
1148 | do |
1149 | { | |
1150 | new_base = arm_reg_parse (str, regtype); | |
1151 | if (new_base == FAIL) | |
a737bd4d | 1152 | { |
c19d1205 ZW |
1153 | inst.error = gettext (reg_expected_msgs[regtype]); |
1154 | return FAIL; | |
1155 | } | |
a737bd4d | 1156 | |
c19d1205 ZW |
1157 | if (new_base < base_reg) |
1158 | base_reg = new_base; | |
a737bd4d | 1159 | |
c19d1205 ZW |
1160 | if (mask & (1 << new_base)) |
1161 | { | |
1162 | inst.error = _("invalid register list"); | |
1163 | return FAIL; | |
a737bd4d | 1164 | } |
a737bd4d | 1165 | |
c19d1205 ZW |
1166 | if ((mask >> new_base) != 0 && ! warned) |
1167 | { | |
1168 | as_tsktsk (_("register list not in ascending order")); | |
1169 | warned = 1; | |
1170 | } | |
0bbf2aa4 | 1171 | |
c19d1205 ZW |
1172 | mask |= 1 << new_base; |
1173 | count++; | |
0bbf2aa4 | 1174 | |
c19d1205 ZW |
1175 | if (**str == '-') /* We have the start of a range expression */ |
1176 | { | |
1177 | int high_range; | |
0bbf2aa4 | 1178 | |
c19d1205 | 1179 | (*str)++; |
0bbf2aa4 | 1180 | |
c19d1205 ZW |
1181 | if ((high_range = arm_reg_parse (str, regtype)) == FAIL) |
1182 | { | |
1183 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1184 | return FAIL; | |
1185 | } | |
0bbf2aa4 | 1186 | |
c19d1205 ZW |
1187 | if (high_range <= new_base) |
1188 | { | |
1189 | inst.error = _("register range not in ascending order"); | |
1190 | return FAIL; | |
1191 | } | |
0bbf2aa4 | 1192 | |
c19d1205 | 1193 | for (new_base++; new_base <= high_range; new_base++) |
0bbf2aa4 | 1194 | { |
c19d1205 | 1195 | if (mask & (1 << new_base)) |
0bbf2aa4 | 1196 | { |
c19d1205 ZW |
1197 | inst.error = _("invalid register list"); |
1198 | return FAIL; | |
0bbf2aa4 | 1199 | } |
c19d1205 ZW |
1200 | |
1201 | mask |= 1 << new_base; | |
1202 | count++; | |
0bbf2aa4 | 1203 | } |
0bbf2aa4 | 1204 | } |
0bbf2aa4 | 1205 | } |
c19d1205 | 1206 | while (skip_past_comma (str) != FAIL); |
0bbf2aa4 | 1207 | |
c19d1205 | 1208 | (*str)++; |
0bbf2aa4 | 1209 | |
c19d1205 ZW |
1210 | /* Sanity check -- should have raised a parse error above. */ |
1211 | if (count == 0 || count > max_regs) | |
1212 | abort (); | |
1213 | ||
1214 | *pbase = base_reg; | |
1215 | ||
1216 | /* Final test -- the registers must be consecutive. */ | |
1217 | mask >>= base_reg; | |
1218 | for (i = 0; i < count; i++) | |
1219 | { | |
1220 | if ((mask & (1u << i)) == 0) | |
1221 | { | |
1222 | inst.error = _("non-contiguous register range"); | |
1223 | return FAIL; | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | return count; | |
b99bd4ef NC |
1228 | } |
1229 | ||
c19d1205 ZW |
1230 | /* Parse an explicit relocation suffix on an expression. This is |
1231 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
1232 | arm_reloc_hsh contains no entries, so this function can only | |
1233 | succeed if there is no () after the word. Returns -1 on error, | |
1234 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
1235 | static int | |
1236 | parse_reloc (char **str) | |
b99bd4ef | 1237 | { |
c19d1205 ZW |
1238 | struct reloc_entry *r; |
1239 | char *p, *q; | |
b99bd4ef | 1240 | |
c19d1205 ZW |
1241 | if (**str != '(') |
1242 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 1243 | |
c19d1205 ZW |
1244 | p = *str + 1; |
1245 | q = p; | |
1246 | ||
1247 | while (*q && *q != ')' && *q != ',') | |
1248 | q++; | |
1249 | if (*q != ')') | |
1250 | return -1; | |
1251 | ||
1252 | if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
1253 | return -1; | |
1254 | ||
1255 | *str = q + 1; | |
1256 | return r->reloc; | |
b99bd4ef NC |
1257 | } |
1258 | ||
c19d1205 ZW |
1259 | /* Directives: register aliases. */ |
1260 | ||
b99bd4ef | 1261 | static void |
c19d1205 | 1262 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 1263 | { |
c19d1205 ZW |
1264 | struct reg_entry *new; |
1265 | const char *name; | |
b99bd4ef | 1266 | |
c19d1205 ZW |
1267 | if ((new = hash_find (arm_reg_hsh, str)) != 0) |
1268 | { | |
1269 | if (new->builtin) | |
1270 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); | |
b99bd4ef | 1271 | |
c19d1205 ZW |
1272 | /* Only warn about a redefinition if it's not defined as the |
1273 | same register. */ | |
1274 | else if (new->number != number || new->type != type) | |
1275 | as_warn (_("ignoring redefinition of register alias '%s'"), str); | |
69b97547 | 1276 | |
c19d1205 ZW |
1277 | return; |
1278 | } | |
b99bd4ef | 1279 | |
c19d1205 ZW |
1280 | name = xstrdup (str); |
1281 | new = xmalloc (sizeof (struct reg_entry)); | |
b99bd4ef | 1282 | |
c19d1205 ZW |
1283 | new->name = name; |
1284 | new->number = number; | |
1285 | new->type = type; | |
1286 | new->builtin = FALSE; | |
b99bd4ef | 1287 | |
c19d1205 ZW |
1288 | if (hash_insert (arm_reg_hsh, name, (PTR) new)) |
1289 | abort (); | |
1290 | } | |
b99bd4ef | 1291 | |
c19d1205 | 1292 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 1293 | |
c19d1205 | 1294 | new_register_name .req existing_register_name |
b99bd4ef | 1295 | |
c19d1205 ZW |
1296 | If we find one, or if it looks sufficiently like one that we want to |
1297 | handle any error here, return non-zero. Otherwise return zero. */ | |
b99bd4ef | 1298 | |
c19d1205 ZW |
1299 | static int |
1300 | create_register_alias (char * newname, char *p) | |
1301 | { | |
1302 | struct reg_entry *old; | |
1303 | char *oldname, *nbuf; | |
1304 | size_t nlen; | |
b99bd4ef | 1305 | |
c19d1205 ZW |
1306 | /* The input scrubber ensures that whitespace after the mnemonic is |
1307 | collapsed to single spaces. */ | |
1308 | oldname = p; | |
1309 | if (strncmp (oldname, " .req ", 6) != 0) | |
1310 | return 0; | |
b99bd4ef | 1311 | |
c19d1205 ZW |
1312 | oldname += 6; |
1313 | if (*oldname == '\0') | |
1314 | return 0; | |
b99bd4ef | 1315 | |
c19d1205 ZW |
1316 | old = hash_find (arm_reg_hsh, oldname); |
1317 | if (!old) | |
b99bd4ef | 1318 | { |
c19d1205 ZW |
1319 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
1320 | return 1; | |
b99bd4ef NC |
1321 | } |
1322 | ||
c19d1205 ZW |
1323 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
1324 | the desired alias name, and p points to its end. If not, then | |
1325 | the desired alias name is in the global original_case_string. */ | |
1326 | #ifdef TC_CASE_SENSITIVE | |
1327 | nlen = p - newname; | |
1328 | #else | |
1329 | newname = original_case_string; | |
1330 | nlen = strlen (newname); | |
1331 | #endif | |
b99bd4ef | 1332 | |
c19d1205 ZW |
1333 | nbuf = alloca (nlen + 1); |
1334 | memcpy (nbuf, newname, nlen); | |
1335 | nbuf[nlen] = '\0'; | |
b99bd4ef | 1336 | |
c19d1205 ZW |
1337 | /* Create aliases under the new name as stated; an all-lowercase |
1338 | version of the new name; and an all-uppercase version of the new | |
1339 | name. */ | |
1340 | insert_reg_alias (nbuf, old->number, old->type); | |
b99bd4ef | 1341 | |
c19d1205 ZW |
1342 | for (p = nbuf; *p; p++) |
1343 | *p = TOUPPER (*p); | |
1344 | ||
1345 | if (strncmp (nbuf, newname, nlen)) | |
1346 | insert_reg_alias (nbuf, old->number, old->type); | |
1347 | ||
1348 | for (p = nbuf; *p; p++) | |
1349 | *p = TOLOWER (*p); | |
1350 | ||
1351 | if (strncmp (nbuf, newname, nlen)) | |
1352 | insert_reg_alias (nbuf, old->number, old->type); | |
1353 | ||
1354 | return 1; | |
b99bd4ef NC |
1355 | } |
1356 | ||
c19d1205 ZW |
1357 | /* Should never be called, as .req goes between the alias and the |
1358 | register name, not at the beginning of the line. */ | |
b99bd4ef | 1359 | static void |
c19d1205 | 1360 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 1361 | { |
c19d1205 ZW |
1362 | as_bad (_("invalid syntax for .req directive")); |
1363 | } | |
b99bd4ef | 1364 | |
c19d1205 ZW |
1365 | /* The .unreq directive deletes an alias which was previously defined |
1366 | by .req. For example: | |
b99bd4ef | 1367 | |
c19d1205 ZW |
1368 | my_alias .req r11 |
1369 | .unreq my_alias */ | |
b99bd4ef NC |
1370 | |
1371 | static void | |
c19d1205 | 1372 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 1373 | { |
c19d1205 ZW |
1374 | char * name; |
1375 | char saved_char; | |
b99bd4ef | 1376 | |
c19d1205 ZW |
1377 | name = input_line_pointer; |
1378 | ||
1379 | while (*input_line_pointer != 0 | |
1380 | && *input_line_pointer != ' ' | |
1381 | && *input_line_pointer != '\n') | |
1382 | ++input_line_pointer; | |
1383 | ||
1384 | saved_char = *input_line_pointer; | |
1385 | *input_line_pointer = 0; | |
1386 | ||
1387 | if (!*name) | |
1388 | as_bad (_("invalid syntax for .unreq directive")); | |
1389 | else | |
1390 | { | |
1391 | struct reg_entry *reg = hash_find (arm_reg_hsh, name); | |
1392 | ||
1393 | if (!reg) | |
1394 | as_bad (_("unknown register alias '%s'"), name); | |
1395 | else if (reg->builtin) | |
1396 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
1397 | name); | |
1398 | else | |
1399 | { | |
1400 | hash_delete (arm_reg_hsh, name); | |
1401 | free ((char *) reg->name); | |
1402 | free (reg); | |
1403 | } | |
1404 | } | |
b99bd4ef | 1405 | |
c19d1205 | 1406 | *input_line_pointer = saved_char; |
b99bd4ef NC |
1407 | demand_empty_rest_of_line (); |
1408 | } | |
1409 | ||
c19d1205 ZW |
1410 | /* Directives: Instruction set selection. */ |
1411 | ||
1412 | #ifdef OBJ_ELF | |
1413 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
1414 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
1415 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
1416 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
1417 | ||
1418 | static enum mstate mapstate = MAP_UNDEFINED; | |
b99bd4ef NC |
1419 | |
1420 | static void | |
c19d1205 | 1421 | mapping_state (enum mstate state) |
b99bd4ef | 1422 | { |
a737bd4d | 1423 | symbolS * symbolP; |
c19d1205 ZW |
1424 | const char * symname; |
1425 | int type; | |
b99bd4ef | 1426 | |
c19d1205 ZW |
1427 | if (mapstate == state) |
1428 | /* The mapping symbol has already been emitted. | |
1429 | There is nothing else to do. */ | |
1430 | return; | |
b99bd4ef | 1431 | |
c19d1205 | 1432 | mapstate = state; |
b99bd4ef | 1433 | |
c19d1205 | 1434 | switch (state) |
b99bd4ef | 1435 | { |
c19d1205 ZW |
1436 | case MAP_DATA: |
1437 | symname = "$d"; | |
1438 | type = BSF_NO_FLAGS; | |
1439 | break; | |
1440 | case MAP_ARM: | |
1441 | symname = "$a"; | |
1442 | type = BSF_NO_FLAGS; | |
1443 | break; | |
1444 | case MAP_THUMB: | |
1445 | symname = "$t"; | |
1446 | type = BSF_NO_FLAGS; | |
1447 | break; | |
1448 | case MAP_UNDEFINED: | |
1449 | return; | |
1450 | default: | |
1451 | abort (); | |
1452 | } | |
1453 | ||
1454 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; | |
1455 | ||
1456 | symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); | |
1457 | symbol_table_insert (symbolP); | |
1458 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; | |
1459 | ||
1460 | switch (state) | |
1461 | { | |
1462 | case MAP_ARM: | |
1463 | THUMB_SET_FUNC (symbolP, 0); | |
1464 | ARM_SET_THUMB (symbolP, 0); | |
1465 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1466 | break; | |
1467 | ||
1468 | case MAP_THUMB: | |
1469 | THUMB_SET_FUNC (symbolP, 1); | |
1470 | ARM_SET_THUMB (symbolP, 1); | |
1471 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1472 | break; | |
1473 | ||
1474 | case MAP_DATA: | |
1475 | default: | |
1476 | return; | |
1477 | } | |
1478 | } | |
1479 | #else | |
1480 | #define mapping_state(x) /* nothing */ | |
1481 | #endif | |
1482 | ||
1483 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
1484 | ||
1485 | static symbolS * | |
1486 | find_real_start (symbolS * symbolP) | |
1487 | { | |
1488 | char * real_start; | |
1489 | const char * name = S_GET_NAME (symbolP); | |
1490 | symbolS * new_target; | |
1491 | ||
1492 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
1493 | #define STUB_NAME ".real_start_of" | |
1494 | ||
1495 | if (name == NULL) | |
1496 | abort (); | |
1497 | ||
37f6032b ZW |
1498 | /* The compiler may generate BL instructions to local labels because |
1499 | it needs to perform a branch to a far away location. These labels | |
1500 | do not have a corresponding ".real_start_of" label. We check | |
1501 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
1502 | the ".real_start_of" convention for nonlocal branches. */ | |
1503 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
1504 | return symbolP; |
1505 | ||
37f6032b | 1506 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
1507 | new_target = symbol_find (real_start); |
1508 | ||
1509 | if (new_target == NULL) | |
1510 | { | |
1511 | as_warn ("Failed to find real start of function: %s\n", name); | |
1512 | new_target = symbolP; | |
1513 | } | |
1514 | ||
c19d1205 ZW |
1515 | return new_target; |
1516 | } | |
1517 | ||
1518 | static void | |
1519 | opcode_select (int width) | |
1520 | { | |
1521 | switch (width) | |
1522 | { | |
1523 | case 16: | |
1524 | if (! thumb_mode) | |
1525 | { | |
e74cfd16 | 1526 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
1527 | as_bad (_("selected processor does not support THUMB opcodes")); |
1528 | ||
1529 | thumb_mode = 1; | |
1530 | /* No need to force the alignment, since we will have been | |
1531 | coming from ARM mode, which is word-aligned. */ | |
1532 | record_alignment (now_seg, 1); | |
1533 | } | |
1534 | mapping_state (MAP_THUMB); | |
1535 | break; | |
1536 | ||
1537 | case 32: | |
1538 | if (thumb_mode) | |
1539 | { | |
e74cfd16 | 1540 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
1541 | as_bad (_("selected processor does not support ARM opcodes")); |
1542 | ||
1543 | thumb_mode = 0; | |
1544 | ||
1545 | if (!need_pass_2) | |
1546 | frag_align (2, 0, 0); | |
1547 | ||
1548 | record_alignment (now_seg, 1); | |
1549 | } | |
1550 | mapping_state (MAP_ARM); | |
1551 | break; | |
1552 | ||
1553 | default: | |
1554 | as_bad (_("invalid instruction size selected (%d)"), width); | |
1555 | } | |
1556 | } | |
1557 | ||
1558 | static void | |
1559 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
1560 | { | |
1561 | opcode_select (32); | |
1562 | demand_empty_rest_of_line (); | |
1563 | } | |
1564 | ||
1565 | static void | |
1566 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
1567 | { | |
1568 | opcode_select (16); | |
1569 | demand_empty_rest_of_line (); | |
1570 | } | |
1571 | ||
1572 | static void | |
1573 | s_code (int unused ATTRIBUTE_UNUSED) | |
1574 | { | |
1575 | int temp; | |
1576 | ||
1577 | temp = get_absolute_expression (); | |
1578 | switch (temp) | |
1579 | { | |
1580 | case 16: | |
1581 | case 32: | |
1582 | opcode_select (temp); | |
1583 | break; | |
1584 | ||
1585 | default: | |
1586 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | static void | |
1591 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
1592 | { | |
1593 | /* If we are not already in thumb mode go into it, EVEN if | |
1594 | the target processor does not support thumb instructions. | |
1595 | This is used by gcc/config/arm/lib1funcs.asm for example | |
1596 | to compile interworking support functions even if the | |
1597 | target processor should not support interworking. */ | |
1598 | if (! thumb_mode) | |
1599 | { | |
1600 | thumb_mode = 2; | |
1601 | record_alignment (now_seg, 1); | |
1602 | } | |
1603 | ||
1604 | demand_empty_rest_of_line (); | |
1605 | } | |
1606 | ||
1607 | static void | |
1608 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
1609 | { | |
1610 | s_thumb (0); | |
1611 | ||
1612 | /* The following label is the name/address of the start of a Thumb function. | |
1613 | We need to know this for the interworking support. */ | |
1614 | label_is_thumb_function_name = TRUE; | |
1615 | } | |
1616 | ||
1617 | /* Perform a .set directive, but also mark the alias as | |
1618 | being a thumb function. */ | |
1619 | ||
1620 | static void | |
1621 | s_thumb_set (int equiv) | |
1622 | { | |
1623 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
1624 | We cannot just call that code as we need to get at the symbol that | |
1625 | is created. */ | |
1626 | char * name; | |
1627 | char delim; | |
1628 | char * end_name; | |
1629 | symbolS * symbolP; | |
1630 | ||
1631 | /* Especial apologies for the random logic: | |
1632 | This just grew, and could be parsed much more simply! | |
1633 | Dean - in haste. */ | |
1634 | name = input_line_pointer; | |
1635 | delim = get_symbol_end (); | |
1636 | end_name = input_line_pointer; | |
1637 | *end_name = delim; | |
1638 | ||
1639 | if (*input_line_pointer != ',') | |
1640 | { | |
1641 | *end_name = 0; | |
1642 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
1643 | *end_name = delim; |
1644 | ignore_rest_of_line (); | |
1645 | return; | |
1646 | } | |
1647 | ||
1648 | input_line_pointer++; | |
1649 | *end_name = 0; | |
1650 | ||
1651 | if (name[0] == '.' && name[1] == '\0') | |
1652 | { | |
1653 | /* XXX - this should not happen to .thumb_set. */ | |
1654 | abort (); | |
1655 | } | |
1656 | ||
1657 | if ((symbolP = symbol_find (name)) == NULL | |
1658 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
1659 | { | |
1660 | #ifndef NO_LISTING | |
1661 | /* When doing symbol listings, play games with dummy fragments living | |
1662 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 1663 | for this symbol. */ |
b99bd4ef NC |
1664 | if (listing & LISTING_SYMBOLS) |
1665 | { | |
1666 | extern struct list_info_struct * listing_tail; | |
a737bd4d | 1667 | fragS * dummy_frag = xmalloc (sizeof (fragS)); |
b99bd4ef NC |
1668 | |
1669 | memset (dummy_frag, 0, sizeof (fragS)); | |
1670 | dummy_frag->fr_type = rs_fill; | |
1671 | dummy_frag->line = listing_tail; | |
1672 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
1673 | dummy_frag->fr_symbol = symbolP; | |
1674 | } | |
1675 | else | |
1676 | #endif | |
1677 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
1678 | ||
1679 | #ifdef OBJ_COFF | |
1680 | /* "set" symbols are local unless otherwise specified. */ | |
1681 | SF_SET_LOCAL (symbolP); | |
1682 | #endif /* OBJ_COFF */ | |
1683 | } /* Make a new symbol. */ | |
1684 | ||
1685 | symbol_table_insert (symbolP); | |
1686 | ||
1687 | * end_name = delim; | |
1688 | ||
1689 | if (equiv | |
1690 | && S_IS_DEFINED (symbolP) | |
1691 | && S_GET_SEGMENT (symbolP) != reg_section) | |
1692 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
1693 | ||
1694 | pseudo_set (symbolP); | |
1695 | ||
1696 | demand_empty_rest_of_line (); | |
1697 | ||
c19d1205 | 1698 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
1699 | |
1700 | THUMB_SET_FUNC (symbolP, 1); | |
1701 | ARM_SET_THUMB (symbolP, 1); | |
1702 | #if defined OBJ_ELF || defined OBJ_COFF | |
1703 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1704 | #endif | |
1705 | } | |
1706 | ||
c19d1205 | 1707 | /* Directives: Mode selection. */ |
b99bd4ef | 1708 | |
c19d1205 ZW |
1709 | /* .syntax [unified|divided] - choose the new unified syntax |
1710 | (same for Arm and Thumb encoding, modulo slight differences in what | |
1711 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 1712 | static void |
c19d1205 | 1713 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 1714 | { |
c19d1205 ZW |
1715 | char *name, delim; |
1716 | ||
1717 | name = input_line_pointer; | |
1718 | delim = get_symbol_end (); | |
1719 | ||
1720 | if (!strcasecmp (name, "unified")) | |
1721 | unified_syntax = TRUE; | |
1722 | else if (!strcasecmp (name, "divided")) | |
1723 | unified_syntax = FALSE; | |
1724 | else | |
1725 | { | |
1726 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
1727 | return; | |
1728 | } | |
1729 | *input_line_pointer = delim; | |
b99bd4ef NC |
1730 | demand_empty_rest_of_line (); |
1731 | } | |
1732 | ||
c19d1205 ZW |
1733 | /* Directives: sectioning and alignment. */ |
1734 | ||
1735 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
1736 | ||
b99bd4ef | 1737 | static void |
c19d1205 | 1738 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 1739 | { |
a737bd4d | 1740 | int temp; |
c19d1205 ZW |
1741 | long temp_fill; |
1742 | long max_alignment = 15; | |
b99bd4ef NC |
1743 | |
1744 | temp = get_absolute_expression (); | |
c19d1205 ZW |
1745 | if (temp > max_alignment) |
1746 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
1747 | else if (temp < 0) | |
b99bd4ef | 1748 | { |
c19d1205 ZW |
1749 | as_bad (_("alignment negative. 0 assumed.")); |
1750 | temp = 0; | |
1751 | } | |
b99bd4ef | 1752 | |
c19d1205 ZW |
1753 | if (*input_line_pointer == ',') |
1754 | { | |
1755 | input_line_pointer++; | |
1756 | temp_fill = get_absolute_expression (); | |
b99bd4ef | 1757 | } |
c19d1205 ZW |
1758 | else |
1759 | temp_fill = 0; | |
b99bd4ef | 1760 | |
c19d1205 ZW |
1761 | if (!temp) |
1762 | temp = 2; | |
b99bd4ef | 1763 | |
c19d1205 ZW |
1764 | /* Only make a frag if we HAVE to. */ |
1765 | if (temp && !need_pass_2) | |
1766 | frag_align (temp, (int) temp_fill, 0); | |
1767 | demand_empty_rest_of_line (); | |
1768 | ||
1769 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
1770 | } |
1771 | ||
c19d1205 ZW |
1772 | static void |
1773 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 1774 | { |
c19d1205 ZW |
1775 | /* We don't support putting frags in the BSS segment, we fake it by |
1776 | marking in_bss, then looking at s_skip for clues. */ | |
1777 | subseg_set (bss_section, 0); | |
1778 | demand_empty_rest_of_line (); | |
1779 | mapping_state (MAP_DATA); | |
1780 | } | |
b99bd4ef | 1781 | |
c19d1205 ZW |
1782 | static void |
1783 | s_even (int ignore ATTRIBUTE_UNUSED) | |
1784 | { | |
1785 | /* Never make frag if expect extra pass. */ | |
1786 | if (!need_pass_2) | |
1787 | frag_align (1, 0, 0); | |
b99bd4ef | 1788 | |
c19d1205 | 1789 | record_alignment (now_seg, 1); |
b99bd4ef | 1790 | |
c19d1205 | 1791 | demand_empty_rest_of_line (); |
b99bd4ef NC |
1792 | } |
1793 | ||
c19d1205 | 1794 | /* Directives: Literal pools. */ |
a737bd4d | 1795 | |
c19d1205 ZW |
1796 | static literal_pool * |
1797 | find_literal_pool (void) | |
a737bd4d | 1798 | { |
c19d1205 | 1799 | literal_pool * pool; |
a737bd4d | 1800 | |
c19d1205 | 1801 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 1802 | { |
c19d1205 ZW |
1803 | if (pool->section == now_seg |
1804 | && pool->sub_section == now_subseg) | |
1805 | break; | |
a737bd4d NC |
1806 | } |
1807 | ||
c19d1205 | 1808 | return pool; |
a737bd4d NC |
1809 | } |
1810 | ||
c19d1205 ZW |
1811 | static literal_pool * |
1812 | find_or_make_literal_pool (void) | |
a737bd4d | 1813 | { |
c19d1205 ZW |
1814 | /* Next literal pool ID number. */ |
1815 | static unsigned int latest_pool_num = 1; | |
1816 | literal_pool * pool; | |
a737bd4d | 1817 | |
c19d1205 | 1818 | pool = find_literal_pool (); |
a737bd4d | 1819 | |
c19d1205 | 1820 | if (pool == NULL) |
a737bd4d | 1821 | { |
c19d1205 ZW |
1822 | /* Create a new pool. */ |
1823 | pool = xmalloc (sizeof (* pool)); | |
1824 | if (! pool) | |
1825 | return NULL; | |
a737bd4d | 1826 | |
c19d1205 ZW |
1827 | pool->next_free_entry = 0; |
1828 | pool->section = now_seg; | |
1829 | pool->sub_section = now_subseg; | |
1830 | pool->next = list_of_pools; | |
1831 | pool->symbol = NULL; | |
1832 | ||
1833 | /* Add it to the list. */ | |
1834 | list_of_pools = pool; | |
a737bd4d | 1835 | } |
a737bd4d | 1836 | |
c19d1205 ZW |
1837 | /* New pools, and emptied pools, will have a NULL symbol. */ |
1838 | if (pool->symbol == NULL) | |
a737bd4d | 1839 | { |
c19d1205 ZW |
1840 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
1841 | (valueT) 0, &zero_address_frag); | |
1842 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
1843 | } |
1844 | ||
c19d1205 ZW |
1845 | /* Done. */ |
1846 | return pool; | |
a737bd4d NC |
1847 | } |
1848 | ||
c19d1205 ZW |
1849 | /* Add the literal in the global 'inst' |
1850 | structure to the relevent literal pool. */ | |
b99bd4ef NC |
1851 | |
1852 | static int | |
c19d1205 | 1853 | add_to_lit_pool (void) |
b99bd4ef | 1854 | { |
c19d1205 ZW |
1855 | literal_pool * pool; |
1856 | unsigned int entry; | |
b99bd4ef | 1857 | |
c19d1205 ZW |
1858 | pool = find_or_make_literal_pool (); |
1859 | ||
1860 | /* Check if this literal value is already in the pool. */ | |
1861 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 1862 | { |
c19d1205 ZW |
1863 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
1864 | && (inst.reloc.exp.X_op == O_constant) | |
1865 | && (pool->literals[entry].X_add_number | |
1866 | == inst.reloc.exp.X_add_number) | |
1867 | && (pool->literals[entry].X_unsigned | |
1868 | == inst.reloc.exp.X_unsigned)) | |
1869 | break; | |
1870 | ||
1871 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
1872 | && (inst.reloc.exp.X_op == O_symbol) | |
1873 | && (pool->literals[entry].X_add_number | |
1874 | == inst.reloc.exp.X_add_number) | |
1875 | && (pool->literals[entry].X_add_symbol | |
1876 | == inst.reloc.exp.X_add_symbol) | |
1877 | && (pool->literals[entry].X_op_symbol | |
1878 | == inst.reloc.exp.X_op_symbol)) | |
1879 | break; | |
b99bd4ef NC |
1880 | } |
1881 | ||
c19d1205 ZW |
1882 | /* Do we need to create a new entry? */ |
1883 | if (entry == pool->next_free_entry) | |
1884 | { | |
1885 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
1886 | { | |
1887 | inst.error = _("literal pool overflow"); | |
1888 | return FAIL; | |
1889 | } | |
1890 | ||
1891 | pool->literals[entry] = inst.reloc.exp; | |
1892 | pool->next_free_entry += 1; | |
1893 | } | |
b99bd4ef | 1894 | |
c19d1205 ZW |
1895 | inst.reloc.exp.X_op = O_symbol; |
1896 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
1897 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 1898 | |
c19d1205 | 1899 | return SUCCESS; |
b99bd4ef NC |
1900 | } |
1901 | ||
c19d1205 ZW |
1902 | /* Can't use symbol_new here, so have to create a symbol and then at |
1903 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 1904 | |
c19d1205 ZW |
1905 | static void |
1906 | symbol_locate (symbolS * symbolP, | |
1907 | const char * name, /* It is copied, the caller can modify. */ | |
1908 | segT segment, /* Segment identifier (SEG_<something>). */ | |
1909 | valueT valu, /* Symbol value. */ | |
1910 | fragS * frag) /* Associated fragment. */ | |
1911 | { | |
1912 | unsigned int name_length; | |
1913 | char * preserved_copy_of_name; | |
e16bb312 | 1914 | |
c19d1205 ZW |
1915 | name_length = strlen (name) + 1; /* +1 for \0. */ |
1916 | obstack_grow (¬es, name, name_length); | |
1917 | preserved_copy_of_name = obstack_finish (¬es); | |
e16bb312 | 1918 | |
c19d1205 ZW |
1919 | #ifdef tc_canonicalize_symbol_name |
1920 | preserved_copy_of_name = | |
1921 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
1922 | #endif | |
b99bd4ef | 1923 | |
c19d1205 | 1924 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 1925 | |
c19d1205 ZW |
1926 | S_SET_SEGMENT (symbolP, segment); |
1927 | S_SET_VALUE (symbolP, valu); | |
1928 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 1929 | |
c19d1205 | 1930 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 1931 | |
c19d1205 ZW |
1932 | /* Link to end of symbol chain. */ |
1933 | { | |
1934 | extern int symbol_table_frozen; | |
b99bd4ef | 1935 | |
c19d1205 ZW |
1936 | if (symbol_table_frozen) |
1937 | abort (); | |
1938 | } | |
b99bd4ef | 1939 | |
c19d1205 | 1940 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 1941 | |
c19d1205 | 1942 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 1943 | |
c19d1205 ZW |
1944 | #ifdef tc_symbol_new_hook |
1945 | tc_symbol_new_hook (symbolP); | |
1946 | #endif | |
1947 | ||
1948 | #ifdef DEBUG_SYMS | |
1949 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
1950 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
1951 | } |
1952 | ||
b99bd4ef | 1953 | |
c19d1205 ZW |
1954 | static void |
1955 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 1956 | { |
c19d1205 ZW |
1957 | unsigned int entry; |
1958 | literal_pool * pool; | |
1959 | char sym_name[20]; | |
b99bd4ef | 1960 | |
c19d1205 ZW |
1961 | pool = find_literal_pool (); |
1962 | if (pool == NULL | |
1963 | || pool->symbol == NULL | |
1964 | || pool->next_free_entry == 0) | |
1965 | return; | |
b99bd4ef | 1966 | |
c19d1205 | 1967 | mapping_state (MAP_DATA); |
b99bd4ef | 1968 | |
c19d1205 ZW |
1969 | /* Align pool as you have word accesses. |
1970 | Only make a frag if we have to. */ | |
1971 | if (!need_pass_2) | |
1972 | frag_align (2, 0, 0); | |
b99bd4ef | 1973 | |
c19d1205 | 1974 | record_alignment (now_seg, 2); |
b99bd4ef | 1975 | |
c19d1205 | 1976 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 1977 | |
c19d1205 ZW |
1978 | symbol_locate (pool->symbol, sym_name, now_seg, |
1979 | (valueT) frag_now_fix (), frag_now); | |
1980 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 1981 | |
c19d1205 | 1982 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 1983 | |
c19d1205 ZW |
1984 | #if defined OBJ_COFF || defined OBJ_ELF |
1985 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
1986 | #endif | |
6c43fab6 | 1987 | |
c19d1205 ZW |
1988 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
1989 | /* First output the expression in the instruction to the pool. */ | |
1990 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 1991 | |
c19d1205 ZW |
1992 | /* Mark the pool as empty. */ |
1993 | pool->next_free_entry = 0; | |
1994 | pool->symbol = NULL; | |
b99bd4ef NC |
1995 | } |
1996 | ||
c19d1205 ZW |
1997 | #ifdef OBJ_ELF |
1998 | /* Forward declarations for functions below, in the MD interface | |
1999 | section. */ | |
2000 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
2001 | static valueT create_unwind_entry (int); | |
2002 | static void start_unwind_section (const segT, int); | |
2003 | static void add_unwind_opcode (valueT, int); | |
2004 | static void flush_pending_unwind (void); | |
b99bd4ef | 2005 | |
c19d1205 | 2006 | /* Directives: Data. */ |
b99bd4ef | 2007 | |
c19d1205 ZW |
2008 | static void |
2009 | s_arm_elf_cons (int nbytes) | |
2010 | { | |
2011 | expressionS exp; | |
b99bd4ef | 2012 | |
c19d1205 ZW |
2013 | #ifdef md_flush_pending_output |
2014 | md_flush_pending_output (); | |
2015 | #endif | |
b99bd4ef | 2016 | |
c19d1205 | 2017 | if (is_it_end_of_statement ()) |
b99bd4ef | 2018 | { |
c19d1205 ZW |
2019 | demand_empty_rest_of_line (); |
2020 | return; | |
b99bd4ef NC |
2021 | } |
2022 | ||
c19d1205 ZW |
2023 | #ifdef md_cons_align |
2024 | md_cons_align (nbytes); | |
2025 | #endif | |
b99bd4ef | 2026 | |
c19d1205 ZW |
2027 | mapping_state (MAP_DATA); |
2028 | do | |
b99bd4ef | 2029 | { |
c19d1205 ZW |
2030 | int reloc; |
2031 | char *base = input_line_pointer; | |
b99bd4ef | 2032 | |
c19d1205 | 2033 | expression (& exp); |
b99bd4ef | 2034 | |
c19d1205 ZW |
2035 | if (exp.X_op != O_symbol) |
2036 | emit_expr (&exp, (unsigned int) nbytes); | |
2037 | else | |
2038 | { | |
2039 | char *before_reloc = input_line_pointer; | |
2040 | reloc = parse_reloc (&input_line_pointer); | |
2041 | if (reloc == -1) | |
2042 | { | |
2043 | as_bad (_("unrecognized relocation suffix")); | |
2044 | ignore_rest_of_line (); | |
2045 | return; | |
2046 | } | |
2047 | else if (reloc == BFD_RELOC_UNUSED) | |
2048 | emit_expr (&exp, (unsigned int) nbytes); | |
2049 | else | |
2050 | { | |
2051 | reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
2052 | int size = bfd_get_reloc_size (howto); | |
b99bd4ef | 2053 | |
2fc8bdac ZW |
2054 | if (reloc == BFD_RELOC_ARM_PLT32) |
2055 | { | |
2056 | as_bad (_("(plt) is only valid on branch targets")); | |
2057 | reloc = BFD_RELOC_UNUSED; | |
2058 | size = 0; | |
2059 | } | |
2060 | ||
c19d1205 | 2061 | if (size > nbytes) |
2fc8bdac | 2062 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
2063 | howto->name, nbytes); |
2064 | else | |
2065 | { | |
2066 | /* We've parsed an expression stopping at O_symbol. | |
2067 | But there may be more expression left now that we | |
2068 | have parsed the relocation marker. Parse it again. | |
2069 | XXX Surely there is a cleaner way to do this. */ | |
2070 | char *p = input_line_pointer; | |
2071 | int offset; | |
2072 | char *save_buf = alloca (input_line_pointer - base); | |
2073 | memcpy (save_buf, base, input_line_pointer - base); | |
2074 | memmove (base + (input_line_pointer - before_reloc), | |
2075 | base, before_reloc - base); | |
2076 | ||
2077 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
2078 | expression (&exp); | |
2079 | memcpy (base, save_buf, p - base); | |
2080 | ||
2081 | offset = nbytes - size; | |
2082 | p = frag_more ((int) nbytes); | |
2083 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
2084 | size, &exp, 0, reloc); | |
2085 | } | |
2086 | } | |
2087 | } | |
b99bd4ef | 2088 | } |
c19d1205 | 2089 | while (*input_line_pointer++ == ','); |
b99bd4ef | 2090 | |
c19d1205 ZW |
2091 | /* Put terminator back into stream. */ |
2092 | input_line_pointer --; | |
2093 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
2094 | } |
2095 | ||
b99bd4ef | 2096 | |
c19d1205 | 2097 | /* Parse a .rel31 directive. */ |
b99bd4ef | 2098 | |
c19d1205 ZW |
2099 | static void |
2100 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
2101 | { | |
2102 | expressionS exp; | |
2103 | char *p; | |
2104 | valueT highbit; | |
b99bd4ef | 2105 | |
c19d1205 ZW |
2106 | highbit = 0; |
2107 | if (*input_line_pointer == '1') | |
2108 | highbit = 0x80000000; | |
2109 | else if (*input_line_pointer != '0') | |
2110 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 2111 | |
c19d1205 ZW |
2112 | input_line_pointer++; |
2113 | if (*input_line_pointer != ',') | |
2114 | as_bad (_("missing comma")); | |
2115 | input_line_pointer++; | |
b99bd4ef | 2116 | |
c19d1205 ZW |
2117 | #ifdef md_flush_pending_output |
2118 | md_flush_pending_output (); | |
2119 | #endif | |
b99bd4ef | 2120 | |
c19d1205 ZW |
2121 | #ifdef md_cons_align |
2122 | md_cons_align (4); | |
2123 | #endif | |
b99bd4ef | 2124 | |
c19d1205 | 2125 | mapping_state (MAP_DATA); |
b99bd4ef | 2126 | |
c19d1205 | 2127 | expression (&exp); |
b99bd4ef | 2128 | |
c19d1205 ZW |
2129 | p = frag_more (4); |
2130 | md_number_to_chars (p, highbit, 4); | |
2131 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
2132 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 2133 | |
c19d1205 | 2134 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2135 | } |
2136 | ||
c19d1205 | 2137 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 2138 | |
c19d1205 | 2139 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 2140 | |
c19d1205 ZW |
2141 | static void |
2142 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
2143 | { | |
2144 | demand_empty_rest_of_line (); | |
2145 | /* Mark the start of the function. */ | |
2146 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 2147 | |
c19d1205 ZW |
2148 | /* Reset the rest of the unwind info. */ |
2149 | unwind.opcode_count = 0; | |
2150 | unwind.table_entry = NULL; | |
2151 | unwind.personality_routine = NULL; | |
2152 | unwind.personality_index = -1; | |
2153 | unwind.frame_size = 0; | |
2154 | unwind.fp_offset = 0; | |
2155 | unwind.fp_reg = 13; | |
2156 | unwind.fp_used = 0; | |
2157 | unwind.sp_restored = 0; | |
2158 | } | |
b99bd4ef | 2159 | |
b99bd4ef | 2160 | |
c19d1205 ZW |
2161 | /* Parse a handlerdata directive. Creates the exception handling table entry |
2162 | for the function. */ | |
b99bd4ef | 2163 | |
c19d1205 ZW |
2164 | static void |
2165 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
2166 | { | |
2167 | demand_empty_rest_of_line (); | |
2168 | if (unwind.table_entry) | |
2169 | as_bad (_("dupicate .handlerdata directive")); | |
f02232aa | 2170 | |
c19d1205 ZW |
2171 | create_unwind_entry (1); |
2172 | } | |
a737bd4d | 2173 | |
c19d1205 | 2174 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 2175 | |
c19d1205 ZW |
2176 | static void |
2177 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
2178 | { | |
2179 | long where; | |
2180 | char *ptr; | |
2181 | valueT val; | |
f02232aa | 2182 | |
c19d1205 | 2183 | demand_empty_rest_of_line (); |
f02232aa | 2184 | |
c19d1205 ZW |
2185 | /* Add eh table entry. */ |
2186 | if (unwind.table_entry == NULL) | |
2187 | val = create_unwind_entry (0); | |
2188 | else | |
2189 | val = 0; | |
f02232aa | 2190 | |
c19d1205 ZW |
2191 | /* Add index table entry. This is two words. */ |
2192 | start_unwind_section (unwind.saved_seg, 1); | |
2193 | frag_align (2, 0, 0); | |
2194 | record_alignment (now_seg, 2); | |
b99bd4ef | 2195 | |
c19d1205 ZW |
2196 | ptr = frag_more (8); |
2197 | where = frag_now_fix () - 8; | |
f02232aa | 2198 | |
c19d1205 ZW |
2199 | /* Self relative offset of the function start. */ |
2200 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
2201 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 2202 | |
c19d1205 ZW |
2203 | /* Indicate dependency on EHABI-defined personality routines to the |
2204 | linker, if it hasn't been done already. */ | |
2205 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 | |
2206 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
2207 | { | |
2208 | static const char *const name[] = { | |
2209 | "__aeabi_unwind_cpp_pr0", | |
2210 | "__aeabi_unwind_cpp_pr1", | |
2211 | "__aeabi_unwind_cpp_pr2" | |
2212 | }; | |
2213 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); | |
2214 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
2215 | marked_pr_dependency |= 1 << unwind.personality_index; | |
2216 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency | |
2217 | = marked_pr_dependency; | |
2218 | } | |
f02232aa | 2219 | |
c19d1205 ZW |
2220 | if (val) |
2221 | /* Inline exception table entry. */ | |
2222 | md_number_to_chars (ptr + 4, val, 4); | |
2223 | else | |
2224 | /* Self relative offset of the table entry. */ | |
2225 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
2226 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 2227 | |
c19d1205 ZW |
2228 | /* Restore the original section. */ |
2229 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
2230 | } | |
f02232aa | 2231 | |
f02232aa | 2232 | |
c19d1205 | 2233 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 2234 | |
c19d1205 ZW |
2235 | static void |
2236 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
2237 | { | |
2238 | demand_empty_rest_of_line (); | |
2239 | if (unwind.personality_routine || unwind.personality_index != -1) | |
2240 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 2241 | |
c19d1205 ZW |
2242 | unwind.personality_index = -2; |
2243 | } | |
b99bd4ef | 2244 | |
b99bd4ef | 2245 | |
c19d1205 | 2246 | /* Parse a personalityindex directive. */ |
b99bd4ef | 2247 | |
c19d1205 ZW |
2248 | static void |
2249 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
2250 | { | |
2251 | expressionS exp; | |
b99bd4ef | 2252 | |
c19d1205 ZW |
2253 | if (unwind.personality_routine || unwind.personality_index != -1) |
2254 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 2255 | |
c19d1205 | 2256 | expression (&exp); |
b99bd4ef | 2257 | |
c19d1205 ZW |
2258 | if (exp.X_op != O_constant |
2259 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 2260 | { |
c19d1205 ZW |
2261 | as_bad (_("bad personality routine number")); |
2262 | ignore_rest_of_line (); | |
2263 | return; | |
b99bd4ef NC |
2264 | } |
2265 | ||
c19d1205 | 2266 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 2267 | |
c19d1205 ZW |
2268 | demand_empty_rest_of_line (); |
2269 | } | |
e16bb312 | 2270 | |
e16bb312 | 2271 | |
c19d1205 | 2272 | /* Parse a personality directive. */ |
e16bb312 | 2273 | |
c19d1205 ZW |
2274 | static void |
2275 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
2276 | { | |
2277 | char *name, *p, c; | |
a737bd4d | 2278 | |
c19d1205 ZW |
2279 | if (unwind.personality_routine || unwind.personality_index != -1) |
2280 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 2281 | |
c19d1205 ZW |
2282 | name = input_line_pointer; |
2283 | c = get_symbol_end (); | |
2284 | p = input_line_pointer; | |
2285 | unwind.personality_routine = symbol_find_or_make (name); | |
2286 | *p = c; | |
2287 | demand_empty_rest_of_line (); | |
2288 | } | |
e16bb312 | 2289 | |
e16bb312 | 2290 | |
c19d1205 | 2291 | /* Parse a directive saving core registers. */ |
e16bb312 | 2292 | |
c19d1205 ZW |
2293 | static void |
2294 | s_arm_unwind_save_core (void) | |
e16bb312 | 2295 | { |
c19d1205 ZW |
2296 | valueT op; |
2297 | long range; | |
2298 | int n; | |
e16bb312 | 2299 | |
c19d1205 ZW |
2300 | range = parse_reg_list (&input_line_pointer); |
2301 | if (range == FAIL) | |
e16bb312 | 2302 | { |
c19d1205 ZW |
2303 | as_bad (_("expected register list")); |
2304 | ignore_rest_of_line (); | |
2305 | return; | |
2306 | } | |
e16bb312 | 2307 | |
c19d1205 | 2308 | demand_empty_rest_of_line (); |
e16bb312 | 2309 | |
c19d1205 ZW |
2310 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
2311 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
2312 | ip because it is clobbered by calls. */ | |
2313 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
2314 | && (range & 0x3000) == 0x1000) | |
2315 | { | |
2316 | unwind.opcode_count--; | |
2317 | unwind.sp_restored = 0; | |
2318 | range = (range | 0x2000) & ~0x1000; | |
2319 | unwind.pending_offset = 0; | |
2320 | } | |
e16bb312 | 2321 | |
01ae4198 DJ |
2322 | /* Pop r4-r15. */ |
2323 | if (range & 0xfff0) | |
c19d1205 | 2324 | { |
01ae4198 DJ |
2325 | /* See if we can use the short opcodes. These pop a block of up to 8 |
2326 | registers starting with r4, plus maybe r14. */ | |
2327 | for (n = 0; n < 8; n++) | |
2328 | { | |
2329 | /* Break at the first non-saved register. */ | |
2330 | if ((range & (1 << (n + 4))) == 0) | |
2331 | break; | |
2332 | } | |
2333 | /* See if there are any other bits set. */ | |
2334 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
2335 | { | |
2336 | /* Use the long form. */ | |
2337 | op = 0x8000 | ((range >> 4) & 0xfff); | |
2338 | add_unwind_opcode (op, 2); | |
2339 | } | |
0dd132b6 | 2340 | else |
01ae4198 DJ |
2341 | { |
2342 | /* Use the short form. */ | |
2343 | if (range & 0x4000) | |
2344 | op = 0xa8; /* Pop r14. */ | |
2345 | else | |
2346 | op = 0xa0; /* Do not pop r14. */ | |
2347 | op |= (n - 1); | |
2348 | add_unwind_opcode (op, 1); | |
2349 | } | |
c19d1205 | 2350 | } |
0dd132b6 | 2351 | |
c19d1205 ZW |
2352 | /* Pop r0-r3. */ |
2353 | if (range & 0xf) | |
2354 | { | |
2355 | op = 0xb100 | (range & 0xf); | |
2356 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
2357 | } |
2358 | ||
c19d1205 ZW |
2359 | /* Record the number of bytes pushed. */ |
2360 | for (n = 0; n < 16; n++) | |
2361 | { | |
2362 | if (range & (1 << n)) | |
2363 | unwind.frame_size += 4; | |
2364 | } | |
0dd132b6 NC |
2365 | } |
2366 | ||
c19d1205 ZW |
2367 | |
2368 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
2369 | |
2370 | static void | |
c19d1205 | 2371 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 2372 | { |
c19d1205 ZW |
2373 | expressionS exp; |
2374 | int num_regs; | |
2375 | valueT op; | |
b99bd4ef | 2376 | |
c19d1205 ZW |
2377 | /* Get Number of registers to transfer. */ |
2378 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
2379 | expression (&exp); | |
2380 | else | |
2381 | exp.X_op = O_illegal; | |
b99bd4ef | 2382 | |
c19d1205 | 2383 | if (exp.X_op != O_constant) |
b99bd4ef | 2384 | { |
c19d1205 ZW |
2385 | as_bad (_("expected , <constant>")); |
2386 | ignore_rest_of_line (); | |
b99bd4ef NC |
2387 | return; |
2388 | } | |
2389 | ||
c19d1205 ZW |
2390 | num_regs = exp.X_add_number; |
2391 | ||
2392 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 2393 | { |
c19d1205 ZW |
2394 | as_bad (_("number of registers must be in the range [1:4]")); |
2395 | ignore_rest_of_line (); | |
b99bd4ef NC |
2396 | return; |
2397 | } | |
2398 | ||
c19d1205 | 2399 | demand_empty_rest_of_line (); |
b99bd4ef | 2400 | |
c19d1205 ZW |
2401 | if (reg == 4) |
2402 | { | |
2403 | /* Short form. */ | |
2404 | op = 0xb4 | (num_regs - 1); | |
2405 | add_unwind_opcode (op, 1); | |
2406 | } | |
b99bd4ef NC |
2407 | else |
2408 | { | |
c19d1205 ZW |
2409 | /* Long form. */ |
2410 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
2411 | add_unwind_opcode (op, 2); | |
b99bd4ef | 2412 | } |
c19d1205 | 2413 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
2414 | } |
2415 | ||
c19d1205 ZW |
2416 | |
2417 | /* Parse a directive saving VFP registers. */ | |
b99bd4ef NC |
2418 | |
2419 | static void | |
c19d1205 | 2420 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 2421 | { |
c19d1205 | 2422 | int count; |
ca3f61f7 | 2423 | unsigned int reg; |
c19d1205 | 2424 | valueT op; |
b99bd4ef | 2425 | |
c19d1205 ZW |
2426 | count = parse_vfp_reg_list (&input_line_pointer, ®, 1); |
2427 | if (count == FAIL) | |
b99bd4ef | 2428 | { |
c19d1205 ZW |
2429 | as_bad (_("expected register list")); |
2430 | ignore_rest_of_line (); | |
b99bd4ef NC |
2431 | return; |
2432 | } | |
2433 | ||
c19d1205 | 2434 | demand_empty_rest_of_line (); |
b99bd4ef | 2435 | |
c19d1205 | 2436 | if (reg == 8) |
b99bd4ef | 2437 | { |
c19d1205 ZW |
2438 | /* Short form. */ |
2439 | op = 0xb8 | (count - 1); | |
2440 | add_unwind_opcode (op, 1); | |
b99bd4ef | 2441 | } |
c19d1205 | 2442 | else |
b99bd4ef | 2443 | { |
c19d1205 ZW |
2444 | /* Long form. */ |
2445 | op = 0xb300 | (reg << 4) | (count - 1); | |
2446 | add_unwind_opcode (op, 2); | |
b99bd4ef | 2447 | } |
c19d1205 ZW |
2448 | unwind.frame_size += count * 8 + 4; |
2449 | } | |
b99bd4ef | 2450 | |
b99bd4ef | 2451 | |
c19d1205 ZW |
2452 | /* Parse a directive saving iWMMXt data registers. */ |
2453 | ||
2454 | static void | |
2455 | s_arm_unwind_save_mmxwr (void) | |
2456 | { | |
2457 | int reg; | |
2458 | int hi_reg; | |
2459 | int i; | |
2460 | unsigned mask = 0; | |
2461 | valueT op; | |
b99bd4ef | 2462 | |
c19d1205 ZW |
2463 | if (*input_line_pointer == '{') |
2464 | input_line_pointer++; | |
b99bd4ef | 2465 | |
c19d1205 | 2466 | do |
b99bd4ef | 2467 | { |
c19d1205 | 2468 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 2469 | |
c19d1205 | 2470 | if (reg == FAIL) |
b99bd4ef | 2471 | { |
c19d1205 ZW |
2472 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); |
2473 | goto error; | |
b99bd4ef NC |
2474 | } |
2475 | ||
c19d1205 ZW |
2476 | if (mask >> reg) |
2477 | as_tsktsk (_("register list not in ascending order")); | |
2478 | mask |= 1 << reg; | |
b99bd4ef | 2479 | |
c19d1205 ZW |
2480 | if (*input_line_pointer == '-') |
2481 | { | |
2482 | input_line_pointer++; | |
2483 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); | |
2484 | if (hi_reg == FAIL) | |
2485 | { | |
2486 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); | |
2487 | goto error; | |
2488 | } | |
2489 | else if (reg >= hi_reg) | |
2490 | { | |
2491 | as_bad (_("bad register range")); | |
2492 | goto error; | |
2493 | } | |
2494 | for (; reg < hi_reg; reg++) | |
2495 | mask |= 1 << reg; | |
2496 | } | |
2497 | } | |
2498 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 2499 | |
c19d1205 ZW |
2500 | if (*input_line_pointer == '}') |
2501 | input_line_pointer++; | |
b99bd4ef | 2502 | |
c19d1205 | 2503 | demand_empty_rest_of_line (); |
b99bd4ef | 2504 | |
c19d1205 ZW |
2505 | /* Generate any deferred opcodes becuuse we're going to be looking at |
2506 | the list. */ | |
2507 | flush_pending_unwind (); | |
b99bd4ef | 2508 | |
c19d1205 | 2509 | for (i = 0; i < 16; i++) |
b99bd4ef | 2510 | { |
c19d1205 ZW |
2511 | if (mask & (1 << i)) |
2512 | unwind.frame_size += 8; | |
b99bd4ef NC |
2513 | } |
2514 | ||
c19d1205 ZW |
2515 | /* Attempt to combine with a previous opcode. We do this because gcc |
2516 | likes to output separate unwind directives for a single block of | |
2517 | registers. */ | |
2518 | if (unwind.opcode_count > 0) | |
b99bd4ef | 2519 | { |
c19d1205 ZW |
2520 | i = unwind.opcodes[unwind.opcode_count - 1]; |
2521 | if ((i & 0xf8) == 0xc0) | |
2522 | { | |
2523 | i &= 7; | |
2524 | /* Only merge if the blocks are contiguous. */ | |
2525 | if (i < 6) | |
2526 | { | |
2527 | if ((mask & 0xfe00) == (1 << 9)) | |
2528 | { | |
2529 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
2530 | unwind.opcode_count--; | |
2531 | } | |
2532 | } | |
2533 | else if (i == 6 && unwind.opcode_count >= 2) | |
2534 | { | |
2535 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
2536 | reg = i >> 4; | |
2537 | i &= 0xf; | |
b99bd4ef | 2538 | |
c19d1205 ZW |
2539 | op = 0xffff << (reg - 1); |
2540 | if (reg > 0 | |
2541 | || ((mask & op) == (1u << (reg - 1)))) | |
2542 | { | |
2543 | op = (1 << (reg + i + 1)) - 1; | |
2544 | op &= ~((1 << reg) - 1); | |
2545 | mask |= op; | |
2546 | unwind.opcode_count -= 2; | |
2547 | } | |
2548 | } | |
2549 | } | |
b99bd4ef NC |
2550 | } |
2551 | ||
c19d1205 ZW |
2552 | hi_reg = 15; |
2553 | /* We want to generate opcodes in the order the registers have been | |
2554 | saved, ie. descending order. */ | |
2555 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 2556 | { |
c19d1205 ZW |
2557 | /* Save registers in blocks. */ |
2558 | if (reg < 0 | |
2559 | || !(mask & (1 << reg))) | |
2560 | { | |
2561 | /* We found an unsaved reg. Generate opcodes to save the | |
2562 | preceeding block. */ | |
2563 | if (reg != hi_reg) | |
2564 | { | |
2565 | if (reg == 9) | |
2566 | { | |
2567 | /* Short form. */ | |
2568 | op = 0xc0 | (hi_reg - 10); | |
2569 | add_unwind_opcode (op, 1); | |
2570 | } | |
2571 | else | |
2572 | { | |
2573 | /* Long form. */ | |
2574 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
2575 | add_unwind_opcode (op, 2); | |
2576 | } | |
2577 | } | |
2578 | hi_reg = reg - 1; | |
2579 | } | |
b99bd4ef NC |
2580 | } |
2581 | ||
c19d1205 ZW |
2582 | return; |
2583 | error: | |
2584 | ignore_rest_of_line (); | |
b99bd4ef NC |
2585 | } |
2586 | ||
2587 | static void | |
c19d1205 | 2588 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 2589 | { |
c19d1205 ZW |
2590 | int reg; |
2591 | int hi_reg; | |
2592 | unsigned mask = 0; | |
2593 | valueT op; | |
b99bd4ef | 2594 | |
c19d1205 ZW |
2595 | if (*input_line_pointer == '{') |
2596 | input_line_pointer++; | |
b99bd4ef | 2597 | |
c19d1205 | 2598 | do |
b99bd4ef | 2599 | { |
c19d1205 | 2600 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 2601 | |
c19d1205 ZW |
2602 | if (reg == FAIL) |
2603 | { | |
2604 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
2605 | goto error; | |
2606 | } | |
b99bd4ef | 2607 | |
c19d1205 ZW |
2608 | reg -= 8; |
2609 | if (mask >> reg) | |
2610 | as_tsktsk (_("register list not in ascending order")); | |
2611 | mask |= 1 << reg; | |
b99bd4ef | 2612 | |
c19d1205 ZW |
2613 | if (*input_line_pointer == '-') |
2614 | { | |
2615 | input_line_pointer++; | |
2616 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); | |
2617 | if (hi_reg == FAIL) | |
2618 | { | |
2619 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
2620 | goto error; | |
2621 | } | |
2622 | else if (reg >= hi_reg) | |
2623 | { | |
2624 | as_bad (_("bad register range")); | |
2625 | goto error; | |
2626 | } | |
2627 | for (; reg < hi_reg; reg++) | |
2628 | mask |= 1 << reg; | |
2629 | } | |
b99bd4ef | 2630 | } |
c19d1205 | 2631 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 2632 | |
c19d1205 ZW |
2633 | if (*input_line_pointer == '}') |
2634 | input_line_pointer++; | |
b99bd4ef | 2635 | |
c19d1205 ZW |
2636 | demand_empty_rest_of_line (); |
2637 | ||
2638 | /* Generate any deferred opcodes becuuse we're going to be looking at | |
2639 | the list. */ | |
2640 | flush_pending_unwind (); | |
b99bd4ef | 2641 | |
c19d1205 | 2642 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 2643 | { |
c19d1205 ZW |
2644 | if (mask & (1 << reg)) |
2645 | unwind.frame_size += 4; | |
b99bd4ef | 2646 | } |
c19d1205 ZW |
2647 | op = 0xc700 | mask; |
2648 | add_unwind_opcode (op, 2); | |
2649 | return; | |
2650 | error: | |
2651 | ignore_rest_of_line (); | |
b99bd4ef NC |
2652 | } |
2653 | ||
c19d1205 ZW |
2654 | |
2655 | /* Parse an unwind_save directive. */ | |
2656 | ||
b99bd4ef | 2657 | static void |
c19d1205 | 2658 | s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED) |
b99bd4ef | 2659 | { |
c19d1205 ZW |
2660 | char *peek; |
2661 | struct reg_entry *reg; | |
2662 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 2663 | |
c19d1205 ZW |
2664 | /* Figure out what sort of save we have. */ |
2665 | peek = input_line_pointer; | |
b99bd4ef | 2666 | |
c19d1205 | 2667 | if (*peek == '{') |
b99bd4ef | 2668 | { |
c19d1205 ZW |
2669 | had_brace = TRUE; |
2670 | peek++; | |
b99bd4ef NC |
2671 | } |
2672 | ||
c19d1205 | 2673 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 2674 | |
c19d1205 | 2675 | if (!reg) |
b99bd4ef | 2676 | { |
c19d1205 ZW |
2677 | as_bad (_("register expected")); |
2678 | ignore_rest_of_line (); | |
b99bd4ef NC |
2679 | return; |
2680 | } | |
2681 | ||
c19d1205 | 2682 | switch (reg->type) |
b99bd4ef | 2683 | { |
c19d1205 ZW |
2684 | case REG_TYPE_FN: |
2685 | if (had_brace) | |
2686 | { | |
2687 | as_bad (_("FPA .unwind_save does not take a register list")); | |
2688 | ignore_rest_of_line (); | |
2689 | return; | |
2690 | } | |
2691 | s_arm_unwind_save_fpa (reg->number); | |
b99bd4ef | 2692 | return; |
c19d1205 ZW |
2693 | |
2694 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
2695 | case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return; | |
2696 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; | |
2697 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
2698 | ||
2699 | default: | |
2700 | as_bad (_(".unwind_save does not support this kind of register")); | |
2701 | ignore_rest_of_line (); | |
b99bd4ef | 2702 | } |
c19d1205 | 2703 | } |
b99bd4ef | 2704 | |
b99bd4ef | 2705 | |
c19d1205 ZW |
2706 | /* Parse an unwind_movsp directive. */ |
2707 | ||
2708 | static void | |
2709 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
2710 | { | |
2711 | int reg; | |
2712 | valueT op; | |
2713 | ||
2714 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
2715 | if (reg == FAIL) | |
b99bd4ef | 2716 | { |
c19d1205 ZW |
2717 | as_bad (_(reg_expected_msgs[REG_TYPE_RN])); |
2718 | ignore_rest_of_line (); | |
b99bd4ef NC |
2719 | return; |
2720 | } | |
c19d1205 | 2721 | demand_empty_rest_of_line (); |
b99bd4ef | 2722 | |
c19d1205 | 2723 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 2724 | { |
c19d1205 | 2725 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
2726 | return; |
2727 | } | |
2728 | ||
c19d1205 ZW |
2729 | if (unwind.fp_reg != REG_SP) |
2730 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 2731 | |
c19d1205 ZW |
2732 | /* Generate opcode to restore the value. */ |
2733 | op = 0x90 | reg; | |
2734 | add_unwind_opcode (op, 1); | |
2735 | ||
2736 | /* Record the information for later. */ | |
2737 | unwind.fp_reg = reg; | |
2738 | unwind.fp_offset = unwind.frame_size; | |
2739 | unwind.sp_restored = 1; | |
b05fe5cf ZW |
2740 | } |
2741 | ||
c19d1205 ZW |
2742 | /* Parse an unwind_pad directive. */ |
2743 | ||
b05fe5cf | 2744 | static void |
c19d1205 | 2745 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 2746 | { |
c19d1205 | 2747 | int offset; |
b05fe5cf | 2748 | |
c19d1205 ZW |
2749 | if (immediate_for_directive (&offset) == FAIL) |
2750 | return; | |
b99bd4ef | 2751 | |
c19d1205 ZW |
2752 | if (offset & 3) |
2753 | { | |
2754 | as_bad (_("stack increment must be multiple of 4")); | |
2755 | ignore_rest_of_line (); | |
2756 | return; | |
2757 | } | |
b99bd4ef | 2758 | |
c19d1205 ZW |
2759 | /* Don't generate any opcodes, just record the details for later. */ |
2760 | unwind.frame_size += offset; | |
2761 | unwind.pending_offset += offset; | |
2762 | ||
2763 | demand_empty_rest_of_line (); | |
2764 | } | |
2765 | ||
2766 | /* Parse an unwind_setfp directive. */ | |
2767 | ||
2768 | static void | |
2769 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 2770 | { |
c19d1205 ZW |
2771 | int sp_reg; |
2772 | int fp_reg; | |
2773 | int offset; | |
2774 | ||
2775 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
2776 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2777 | sp_reg = FAIL; | |
2778 | else | |
2779 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
b99bd4ef | 2780 | |
c19d1205 ZW |
2781 | if (fp_reg == FAIL || sp_reg == FAIL) |
2782 | { | |
2783 | as_bad (_("expected <reg>, <reg>")); | |
2784 | ignore_rest_of_line (); | |
2785 | return; | |
2786 | } | |
b99bd4ef | 2787 | |
c19d1205 ZW |
2788 | /* Optional constant. */ |
2789 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
2790 | { | |
2791 | if (immediate_for_directive (&offset) == FAIL) | |
2792 | return; | |
2793 | } | |
2794 | else | |
2795 | offset = 0; | |
a737bd4d | 2796 | |
c19d1205 | 2797 | demand_empty_rest_of_line (); |
a737bd4d | 2798 | |
c19d1205 | 2799 | if (sp_reg != 13 && sp_reg != unwind.fp_reg) |
a737bd4d | 2800 | { |
c19d1205 ZW |
2801 | as_bad (_("register must be either sp or set by a previous" |
2802 | "unwind_movsp directive")); | |
2803 | return; | |
a737bd4d NC |
2804 | } |
2805 | ||
c19d1205 ZW |
2806 | /* Don't generate any opcodes, just record the information for later. */ |
2807 | unwind.fp_reg = fp_reg; | |
2808 | unwind.fp_used = 1; | |
2809 | if (sp_reg == 13) | |
2810 | unwind.fp_offset = unwind.frame_size - offset; | |
2811 | else | |
2812 | unwind.fp_offset -= offset; | |
a737bd4d NC |
2813 | } |
2814 | ||
c19d1205 ZW |
2815 | /* Parse an unwind_raw directive. */ |
2816 | ||
2817 | static void | |
2818 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 2819 | { |
c19d1205 ZW |
2820 | expressionS exp; |
2821 | /* This is an arbitary limit. */ | |
2822 | unsigned char op[16]; | |
2823 | int count; | |
a737bd4d | 2824 | |
c19d1205 ZW |
2825 | expression (&exp); |
2826 | if (exp.X_op == O_constant | |
2827 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 2828 | { |
c19d1205 ZW |
2829 | unwind.frame_size += exp.X_add_number; |
2830 | expression (&exp); | |
2831 | } | |
2832 | else | |
2833 | exp.X_op = O_illegal; | |
a737bd4d | 2834 | |
c19d1205 ZW |
2835 | if (exp.X_op != O_constant) |
2836 | { | |
2837 | as_bad (_("expected <offset>, <opcode>")); | |
2838 | ignore_rest_of_line (); | |
2839 | return; | |
2840 | } | |
a737bd4d | 2841 | |
c19d1205 | 2842 | count = 0; |
a737bd4d | 2843 | |
c19d1205 ZW |
2844 | /* Parse the opcode. */ |
2845 | for (;;) | |
2846 | { | |
2847 | if (count >= 16) | |
2848 | { | |
2849 | as_bad (_("unwind opcode too long")); | |
2850 | ignore_rest_of_line (); | |
a737bd4d | 2851 | } |
c19d1205 | 2852 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 2853 | { |
c19d1205 ZW |
2854 | as_bad (_("invalid unwind opcode")); |
2855 | ignore_rest_of_line (); | |
2856 | return; | |
a737bd4d | 2857 | } |
c19d1205 | 2858 | op[count++] = exp.X_add_number; |
a737bd4d | 2859 | |
c19d1205 ZW |
2860 | /* Parse the next byte. */ |
2861 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2862 | break; | |
a737bd4d | 2863 | |
c19d1205 ZW |
2864 | expression (&exp); |
2865 | } | |
b99bd4ef | 2866 | |
c19d1205 ZW |
2867 | /* Add the opcode bytes in reverse order. */ |
2868 | while (count--) | |
2869 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 2870 | |
c19d1205 | 2871 | demand_empty_rest_of_line (); |
b99bd4ef | 2872 | } |
ee065d83 PB |
2873 | |
2874 | ||
2875 | /* Parse a .eabi_attribute directive. */ | |
2876 | ||
2877 | static void | |
2878 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
2879 | { | |
2880 | expressionS exp; | |
2881 | bfd_boolean is_string; | |
2882 | int tag; | |
2883 | unsigned int i = 0; | |
2884 | char *s = NULL; | |
2885 | char saved_char; | |
2886 | ||
2887 | expression (& exp); | |
2888 | if (exp.X_op != O_constant) | |
2889 | goto bad; | |
2890 | ||
2891 | tag = exp.X_add_number; | |
2892 | if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0)) | |
2893 | is_string = 1; | |
2894 | else | |
2895 | is_string = 0; | |
2896 | ||
2897 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2898 | goto bad; | |
2899 | if (tag == 32 || !is_string) | |
2900 | { | |
2901 | expression (& exp); | |
2902 | if (exp.X_op != O_constant) | |
2903 | { | |
2904 | as_bad (_("expected numeric constant")); | |
2905 | ignore_rest_of_line (); | |
2906 | return; | |
2907 | } | |
2908 | i = exp.X_add_number; | |
2909 | } | |
2910 | if (tag == Tag_compatibility | |
2911 | && skip_past_comma (&input_line_pointer) == FAIL) | |
2912 | { | |
2913 | as_bad (_("expected comma")); | |
2914 | ignore_rest_of_line (); | |
2915 | return; | |
2916 | } | |
2917 | if (is_string) | |
2918 | { | |
2919 | skip_whitespace(input_line_pointer); | |
2920 | if (*input_line_pointer != '"') | |
2921 | goto bad_string; | |
2922 | input_line_pointer++; | |
2923 | s = input_line_pointer; | |
2924 | while (*input_line_pointer && *input_line_pointer != '"') | |
2925 | input_line_pointer++; | |
2926 | if (*input_line_pointer != '"') | |
2927 | goto bad_string; | |
2928 | saved_char = *input_line_pointer; | |
2929 | *input_line_pointer = 0; | |
2930 | } | |
2931 | else | |
2932 | { | |
2933 | s = NULL; | |
2934 | saved_char = 0; | |
2935 | } | |
2936 | ||
2937 | if (tag == Tag_compatibility) | |
2938 | elf32_arm_add_eabi_attr_compat (stdoutput, i, s); | |
2939 | else if (is_string) | |
2940 | elf32_arm_add_eabi_attr_string (stdoutput, tag, s); | |
2941 | else | |
2942 | elf32_arm_add_eabi_attr_int (stdoutput, tag, i); | |
2943 | ||
2944 | if (s) | |
2945 | { | |
2946 | *input_line_pointer = saved_char; | |
2947 | input_line_pointer++; | |
2948 | } | |
2949 | demand_empty_rest_of_line (); | |
2950 | return; | |
2951 | bad_string: | |
2952 | as_bad (_("bad string constant")); | |
2953 | ignore_rest_of_line (); | |
2954 | return; | |
2955 | bad: | |
2956 | as_bad (_("expected <tag> , <value>")); | |
2957 | ignore_rest_of_line (); | |
2958 | } | |
2959 | ||
2960 | static void s_arm_arch (int); | |
2961 | static void s_arm_cpu (int); | |
2962 | static void s_arm_fpu (int); | |
c19d1205 | 2963 | #endif /* OBJ_ELF */ |
b99bd4ef | 2964 | |
c19d1205 ZW |
2965 | /* This table describes all the machine specific pseudo-ops the assembler |
2966 | has to support. The fields are: | |
2967 | pseudo-op name without dot | |
2968 | function to call to execute this pseudo-op | |
2969 | Integer arg to pass to the function. */ | |
b99bd4ef | 2970 | |
c19d1205 | 2971 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 2972 | { |
c19d1205 ZW |
2973 | /* Never called because '.req' does not start a line. */ |
2974 | { "req", s_req, 0 }, | |
2975 | { "unreq", s_unreq, 0 }, | |
2976 | { "bss", s_bss, 0 }, | |
2977 | { "align", s_align, 0 }, | |
2978 | { "arm", s_arm, 0 }, | |
2979 | { "thumb", s_thumb, 0 }, | |
2980 | { "code", s_code, 0 }, | |
2981 | { "force_thumb", s_force_thumb, 0 }, | |
2982 | { "thumb_func", s_thumb_func, 0 }, | |
2983 | { "thumb_set", s_thumb_set, 0 }, | |
2984 | { "even", s_even, 0 }, | |
2985 | { "ltorg", s_ltorg, 0 }, | |
2986 | { "pool", s_ltorg, 0 }, | |
2987 | { "syntax", s_syntax, 0 }, | |
2988 | #ifdef OBJ_ELF | |
2989 | { "word", s_arm_elf_cons, 4 }, | |
2990 | { "long", s_arm_elf_cons, 4 }, | |
2991 | { "rel31", s_arm_rel31, 0 }, | |
2992 | { "fnstart", s_arm_unwind_fnstart, 0 }, | |
2993 | { "fnend", s_arm_unwind_fnend, 0 }, | |
2994 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
2995 | { "personality", s_arm_unwind_personality, 0 }, | |
2996 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
2997 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
2998 | { "save", s_arm_unwind_save, 0 }, | |
2999 | { "movsp", s_arm_unwind_movsp, 0 }, | |
3000 | { "pad", s_arm_unwind_pad, 0 }, | |
3001 | { "setfp", s_arm_unwind_setfp, 0 }, | |
3002 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 PB |
3003 | { "cpu", s_arm_cpu, 0 }, |
3004 | { "arch", s_arm_arch, 0 }, | |
3005 | { "fpu", s_arm_fpu, 0 }, | |
3006 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, | |
c19d1205 ZW |
3007 | #else |
3008 | { "word", cons, 4}, | |
3009 | #endif | |
3010 | { "extend", float_cons, 'x' }, | |
3011 | { "ldouble", float_cons, 'x' }, | |
3012 | { "packed", float_cons, 'p' }, | |
3013 | { 0, 0, 0 } | |
3014 | }; | |
3015 | \f | |
3016 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 3017 | |
c19d1205 ZW |
3018 | /* Generic immediate-value read function for use in insn parsing. |
3019 | STR points to the beginning of the immediate (the leading #); | |
3020 | VAL receives the value; if the value is outside [MIN, MAX] | |
3021 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
3022 | optional. */ | |
b99bd4ef | 3023 | |
c19d1205 ZW |
3024 | static int |
3025 | parse_immediate (char **str, int *val, int min, int max, | |
3026 | bfd_boolean prefix_opt) | |
3027 | { | |
3028 | expressionS exp; | |
3029 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
3030 | if (exp.X_op != O_constant) | |
b99bd4ef | 3031 | { |
c19d1205 ZW |
3032 | inst.error = _("constant expression required"); |
3033 | return FAIL; | |
3034 | } | |
b99bd4ef | 3035 | |
c19d1205 ZW |
3036 | if (exp.X_add_number < min || exp.X_add_number > max) |
3037 | { | |
3038 | inst.error = _("immediate value out of range"); | |
3039 | return FAIL; | |
3040 | } | |
b99bd4ef | 3041 | |
c19d1205 ZW |
3042 | *val = exp.X_add_number; |
3043 | return SUCCESS; | |
3044 | } | |
b99bd4ef | 3045 | |
c19d1205 ZW |
3046 | /* Returns the pseudo-register number of an FPA immediate constant, |
3047 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 3048 | |
c19d1205 ZW |
3049 | static int |
3050 | parse_fpa_immediate (char ** str) | |
3051 | { | |
3052 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3053 | char * save_in; | |
3054 | expressionS exp; | |
3055 | int i; | |
3056 | int j; | |
b99bd4ef | 3057 | |
c19d1205 ZW |
3058 | /* First try and match exact strings, this is to guarantee |
3059 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 3060 | |
c19d1205 ZW |
3061 | for (i = 0; fp_const[i]; i++) |
3062 | { | |
3063 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 3064 | { |
c19d1205 | 3065 | char *start = *str; |
b99bd4ef | 3066 | |
c19d1205 ZW |
3067 | *str += strlen (fp_const[i]); |
3068 | if (is_end_of_line[(unsigned char) **str]) | |
3069 | return i + 8; | |
3070 | *str = start; | |
3071 | } | |
3072 | } | |
b99bd4ef | 3073 | |
c19d1205 ZW |
3074 | /* Just because we didn't get a match doesn't mean that the constant |
3075 | isn't valid, just that it is in a format that we don't | |
3076 | automatically recognize. Try parsing it with the standard | |
3077 | expression routines. */ | |
b99bd4ef | 3078 | |
c19d1205 | 3079 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 3080 | |
c19d1205 ZW |
3081 | /* Look for a raw floating point number. */ |
3082 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
3083 | && is_end_of_line[(unsigned char) *save_in]) | |
3084 | { | |
3085 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
3086 | { | |
3087 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 3088 | { |
c19d1205 ZW |
3089 | if (words[j] != fp_values[i][j]) |
3090 | break; | |
b99bd4ef NC |
3091 | } |
3092 | ||
c19d1205 | 3093 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 3094 | { |
c19d1205 ZW |
3095 | *str = save_in; |
3096 | return i + 8; | |
b99bd4ef NC |
3097 | } |
3098 | } | |
3099 | } | |
b99bd4ef | 3100 | |
c19d1205 ZW |
3101 | /* Try and parse a more complex expression, this will probably fail |
3102 | unless the code uses a floating point prefix (eg "0f"). */ | |
3103 | save_in = input_line_pointer; | |
3104 | input_line_pointer = *str; | |
3105 | if (expression (&exp) == absolute_section | |
3106 | && exp.X_op == O_big | |
3107 | && exp.X_add_number < 0) | |
3108 | { | |
3109 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
3110 | Ditto for 15. */ | |
3111 | if (gen_to_words (words, 5, (long) 15) == 0) | |
3112 | { | |
3113 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
3114 | { | |
3115 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
3116 | { | |
3117 | if (words[j] != fp_values[i][j]) | |
3118 | break; | |
3119 | } | |
b99bd4ef | 3120 | |
c19d1205 ZW |
3121 | if (j == MAX_LITTLENUMS) |
3122 | { | |
3123 | *str = input_line_pointer; | |
3124 | input_line_pointer = save_in; | |
3125 | return i + 8; | |
3126 | } | |
3127 | } | |
3128 | } | |
b99bd4ef NC |
3129 | } |
3130 | ||
c19d1205 ZW |
3131 | *str = input_line_pointer; |
3132 | input_line_pointer = save_in; | |
3133 | inst.error = _("invalid FPA immediate expression"); | |
3134 | return FAIL; | |
b99bd4ef NC |
3135 | } |
3136 | ||
c19d1205 ZW |
3137 | /* Shift operands. */ |
3138 | enum shift_kind | |
b99bd4ef | 3139 | { |
c19d1205 ZW |
3140 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
3141 | }; | |
b99bd4ef | 3142 | |
c19d1205 ZW |
3143 | struct asm_shift_name |
3144 | { | |
3145 | const char *name; | |
3146 | enum shift_kind kind; | |
3147 | }; | |
b99bd4ef | 3148 | |
c19d1205 ZW |
3149 | /* Third argument to parse_shift. */ |
3150 | enum parse_shift_mode | |
3151 | { | |
3152 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
3153 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
3154 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
3155 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
3156 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
3157 | }; | |
b99bd4ef | 3158 | |
c19d1205 ZW |
3159 | /* Parse a <shift> specifier on an ARM data processing instruction. |
3160 | This has three forms: | |
b99bd4ef | 3161 | |
c19d1205 ZW |
3162 | (LSL|LSR|ASL|ASR|ROR) Rs |
3163 | (LSL|LSR|ASL|ASR|ROR) #imm | |
3164 | RRX | |
b99bd4ef | 3165 | |
c19d1205 ZW |
3166 | Note that ASL is assimilated to LSL in the instruction encoding, and |
3167 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 3168 | |
c19d1205 ZW |
3169 | static int |
3170 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 3171 | { |
c19d1205 ZW |
3172 | const struct asm_shift_name *shift_name; |
3173 | enum shift_kind shift; | |
3174 | char *s = *str; | |
3175 | char *p = s; | |
3176 | int reg; | |
b99bd4ef | 3177 | |
c19d1205 ZW |
3178 | for (p = *str; ISALPHA (*p); p++) |
3179 | ; | |
b99bd4ef | 3180 | |
c19d1205 | 3181 | if (p == *str) |
b99bd4ef | 3182 | { |
c19d1205 ZW |
3183 | inst.error = _("shift expression expected"); |
3184 | return FAIL; | |
b99bd4ef NC |
3185 | } |
3186 | ||
c19d1205 ZW |
3187 | shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); |
3188 | ||
3189 | if (shift_name == NULL) | |
b99bd4ef | 3190 | { |
c19d1205 ZW |
3191 | inst.error = _("shift expression expected"); |
3192 | return FAIL; | |
b99bd4ef NC |
3193 | } |
3194 | ||
c19d1205 | 3195 | shift = shift_name->kind; |
b99bd4ef | 3196 | |
c19d1205 ZW |
3197 | switch (mode) |
3198 | { | |
3199 | case NO_SHIFT_RESTRICT: | |
3200 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 3201 | |
c19d1205 ZW |
3202 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
3203 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
3204 | { | |
3205 | inst.error = _("'LSL' or 'ASR' required"); | |
3206 | return FAIL; | |
3207 | } | |
3208 | break; | |
b99bd4ef | 3209 | |
c19d1205 ZW |
3210 | case SHIFT_LSL_IMMEDIATE: |
3211 | if (shift != SHIFT_LSL) | |
3212 | { | |
3213 | inst.error = _("'LSL' required"); | |
3214 | return FAIL; | |
3215 | } | |
3216 | break; | |
b99bd4ef | 3217 | |
c19d1205 ZW |
3218 | case SHIFT_ASR_IMMEDIATE: |
3219 | if (shift != SHIFT_ASR) | |
3220 | { | |
3221 | inst.error = _("'ASR' required"); | |
3222 | return FAIL; | |
3223 | } | |
3224 | break; | |
b99bd4ef | 3225 | |
c19d1205 ZW |
3226 | default: abort (); |
3227 | } | |
b99bd4ef | 3228 | |
c19d1205 ZW |
3229 | if (shift != SHIFT_RRX) |
3230 | { | |
3231 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
3232 | skip_whitespace (p); | |
b99bd4ef | 3233 | |
c19d1205 ZW |
3234 | if (mode == NO_SHIFT_RESTRICT |
3235 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
3236 | { | |
3237 | inst.operands[i].imm = reg; | |
3238 | inst.operands[i].immisreg = 1; | |
3239 | } | |
3240 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3241 | return FAIL; | |
3242 | } | |
3243 | inst.operands[i].shift_kind = shift; | |
3244 | inst.operands[i].shifted = 1; | |
3245 | *str = p; | |
3246 | return SUCCESS; | |
b99bd4ef NC |
3247 | } |
3248 | ||
c19d1205 | 3249 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 3250 | |
c19d1205 ZW |
3251 | #<immediate> |
3252 | #<immediate>, <rotate> | |
3253 | <Rm> | |
3254 | <Rm>, <shift> | |
b99bd4ef | 3255 | |
c19d1205 ZW |
3256 | where <shift> is defined by parse_shift above, and <rotate> is a |
3257 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 3258 | is deferred to md_apply_fix. */ |
b99bd4ef | 3259 | |
c19d1205 ZW |
3260 | static int |
3261 | parse_shifter_operand (char **str, int i) | |
3262 | { | |
3263 | int value; | |
3264 | expressionS expr; | |
b99bd4ef | 3265 | |
c19d1205 ZW |
3266 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
3267 | { | |
3268 | inst.operands[i].reg = value; | |
3269 | inst.operands[i].isreg = 1; | |
b99bd4ef | 3270 | |
c19d1205 ZW |
3271 | /* parse_shift will override this if appropriate */ |
3272 | inst.reloc.exp.X_op = O_constant; | |
3273 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 3274 | |
c19d1205 ZW |
3275 | if (skip_past_comma (str) == FAIL) |
3276 | return SUCCESS; | |
b99bd4ef | 3277 | |
c19d1205 ZW |
3278 | /* Shift operation on register. */ |
3279 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
3280 | } |
3281 | ||
c19d1205 ZW |
3282 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
3283 | return FAIL; | |
b99bd4ef | 3284 | |
c19d1205 | 3285 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 3286 | { |
c19d1205 ZW |
3287 | /* #x, y -- ie explicit rotation by Y. */ |
3288 | if (my_get_expression (&expr, str, GE_NO_PREFIX)) | |
3289 | return FAIL; | |
b99bd4ef | 3290 | |
c19d1205 ZW |
3291 | if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
3292 | { | |
3293 | inst.error = _("constant expression expected"); | |
3294 | return FAIL; | |
3295 | } | |
b99bd4ef | 3296 | |
c19d1205 ZW |
3297 | value = expr.X_add_number; |
3298 | if (value < 0 || value > 30 || value % 2 != 0) | |
3299 | { | |
3300 | inst.error = _("invalid rotation"); | |
3301 | return FAIL; | |
3302 | } | |
3303 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
3304 | { | |
3305 | inst.error = _("invalid constant"); | |
3306 | return FAIL; | |
3307 | } | |
09d92015 | 3308 | |
55cf6793 | 3309 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
3310 | inst.reloc.exp.X_add_number |
3311 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
3312 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
3313 | } |
3314 | ||
c19d1205 ZW |
3315 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
3316 | inst.reloc.pc_rel = 0; | |
3317 | return SUCCESS; | |
09d92015 MM |
3318 | } |
3319 | ||
c19d1205 ZW |
3320 | /* Parse all forms of an ARM address expression. Information is written |
3321 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 3322 | |
c19d1205 | 3323 | Preindexed addressing (.preind=1): |
09d92015 | 3324 | |
c19d1205 ZW |
3325 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
3326 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3327 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3328 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 3329 | |
c19d1205 | 3330 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 3331 | |
c19d1205 | 3332 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 3333 | |
c19d1205 ZW |
3334 | [Rn], #offset .reg=Rn .reloc.exp=offset |
3335 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3336 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3337 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 3338 | |
c19d1205 | 3339 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 3340 | |
c19d1205 | 3341 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 3342 | |
c19d1205 | 3343 | Other: |
09d92015 | 3344 | |
c19d1205 ZW |
3345 | [Rn]{!} shorthand for [Rn,#0]{!} |
3346 | =immediate .isreg=0 .reloc.exp=immediate | |
3347 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 3348 | |
c19d1205 ZW |
3349 | It is the caller's responsibility to check for addressing modes not |
3350 | supported by the instruction, and to set inst.reloc.type. */ | |
3351 | ||
3352 | static int | |
3353 | parse_address (char **str, int i) | |
09d92015 | 3354 | { |
c19d1205 ZW |
3355 | char *p = *str; |
3356 | int reg; | |
09d92015 | 3357 | |
c19d1205 | 3358 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 3359 | { |
c19d1205 ZW |
3360 | if (skip_past_char (&p, '=') == FAIL) |
3361 | { | |
3362 | /* bare address - translate to PC-relative offset */ | |
3363 | inst.reloc.pc_rel = 1; | |
3364 | inst.operands[i].reg = REG_PC; | |
3365 | inst.operands[i].isreg = 1; | |
3366 | inst.operands[i].preind = 1; | |
3367 | } | |
3368 | /* else a load-constant pseudo op, no special treatment needed here */ | |
09d92015 | 3369 | |
c19d1205 ZW |
3370 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
3371 | return FAIL; | |
09d92015 | 3372 | |
c19d1205 ZW |
3373 | *str = p; |
3374 | return SUCCESS; | |
09d92015 MM |
3375 | } |
3376 | ||
c19d1205 | 3377 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 3378 | { |
c19d1205 ZW |
3379 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
3380 | return FAIL; | |
09d92015 | 3381 | } |
c19d1205 ZW |
3382 | inst.operands[i].reg = reg; |
3383 | inst.operands[i].isreg = 1; | |
09d92015 | 3384 | |
c19d1205 | 3385 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 3386 | { |
c19d1205 | 3387 | inst.operands[i].preind = 1; |
09d92015 | 3388 | |
c19d1205 ZW |
3389 | if (*p == '+') p++; |
3390 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
3391 | ||
3392 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
09d92015 | 3393 | { |
c19d1205 ZW |
3394 | inst.operands[i].imm = reg; |
3395 | inst.operands[i].immisreg = 1; | |
3396 | ||
3397 | if (skip_past_comma (&p) == SUCCESS) | |
3398 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
3399 | return FAIL; | |
3400 | } | |
3401 | else | |
3402 | { | |
3403 | if (inst.operands[i].negative) | |
3404 | { | |
3405 | inst.operands[i].negative = 0; | |
3406 | p--; | |
3407 | } | |
3408 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3409 | return FAIL; | |
09d92015 MM |
3410 | } |
3411 | } | |
3412 | ||
c19d1205 | 3413 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 3414 | { |
c19d1205 ZW |
3415 | inst.error = _("']' expected"); |
3416 | return FAIL; | |
09d92015 MM |
3417 | } |
3418 | ||
c19d1205 ZW |
3419 | if (skip_past_char (&p, '!') == SUCCESS) |
3420 | inst.operands[i].writeback = 1; | |
09d92015 | 3421 | |
c19d1205 | 3422 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 3423 | { |
c19d1205 ZW |
3424 | if (skip_past_char (&p, '{') == SUCCESS) |
3425 | { | |
3426 | /* [Rn], {expr} - unindexed, with option */ | |
3427 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 3428 | 0, 255, TRUE) == FAIL) |
c19d1205 | 3429 | return FAIL; |
09d92015 | 3430 | |
c19d1205 ZW |
3431 | if (skip_past_char (&p, '}') == FAIL) |
3432 | { | |
3433 | inst.error = _("'}' expected at end of 'option' field"); | |
3434 | return FAIL; | |
3435 | } | |
3436 | if (inst.operands[i].preind) | |
3437 | { | |
3438 | inst.error = _("cannot combine index with option"); | |
3439 | return FAIL; | |
3440 | } | |
3441 | *str = p; | |
3442 | return SUCCESS; | |
09d92015 | 3443 | } |
c19d1205 ZW |
3444 | else |
3445 | { | |
3446 | inst.operands[i].postind = 1; | |
3447 | inst.operands[i].writeback = 1; | |
09d92015 | 3448 | |
c19d1205 ZW |
3449 | if (inst.operands[i].preind) |
3450 | { | |
3451 | inst.error = _("cannot combine pre- and post-indexing"); | |
3452 | return FAIL; | |
3453 | } | |
09d92015 | 3454 | |
c19d1205 ZW |
3455 | if (*p == '+') p++; |
3456 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 3457 | |
c19d1205 ZW |
3458 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
3459 | { | |
3460 | inst.operands[i].imm = reg; | |
3461 | inst.operands[i].immisreg = 1; | |
a737bd4d | 3462 | |
c19d1205 ZW |
3463 | if (skip_past_comma (&p) == SUCCESS) |
3464 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
3465 | return FAIL; | |
3466 | } | |
3467 | else | |
3468 | { | |
3469 | if (inst.operands[i].negative) | |
3470 | { | |
3471 | inst.operands[i].negative = 0; | |
3472 | p--; | |
3473 | } | |
3474 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3475 | return FAIL; | |
3476 | } | |
3477 | } | |
a737bd4d NC |
3478 | } |
3479 | ||
c19d1205 ZW |
3480 | /* If at this point neither .preind nor .postind is set, we have a |
3481 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
3482 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
3483 | { | |
3484 | inst.operands[i].preind = 1; | |
3485 | inst.reloc.exp.X_op = O_constant; | |
3486 | inst.reloc.exp.X_add_number = 0; | |
3487 | } | |
3488 | *str = p; | |
3489 | return SUCCESS; | |
a737bd4d NC |
3490 | } |
3491 | ||
c19d1205 | 3492 | /* Miscellaneous. */ |
a737bd4d | 3493 | |
c19d1205 ZW |
3494 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
3495 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
3496 | static int | |
3497 | parse_psr (char **str) | |
09d92015 | 3498 | { |
c19d1205 ZW |
3499 | char *p; |
3500 | unsigned long psr_field; | |
62b3e311 PB |
3501 | const struct asm_psr *psr; |
3502 | char *start; | |
09d92015 | 3503 | |
c19d1205 ZW |
3504 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
3505 | feature for ease of use and backwards compatibility. */ | |
3506 | p = *str; | |
62b3e311 | 3507 | if (strncasecmp (p, "SPSR", 4) == 0) |
c19d1205 | 3508 | psr_field = SPSR_BIT; |
62b3e311 | 3509 | else if (strncasecmp (p, "CPSR", 4) == 0) |
c19d1205 ZW |
3510 | psr_field = 0; |
3511 | else | |
62b3e311 PB |
3512 | { |
3513 | start = p; | |
3514 | do | |
3515 | p++; | |
3516 | while (ISALNUM (*p) || *p == '_'); | |
3517 | ||
3518 | psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); | |
3519 | if (!psr) | |
3520 | return FAIL; | |
09d92015 | 3521 | |
62b3e311 PB |
3522 | *str = p; |
3523 | return psr->field; | |
3524 | } | |
09d92015 | 3525 | |
62b3e311 | 3526 | p += 4; |
c19d1205 ZW |
3527 | if (*p == '_') |
3528 | { | |
3529 | /* A suffix follows. */ | |
c19d1205 ZW |
3530 | p++; |
3531 | start = p; | |
a737bd4d | 3532 | |
c19d1205 ZW |
3533 | do |
3534 | p++; | |
3535 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 3536 | |
c19d1205 ZW |
3537 | psr = hash_find_n (arm_psr_hsh, start, p - start); |
3538 | if (!psr) | |
3539 | goto error; | |
a737bd4d | 3540 | |
c19d1205 | 3541 | psr_field |= psr->field; |
a737bd4d | 3542 | } |
c19d1205 | 3543 | else |
a737bd4d | 3544 | { |
c19d1205 ZW |
3545 | if (ISALNUM (*p)) |
3546 | goto error; /* Garbage after "[CS]PSR". */ | |
3547 | ||
3548 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 3549 | } |
c19d1205 ZW |
3550 | *str = p; |
3551 | return psr_field; | |
a737bd4d | 3552 | |
c19d1205 ZW |
3553 | error: |
3554 | inst.error = _("flag for {c}psr instruction expected"); | |
3555 | return FAIL; | |
a737bd4d NC |
3556 | } |
3557 | ||
c19d1205 ZW |
3558 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
3559 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 3560 | |
c19d1205 ZW |
3561 | static int |
3562 | parse_cps_flags (char **str) | |
a737bd4d | 3563 | { |
c19d1205 ZW |
3564 | int val = 0; |
3565 | int saw_a_flag = 0; | |
3566 | char *s = *str; | |
a737bd4d | 3567 | |
c19d1205 ZW |
3568 | for (;;) |
3569 | switch (*s++) | |
3570 | { | |
3571 | case '\0': case ',': | |
3572 | goto done; | |
a737bd4d | 3573 | |
c19d1205 ZW |
3574 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
3575 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
3576 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 3577 | |
c19d1205 ZW |
3578 | default: |
3579 | inst.error = _("unrecognized CPS flag"); | |
3580 | return FAIL; | |
3581 | } | |
a737bd4d | 3582 | |
c19d1205 ZW |
3583 | done: |
3584 | if (saw_a_flag == 0) | |
a737bd4d | 3585 | { |
c19d1205 ZW |
3586 | inst.error = _("missing CPS flags"); |
3587 | return FAIL; | |
a737bd4d | 3588 | } |
a737bd4d | 3589 | |
c19d1205 ZW |
3590 | *str = s - 1; |
3591 | return val; | |
a737bd4d NC |
3592 | } |
3593 | ||
c19d1205 ZW |
3594 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
3595 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
3596 | |
3597 | static int | |
c19d1205 | 3598 | parse_endian_specifier (char **str) |
a737bd4d | 3599 | { |
c19d1205 ZW |
3600 | int little_endian; |
3601 | char *s = *str; | |
a737bd4d | 3602 | |
c19d1205 ZW |
3603 | if (strncasecmp (s, "BE", 2)) |
3604 | little_endian = 0; | |
3605 | else if (strncasecmp (s, "LE", 2)) | |
3606 | little_endian = 1; | |
3607 | else | |
a737bd4d | 3608 | { |
c19d1205 | 3609 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
3610 | return FAIL; |
3611 | } | |
3612 | ||
c19d1205 | 3613 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 3614 | { |
c19d1205 | 3615 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
3616 | return FAIL; |
3617 | } | |
3618 | ||
c19d1205 ZW |
3619 | *str = s + 2; |
3620 | return little_endian; | |
3621 | } | |
a737bd4d | 3622 | |
c19d1205 ZW |
3623 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
3624 | value suitable for poking into the rotate field of an sxt or sxta | |
3625 | instruction, or FAIL on error. */ | |
3626 | ||
3627 | static int | |
3628 | parse_ror (char **str) | |
3629 | { | |
3630 | int rot; | |
3631 | char *s = *str; | |
3632 | ||
3633 | if (strncasecmp (s, "ROR", 3) == 0) | |
3634 | s += 3; | |
3635 | else | |
a737bd4d | 3636 | { |
c19d1205 | 3637 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
3638 | return FAIL; |
3639 | } | |
c19d1205 ZW |
3640 | |
3641 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
3642 | return FAIL; | |
3643 | ||
3644 | switch (rot) | |
a737bd4d | 3645 | { |
c19d1205 ZW |
3646 | case 0: *str = s; return 0x0; |
3647 | case 8: *str = s; return 0x1; | |
3648 | case 16: *str = s; return 0x2; | |
3649 | case 24: *str = s; return 0x3; | |
3650 | ||
3651 | default: | |
3652 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
3653 | return FAIL; |
3654 | } | |
c19d1205 | 3655 | } |
a737bd4d | 3656 | |
c19d1205 ZW |
3657 | /* Parse a conditional code (from conds[] below). The value returned is in the |
3658 | range 0 .. 14, or FAIL. */ | |
3659 | static int | |
3660 | parse_cond (char **str) | |
3661 | { | |
3662 | char *p, *q; | |
3663 | const struct asm_cond *c; | |
a737bd4d | 3664 | |
c19d1205 ZW |
3665 | p = q = *str; |
3666 | while (ISALPHA (*q)) | |
3667 | q++; | |
a737bd4d | 3668 | |
c19d1205 ZW |
3669 | c = hash_find_n (arm_cond_hsh, p, q - p); |
3670 | if (!c) | |
a737bd4d | 3671 | { |
c19d1205 | 3672 | inst.error = _("condition required"); |
a737bd4d NC |
3673 | return FAIL; |
3674 | } | |
3675 | ||
c19d1205 ZW |
3676 | *str = q; |
3677 | return c->value; | |
3678 | } | |
3679 | ||
62b3e311 PB |
3680 | /* Parse an option for a barrier instruction. Returns the encoding for the |
3681 | option, or FAIL. */ | |
3682 | static int | |
3683 | parse_barrier (char **str) | |
3684 | { | |
3685 | char *p, *q; | |
3686 | const struct asm_barrier_opt *o; | |
3687 | ||
3688 | p = q = *str; | |
3689 | while (ISALPHA (*q)) | |
3690 | q++; | |
3691 | ||
3692 | o = hash_find_n (arm_barrier_opt_hsh, p, q - p); | |
3693 | if (!o) | |
3694 | return FAIL; | |
3695 | ||
3696 | *str = q; | |
3697 | return o->value; | |
3698 | } | |
3699 | ||
92e90b6e PB |
3700 | /* Parse the operands of a table branch instruction. Similar to a memory |
3701 | operand. */ | |
3702 | static int | |
3703 | parse_tb (char **str) | |
3704 | { | |
3705 | char * p = *str; | |
3706 | int reg; | |
3707 | ||
3708 | if (skip_past_char (&p, '[') == FAIL) | |
3709 | return FAIL; | |
3710 | ||
3711 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
3712 | { | |
3713 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
3714 | return FAIL; | |
3715 | } | |
3716 | inst.operands[0].reg = reg; | |
3717 | ||
3718 | if (skip_past_comma (&p) == FAIL) | |
3719 | return FAIL; | |
3720 | ||
3721 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
3722 | { | |
3723 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
3724 | return FAIL; | |
3725 | } | |
3726 | inst.operands[0].imm = reg; | |
3727 | ||
3728 | if (skip_past_comma (&p) == SUCCESS) | |
3729 | { | |
3730 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
3731 | return FAIL; | |
3732 | if (inst.reloc.exp.X_add_number != 1) | |
3733 | { | |
3734 | inst.error = _("invalid shift"); | |
3735 | return FAIL; | |
3736 | } | |
3737 | inst.operands[0].shifted = 1; | |
3738 | } | |
3739 | ||
3740 | if (skip_past_char (&p, ']') == FAIL) | |
3741 | { | |
3742 | inst.error = _("']' expected"); | |
3743 | return FAIL; | |
3744 | } | |
3745 | *str = p; | |
3746 | return SUCCESS; | |
3747 | } | |
3748 | ||
c19d1205 ZW |
3749 | /* Matcher codes for parse_operands. */ |
3750 | enum operand_parse_code | |
3751 | { | |
3752 | OP_stop, /* end of line */ | |
3753 | ||
3754 | OP_RR, /* ARM register */ | |
3755 | OP_RRnpc, /* ARM register, not r15 */ | |
3756 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ | |
3757 | OP_RRw, /* ARM register, not r15, optional trailing ! */ | |
3758 | OP_RCP, /* Coprocessor number */ | |
3759 | OP_RCN, /* Coprocessor register */ | |
3760 | OP_RF, /* FPA register */ | |
3761 | OP_RVS, /* VFP single precision register */ | |
3762 | OP_RVD, /* VFP double precision register */ | |
3763 | OP_RVC, /* VFP control register */ | |
3764 | OP_RMF, /* Maverick F register */ | |
3765 | OP_RMD, /* Maverick D register */ | |
3766 | OP_RMFX, /* Maverick FX register */ | |
3767 | OP_RMDX, /* Maverick DX register */ | |
3768 | OP_RMAX, /* Maverick AX register */ | |
3769 | OP_RMDS, /* Maverick DSPSC register */ | |
3770 | OP_RIWR, /* iWMMXt wR register */ | |
3771 | OP_RIWC, /* iWMMXt wC register */ | |
3772 | OP_RIWG, /* iWMMXt wCG register */ | |
3773 | OP_RXA, /* XScale accumulator register */ | |
3774 | ||
3775 | OP_REGLST, /* ARM register list */ | |
3776 | OP_VRSLST, /* VFP single-precision register list */ | |
3777 | OP_VRDLST, /* VFP double-precision register list */ | |
3778 | ||
3779 | OP_I7, /* immediate value 0 .. 7 */ | |
3780 | OP_I15, /* 0 .. 15 */ | |
3781 | OP_I16, /* 1 .. 16 */ | |
3782 | OP_I31, /* 0 .. 31 */ | |
3783 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
3784 | OP_I32, /* 1 .. 32 */ | |
3785 | OP_I63s, /* -64 .. 63 */ | |
3786 | OP_I255, /* 0 .. 255 */ | |
3787 | OP_Iffff, /* 0 .. 65535 */ | |
3788 | ||
3789 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
3790 | OP_I7b, /* 0 .. 7 */ | |
3791 | OP_I15b, /* 0 .. 15 */ | |
3792 | OP_I31b, /* 0 .. 31 */ | |
3793 | ||
3794 | OP_SH, /* shifter operand */ | |
3795 | OP_ADDR, /* Memory address expression (any mode) */ | |
3796 | OP_EXP, /* arbitrary expression */ | |
3797 | OP_EXPi, /* same, with optional immediate prefix */ | |
3798 | OP_EXPr, /* same, with optional relocation suffix */ | |
3799 | ||
3800 | OP_CPSF, /* CPS flags */ | |
3801 | OP_ENDI, /* Endianness specifier */ | |
3802 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
3803 | OP_COND, /* conditional code */ | |
92e90b6e | 3804 | OP_TB, /* Table branch. */ |
c19d1205 ZW |
3805 | |
3806 | OP_RRnpc_I0, /* ARM register or literal 0 */ | |
3807 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
3808 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
3809 | OP_RF_IF, /* FPA register or immediate */ | |
3810 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
3811 | ||
3812 | /* Optional operands. */ | |
3813 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
3814 | OP_oI31b, /* 0 .. 31 */ | |
3815 | OP_oIffffb, /* 0 .. 65535 */ | |
3816 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
3817 | ||
3818 | OP_oRR, /* ARM register */ | |
3819 | OP_oRRnpc, /* ARM register, not the PC */ | |
3820 | OP_oSHll, /* LSL immediate */ | |
3821 | OP_oSHar, /* ASR immediate */ | |
3822 | OP_oSHllar, /* LSL or ASR immediate */ | |
3823 | OP_oROR, /* ROR 0/8/16/24 */ | |
62b3e311 | 3824 | OP_oBARRIER, /* Option argument for a barrier instruction. */ |
c19d1205 ZW |
3825 | |
3826 | OP_FIRST_OPTIONAL = OP_oI7b | |
3827 | }; | |
a737bd4d | 3828 | |
c19d1205 ZW |
3829 | /* Generic instruction operand parser. This does no encoding and no |
3830 | semantic validation; it merely squirrels values away in the inst | |
3831 | structure. Returns SUCCESS or FAIL depending on whether the | |
3832 | specified grammar matched. */ | |
3833 | static int | |
ca3f61f7 | 3834 | parse_operands (char *str, const unsigned char *pattern) |
c19d1205 ZW |
3835 | { |
3836 | unsigned const char *upat = pattern; | |
3837 | char *backtrack_pos = 0; | |
3838 | const char *backtrack_error = 0; | |
3839 | int i, val, backtrack_index = 0; | |
3840 | ||
3841 | #define po_char_or_fail(chr) do { \ | |
3842 | if (skip_past_char (&str, chr) == FAIL) \ | |
3843 | goto bad_args; \ | |
3844 | } while (0) | |
3845 | ||
3846 | #define po_reg_or_fail(regtype) do { \ | |
3847 | val = arm_reg_parse (&str, regtype); \ | |
3848 | if (val == FAIL) \ | |
3849 | { \ | |
3850 | inst.error = _(reg_expected_msgs[regtype]); \ | |
3851 | goto failure; \ | |
3852 | } \ | |
3853 | inst.operands[i].reg = val; \ | |
3854 | inst.operands[i].isreg = 1; \ | |
3855 | } while (0) | |
3856 | ||
3857 | #define po_reg_or_goto(regtype, label) do { \ | |
3858 | val = arm_reg_parse (&str, regtype); \ | |
3859 | if (val == FAIL) \ | |
3860 | goto label; \ | |
3861 | \ | |
3862 | inst.operands[i].reg = val; \ | |
3863 | inst.operands[i].isreg = 1; \ | |
3864 | } while (0) | |
3865 | ||
3866 | #define po_imm_or_fail(min, max, popt) do { \ | |
3867 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
3868 | goto failure; \ | |
3869 | inst.operands[i].imm = val; \ | |
3870 | } while (0) | |
3871 | ||
3872 | #define po_misc_or_fail(expr) do { \ | |
3873 | if (expr) \ | |
3874 | goto failure; \ | |
3875 | } while (0) | |
3876 | ||
3877 | skip_whitespace (str); | |
3878 | ||
3879 | for (i = 0; upat[i] != OP_stop; i++) | |
3880 | { | |
3881 | if (upat[i] >= OP_FIRST_OPTIONAL) | |
3882 | { | |
3883 | /* Remember where we are in case we need to backtrack. */ | |
3884 | assert (!backtrack_pos); | |
3885 | backtrack_pos = str; | |
3886 | backtrack_error = inst.error; | |
3887 | backtrack_index = i; | |
3888 | } | |
3889 | ||
3890 | if (i > 0) | |
3891 | po_char_or_fail (','); | |
3892 | ||
3893 | switch (upat[i]) | |
3894 | { | |
3895 | /* Registers */ | |
3896 | case OP_oRRnpc: | |
3897 | case OP_RRnpc: | |
3898 | case OP_oRR: | |
3899 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
3900 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
3901 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
3902 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
3903 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
3904 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
3905 | case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break; | |
3906 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; | |
3907 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
3908 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
3909 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
3910 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
3911 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
3912 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
3913 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
3914 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
3915 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
3916 | ||
3917 | case OP_RRnpcb: | |
3918 | po_char_or_fail ('['); | |
3919 | po_reg_or_fail (REG_TYPE_RN); | |
3920 | po_char_or_fail (']'); | |
3921 | break; | |
a737bd4d | 3922 | |
c19d1205 ZW |
3923 | case OP_RRw: |
3924 | po_reg_or_fail (REG_TYPE_RN); | |
3925 | if (skip_past_char (&str, '!') == SUCCESS) | |
3926 | inst.operands[i].writeback = 1; | |
3927 | break; | |
3928 | ||
3929 | /* Immediates */ | |
3930 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
3931 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
3932 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
3933 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; | |
3934 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
3935 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; | |
3936 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; | |
3937 | case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break; | |
3938 | ||
3939 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
3940 | case OP_oI7b: | |
3941 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
3942 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
3943 | case OP_oI31b: | |
3944 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
3945 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; | |
3946 | ||
3947 | /* Immediate variants */ | |
3948 | case OP_oI255c: | |
3949 | po_char_or_fail ('{'); | |
3950 | po_imm_or_fail (0, 255, TRUE); | |
3951 | po_char_or_fail ('}'); | |
3952 | break; | |
3953 | ||
3954 | case OP_I31w: | |
3955 | /* The expression parser chokes on a trailing !, so we have | |
3956 | to find it first and zap it. */ | |
3957 | { | |
3958 | char *s = str; | |
3959 | while (*s && *s != ',') | |
3960 | s++; | |
3961 | if (s[-1] == '!') | |
3962 | { | |
3963 | s[-1] = '\0'; | |
3964 | inst.operands[i].writeback = 1; | |
3965 | } | |
3966 | po_imm_or_fail (0, 31, TRUE); | |
3967 | if (str == s - 1) | |
3968 | str = s; | |
3969 | } | |
3970 | break; | |
3971 | ||
3972 | /* Expressions */ | |
3973 | case OP_EXPi: EXPi: | |
3974 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3975 | GE_OPT_PREFIX)); | |
3976 | break; | |
3977 | ||
3978 | case OP_EXP: | |
3979 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3980 | GE_NO_PREFIX)); | |
3981 | break; | |
3982 | ||
3983 | case OP_EXPr: EXPr: | |
3984 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3985 | GE_NO_PREFIX)); | |
3986 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 3987 | { |
c19d1205 ZW |
3988 | val = parse_reloc (&str); |
3989 | if (val == -1) | |
3990 | { | |
3991 | inst.error = _("unrecognized relocation suffix"); | |
3992 | goto failure; | |
3993 | } | |
3994 | else if (val != BFD_RELOC_UNUSED) | |
3995 | { | |
3996 | inst.operands[i].imm = val; | |
3997 | inst.operands[i].hasreloc = 1; | |
3998 | } | |
a737bd4d | 3999 | } |
c19d1205 | 4000 | break; |
a737bd4d | 4001 | |
c19d1205 ZW |
4002 | /* Register or expression */ |
4003 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; | |
4004 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 4005 | |
c19d1205 ZW |
4006 | /* Register or immediate */ |
4007 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; | |
4008 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 4009 | |
c19d1205 ZW |
4010 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
4011 | IF: | |
4012 | if (!is_immediate_prefix (*str)) | |
4013 | goto bad_args; | |
4014 | str++; | |
4015 | val = parse_fpa_immediate (&str); | |
4016 | if (val == FAIL) | |
4017 | goto failure; | |
4018 | /* FPA immediates are encoded as registers 8-15. | |
4019 | parse_fpa_immediate has already applied the offset. */ | |
4020 | inst.operands[i].reg = val; | |
4021 | inst.operands[i].isreg = 1; | |
4022 | break; | |
09d92015 | 4023 | |
c19d1205 ZW |
4024 | /* Two kinds of register */ |
4025 | case OP_RIWR_RIWC: | |
4026 | { | |
4027 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
4028 | if (rege->type != REG_TYPE_MMXWR | |
4029 | && rege->type != REG_TYPE_MMXWC | |
4030 | && rege->type != REG_TYPE_MMXWCG) | |
4031 | { | |
4032 | inst.error = _("iWMMXt data or control register expected"); | |
4033 | goto failure; | |
4034 | } | |
4035 | inst.operands[i].reg = rege->number; | |
4036 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
4037 | } | |
4038 | break; | |
09d92015 | 4039 | |
c19d1205 ZW |
4040 | /* Misc */ |
4041 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
4042 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
4043 | case OP_oROR: val = parse_ror (&str); break; | |
4044 | case OP_PSR: val = parse_psr (&str); break; | |
4045 | case OP_COND: val = parse_cond (&str); break; | |
62b3e311 | 4046 | case OP_oBARRIER:val = parse_barrier (&str); break; |
c19d1205 | 4047 | |
92e90b6e PB |
4048 | case OP_TB: |
4049 | po_misc_or_fail (parse_tb (&str)); | |
4050 | break; | |
4051 | ||
c19d1205 ZW |
4052 | /* Register lists */ |
4053 | case OP_REGLST: | |
4054 | val = parse_reg_list (&str); | |
4055 | if (*str == '^') | |
4056 | { | |
4057 | inst.operands[1].writeback = 1; | |
4058 | str++; | |
4059 | } | |
4060 | break; | |
09d92015 | 4061 | |
c19d1205 ZW |
4062 | case OP_VRSLST: |
4063 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0); | |
4064 | break; | |
09d92015 | 4065 | |
c19d1205 ZW |
4066 | case OP_VRDLST: |
4067 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1); | |
4068 | break; | |
a737bd4d | 4069 | |
c19d1205 ZW |
4070 | /* Addressing modes */ |
4071 | case OP_ADDR: | |
4072 | po_misc_or_fail (parse_address (&str, i)); | |
4073 | break; | |
09d92015 | 4074 | |
c19d1205 ZW |
4075 | case OP_SH: |
4076 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
4077 | break; | |
09d92015 | 4078 | |
c19d1205 ZW |
4079 | case OP_oSHll: |
4080 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
4081 | break; | |
09d92015 | 4082 | |
c19d1205 ZW |
4083 | case OP_oSHar: |
4084 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
4085 | break; | |
09d92015 | 4086 | |
c19d1205 ZW |
4087 | case OP_oSHllar: |
4088 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
4089 | break; | |
09d92015 | 4090 | |
c19d1205 ZW |
4091 | default: |
4092 | as_fatal ("unhandled operand code %d", upat[i]); | |
4093 | } | |
09d92015 | 4094 | |
c19d1205 ZW |
4095 | /* Various value-based sanity checks and shared operations. We |
4096 | do not signal immediate failures for the register constraints; | |
4097 | this allows a syntax error to take precedence. */ | |
4098 | switch (upat[i]) | |
4099 | { | |
4100 | case OP_oRRnpc: | |
4101 | case OP_RRnpc: | |
4102 | case OP_RRnpcb: | |
4103 | case OP_RRw: | |
4104 | case OP_RRnpc_I0: | |
4105 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
4106 | inst.error = BAD_PC; | |
4107 | break; | |
09d92015 | 4108 | |
c19d1205 ZW |
4109 | case OP_CPSF: |
4110 | case OP_ENDI: | |
4111 | case OP_oROR: | |
4112 | case OP_PSR: | |
4113 | case OP_COND: | |
62b3e311 | 4114 | case OP_oBARRIER: |
c19d1205 ZW |
4115 | case OP_REGLST: |
4116 | case OP_VRSLST: | |
4117 | case OP_VRDLST: | |
4118 | if (val == FAIL) | |
4119 | goto failure; | |
4120 | inst.operands[i].imm = val; | |
4121 | break; | |
a737bd4d | 4122 | |
c19d1205 ZW |
4123 | default: |
4124 | break; | |
4125 | } | |
09d92015 | 4126 | |
c19d1205 ZW |
4127 | /* If we get here, this operand was successfully parsed. */ |
4128 | inst.operands[i].present = 1; | |
4129 | continue; | |
09d92015 | 4130 | |
c19d1205 | 4131 | bad_args: |
09d92015 | 4132 | inst.error = BAD_ARGS; |
c19d1205 ZW |
4133 | |
4134 | failure: | |
4135 | if (!backtrack_pos) | |
4136 | return FAIL; | |
4137 | ||
4138 | /* Do not backtrack over a trailing optional argument that | |
4139 | absorbed some text. We will only fail again, with the | |
4140 | 'garbage following instruction' error message, which is | |
4141 | probably less helpful than the current one. */ | |
4142 | if (backtrack_index == i && backtrack_pos != str | |
4143 | && upat[i+1] == OP_stop) | |
4144 | return FAIL; | |
4145 | ||
4146 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
4147 | str = backtrack_pos; | |
4148 | inst.error = backtrack_error; | |
4149 | inst.operands[backtrack_index].present = 0; | |
4150 | i = backtrack_index; | |
4151 | backtrack_pos = 0; | |
09d92015 | 4152 | } |
09d92015 | 4153 | |
c19d1205 ZW |
4154 | /* Check that we have parsed all the arguments. */ |
4155 | if (*str != '\0' && !inst.error) | |
4156 | inst.error = _("garbage following instruction"); | |
09d92015 | 4157 | |
c19d1205 | 4158 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
4159 | } |
4160 | ||
c19d1205 ZW |
4161 | #undef po_char_or_fail |
4162 | #undef po_reg_or_fail | |
4163 | #undef po_reg_or_goto | |
4164 | #undef po_imm_or_fail | |
4165 | \f | |
4166 | /* Shorthand macro for instruction encoding functions issuing errors. */ | |
4167 | #define constraint(expr, err) do { \ | |
4168 | if (expr) \ | |
4169 | { \ | |
4170 | inst.error = err; \ | |
4171 | return; \ | |
4172 | } \ | |
4173 | } while (0) | |
4174 | ||
4175 | /* Functions for operand encoding. ARM, then Thumb. */ | |
4176 | ||
4177 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
4178 | ||
4179 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
4180 | return the encoded form. Otherwise, return FAIL. */ | |
4181 | ||
4182 | static unsigned int | |
4183 | encode_arm_immediate (unsigned int val) | |
09d92015 | 4184 | { |
c19d1205 ZW |
4185 | unsigned int a, i; |
4186 | ||
4187 | for (i = 0; i < 32; i += 2) | |
4188 | if ((a = rotate_left (val, i)) <= 0xff) | |
4189 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
4190 | ||
4191 | return FAIL; | |
09d92015 MM |
4192 | } |
4193 | ||
c19d1205 ZW |
4194 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
4195 | return the encoded form. Otherwise, return FAIL. */ | |
4196 | static unsigned int | |
4197 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 4198 | { |
c19d1205 | 4199 | unsigned int a, i; |
09d92015 | 4200 | |
9c3c69f2 | 4201 | if (val <= 0xff) |
c19d1205 | 4202 | return val; |
a737bd4d | 4203 | |
9c3c69f2 | 4204 | for (i = 1; i <= 24; i++) |
09d92015 | 4205 | { |
9c3c69f2 PB |
4206 | a = val >> i; |
4207 | if ((val & ~(0xff << i)) == 0) | |
4208 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 4209 | } |
a737bd4d | 4210 | |
c19d1205 ZW |
4211 | a = val & 0xff; |
4212 | if (val == ((a << 16) | a)) | |
4213 | return 0x100 | a; | |
4214 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
4215 | return 0x300 | a; | |
09d92015 | 4216 | |
c19d1205 ZW |
4217 | a = val & 0xff00; |
4218 | if (val == ((a << 16) | a)) | |
4219 | return 0x200 | (a >> 8); | |
a737bd4d | 4220 | |
c19d1205 | 4221 | return FAIL; |
09d92015 | 4222 | } |
c19d1205 | 4223 | /* Encode a VFP SP register number into inst.instruction. */ |
09d92015 MM |
4224 | |
4225 | static void | |
c19d1205 | 4226 | encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos) |
09d92015 | 4227 | { |
c19d1205 | 4228 | switch (pos) |
09d92015 | 4229 | { |
c19d1205 ZW |
4230 | case VFP_REG_Sd: |
4231 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
4232 | break; | |
4233 | ||
4234 | case VFP_REG_Sn: | |
4235 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
4236 | break; | |
4237 | ||
4238 | case VFP_REG_Sm: | |
4239 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
4240 | break; | |
4241 | ||
4242 | default: | |
4243 | abort (); | |
09d92015 | 4244 | } |
09d92015 MM |
4245 | } |
4246 | ||
c19d1205 | 4247 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 4248 | if any, is handled by md_apply_fix. */ |
09d92015 | 4249 | static void |
c19d1205 | 4250 | encode_arm_shift (int i) |
09d92015 | 4251 | { |
c19d1205 ZW |
4252 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
4253 | inst.instruction |= SHIFT_ROR << 5; | |
4254 | else | |
09d92015 | 4255 | { |
c19d1205 ZW |
4256 | inst.instruction |= inst.operands[i].shift_kind << 5; |
4257 | if (inst.operands[i].immisreg) | |
4258 | { | |
4259 | inst.instruction |= SHIFT_BY_REG; | |
4260 | inst.instruction |= inst.operands[i].imm << 8; | |
4261 | } | |
4262 | else | |
4263 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 4264 | } |
c19d1205 | 4265 | } |
09d92015 | 4266 | |
c19d1205 ZW |
4267 | static void |
4268 | encode_arm_shifter_operand (int i) | |
4269 | { | |
4270 | if (inst.operands[i].isreg) | |
09d92015 | 4271 | { |
c19d1205 ZW |
4272 | inst.instruction |= inst.operands[i].reg; |
4273 | encode_arm_shift (i); | |
09d92015 | 4274 | } |
c19d1205 ZW |
4275 | else |
4276 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
4277 | } |
4278 | ||
c19d1205 | 4279 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 4280 | static void |
c19d1205 | 4281 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 4282 | { |
c19d1205 ZW |
4283 | assert (inst.operands[i].isreg); |
4284 | inst.instruction |= inst.operands[i].reg << 16; | |
a737bd4d | 4285 | |
c19d1205 | 4286 | if (inst.operands[i].preind) |
09d92015 | 4287 | { |
c19d1205 ZW |
4288 | if (is_t) |
4289 | { | |
4290 | inst.error = _("instruction does not accept preindexed addressing"); | |
4291 | return; | |
4292 | } | |
4293 | inst.instruction |= PRE_INDEX; | |
4294 | if (inst.operands[i].writeback) | |
4295 | inst.instruction |= WRITE_BACK; | |
09d92015 | 4296 | |
c19d1205 ZW |
4297 | } |
4298 | else if (inst.operands[i].postind) | |
4299 | { | |
4300 | assert (inst.operands[i].writeback); | |
4301 | if (is_t) | |
4302 | inst.instruction |= WRITE_BACK; | |
4303 | } | |
4304 | else /* unindexed - only for coprocessor */ | |
09d92015 | 4305 | { |
c19d1205 | 4306 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
4307 | return; |
4308 | } | |
4309 | ||
c19d1205 ZW |
4310 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
4311 | && (((inst.instruction & 0x000f0000) >> 16) | |
4312 | == ((inst.instruction & 0x0000f000) >> 12))) | |
4313 | as_warn ((inst.instruction & LOAD_BIT) | |
4314 | ? _("destination register same as write-back base") | |
4315 | : _("source register same as write-back base")); | |
09d92015 MM |
4316 | } |
4317 | ||
c19d1205 ZW |
4318 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4319 | ARM-format mode 2 load or store instruction. If is_t is true, | |
4320 | reject forms that cannot be used with a T instruction (i.e. not | |
4321 | post-indexed). */ | |
a737bd4d | 4322 | static void |
c19d1205 | 4323 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 4324 | { |
c19d1205 | 4325 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 4326 | |
c19d1205 | 4327 | if (inst.operands[i].immisreg) |
09d92015 | 4328 | { |
c19d1205 ZW |
4329 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
4330 | inst.instruction |= inst.operands[i].imm; | |
4331 | if (!inst.operands[i].negative) | |
4332 | inst.instruction |= INDEX_UP; | |
4333 | if (inst.operands[i].shifted) | |
4334 | { | |
4335 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
4336 | inst.instruction |= SHIFT_ROR << 5; | |
4337 | else | |
4338 | { | |
4339 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
4340 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
4341 | } | |
4342 | } | |
09d92015 | 4343 | } |
c19d1205 | 4344 | else /* immediate offset in inst.reloc */ |
09d92015 | 4345 | { |
c19d1205 ZW |
4346 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
4347 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 4348 | } |
09d92015 MM |
4349 | } |
4350 | ||
c19d1205 ZW |
4351 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4352 | ARM-format mode 3 load or store instruction. Reject forms that | |
4353 | cannot be used with such instructions. If is_t is true, reject | |
4354 | forms that cannot be used with a T instruction (i.e. not | |
4355 | post-indexed). */ | |
4356 | static void | |
4357 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 4358 | { |
c19d1205 | 4359 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 4360 | { |
c19d1205 ZW |
4361 | inst.error = _("instruction does not accept scaled register index"); |
4362 | return; | |
09d92015 | 4363 | } |
a737bd4d | 4364 | |
c19d1205 | 4365 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 4366 | |
c19d1205 ZW |
4367 | if (inst.operands[i].immisreg) |
4368 | { | |
4369 | inst.instruction |= inst.operands[i].imm; | |
4370 | if (!inst.operands[i].negative) | |
4371 | inst.instruction |= INDEX_UP; | |
4372 | } | |
4373 | else /* immediate offset in inst.reloc */ | |
4374 | { | |
4375 | inst.instruction |= HWOFFSET_IMM; | |
4376 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
4377 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 4378 | } |
a737bd4d NC |
4379 | } |
4380 | ||
c19d1205 ZW |
4381 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4382 | ARM-format instruction. Reject all forms which cannot be encoded | |
4383 | into a coprocessor load/store instruction. If wb_ok is false, | |
4384 | reject use of writeback; if unind_ok is false, reject use of | |
4385 | unindexed addressing. If reloc_override is not 0, use it instead | |
4386 | of BFD_ARM_CP_OFF_IMM. */ | |
09d92015 | 4387 | |
c19d1205 ZW |
4388 | static int |
4389 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 4390 | { |
c19d1205 | 4391 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 4392 | |
c19d1205 | 4393 | assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 4394 | |
c19d1205 | 4395 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 4396 | { |
c19d1205 ZW |
4397 | assert (!inst.operands[i].writeback); |
4398 | if (!unind_ok) | |
4399 | { | |
4400 | inst.error = _("instruction does not support unindexed addressing"); | |
4401 | return FAIL; | |
4402 | } | |
4403 | inst.instruction |= inst.operands[i].imm; | |
4404 | inst.instruction |= INDEX_UP; | |
4405 | return SUCCESS; | |
09d92015 | 4406 | } |
a737bd4d | 4407 | |
c19d1205 ZW |
4408 | if (inst.operands[i].preind) |
4409 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 4410 | |
c19d1205 | 4411 | if (inst.operands[i].writeback) |
09d92015 | 4412 | { |
c19d1205 ZW |
4413 | if (inst.operands[i].reg == REG_PC) |
4414 | { | |
4415 | inst.error = _("pc may not be used with write-back"); | |
4416 | return FAIL; | |
4417 | } | |
4418 | if (!wb_ok) | |
4419 | { | |
4420 | inst.error = _("instruction does not support writeback"); | |
4421 | return FAIL; | |
4422 | } | |
4423 | inst.instruction |= WRITE_BACK; | |
09d92015 | 4424 | } |
a737bd4d | 4425 | |
c19d1205 ZW |
4426 | if (reloc_override) |
4427 | inst.reloc.type = reloc_override; | |
8f06b2d8 PB |
4428 | else if (thumb_mode) |
4429 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
09d92015 | 4430 | else |
c19d1205 | 4431 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; |
c19d1205 ZW |
4432 | return SUCCESS; |
4433 | } | |
a737bd4d | 4434 | |
c19d1205 ZW |
4435 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
4436 | Determine whether it can be performed with a move instruction; if | |
4437 | it can, convert inst.instruction to that move instruction and | |
4438 | return 1; if it can't, convert inst.instruction to a literal-pool | |
4439 | load and return 0. If this is not a valid thing to do in the | |
4440 | current context, set inst.error and return 1. | |
a737bd4d | 4441 | |
c19d1205 ZW |
4442 | inst.operands[i] describes the destination register. */ |
4443 | ||
4444 | static int | |
4445 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) | |
4446 | { | |
53365c0d PB |
4447 | unsigned long tbit; |
4448 | ||
4449 | if (thumb_p) | |
4450 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
4451 | else | |
4452 | tbit = LOAD_BIT; | |
4453 | ||
4454 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 4455 | { |
c19d1205 ZW |
4456 | inst.error = _("invalid pseudo operation"); |
4457 | return 1; | |
09d92015 | 4458 | } |
c19d1205 | 4459 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
4460 | { |
4461 | inst.error = _("constant expression expected"); | |
c19d1205 | 4462 | return 1; |
09d92015 | 4463 | } |
c19d1205 | 4464 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 4465 | { |
c19d1205 ZW |
4466 | if (thumb_p) |
4467 | { | |
53365c0d | 4468 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
4469 | { |
4470 | /* This can be done with a mov(1) instruction. */ | |
4471 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
4472 | inst.instruction |= inst.reloc.exp.X_add_number; | |
4473 | return 1; | |
4474 | } | |
4475 | } | |
4476 | else | |
4477 | { | |
4478 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
4479 | if (value != FAIL) | |
4480 | { | |
4481 | /* This can be done with a mov instruction. */ | |
4482 | inst.instruction &= LITERAL_MASK; | |
4483 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
4484 | inst.instruction |= value & 0xfff; | |
4485 | return 1; | |
4486 | } | |
09d92015 | 4487 | |
c19d1205 ZW |
4488 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
4489 | if (value != FAIL) | |
4490 | { | |
4491 | /* This can be done with a mvn instruction. */ | |
4492 | inst.instruction &= LITERAL_MASK; | |
4493 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
4494 | inst.instruction |= value & 0xfff; | |
4495 | return 1; | |
4496 | } | |
4497 | } | |
09d92015 MM |
4498 | } |
4499 | ||
c19d1205 ZW |
4500 | if (add_to_lit_pool () == FAIL) |
4501 | { | |
4502 | inst.error = _("literal pool insertion failed"); | |
4503 | return 1; | |
4504 | } | |
4505 | inst.operands[1].reg = REG_PC; | |
4506 | inst.operands[1].isreg = 1; | |
4507 | inst.operands[1].preind = 1; | |
4508 | inst.reloc.pc_rel = 1; | |
4509 | inst.reloc.type = (thumb_p | |
4510 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
4511 | : (mode_3 | |
4512 | ? BFD_RELOC_ARM_HWLITERAL | |
4513 | : BFD_RELOC_ARM_LITERAL)); | |
4514 | return 0; | |
09d92015 MM |
4515 | } |
4516 | ||
c19d1205 ZW |
4517 | /* Functions for instruction encoding, sorted by subarchitecture. |
4518 | First some generics; their names are taken from the conventional | |
4519 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 4520 | |
a737bd4d | 4521 | static void |
c19d1205 | 4522 | do_noargs (void) |
09d92015 | 4523 | { |
c19d1205 | 4524 | } |
a737bd4d | 4525 | |
c19d1205 ZW |
4526 | static void |
4527 | do_rd (void) | |
4528 | { | |
4529 | inst.instruction |= inst.operands[0].reg << 12; | |
4530 | } | |
a737bd4d | 4531 | |
c19d1205 ZW |
4532 | static void |
4533 | do_rd_rm (void) | |
4534 | { | |
4535 | inst.instruction |= inst.operands[0].reg << 12; | |
4536 | inst.instruction |= inst.operands[1].reg; | |
4537 | } | |
09d92015 | 4538 | |
c19d1205 ZW |
4539 | static void |
4540 | do_rd_rn (void) | |
4541 | { | |
4542 | inst.instruction |= inst.operands[0].reg << 12; | |
4543 | inst.instruction |= inst.operands[1].reg << 16; | |
4544 | } | |
a737bd4d | 4545 | |
c19d1205 ZW |
4546 | static void |
4547 | do_rn_rd (void) | |
4548 | { | |
4549 | inst.instruction |= inst.operands[0].reg << 16; | |
4550 | inst.instruction |= inst.operands[1].reg << 12; | |
4551 | } | |
09d92015 | 4552 | |
c19d1205 ZW |
4553 | static void |
4554 | do_rd_rm_rn (void) | |
4555 | { | |
9a64e435 PB |
4556 | unsigned Rn = inst.operands[2].reg; |
4557 | /* Enforce resutrictions on SWP instruction. */ | |
4558 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) | |
4559 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
4560 | _("Rn must not overlap other operands")); | |
c19d1205 ZW |
4561 | inst.instruction |= inst.operands[0].reg << 12; |
4562 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 4563 | inst.instruction |= Rn << 16; |
c19d1205 | 4564 | } |
09d92015 | 4565 | |
c19d1205 ZW |
4566 | static void |
4567 | do_rd_rn_rm (void) | |
4568 | { | |
4569 | inst.instruction |= inst.operands[0].reg << 12; | |
4570 | inst.instruction |= inst.operands[1].reg << 16; | |
4571 | inst.instruction |= inst.operands[2].reg; | |
4572 | } | |
a737bd4d | 4573 | |
c19d1205 ZW |
4574 | static void |
4575 | do_rm_rd_rn (void) | |
4576 | { | |
4577 | inst.instruction |= inst.operands[0].reg; | |
4578 | inst.instruction |= inst.operands[1].reg << 12; | |
4579 | inst.instruction |= inst.operands[2].reg << 16; | |
4580 | } | |
09d92015 | 4581 | |
c19d1205 ZW |
4582 | static void |
4583 | do_imm0 (void) | |
4584 | { | |
4585 | inst.instruction |= inst.operands[0].imm; | |
4586 | } | |
09d92015 | 4587 | |
c19d1205 ZW |
4588 | static void |
4589 | do_rd_cpaddr (void) | |
4590 | { | |
4591 | inst.instruction |= inst.operands[0].reg << 12; | |
4592 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 4593 | } |
a737bd4d | 4594 | |
c19d1205 ZW |
4595 | /* ARM instructions, in alphabetical order by function name (except |
4596 | that wrapper functions appear immediately after the function they | |
4597 | wrap). */ | |
09d92015 | 4598 | |
c19d1205 ZW |
4599 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
4600 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
4601 | |
4602 | static void | |
c19d1205 | 4603 | do_adr (void) |
09d92015 | 4604 | { |
c19d1205 | 4605 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 4606 | |
c19d1205 ZW |
4607 | /* Frag hacking will turn this into a sub instruction if the offset turns |
4608 | out to be negative. */ | |
4609 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 4610 | inst.reloc.pc_rel = 1; |
2fc8bdac | 4611 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 4612 | } |
b99bd4ef | 4613 | |
c19d1205 ZW |
4614 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
4615 | into a relative address of the form: | |
4616 | add rd, pc, #low(label-.-8)" | |
4617 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 4618 | |
c19d1205 ZW |
4619 | static void |
4620 | do_adrl (void) | |
4621 | { | |
4622 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 4623 | |
c19d1205 ZW |
4624 | /* Frag hacking will turn this into a sub instruction if the offset turns |
4625 | out to be negative. */ | |
4626 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
4627 | inst.reloc.pc_rel = 1; |
4628 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 4629 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
4630 | } |
4631 | ||
b99bd4ef | 4632 | static void |
c19d1205 | 4633 | do_arit (void) |
b99bd4ef | 4634 | { |
c19d1205 ZW |
4635 | if (!inst.operands[1].present) |
4636 | inst.operands[1].reg = inst.operands[0].reg; | |
4637 | inst.instruction |= inst.operands[0].reg << 12; | |
4638 | inst.instruction |= inst.operands[1].reg << 16; | |
4639 | encode_arm_shifter_operand (2); | |
4640 | } | |
b99bd4ef | 4641 | |
62b3e311 PB |
4642 | static void |
4643 | do_barrier (void) | |
4644 | { | |
4645 | if (inst.operands[0].present) | |
4646 | { | |
4647 | constraint ((inst.instruction & 0xf0) != 0x40 | |
4648 | && inst.operands[0].imm != 0xf, | |
4649 | "bad barrier type"); | |
4650 | inst.instruction |= inst.operands[0].imm; | |
4651 | } | |
4652 | else | |
4653 | inst.instruction |= 0xf; | |
4654 | } | |
4655 | ||
c19d1205 ZW |
4656 | static void |
4657 | do_bfc (void) | |
4658 | { | |
4659 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
4660 | constraint (msb > 32, _("bit-field extends past end of register")); | |
4661 | /* The instruction encoding stores the LSB and MSB, | |
4662 | not the LSB and width. */ | |
4663 | inst.instruction |= inst.operands[0].reg << 12; | |
4664 | inst.instruction |= inst.operands[1].imm << 7; | |
4665 | inst.instruction |= (msb - 1) << 16; | |
4666 | } | |
b99bd4ef | 4667 | |
c19d1205 ZW |
4668 | static void |
4669 | do_bfi (void) | |
4670 | { | |
4671 | unsigned int msb; | |
b99bd4ef | 4672 | |
c19d1205 ZW |
4673 | /* #0 in second position is alternative syntax for bfc, which is |
4674 | the same instruction but with REG_PC in the Rm field. */ | |
4675 | if (!inst.operands[1].isreg) | |
4676 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 4677 | |
c19d1205 ZW |
4678 | msb = inst.operands[2].imm + inst.operands[3].imm; |
4679 | constraint (msb > 32, _("bit-field extends past end of register")); | |
4680 | /* The instruction encoding stores the LSB and MSB, | |
4681 | not the LSB and width. */ | |
4682 | inst.instruction |= inst.operands[0].reg << 12; | |
4683 | inst.instruction |= inst.operands[1].reg; | |
4684 | inst.instruction |= inst.operands[2].imm << 7; | |
4685 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
4686 | } |
4687 | ||
b99bd4ef | 4688 | static void |
c19d1205 | 4689 | do_bfx (void) |
b99bd4ef | 4690 | { |
c19d1205 ZW |
4691 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
4692 | _("bit-field extends past end of register")); | |
4693 | inst.instruction |= inst.operands[0].reg << 12; | |
4694 | inst.instruction |= inst.operands[1].reg; | |
4695 | inst.instruction |= inst.operands[2].imm << 7; | |
4696 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
4697 | } | |
09d92015 | 4698 | |
c19d1205 ZW |
4699 | /* ARM V5 breakpoint instruction (argument parse) |
4700 | BKPT <16 bit unsigned immediate> | |
4701 | Instruction is not conditional. | |
4702 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
4703 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 4704 | |
c19d1205 ZW |
4705 | static void |
4706 | do_bkpt (void) | |
4707 | { | |
4708 | /* Top 12 of 16 bits to bits 19:8. */ | |
4709 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 4710 | |
c19d1205 ZW |
4711 | /* Bottom 4 of 16 bits to bits 3:0. */ |
4712 | inst.instruction |= inst.operands[0].imm & 0xf; | |
4713 | } | |
09d92015 | 4714 | |
c19d1205 ZW |
4715 | static void |
4716 | encode_branch (int default_reloc) | |
4717 | { | |
4718 | if (inst.operands[0].hasreloc) | |
4719 | { | |
4720 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
4721 | _("the only suffix valid here is '(plt)'")); | |
4722 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
c19d1205 | 4723 | } |
b99bd4ef | 4724 | else |
c19d1205 ZW |
4725 | { |
4726 | inst.reloc.type = default_reloc; | |
c19d1205 | 4727 | } |
2fc8bdac | 4728 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
4729 | } |
4730 | ||
b99bd4ef | 4731 | static void |
c19d1205 | 4732 | do_branch (void) |
b99bd4ef | 4733 | { |
39b41c9c PB |
4734 | #ifdef OBJ_ELF |
4735 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
4736 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
4737 | else | |
4738 | #endif | |
4739 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
4740 | } | |
4741 | ||
4742 | static void | |
4743 | do_bl (void) | |
4744 | { | |
4745 | #ifdef OBJ_ELF | |
4746 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
4747 | { | |
4748 | if (inst.cond == COND_ALWAYS) | |
4749 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
4750 | else | |
4751 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
4752 | } | |
4753 | else | |
4754 | #endif | |
4755 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 4756 | } |
b99bd4ef | 4757 | |
c19d1205 ZW |
4758 | /* ARM V5 branch-link-exchange instruction (argument parse) |
4759 | BLX <target_addr> ie BLX(1) | |
4760 | BLX{<condition>} <Rm> ie BLX(2) | |
4761 | Unfortunately, there are two different opcodes for this mnemonic. | |
4762 | So, the insns[].value is not used, and the code here zaps values | |
4763 | into inst.instruction. | |
4764 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 4765 | |
c19d1205 ZW |
4766 | static void |
4767 | do_blx (void) | |
4768 | { | |
4769 | if (inst.operands[0].isreg) | |
b99bd4ef | 4770 | { |
c19d1205 ZW |
4771 | /* Arg is a register; the opcode provided by insns[] is correct. |
4772 | It is not illegal to do "blx pc", just useless. */ | |
4773 | if (inst.operands[0].reg == REG_PC) | |
4774 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 4775 | |
c19d1205 ZW |
4776 | inst.instruction |= inst.operands[0].reg; |
4777 | } | |
4778 | else | |
b99bd4ef | 4779 | { |
c19d1205 ZW |
4780 | /* Arg is an address; this instruction cannot be executed |
4781 | conditionally, and the opcode must be adjusted. */ | |
4782 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
2fc8bdac | 4783 | inst.instruction = 0xfa000000; |
39b41c9c PB |
4784 | #ifdef OBJ_ELF |
4785 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
4786 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
4787 | else | |
4788 | #endif | |
4789 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); | |
b99bd4ef | 4790 | } |
c19d1205 ZW |
4791 | } |
4792 | ||
4793 | static void | |
4794 | do_bx (void) | |
4795 | { | |
4796 | if (inst.operands[0].reg == REG_PC) | |
4797 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 4798 | |
c19d1205 | 4799 | inst.instruction |= inst.operands[0].reg; |
09d92015 MM |
4800 | } |
4801 | ||
c19d1205 ZW |
4802 | |
4803 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
4804 | |
4805 | static void | |
c19d1205 | 4806 | do_bxj (void) |
a737bd4d | 4807 | { |
c19d1205 ZW |
4808 | if (inst.operands[0].reg == REG_PC) |
4809 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
4810 | ||
4811 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
4812 | } |
4813 | ||
c19d1205 ZW |
4814 | /* Co-processor data operation: |
4815 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
4816 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
4817 | static void | |
4818 | do_cdp (void) | |
4819 | { | |
4820 | inst.instruction |= inst.operands[0].reg << 8; | |
4821 | inst.instruction |= inst.operands[1].imm << 20; | |
4822 | inst.instruction |= inst.operands[2].reg << 12; | |
4823 | inst.instruction |= inst.operands[3].reg << 16; | |
4824 | inst.instruction |= inst.operands[4].reg; | |
4825 | inst.instruction |= inst.operands[5].imm << 5; | |
4826 | } | |
a737bd4d NC |
4827 | |
4828 | static void | |
c19d1205 | 4829 | do_cmp (void) |
a737bd4d | 4830 | { |
c19d1205 ZW |
4831 | inst.instruction |= inst.operands[0].reg << 16; |
4832 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
4833 | } |
4834 | ||
c19d1205 ZW |
4835 | /* Transfer between coprocessor and ARM registers. |
4836 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
4837 | MRC2 | |
4838 | MCR{cond} | |
4839 | MCR2 | |
4840 | ||
4841 | No special properties. */ | |
09d92015 MM |
4842 | |
4843 | static void | |
c19d1205 | 4844 | do_co_reg (void) |
09d92015 | 4845 | { |
c19d1205 ZW |
4846 | inst.instruction |= inst.operands[0].reg << 8; |
4847 | inst.instruction |= inst.operands[1].imm << 21; | |
4848 | inst.instruction |= inst.operands[2].reg << 12; | |
4849 | inst.instruction |= inst.operands[3].reg << 16; | |
4850 | inst.instruction |= inst.operands[4].reg; | |
4851 | inst.instruction |= inst.operands[5].imm << 5; | |
4852 | } | |
09d92015 | 4853 | |
c19d1205 ZW |
4854 | /* Transfer between coprocessor register and pair of ARM registers. |
4855 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
4856 | MCRR2 | |
4857 | MRRC{cond} | |
4858 | MRRC2 | |
b99bd4ef | 4859 | |
c19d1205 | 4860 | Two XScale instructions are special cases of these: |
09d92015 | 4861 | |
c19d1205 ZW |
4862 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
4863 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 4864 | |
c19d1205 | 4865 | Result unpredicatable if Rd or Rn is R15. */ |
a737bd4d | 4866 | |
c19d1205 ZW |
4867 | static void |
4868 | do_co_reg2c (void) | |
4869 | { | |
4870 | inst.instruction |= inst.operands[0].reg << 8; | |
4871 | inst.instruction |= inst.operands[1].imm << 4; | |
4872 | inst.instruction |= inst.operands[2].reg << 12; | |
4873 | inst.instruction |= inst.operands[3].reg << 16; | |
4874 | inst.instruction |= inst.operands[4].reg; | |
b99bd4ef NC |
4875 | } |
4876 | ||
c19d1205 ZW |
4877 | static void |
4878 | do_cpsi (void) | |
4879 | { | |
4880 | inst.instruction |= inst.operands[0].imm << 6; | |
4881 | inst.instruction |= inst.operands[1].imm; | |
4882 | } | |
b99bd4ef | 4883 | |
62b3e311 PB |
4884 | static void |
4885 | do_dbg (void) | |
4886 | { | |
4887 | inst.instruction |= inst.operands[0].imm; | |
4888 | } | |
4889 | ||
b99bd4ef | 4890 | static void |
c19d1205 | 4891 | do_it (void) |
b99bd4ef | 4892 | { |
c19d1205 ZW |
4893 | /* There is no IT instruction in ARM mode. We |
4894 | process it but do not generate code for it. */ | |
4895 | inst.size = 0; | |
09d92015 | 4896 | } |
b99bd4ef | 4897 | |
09d92015 | 4898 | static void |
c19d1205 | 4899 | do_ldmstm (void) |
ea6ef066 | 4900 | { |
c19d1205 ZW |
4901 | int base_reg = inst.operands[0].reg; |
4902 | int range = inst.operands[1].imm; | |
ea6ef066 | 4903 | |
c19d1205 ZW |
4904 | inst.instruction |= base_reg << 16; |
4905 | inst.instruction |= range; | |
ea6ef066 | 4906 | |
c19d1205 ZW |
4907 | if (inst.operands[1].writeback) |
4908 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 4909 | |
c19d1205 | 4910 | if (inst.operands[0].writeback) |
ea6ef066 | 4911 | { |
c19d1205 ZW |
4912 | inst.instruction |= WRITE_BACK; |
4913 | /* Check for unpredictable uses of writeback. */ | |
4914 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 4915 | { |
c19d1205 ZW |
4916 | /* Not allowed in LDM type 2. */ |
4917 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
4918 | && ((range & (1 << REG_PC)) == 0)) | |
4919 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
4920 | /* Only allowed if base reg not in list for other types. */ | |
4921 | else if (range & (1 << base_reg)) | |
4922 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
4923 | } | |
4924 | else /* STM. */ | |
4925 | { | |
4926 | /* Not allowed for type 2. */ | |
4927 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
4928 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
4929 | /* Only allowed if base reg not in list, or first in list. */ | |
4930 | else if ((range & (1 << base_reg)) | |
4931 | && (range & ((1 << base_reg) - 1))) | |
4932 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 4933 | } |
ea6ef066 | 4934 | } |
a737bd4d NC |
4935 | } |
4936 | ||
c19d1205 ZW |
4937 | /* ARMv5TE load-consecutive (argument parse) |
4938 | Mode is like LDRH. | |
4939 | ||
4940 | LDRccD R, mode | |
4941 | STRccD R, mode. */ | |
4942 | ||
a737bd4d | 4943 | static void |
c19d1205 | 4944 | do_ldrd (void) |
a737bd4d | 4945 | { |
c19d1205 ZW |
4946 | constraint (inst.operands[0].reg % 2 != 0, |
4947 | _("first destination register must be even")); | |
4948 | constraint (inst.operands[1].present | |
4949 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
4950 | _("can only load two consecutive registers")); | |
4951 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
4952 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 4953 | |
c19d1205 ZW |
4954 | if (!inst.operands[1].present) |
4955 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
4956 | ||
4957 | if (inst.instruction & LOAD_BIT) | |
a737bd4d | 4958 | { |
c19d1205 ZW |
4959 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
4960 | register and the first register written; we have to diagnose | |
4961 | overlap between the base and the second register written here. */ | |
ea6ef066 | 4962 | |
c19d1205 ZW |
4963 | if (inst.operands[2].reg == inst.operands[1].reg |
4964 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
4965 | as_warn (_("base register written back, and overlaps " | |
4966 | "second destination register")); | |
b05fe5cf | 4967 | |
c19d1205 ZW |
4968 | /* For an index-register load, the index register must not overlap the |
4969 | destination (even if not write-back). */ | |
4970 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
4971 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
4972 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 4973 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 4974 | } |
c19d1205 ZW |
4975 | |
4976 | inst.instruction |= inst.operands[0].reg << 12; | |
4977 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
4978 | } |
4979 | ||
4980 | static void | |
c19d1205 | 4981 | do_ldrex (void) |
b05fe5cf | 4982 | { |
c19d1205 ZW |
4983 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
4984 | || inst.operands[1].postind || inst.operands[1].writeback | |
4985 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
4986 | || inst.operands[1].negative |
4987 | /* This can arise if the programmer has written | |
4988 | strex rN, rM, foo | |
4989 | or if they have mistakenly used a register name as the last | |
4990 | operand, eg: | |
4991 | strex rN, rM, rX | |
4992 | It is very difficult to distinguish between these two cases | |
4993 | because "rX" might actually be a label. ie the register | |
4994 | name has been occluded by a symbol of the same name. So we | |
4995 | just generate a general 'bad addressing mode' type error | |
4996 | message and leave it up to the programmer to discover the | |
4997 | true cause and fix their mistake. */ | |
4998 | || (inst.operands[1].reg == REG_PC), | |
4999 | BAD_ADDR_MODE); | |
b05fe5cf | 5000 | |
c19d1205 ZW |
5001 | constraint (inst.reloc.exp.X_op != O_constant |
5002 | || inst.reloc.exp.X_add_number != 0, | |
5003 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 5004 | |
c19d1205 ZW |
5005 | inst.instruction |= inst.operands[0].reg << 12; |
5006 | inst.instruction |= inst.operands[1].reg << 16; | |
5007 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
5008 | } |
5009 | ||
5010 | static void | |
c19d1205 | 5011 | do_ldrexd (void) |
b05fe5cf | 5012 | { |
c19d1205 ZW |
5013 | constraint (inst.operands[0].reg % 2 != 0, |
5014 | _("even register required")); | |
5015 | constraint (inst.operands[1].present | |
5016 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
5017 | _("can only load two consecutive registers")); | |
5018 | /* If op 1 were present and equal to PC, this function wouldn't | |
5019 | have been called in the first place. */ | |
5020 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 5021 | |
c19d1205 ZW |
5022 | inst.instruction |= inst.operands[0].reg << 12; |
5023 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
5024 | } |
5025 | ||
5026 | static void | |
c19d1205 | 5027 | do_ldst (void) |
b05fe5cf | 5028 | { |
c19d1205 ZW |
5029 | inst.instruction |= inst.operands[0].reg << 12; |
5030 | if (!inst.operands[1].isreg) | |
5031 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 5032 | return; |
c19d1205 | 5033 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
5034 | } |
5035 | ||
5036 | static void | |
c19d1205 | 5037 | do_ldstt (void) |
b05fe5cf | 5038 | { |
c19d1205 ZW |
5039 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
5040 | reject [Rn,...]. */ | |
5041 | if (inst.operands[1].preind) | |
b05fe5cf | 5042 | { |
c19d1205 ZW |
5043 | constraint (inst.reloc.exp.X_op != O_constant || |
5044 | inst.reloc.exp.X_add_number != 0, | |
5045 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 5046 | |
c19d1205 ZW |
5047 | inst.operands[1].preind = 0; |
5048 | inst.operands[1].postind = 1; | |
5049 | inst.operands[1].writeback = 1; | |
b05fe5cf | 5050 | } |
c19d1205 ZW |
5051 | inst.instruction |= inst.operands[0].reg << 12; |
5052 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
5053 | } | |
b05fe5cf | 5054 | |
c19d1205 | 5055 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 5056 | |
c19d1205 ZW |
5057 | static void |
5058 | do_ldstv4 (void) | |
5059 | { | |
5060 | inst.instruction |= inst.operands[0].reg << 12; | |
5061 | if (!inst.operands[1].isreg) | |
5062 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 5063 | return; |
c19d1205 | 5064 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
5065 | } |
5066 | ||
5067 | static void | |
c19d1205 | 5068 | do_ldsttv4 (void) |
b05fe5cf | 5069 | { |
c19d1205 ZW |
5070 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
5071 | reject [Rn,...]. */ | |
5072 | if (inst.operands[1].preind) | |
b05fe5cf | 5073 | { |
c19d1205 ZW |
5074 | constraint (inst.reloc.exp.X_op != O_constant || |
5075 | inst.reloc.exp.X_add_number != 0, | |
5076 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 5077 | |
c19d1205 ZW |
5078 | inst.operands[1].preind = 0; |
5079 | inst.operands[1].postind = 1; | |
5080 | inst.operands[1].writeback = 1; | |
b05fe5cf | 5081 | } |
c19d1205 ZW |
5082 | inst.instruction |= inst.operands[0].reg << 12; |
5083 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
5084 | } | |
b05fe5cf | 5085 | |
c19d1205 ZW |
5086 | /* Co-processor register load/store. |
5087 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
5088 | static void | |
5089 | do_lstc (void) | |
5090 | { | |
5091 | inst.instruction |= inst.operands[0].reg << 8; | |
5092 | inst.instruction |= inst.operands[1].reg << 12; | |
5093 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
5094 | } |
5095 | ||
b05fe5cf | 5096 | static void |
c19d1205 | 5097 | do_mlas (void) |
b05fe5cf | 5098 | { |
c19d1205 ZW |
5099 | /* This restriction does not apply to mls (nor to mla in v6, but |
5100 | that's hard to detect at present). */ | |
5101 | if (inst.operands[0].reg == inst.operands[1].reg | |
5102 | && !(inst.instruction & 0x00400000)) | |
5103 | as_tsktsk (_("rd and rm should be different in mla")); | |
b05fe5cf | 5104 | |
c19d1205 ZW |
5105 | inst.instruction |= inst.operands[0].reg << 16; |
5106 | inst.instruction |= inst.operands[1].reg; | |
5107 | inst.instruction |= inst.operands[2].reg << 8; | |
5108 | inst.instruction |= inst.operands[3].reg << 12; | |
b05fe5cf | 5109 | |
c19d1205 | 5110 | } |
b05fe5cf | 5111 | |
c19d1205 ZW |
5112 | static void |
5113 | do_mov (void) | |
5114 | { | |
5115 | inst.instruction |= inst.operands[0].reg << 12; | |
5116 | encode_arm_shifter_operand (1); | |
5117 | } | |
b05fe5cf | 5118 | |
c19d1205 ZW |
5119 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
5120 | static void | |
5121 | do_mov16 (void) | |
5122 | { | |
5123 | inst.instruction |= inst.operands[0].reg << 12; | |
b05fe5cf | 5124 | /* The value is in two pieces: 0:11, 16:19. */ |
c19d1205 ZW |
5125 | inst.instruction |= (inst.operands[1].imm & 0x00000fff); |
5126 | inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4; | |
b05fe5cf | 5127 | } |
b99bd4ef NC |
5128 | |
5129 | static void | |
c19d1205 | 5130 | do_mrs (void) |
b99bd4ef | 5131 | { |
c19d1205 ZW |
5132 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
5133 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
5134 | != (PSR_c|PSR_f), | |
5135 | _("'CPSR' or 'SPSR' expected")); | |
5136 | inst.instruction |= inst.operands[0].reg << 12; | |
5137 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
5138 | } | |
b99bd4ef | 5139 | |
c19d1205 ZW |
5140 | /* Two possible forms: |
5141 | "{C|S}PSR_<field>, Rm", | |
5142 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 5143 | |
c19d1205 ZW |
5144 | static void |
5145 | do_msr (void) | |
5146 | { | |
5147 | inst.instruction |= inst.operands[0].imm; | |
5148 | if (inst.operands[1].isreg) | |
5149 | inst.instruction |= inst.operands[1].reg; | |
5150 | else | |
b99bd4ef | 5151 | { |
c19d1205 ZW |
5152 | inst.instruction |= INST_IMMEDIATE; |
5153 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
5154 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 5155 | } |
b99bd4ef NC |
5156 | } |
5157 | ||
c19d1205 ZW |
5158 | static void |
5159 | do_mul (void) | |
a737bd4d | 5160 | { |
c19d1205 ZW |
5161 | if (!inst.operands[2].present) |
5162 | inst.operands[2].reg = inst.operands[0].reg; | |
5163 | inst.instruction |= inst.operands[0].reg << 16; | |
5164 | inst.instruction |= inst.operands[1].reg; | |
5165 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 5166 | |
c19d1205 ZW |
5167 | if (inst.operands[0].reg == inst.operands[1].reg) |
5168 | as_tsktsk (_("rd and rm should be different in mul")); | |
a737bd4d NC |
5169 | } |
5170 | ||
c19d1205 ZW |
5171 | /* Long Multiply Parser |
5172 | UMULL RdLo, RdHi, Rm, Rs | |
5173 | SMULL RdLo, RdHi, Rm, Rs | |
5174 | UMLAL RdLo, RdHi, Rm, Rs | |
5175 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
5176 | |
5177 | static void | |
c19d1205 | 5178 | do_mull (void) |
b99bd4ef | 5179 | { |
c19d1205 ZW |
5180 | inst.instruction |= inst.operands[0].reg << 12; |
5181 | inst.instruction |= inst.operands[1].reg << 16; | |
5182 | inst.instruction |= inst.operands[2].reg; | |
5183 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 5184 | |
c19d1205 ZW |
5185 | /* rdhi, rdlo and rm must all be different. */ |
5186 | if (inst.operands[0].reg == inst.operands[1].reg | |
5187 | || inst.operands[0].reg == inst.operands[2].reg | |
5188 | || inst.operands[1].reg == inst.operands[2].reg) | |
5189 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); | |
5190 | } | |
b99bd4ef | 5191 | |
c19d1205 ZW |
5192 | static void |
5193 | do_nop (void) | |
5194 | { | |
5195 | if (inst.operands[0].present) | |
5196 | { | |
5197 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
5198 | inst.instruction &= 0xf0000000; | |
5199 | inst.instruction |= 0x0320f000 + inst.operands[0].imm; | |
5200 | } | |
b99bd4ef NC |
5201 | } |
5202 | ||
c19d1205 ZW |
5203 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
5204 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
5205 | Condition defaults to COND_ALWAYS. | |
5206 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
5207 | |
5208 | static void | |
c19d1205 | 5209 | do_pkhbt (void) |
b99bd4ef | 5210 | { |
c19d1205 ZW |
5211 | inst.instruction |= inst.operands[0].reg << 12; |
5212 | inst.instruction |= inst.operands[1].reg << 16; | |
5213 | inst.instruction |= inst.operands[2].reg; | |
5214 | if (inst.operands[3].present) | |
5215 | encode_arm_shift (3); | |
5216 | } | |
b99bd4ef | 5217 | |
c19d1205 | 5218 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 5219 | |
c19d1205 ZW |
5220 | static void |
5221 | do_pkhtb (void) | |
5222 | { | |
5223 | if (!inst.operands[3].present) | |
b99bd4ef | 5224 | { |
c19d1205 ZW |
5225 | /* If the shift specifier is omitted, turn the instruction |
5226 | into pkhbt rd, rm, rn. */ | |
5227 | inst.instruction &= 0xfff00010; | |
5228 | inst.instruction |= inst.operands[0].reg << 12; | |
5229 | inst.instruction |= inst.operands[1].reg; | |
5230 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
5231 | } |
5232 | else | |
5233 | { | |
c19d1205 ZW |
5234 | inst.instruction |= inst.operands[0].reg << 12; |
5235 | inst.instruction |= inst.operands[1].reg << 16; | |
5236 | inst.instruction |= inst.operands[2].reg; | |
5237 | encode_arm_shift (3); | |
b99bd4ef NC |
5238 | } |
5239 | } | |
5240 | ||
c19d1205 ZW |
5241 | /* ARMv5TE: Preload-Cache |
5242 | ||
5243 | PLD <addr_mode> | |
5244 | ||
5245 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
5246 | |
5247 | static void | |
c19d1205 | 5248 | do_pld (void) |
b99bd4ef | 5249 | { |
c19d1205 ZW |
5250 | constraint (!inst.operands[0].isreg, |
5251 | _("'[' expected after PLD mnemonic")); | |
5252 | constraint (inst.operands[0].postind, | |
5253 | _("post-indexed expression used in preload instruction")); | |
5254 | constraint (inst.operands[0].writeback, | |
5255 | _("writeback used in preload instruction")); | |
5256 | constraint (!inst.operands[0].preind, | |
5257 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
5258 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
5259 | } | |
b99bd4ef | 5260 | |
62b3e311 PB |
5261 | /* ARMv7: PLI <addr_mode> */ |
5262 | static void | |
5263 | do_pli (void) | |
5264 | { | |
5265 | constraint (!inst.operands[0].isreg, | |
5266 | _("'[' expected after PLI mnemonic")); | |
5267 | constraint (inst.operands[0].postind, | |
5268 | _("post-indexed expression used in preload instruction")); | |
5269 | constraint (inst.operands[0].writeback, | |
5270 | _("writeback used in preload instruction")); | |
5271 | constraint (!inst.operands[0].preind, | |
5272 | _("unindexed addressing used in preload instruction")); | |
5273 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
5274 | inst.instruction &= ~PRE_INDEX; | |
5275 | } | |
5276 | ||
c19d1205 ZW |
5277 | static void |
5278 | do_push_pop (void) | |
5279 | { | |
5280 | inst.operands[1] = inst.operands[0]; | |
5281 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
5282 | inst.operands[0].isreg = 1; | |
5283 | inst.operands[0].writeback = 1; | |
5284 | inst.operands[0].reg = REG_SP; | |
5285 | do_ldmstm (); | |
5286 | } | |
b99bd4ef | 5287 | |
c19d1205 ZW |
5288 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
5289 | word at the specified address and the following word | |
5290 | respectively. | |
5291 | Unconditionally executed. | |
5292 | Error if Rn is R15. */ | |
b99bd4ef | 5293 | |
c19d1205 ZW |
5294 | static void |
5295 | do_rfe (void) | |
5296 | { | |
5297 | inst.instruction |= inst.operands[0].reg << 16; | |
5298 | if (inst.operands[0].writeback) | |
5299 | inst.instruction |= WRITE_BACK; | |
5300 | } | |
b99bd4ef | 5301 | |
c19d1205 | 5302 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 5303 | |
c19d1205 ZW |
5304 | static void |
5305 | do_ssat (void) | |
5306 | { | |
5307 | inst.instruction |= inst.operands[0].reg << 12; | |
5308 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
5309 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 5310 | |
c19d1205 ZW |
5311 | if (inst.operands[3].present) |
5312 | encode_arm_shift (3); | |
b99bd4ef NC |
5313 | } |
5314 | ||
c19d1205 | 5315 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
5316 | |
5317 | static void | |
c19d1205 | 5318 | do_usat (void) |
b99bd4ef | 5319 | { |
c19d1205 ZW |
5320 | inst.instruction |= inst.operands[0].reg << 12; |
5321 | inst.instruction |= inst.operands[1].imm << 16; | |
5322 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 5323 | |
c19d1205 ZW |
5324 | if (inst.operands[3].present) |
5325 | encode_arm_shift (3); | |
b99bd4ef NC |
5326 | } |
5327 | ||
c19d1205 | 5328 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
5329 | |
5330 | static void | |
c19d1205 | 5331 | do_ssat16 (void) |
09d92015 | 5332 | { |
c19d1205 ZW |
5333 | inst.instruction |= inst.operands[0].reg << 12; |
5334 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
5335 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
5336 | } |
5337 | ||
c19d1205 ZW |
5338 | static void |
5339 | do_usat16 (void) | |
a737bd4d | 5340 | { |
c19d1205 ZW |
5341 | inst.instruction |= inst.operands[0].reg << 12; |
5342 | inst.instruction |= inst.operands[1].imm << 16; | |
5343 | inst.instruction |= inst.operands[2].reg; | |
5344 | } | |
a737bd4d | 5345 | |
c19d1205 ZW |
5346 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
5347 | preserving the other bits. | |
a737bd4d | 5348 | |
c19d1205 ZW |
5349 | setend <endian_specifier>, where <endian_specifier> is either |
5350 | BE or LE. */ | |
a737bd4d | 5351 | |
c19d1205 ZW |
5352 | static void |
5353 | do_setend (void) | |
5354 | { | |
5355 | if (inst.operands[0].imm) | |
5356 | inst.instruction |= 0x200; | |
a737bd4d NC |
5357 | } |
5358 | ||
5359 | static void | |
c19d1205 | 5360 | do_shift (void) |
a737bd4d | 5361 | { |
c19d1205 ZW |
5362 | unsigned int Rm = (inst.operands[1].present |
5363 | ? inst.operands[1].reg | |
5364 | : inst.operands[0].reg); | |
a737bd4d | 5365 | |
c19d1205 ZW |
5366 | inst.instruction |= inst.operands[0].reg << 12; |
5367 | inst.instruction |= Rm; | |
5368 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 5369 | { |
c19d1205 ZW |
5370 | inst.instruction |= inst.operands[2].reg << 8; |
5371 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
5372 | } |
5373 | else | |
c19d1205 | 5374 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
5375 | } |
5376 | ||
09d92015 | 5377 | static void |
3eb17e6b | 5378 | do_smc (void) |
09d92015 | 5379 | { |
3eb17e6b | 5380 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 5381 | inst.reloc.pc_rel = 0; |
09d92015 MM |
5382 | } |
5383 | ||
09d92015 | 5384 | static void |
c19d1205 | 5385 | do_swi (void) |
09d92015 | 5386 | { |
c19d1205 ZW |
5387 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
5388 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
5389 | } |
5390 | ||
c19d1205 ZW |
5391 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
5392 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
5393 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
5394 | Error if any register is R15. */ | |
e16bb312 | 5395 | |
c19d1205 ZW |
5396 | static void |
5397 | do_smla (void) | |
e16bb312 | 5398 | { |
c19d1205 ZW |
5399 | inst.instruction |= inst.operands[0].reg << 16; |
5400 | inst.instruction |= inst.operands[1].reg; | |
5401 | inst.instruction |= inst.operands[2].reg << 8; | |
5402 | inst.instruction |= inst.operands[3].reg << 12; | |
5403 | } | |
a737bd4d | 5404 | |
c19d1205 ZW |
5405 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
5406 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
5407 | Error if any register is R15. | |
5408 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 5409 | |
c19d1205 ZW |
5410 | static void |
5411 | do_smlal (void) | |
5412 | { | |
5413 | inst.instruction |= inst.operands[0].reg << 12; | |
5414 | inst.instruction |= inst.operands[1].reg << 16; | |
5415 | inst.instruction |= inst.operands[2].reg; | |
5416 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 5417 | |
c19d1205 ZW |
5418 | if (inst.operands[0].reg == inst.operands[1].reg) |
5419 | as_tsktsk (_("rdhi and rdlo must be different")); | |
5420 | } | |
a737bd4d | 5421 | |
c19d1205 ZW |
5422 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
5423 | SMULxy{cond} Rd,Rm,Rs | |
5424 | Error if any register is R15. */ | |
a737bd4d | 5425 | |
c19d1205 ZW |
5426 | static void |
5427 | do_smul (void) | |
5428 | { | |
5429 | inst.instruction |= inst.operands[0].reg << 16; | |
5430 | inst.instruction |= inst.operands[1].reg; | |
5431 | inst.instruction |= inst.operands[2].reg << 8; | |
5432 | } | |
a737bd4d | 5433 | |
c19d1205 | 5434 | /* ARM V6 srs (argument parse). */ |
a737bd4d | 5435 | |
c19d1205 ZW |
5436 | static void |
5437 | do_srs (void) | |
5438 | { | |
5439 | inst.instruction |= inst.operands[0].imm; | |
5440 | if (inst.operands[0].writeback) | |
5441 | inst.instruction |= WRITE_BACK; | |
5442 | } | |
a737bd4d | 5443 | |
c19d1205 | 5444 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 5445 | |
c19d1205 ZW |
5446 | static void |
5447 | do_strex (void) | |
5448 | { | |
5449 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
5450 | || inst.operands[2].postind || inst.operands[2].writeback | |
5451 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
5452 | || inst.operands[2].negative |
5453 | /* See comment in do_ldrex(). */ | |
5454 | || (inst.operands[2].reg == REG_PC), | |
5455 | BAD_ADDR_MODE); | |
a737bd4d | 5456 | |
c19d1205 ZW |
5457 | constraint (inst.operands[0].reg == inst.operands[1].reg |
5458 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 5459 | |
c19d1205 ZW |
5460 | constraint (inst.reloc.exp.X_op != O_constant |
5461 | || inst.reloc.exp.X_add_number != 0, | |
5462 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 5463 | |
c19d1205 ZW |
5464 | inst.instruction |= inst.operands[0].reg << 12; |
5465 | inst.instruction |= inst.operands[1].reg; | |
5466 | inst.instruction |= inst.operands[2].reg << 16; | |
5467 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
5468 | } |
5469 | ||
5470 | static void | |
c19d1205 | 5471 | do_strexd (void) |
e16bb312 | 5472 | { |
c19d1205 ZW |
5473 | constraint (inst.operands[1].reg % 2 != 0, |
5474 | _("even register required")); | |
5475 | constraint (inst.operands[2].present | |
5476 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
5477 | _("can only store two consecutive registers")); | |
5478 | /* If op 2 were present and equal to PC, this function wouldn't | |
5479 | have been called in the first place. */ | |
5480 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 5481 | |
c19d1205 ZW |
5482 | constraint (inst.operands[0].reg == inst.operands[1].reg |
5483 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
5484 | || inst.operands[0].reg == inst.operands[3].reg, | |
5485 | BAD_OVERLAP); | |
e16bb312 | 5486 | |
c19d1205 ZW |
5487 | inst.instruction |= inst.operands[0].reg << 12; |
5488 | inst.instruction |= inst.operands[1].reg; | |
5489 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
5490 | } |
5491 | ||
c19d1205 ZW |
5492 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
5493 | extends it to 32-bits, and adds the result to a value in another | |
5494 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
5495 | before extracting the 16-bit value. | |
5496 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
5497 | Condition defaults to COND_ALWAYS. | |
5498 | Error if any register uses R15. */ | |
5499 | ||
e16bb312 | 5500 | static void |
c19d1205 | 5501 | do_sxtah (void) |
e16bb312 | 5502 | { |
c19d1205 ZW |
5503 | inst.instruction |= inst.operands[0].reg << 12; |
5504 | inst.instruction |= inst.operands[1].reg << 16; | |
5505 | inst.instruction |= inst.operands[2].reg; | |
5506 | inst.instruction |= inst.operands[3].imm << 10; | |
5507 | } | |
e16bb312 | 5508 | |
c19d1205 | 5509 | /* ARM V6 SXTH. |
e16bb312 | 5510 | |
c19d1205 ZW |
5511 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
5512 | Condition defaults to COND_ALWAYS. | |
5513 | Error if any register uses R15. */ | |
e16bb312 NC |
5514 | |
5515 | static void | |
c19d1205 | 5516 | do_sxth (void) |
e16bb312 | 5517 | { |
c19d1205 ZW |
5518 | inst.instruction |= inst.operands[0].reg << 12; |
5519 | inst.instruction |= inst.operands[1].reg; | |
5520 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 5521 | } |
c19d1205 ZW |
5522 | \f |
5523 | /* VFP instructions. In a logical order: SP variant first, monad | |
5524 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
5525 | |
5526 | static void | |
c19d1205 | 5527 | do_vfp_sp_monadic (void) |
e16bb312 | 5528 | { |
c19d1205 ZW |
5529 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5530 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
5531 | } |
5532 | ||
5533 | static void | |
c19d1205 | 5534 | do_vfp_sp_dyadic (void) |
e16bb312 | 5535 | { |
c19d1205 ZW |
5536 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5537 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
5538 | encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
5539 | } |
5540 | ||
5541 | static void | |
c19d1205 | 5542 | do_vfp_sp_compare_z (void) |
e16bb312 | 5543 | { |
c19d1205 | 5544 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
5545 | } |
5546 | ||
5547 | static void | |
c19d1205 | 5548 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 5549 | { |
c19d1205 ZW |
5550 | inst.instruction |= inst.operands[0].reg << 12; |
5551 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
5552 | } |
5553 | ||
5554 | static void | |
c19d1205 | 5555 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 5556 | { |
c19d1205 ZW |
5557 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5558 | inst.instruction |= inst.operands[1].reg; | |
e16bb312 NC |
5559 | } |
5560 | ||
5561 | static void | |
c19d1205 | 5562 | do_vfp_reg_from_sp (void) |
e16bb312 | 5563 | { |
c19d1205 ZW |
5564 | inst.instruction |= inst.operands[0].reg << 12; |
5565 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
e16bb312 NC |
5566 | } |
5567 | ||
5568 | static void | |
c19d1205 | 5569 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 5570 | { |
c19d1205 ZW |
5571 | constraint (inst.operands[2].imm != 2, |
5572 | _("only two consecutive VFP SP registers allowed here")); | |
5573 | inst.instruction |= inst.operands[0].reg << 12; | |
5574 | inst.instruction |= inst.operands[1].reg << 16; | |
5575 | encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
5576 | } |
5577 | ||
5578 | static void | |
c19d1205 | 5579 | do_vfp_sp_from_reg (void) |
e16bb312 | 5580 | { |
c19d1205 ZW |
5581 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn); |
5582 | inst.instruction |= inst.operands[1].reg << 12; | |
e16bb312 NC |
5583 | } |
5584 | ||
5585 | static void | |
c19d1205 | 5586 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 5587 | { |
c19d1205 ZW |
5588 | constraint (inst.operands[0].imm != 2, |
5589 | _("only two consecutive VFP SP registers allowed here")); | |
5590 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm); | |
5591 | inst.instruction |= inst.operands[1].reg << 12; | |
5592 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
5593 | } |
5594 | ||
5595 | static void | |
c19d1205 | 5596 | do_vfp_sp_ldst (void) |
e16bb312 | 5597 | { |
c19d1205 ZW |
5598 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5599 | encode_arm_cp_address (1, FALSE, TRUE, 0); | |
e16bb312 NC |
5600 | } |
5601 | ||
5602 | static void | |
c19d1205 | 5603 | do_vfp_dp_ldst (void) |
e16bb312 | 5604 | { |
c19d1205 ZW |
5605 | inst.instruction |= inst.operands[0].reg << 12; |
5606 | encode_arm_cp_address (1, FALSE, TRUE, 0); | |
e16bb312 NC |
5607 | } |
5608 | ||
c19d1205 | 5609 | |
e16bb312 | 5610 | static void |
c19d1205 | 5611 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 5612 | { |
c19d1205 ZW |
5613 | if (inst.operands[0].writeback) |
5614 | inst.instruction |= WRITE_BACK; | |
5615 | else | |
5616 | constraint (ldstm_type != VFP_LDSTMIA, | |
5617 | _("this addressing mode requires base-register writeback")); | |
5618 | inst.instruction |= inst.operands[0].reg << 16; | |
5619 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd); | |
5620 | inst.instruction |= inst.operands[1].imm; | |
e16bb312 NC |
5621 | } |
5622 | ||
5623 | static void | |
c19d1205 | 5624 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 5625 | { |
c19d1205 | 5626 | int count; |
e16bb312 | 5627 | |
c19d1205 ZW |
5628 | if (inst.operands[0].writeback) |
5629 | inst.instruction |= WRITE_BACK; | |
5630 | else | |
5631 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
5632 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 5633 | |
c19d1205 ZW |
5634 | inst.instruction |= inst.operands[0].reg << 16; |
5635 | inst.instruction |= inst.operands[1].reg << 12; | |
e16bb312 | 5636 | |
c19d1205 ZW |
5637 | count = inst.operands[1].imm << 1; |
5638 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
5639 | count += 1; | |
e16bb312 | 5640 | |
c19d1205 | 5641 | inst.instruction |= count; |
e16bb312 NC |
5642 | } |
5643 | ||
5644 | static void | |
c19d1205 | 5645 | do_vfp_sp_ldstmia (void) |
e16bb312 | 5646 | { |
c19d1205 | 5647 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
5648 | } |
5649 | ||
5650 | static void | |
c19d1205 | 5651 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 5652 | { |
c19d1205 | 5653 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
5654 | } |
5655 | ||
5656 | static void | |
c19d1205 | 5657 | do_vfp_dp_ldstmia (void) |
e16bb312 | 5658 | { |
c19d1205 | 5659 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
5660 | } |
5661 | ||
5662 | static void | |
c19d1205 | 5663 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 5664 | { |
c19d1205 | 5665 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
5666 | } |
5667 | ||
5668 | static void | |
c19d1205 | 5669 | do_vfp_xp_ldstmia (void) |
e16bb312 | 5670 | { |
c19d1205 ZW |
5671 | vfp_dp_ldstm (VFP_LDSTMIAX); |
5672 | } | |
e16bb312 | 5673 | |
c19d1205 ZW |
5674 | static void |
5675 | do_vfp_xp_ldstmdb (void) | |
5676 | { | |
5677 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 5678 | } |
c19d1205 ZW |
5679 | \f |
5680 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 5681 | |
c19d1205 ZW |
5682 | static void |
5683 | do_fpa_cmp (void) | |
5684 | { | |
5685 | inst.instruction |= inst.operands[0].reg << 16; | |
5686 | inst.instruction |= inst.operands[1].reg; | |
5687 | } | |
b99bd4ef NC |
5688 | |
5689 | static void | |
c19d1205 | 5690 | do_fpa_ldmstm (void) |
b99bd4ef | 5691 | { |
c19d1205 ZW |
5692 | inst.instruction |= inst.operands[0].reg << 12; |
5693 | switch (inst.operands[1].imm) | |
5694 | { | |
5695 | case 1: inst.instruction |= CP_T_X; break; | |
5696 | case 2: inst.instruction |= CP_T_Y; break; | |
5697 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
5698 | case 4: break; | |
5699 | default: abort (); | |
5700 | } | |
b99bd4ef | 5701 | |
c19d1205 ZW |
5702 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
5703 | { | |
5704 | /* The instruction specified "ea" or "fd", so we can only accept | |
5705 | [Rn]{!}. The instruction does not really support stacking or | |
5706 | unstacking, so we have to emulate these by setting appropriate | |
5707 | bits and offsets. */ | |
5708 | constraint (inst.reloc.exp.X_op != O_constant | |
5709 | || inst.reloc.exp.X_add_number != 0, | |
5710 | _("this instruction does not support indexing")); | |
b99bd4ef | 5711 | |
c19d1205 ZW |
5712 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
5713 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 5714 | |
c19d1205 ZW |
5715 | if (!(inst.instruction & INDEX_UP)) |
5716 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 5717 | |
c19d1205 ZW |
5718 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
5719 | { | |
5720 | inst.operands[2].preind = 0; | |
5721 | inst.operands[2].postind = 1; | |
5722 | } | |
5723 | } | |
b99bd4ef | 5724 | |
c19d1205 | 5725 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 5726 | } |
c19d1205 ZW |
5727 | \f |
5728 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 5729 | |
c19d1205 ZW |
5730 | static void |
5731 | do_iwmmxt_tandorc (void) | |
5732 | { | |
5733 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
5734 | } | |
b99bd4ef | 5735 | |
c19d1205 ZW |
5736 | static void |
5737 | do_iwmmxt_textrc (void) | |
5738 | { | |
5739 | inst.instruction |= inst.operands[0].reg << 12; | |
5740 | inst.instruction |= inst.operands[1].imm; | |
5741 | } | |
b99bd4ef NC |
5742 | |
5743 | static void | |
c19d1205 | 5744 | do_iwmmxt_textrm (void) |
b99bd4ef | 5745 | { |
c19d1205 ZW |
5746 | inst.instruction |= inst.operands[0].reg << 12; |
5747 | inst.instruction |= inst.operands[1].reg << 16; | |
5748 | inst.instruction |= inst.operands[2].imm; | |
5749 | } | |
b99bd4ef | 5750 | |
c19d1205 ZW |
5751 | static void |
5752 | do_iwmmxt_tinsr (void) | |
5753 | { | |
5754 | inst.instruction |= inst.operands[0].reg << 16; | |
5755 | inst.instruction |= inst.operands[1].reg << 12; | |
5756 | inst.instruction |= inst.operands[2].imm; | |
5757 | } | |
b99bd4ef | 5758 | |
c19d1205 ZW |
5759 | static void |
5760 | do_iwmmxt_tmia (void) | |
5761 | { | |
5762 | inst.instruction |= inst.operands[0].reg << 5; | |
5763 | inst.instruction |= inst.operands[1].reg; | |
5764 | inst.instruction |= inst.operands[2].reg << 12; | |
5765 | } | |
b99bd4ef | 5766 | |
c19d1205 ZW |
5767 | static void |
5768 | do_iwmmxt_waligni (void) | |
5769 | { | |
5770 | inst.instruction |= inst.operands[0].reg << 12; | |
5771 | inst.instruction |= inst.operands[1].reg << 16; | |
5772 | inst.instruction |= inst.operands[2].reg; | |
5773 | inst.instruction |= inst.operands[3].imm << 20; | |
5774 | } | |
b99bd4ef | 5775 | |
c19d1205 ZW |
5776 | static void |
5777 | do_iwmmxt_wmov (void) | |
5778 | { | |
5779 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
5780 | inst.instruction |= inst.operands[0].reg << 12; | |
5781 | inst.instruction |= inst.operands[1].reg << 16; | |
5782 | inst.instruction |= inst.operands[1].reg; | |
5783 | } | |
b99bd4ef | 5784 | |
c19d1205 ZW |
5785 | static void |
5786 | do_iwmmxt_wldstbh (void) | |
5787 | { | |
8f06b2d8 | 5788 | int reloc; |
c19d1205 ZW |
5789 | inst.instruction |= inst.operands[0].reg << 12; |
5790 | inst.reloc.exp.X_add_number *= 4; | |
8f06b2d8 PB |
5791 | if (thumb_mode) |
5792 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
5793 | else | |
5794 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
5795 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
5796 | } |
5797 | ||
c19d1205 ZW |
5798 | static void |
5799 | do_iwmmxt_wldstw (void) | |
5800 | { | |
5801 | /* RIWR_RIWC clears .isreg for a control register. */ | |
5802 | if (!inst.operands[0].isreg) | |
5803 | { | |
5804 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
5805 | inst.instruction |= 0xf0000000; | |
5806 | } | |
b99bd4ef | 5807 | |
c19d1205 ZW |
5808 | inst.instruction |= inst.operands[0].reg << 12; |
5809 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
5810 | } | |
b99bd4ef NC |
5811 | |
5812 | static void | |
c19d1205 | 5813 | do_iwmmxt_wldstd (void) |
b99bd4ef | 5814 | { |
c19d1205 | 5815 | inst.instruction |= inst.operands[0].reg << 12; |
f2184508 | 5816 | encode_arm_cp_address (1, TRUE, FALSE, 0); |
c19d1205 | 5817 | } |
b99bd4ef | 5818 | |
c19d1205 ZW |
5819 | static void |
5820 | do_iwmmxt_wshufh (void) | |
5821 | { | |
5822 | inst.instruction |= inst.operands[0].reg << 12; | |
5823 | inst.instruction |= inst.operands[1].reg << 16; | |
5824 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
5825 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
5826 | } | |
b99bd4ef | 5827 | |
c19d1205 ZW |
5828 | static void |
5829 | do_iwmmxt_wzero (void) | |
5830 | { | |
5831 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
5832 | inst.instruction |= inst.operands[0].reg; | |
5833 | inst.instruction |= inst.operands[0].reg << 12; | |
5834 | inst.instruction |= inst.operands[0].reg << 16; | |
5835 | } | |
5836 | \f | |
5837 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
5838 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 5839 | |
c19d1205 | 5840 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 5841 | |
c19d1205 ZW |
5842 | static void |
5843 | do_mav_triple (void) | |
5844 | { | |
5845 | inst.instruction |= inst.operands[0].reg << 16; | |
5846 | inst.instruction |= inst.operands[1].reg; | |
5847 | inst.instruction |= inst.operands[2].reg << 12; | |
5848 | } | |
b99bd4ef | 5849 | |
c19d1205 ZW |
5850 | /* Insns like "foo W,X,Y,Z". |
5851 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 5852 | |
c19d1205 ZW |
5853 | static void |
5854 | do_mav_quad (void) | |
5855 | { | |
5856 | inst.instruction |= inst.operands[0].reg << 5; | |
5857 | inst.instruction |= inst.operands[1].reg << 12; | |
5858 | inst.instruction |= inst.operands[2].reg << 16; | |
5859 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
5860 | } |
5861 | ||
c19d1205 ZW |
5862 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
5863 | static void | |
5864 | do_mav_dspsc (void) | |
a737bd4d | 5865 | { |
c19d1205 ZW |
5866 | inst.instruction |= inst.operands[1].reg << 12; |
5867 | } | |
a737bd4d | 5868 | |
c19d1205 ZW |
5869 | /* Maverick shift immediate instructions. |
5870 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
5871 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 5872 | |
c19d1205 ZW |
5873 | static void |
5874 | do_mav_shift (void) | |
5875 | { | |
5876 | int imm = inst.operands[2].imm; | |
a737bd4d | 5877 | |
c19d1205 ZW |
5878 | inst.instruction |= inst.operands[0].reg << 12; |
5879 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 5880 | |
c19d1205 ZW |
5881 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
5882 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
5883 | Bit 4 should be 0. */ | |
5884 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 5885 | |
c19d1205 ZW |
5886 | inst.instruction |= imm; |
5887 | } | |
5888 | \f | |
5889 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 5890 | |
c19d1205 ZW |
5891 | /* Xscale multiply-accumulate (argument parse) |
5892 | MIAcc acc0,Rm,Rs | |
5893 | MIAPHcc acc0,Rm,Rs | |
5894 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 5895 | |
c19d1205 ZW |
5896 | static void |
5897 | do_xsc_mia (void) | |
5898 | { | |
5899 | inst.instruction |= inst.operands[1].reg; | |
5900 | inst.instruction |= inst.operands[2].reg << 12; | |
5901 | } | |
a737bd4d | 5902 | |
c19d1205 | 5903 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 5904 | |
c19d1205 | 5905 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 5906 | |
c19d1205 ZW |
5907 | static void |
5908 | do_xsc_mar (void) | |
5909 | { | |
5910 | inst.instruction |= inst.operands[1].reg << 12; | |
5911 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
5912 | } |
5913 | ||
c19d1205 | 5914 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 5915 | |
c19d1205 | 5916 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
5917 | |
5918 | static void | |
c19d1205 | 5919 | do_xsc_mra (void) |
b99bd4ef | 5920 | { |
c19d1205 ZW |
5921 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
5922 | inst.instruction |= inst.operands[0].reg << 12; | |
5923 | inst.instruction |= inst.operands[1].reg << 16; | |
5924 | } | |
5925 | \f | |
5926 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 5927 | |
c19d1205 ZW |
5928 | /* inst.operands[i] is a shifted-register operand; encode |
5929 | it into inst.instruction in the format used by Thumb32. */ | |
5930 | ||
5931 | static void | |
5932 | encode_thumb32_shifted_operand (int i) | |
5933 | { | |
5934 | unsigned int value = inst.reloc.exp.X_add_number; | |
5935 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 5936 | |
9c3c69f2 PB |
5937 | constraint (inst.operands[i].immisreg, |
5938 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
5939 | inst.instruction |= inst.operands[i].reg; |
5940 | if (shift == SHIFT_RRX) | |
5941 | inst.instruction |= SHIFT_ROR << 4; | |
5942 | else | |
b99bd4ef | 5943 | { |
c19d1205 ZW |
5944 | constraint (inst.reloc.exp.X_op != O_constant, |
5945 | _("expression too complex")); | |
5946 | ||
5947 | constraint (value > 32 | |
5948 | || (value == 32 && (shift == SHIFT_LSL | |
5949 | || shift == SHIFT_ROR)), | |
5950 | _("shift expression is too large")); | |
5951 | ||
5952 | if (value == 0) | |
5953 | shift = SHIFT_LSL; | |
5954 | else if (value == 32) | |
5955 | value = 0; | |
5956 | ||
5957 | inst.instruction |= shift << 4; | |
5958 | inst.instruction |= (value & 0x1c) << 10; | |
5959 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 5960 | } |
c19d1205 | 5961 | } |
b99bd4ef | 5962 | |
b99bd4ef | 5963 | |
c19d1205 ZW |
5964 | /* inst.operands[i] was set up by parse_address. Encode it into a |
5965 | Thumb32 format load or store instruction. Reject forms that cannot | |
5966 | be used with such instructions. If is_t is true, reject forms that | |
5967 | cannot be used with a T instruction; if is_d is true, reject forms | |
5968 | that cannot be used with a D instruction. */ | |
b99bd4ef | 5969 | |
c19d1205 ZW |
5970 | static void |
5971 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
5972 | { | |
5973 | bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); | |
5974 | ||
5975 | constraint (!inst.operands[i].isreg, | |
53365c0d | 5976 | _("Instruction does not support =N addresses")); |
b99bd4ef | 5977 | |
c19d1205 ZW |
5978 | inst.instruction |= inst.operands[i].reg << 16; |
5979 | if (inst.operands[i].immisreg) | |
b99bd4ef | 5980 | { |
c19d1205 ZW |
5981 | constraint (is_pc, _("cannot use register index with PC-relative addressing")); |
5982 | constraint (is_t || is_d, _("cannot use register index with this instruction")); | |
5983 | constraint (inst.operands[i].negative, | |
5984 | _("Thumb does not support negative register indexing")); | |
5985 | constraint (inst.operands[i].postind, | |
5986 | _("Thumb does not support register post-indexing")); | |
5987 | constraint (inst.operands[i].writeback, | |
5988 | _("Thumb does not support register indexing with writeback")); | |
5989 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
5990 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 5991 | |
f40d1643 | 5992 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 5993 | if (inst.operands[i].shifted) |
b99bd4ef | 5994 | { |
c19d1205 ZW |
5995 | constraint (inst.reloc.exp.X_op != O_constant, |
5996 | _("expression too complex")); | |
9c3c69f2 PB |
5997 | constraint (inst.reloc.exp.X_add_number < 0 |
5998 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 5999 | _("shift out of range")); |
9c3c69f2 | 6000 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
6001 | } |
6002 | inst.reloc.type = BFD_RELOC_UNUSED; | |
6003 | } | |
6004 | else if (inst.operands[i].preind) | |
6005 | { | |
6006 | constraint (is_pc && inst.operands[i].writeback, | |
6007 | _("cannot use writeback with PC-relative addressing")); | |
f40d1643 | 6008 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 ZW |
6009 | _("cannot use writeback with this instruction")); |
6010 | ||
6011 | if (is_d) | |
6012 | { | |
6013 | inst.instruction |= 0x01000000; | |
6014 | if (inst.operands[i].writeback) | |
6015 | inst.instruction |= 0x00200000; | |
b99bd4ef | 6016 | } |
c19d1205 | 6017 | else |
b99bd4ef | 6018 | { |
c19d1205 ZW |
6019 | inst.instruction |= 0x00000c00; |
6020 | if (inst.operands[i].writeback) | |
6021 | inst.instruction |= 0x00000100; | |
b99bd4ef | 6022 | } |
c19d1205 | 6023 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 6024 | } |
c19d1205 | 6025 | else if (inst.operands[i].postind) |
b99bd4ef | 6026 | { |
c19d1205 ZW |
6027 | assert (inst.operands[i].writeback); |
6028 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); | |
6029 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
6030 | ||
6031 | if (is_d) | |
6032 | inst.instruction |= 0x00200000; | |
6033 | else | |
6034 | inst.instruction |= 0x00000900; | |
6035 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
6036 | } | |
6037 | else /* unindexed - only for coprocessor */ | |
6038 | inst.error = _("instruction does not accept unindexed addressing"); | |
6039 | } | |
6040 | ||
6041 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
6042 | encodings (the latter only in post-V6T2 cores). The index is the | |
6043 | value used in the insns table below. When there is more than one | |
6044 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
6045 | holds variant (1). |
6046 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 ZW |
6047 | #define T16_32_TAB \ |
6048 | X(adc, 4140, eb400000), \ | |
6049 | X(adcs, 4140, eb500000), \ | |
6050 | X(add, 1c00, eb000000), \ | |
6051 | X(adds, 1c00, eb100000), \ | |
0110f2b8 PB |
6052 | X(addi, 0000, f1000000), \ |
6053 | X(addis, 0000, f1100000), \ | |
6054 | X(add_pc,000f, f20f0000), \ | |
6055 | X(add_sp,000d, f10d0000), \ | |
e9f89963 | 6056 | X(adr, 000f, f20f0000), \ |
c19d1205 ZW |
6057 | X(and, 4000, ea000000), \ |
6058 | X(ands, 4000, ea100000), \ | |
6059 | X(asr, 1000, fa40f000), \ | |
6060 | X(asrs, 1000, fa50f000), \ | |
0110f2b8 PB |
6061 | X(b, e000, f000b000), \ |
6062 | X(bcond, d000, f0008000), \ | |
c19d1205 ZW |
6063 | X(bic, 4380, ea200000), \ |
6064 | X(bics, 4380, ea300000), \ | |
6065 | X(cmn, 42c0, eb100f00), \ | |
6066 | X(cmp, 2800, ebb00f00), \ | |
6067 | X(cpsie, b660, f3af8400), \ | |
6068 | X(cpsid, b670, f3af8600), \ | |
6069 | X(cpy, 4600, ea4f0000), \ | |
0110f2b8 | 6070 | X(dec_sp,80dd, f1bd0d00), \ |
c19d1205 ZW |
6071 | X(eor, 4040, ea800000), \ |
6072 | X(eors, 4040, ea900000), \ | |
0110f2b8 | 6073 | X(inc_sp,00dd, f10d0d00), \ |
c19d1205 ZW |
6074 | X(ldmia, c800, e8900000), \ |
6075 | X(ldr, 6800, f8500000), \ | |
6076 | X(ldrb, 7800, f8100000), \ | |
6077 | X(ldrh, 8800, f8300000), \ | |
6078 | X(ldrsb, 5600, f9100000), \ | |
6079 | X(ldrsh, 5e00, f9300000), \ | |
0110f2b8 PB |
6080 | X(ldr_pc,4800, f85f0000), \ |
6081 | X(ldr_pc2,4800, f85f0000), \ | |
6082 | X(ldr_sp,9800, f85d0000), \ | |
c19d1205 ZW |
6083 | X(lsl, 0000, fa00f000), \ |
6084 | X(lsls, 0000, fa10f000), \ | |
6085 | X(lsr, 0800, fa20f000), \ | |
6086 | X(lsrs, 0800, fa30f000), \ | |
6087 | X(mov, 2000, ea4f0000), \ | |
6088 | X(movs, 2000, ea5f0000), \ | |
6089 | X(mul, 4340, fb00f000), \ | |
6090 | X(muls, 4340, ffffffff), /* no 32b muls */ \ | |
6091 | X(mvn, 43c0, ea6f0000), \ | |
6092 | X(mvns, 43c0, ea7f0000), \ | |
6093 | X(neg, 4240, f1c00000), /* rsb #0 */ \ | |
6094 | X(negs, 4240, f1d00000), /* rsbs #0 */ \ | |
6095 | X(orr, 4300, ea400000), \ | |
6096 | X(orrs, 4300, ea500000), \ | |
e9f89963 PB |
6097 | X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ |
6098 | X(push, b400, e92d0000), /* stmdb sp!,... */ \ | |
c19d1205 ZW |
6099 | X(rev, ba00, fa90f080), \ |
6100 | X(rev16, ba40, fa90f090), \ | |
6101 | X(revsh, bac0, fa90f0b0), \ | |
6102 | X(ror, 41c0, fa60f000), \ | |
6103 | X(rors, 41c0, fa70f000), \ | |
6104 | X(sbc, 4180, eb600000), \ | |
6105 | X(sbcs, 4180, eb700000), \ | |
6106 | X(stmia, c000, e8800000), \ | |
6107 | X(str, 6000, f8400000), \ | |
6108 | X(strb, 7000, f8000000), \ | |
6109 | X(strh, 8000, f8200000), \ | |
0110f2b8 | 6110 | X(str_sp,9000, f84d0000), \ |
c19d1205 ZW |
6111 | X(sub, 1e00, eba00000), \ |
6112 | X(subs, 1e00, ebb00000), \ | |
0110f2b8 PB |
6113 | X(subi, 8000, f1a00000), \ |
6114 | X(subis, 8000, f1b00000), \ | |
c19d1205 ZW |
6115 | X(sxtb, b240, fa4ff080), \ |
6116 | X(sxth, b200, fa0ff080), \ | |
6117 | X(tst, 4200, ea100f00), \ | |
6118 | X(uxtb, b2c0, fa5ff080), \ | |
6119 | X(uxth, b280, fa1ff080), \ | |
6120 | X(nop, bf00, f3af8000), \ | |
6121 | X(yield, bf10, f3af8001), \ | |
6122 | X(wfe, bf20, f3af8002), \ | |
6123 | X(wfi, bf30, f3af8003), \ | |
6124 | X(sev, bf40, f3af9004), /* typo, 8004? */ | |
6125 | ||
6126 | /* To catch errors in encoding functions, the codes are all offset by | |
6127 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
6128 | as 16-bit instructions. */ | |
6129 | #define X(a,b,c) T_MNEM_##a | |
6130 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; | |
6131 | #undef X | |
6132 | ||
6133 | #define X(a,b,c) 0x##b | |
6134 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
6135 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
6136 | #undef X | |
6137 | ||
6138 | #define X(a,b,c) 0x##c | |
6139 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
6140 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) | |
6141 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
6142 | #undef X | |
6143 | #undef T16_32_TAB | |
6144 | ||
6145 | /* Thumb instruction encoders, in alphabetical order. */ | |
6146 | ||
92e90b6e PB |
6147 | /* ADDW or SUBW. */ |
6148 | static void | |
6149 | do_t_add_sub_w (void) | |
6150 | { | |
6151 | int Rd, Rn; | |
6152 | ||
6153 | Rd = inst.operands[0].reg; | |
6154 | Rn = inst.operands[1].reg; | |
6155 | ||
6156 | constraint (Rd == 15, _("PC not allowed as destination")); | |
6157 | inst.instruction |= (Rn << 16) | (Rd << 8); | |
6158 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
6159 | } | |
6160 | ||
c19d1205 ZW |
6161 | /* Parse an add or subtract instruction. We get here with inst.instruction |
6162 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
6163 | ||
6164 | static void | |
6165 | do_t_add_sub (void) | |
6166 | { | |
6167 | int Rd, Rs, Rn; | |
6168 | ||
6169 | Rd = inst.operands[0].reg; | |
6170 | Rs = (inst.operands[1].present | |
6171 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6172 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6173 | ||
6174 | if (unified_syntax) | |
6175 | { | |
0110f2b8 PB |
6176 | bfd_boolean flags; |
6177 | bfd_boolean narrow; | |
6178 | int opcode; | |
6179 | ||
6180 | flags = (inst.instruction == T_MNEM_adds | |
6181 | || inst.instruction == T_MNEM_subs); | |
6182 | if (flags) | |
6183 | narrow = (current_it_mask == 0); | |
6184 | else | |
6185 | narrow = (current_it_mask != 0); | |
c19d1205 | 6186 | if (!inst.operands[2].isreg) |
b99bd4ef | 6187 | { |
0110f2b8 PB |
6188 | opcode = 0; |
6189 | if (inst.size_req != 4) | |
6190 | { | |
6191 | int add; | |
6192 | ||
6193 | add = (inst.instruction == T_MNEM_add | |
6194 | || inst.instruction == T_MNEM_adds); | |
6195 | /* Attempt to use a narrow opcode, with relaxation if | |
6196 | appropriate. */ | |
6197 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
6198 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
6199 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
6200 | opcode = T_MNEM_add_sp; | |
6201 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
6202 | opcode = T_MNEM_add_pc; | |
6203 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
6204 | { | |
6205 | if (flags) | |
6206 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
6207 | else | |
6208 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
6209 | } | |
6210 | if (opcode) | |
6211 | { | |
6212 | inst.instruction = THUMB_OP16(opcode); | |
6213 | inst.instruction |= (Rd << 4) | Rs; | |
6214 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
6215 | if (inst.size_req != 2) | |
6216 | inst.relax = opcode; | |
6217 | } | |
6218 | else | |
6219 | constraint (inst.size_req == 2, BAD_HIREG); | |
6220 | } | |
6221 | if (inst.size_req == 4 | |
6222 | || (inst.size_req != 2 && !opcode)) | |
6223 | { | |
6224 | /* ??? Convert large immediates to addw/subw. */ | |
6225 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6226 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6227 | inst.instruction |= inst.operands[0].reg << 8; | |
6228 | inst.instruction |= inst.operands[1].reg << 16; | |
6229 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
6230 | } | |
b99bd4ef | 6231 | } |
c19d1205 ZW |
6232 | else |
6233 | { | |
6234 | Rn = inst.operands[2].reg; | |
6235 | /* See if we can do this with a 16-bit instruction. */ | |
6236 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
6237 | { | |
e27ec89e PB |
6238 | if (Rd > 7 || Rs > 7 || Rn > 7) |
6239 | narrow = FALSE; | |
6240 | ||
6241 | if (narrow) | |
c19d1205 | 6242 | { |
e27ec89e PB |
6243 | inst.instruction = ((inst.instruction == T_MNEM_adds |
6244 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
6245 | ? T_OPCODE_ADD_R3 |
6246 | : T_OPCODE_SUB_R3); | |
6247 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
6248 | return; | |
6249 | } | |
b99bd4ef | 6250 | |
c19d1205 ZW |
6251 | if (inst.instruction == T_MNEM_add) |
6252 | { | |
6253 | if (Rd == Rs) | |
6254 | { | |
6255 | inst.instruction = T_OPCODE_ADD_HI; | |
6256 | inst.instruction |= (Rd & 8) << 4; | |
6257 | inst.instruction |= (Rd & 7); | |
6258 | inst.instruction |= Rn << 3; | |
6259 | return; | |
6260 | } | |
6261 | /* ... because addition is commutative! */ | |
6262 | else if (Rd == Rn) | |
6263 | { | |
6264 | inst.instruction = T_OPCODE_ADD_HI; | |
6265 | inst.instruction |= (Rd & 8) << 4; | |
6266 | inst.instruction |= (Rd & 7); | |
6267 | inst.instruction |= Rs << 3; | |
6268 | return; | |
6269 | } | |
6270 | } | |
6271 | } | |
6272 | /* If we get here, it can't be done in 16 bits. */ | |
6273 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
6274 | _("shift must be constant")); | |
6275 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6276 | inst.instruction |= Rd << 8; | |
6277 | inst.instruction |= Rs << 16; | |
6278 | encode_thumb32_shifted_operand (2); | |
6279 | } | |
6280 | } | |
6281 | else | |
6282 | { | |
6283 | constraint (inst.instruction == T_MNEM_adds | |
6284 | || inst.instruction == T_MNEM_subs, | |
6285 | BAD_THUMB32); | |
b99bd4ef | 6286 | |
c19d1205 | 6287 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 6288 | { |
c19d1205 ZW |
6289 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
6290 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
6291 | BAD_HIREG); | |
6292 | ||
6293 | inst.instruction = (inst.instruction == T_MNEM_add | |
6294 | ? 0x0000 : 0x8000); | |
6295 | inst.instruction |= (Rd << 4) | Rs; | |
6296 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
6297 | return; |
6298 | } | |
6299 | ||
c19d1205 ZW |
6300 | Rn = inst.operands[2].reg; |
6301 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 6302 | |
c19d1205 ZW |
6303 | /* We now have Rd, Rs, and Rn set to registers. */ |
6304 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 6305 | { |
c19d1205 ZW |
6306 | /* Can't do this for SUB. */ |
6307 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
6308 | inst.instruction = T_OPCODE_ADD_HI; | |
6309 | inst.instruction |= (Rd & 8) << 4; | |
6310 | inst.instruction |= (Rd & 7); | |
6311 | if (Rs == Rd) | |
6312 | inst.instruction |= Rn << 3; | |
6313 | else if (Rn == Rd) | |
6314 | inst.instruction |= Rs << 3; | |
6315 | else | |
6316 | constraint (1, _("dest must overlap one source register")); | |
6317 | } | |
6318 | else | |
6319 | { | |
6320 | inst.instruction = (inst.instruction == T_MNEM_add | |
6321 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
6322 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 6323 | } |
b99bd4ef | 6324 | } |
b99bd4ef NC |
6325 | } |
6326 | ||
c19d1205 ZW |
6327 | static void |
6328 | do_t_adr (void) | |
6329 | { | |
0110f2b8 PB |
6330 | if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) |
6331 | { | |
6332 | /* Defer to section relaxation. */ | |
6333 | inst.relax = inst.instruction; | |
6334 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6335 | inst.instruction |= inst.operands[0].reg << 4; | |
6336 | } | |
6337 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 6338 | { |
0110f2b8 | 6339 | /* Generate a 32-bit opcode. */ |
e9f89963 PB |
6340 | inst.instruction = THUMB_OP32 (inst.instruction); |
6341 | inst.instruction |= inst.operands[0].reg << 8; | |
6342 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; | |
6343 | inst.reloc.pc_rel = 1; | |
6344 | } | |
6345 | else | |
6346 | { | |
0110f2b8 | 6347 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
6348 | inst.instruction = THUMB_OP16 (inst.instruction); |
6349 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
6350 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
6351 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 6352 | |
e9f89963 PB |
6353 | inst.instruction |= inst.operands[0].reg << 4; |
6354 | } | |
c19d1205 | 6355 | } |
b99bd4ef | 6356 | |
c19d1205 ZW |
6357 | /* Arithmetic instructions for which there is just one 16-bit |
6358 | instruction encoding, and it allows only two low registers. | |
6359 | For maximal compatibility with ARM syntax, we allow three register | |
6360 | operands even when Thumb-32 instructions are not available, as long | |
6361 | as the first two are identical. For instance, both "sbc r0,r1" and | |
6362 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 6363 | static void |
c19d1205 | 6364 | do_t_arit3 (void) |
b99bd4ef | 6365 | { |
c19d1205 | 6366 | int Rd, Rs, Rn; |
b99bd4ef | 6367 | |
c19d1205 ZW |
6368 | Rd = inst.operands[0].reg; |
6369 | Rs = (inst.operands[1].present | |
6370 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6371 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6372 | Rn = inst.operands[2].reg; | |
b99bd4ef | 6373 | |
c19d1205 | 6374 | if (unified_syntax) |
b99bd4ef | 6375 | { |
c19d1205 ZW |
6376 | if (!inst.operands[2].isreg) |
6377 | { | |
6378 | /* For an immediate, we always generate a 32-bit opcode; | |
6379 | section relaxation will shrink it later if possible. */ | |
6380 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6381 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6382 | inst.instruction |= Rd << 8; | |
6383 | inst.instruction |= Rs << 16; | |
6384 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
6385 | } | |
6386 | else | |
6387 | { | |
e27ec89e PB |
6388 | bfd_boolean narrow; |
6389 | ||
c19d1205 | 6390 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
6391 | if (THUMB_SETS_FLAGS (inst.instruction)) |
6392 | narrow = current_it_mask == 0; | |
6393 | else | |
6394 | narrow = current_it_mask != 0; | |
6395 | ||
6396 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
6397 | narrow = FALSE; | |
6398 | if (inst.operands[2].shifted) | |
6399 | narrow = FALSE; | |
6400 | if (inst.size_req == 4) | |
6401 | narrow = FALSE; | |
6402 | ||
6403 | if (narrow | |
c19d1205 ZW |
6404 | && Rd == Rs) |
6405 | { | |
6406 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6407 | inst.instruction |= Rd; | |
6408 | inst.instruction |= Rn << 3; | |
6409 | return; | |
6410 | } | |
b99bd4ef | 6411 | |
c19d1205 ZW |
6412 | /* If we get here, it can't be done in 16 bits. */ |
6413 | constraint (inst.operands[2].shifted | |
6414 | && inst.operands[2].immisreg, | |
6415 | _("shift must be constant")); | |
6416 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6417 | inst.instruction |= Rd << 8; | |
6418 | inst.instruction |= Rs << 16; | |
6419 | encode_thumb32_shifted_operand (2); | |
6420 | } | |
a737bd4d | 6421 | } |
c19d1205 | 6422 | else |
b99bd4ef | 6423 | { |
c19d1205 ZW |
6424 | /* On its face this is a lie - the instruction does set the |
6425 | flags. However, the only supported mnemonic in this mode | |
6426 | says it doesn't. */ | |
6427 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 6428 | |
c19d1205 ZW |
6429 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
6430 | _("unshifted register required")); | |
6431 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
6432 | constraint (Rd != Rs, | |
6433 | _("dest and source1 must be the same register")); | |
a737bd4d | 6434 | |
c19d1205 ZW |
6435 | inst.instruction = THUMB_OP16 (inst.instruction); |
6436 | inst.instruction |= Rd; | |
6437 | inst.instruction |= Rn << 3; | |
b99bd4ef | 6438 | } |
a737bd4d | 6439 | } |
b99bd4ef | 6440 | |
c19d1205 ZW |
6441 | /* Similarly, but for instructions where the arithmetic operation is |
6442 | commutative, so we can allow either of them to be different from | |
6443 | the destination operand in a 16-bit instruction. For instance, all | |
6444 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
6445 | accepted. */ | |
6446 | static void | |
6447 | do_t_arit3c (void) | |
a737bd4d | 6448 | { |
c19d1205 | 6449 | int Rd, Rs, Rn; |
b99bd4ef | 6450 | |
c19d1205 ZW |
6451 | Rd = inst.operands[0].reg; |
6452 | Rs = (inst.operands[1].present | |
6453 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6454 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6455 | Rn = inst.operands[2].reg; | |
a737bd4d | 6456 | |
c19d1205 | 6457 | if (unified_syntax) |
a737bd4d | 6458 | { |
c19d1205 | 6459 | if (!inst.operands[2].isreg) |
b99bd4ef | 6460 | { |
c19d1205 ZW |
6461 | /* For an immediate, we always generate a 32-bit opcode; |
6462 | section relaxation will shrink it later if possible. */ | |
6463 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6464 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6465 | inst.instruction |= Rd << 8; | |
6466 | inst.instruction |= Rs << 16; | |
6467 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 6468 | } |
c19d1205 | 6469 | else |
a737bd4d | 6470 | { |
e27ec89e PB |
6471 | bfd_boolean narrow; |
6472 | ||
c19d1205 | 6473 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
6474 | if (THUMB_SETS_FLAGS (inst.instruction)) |
6475 | narrow = current_it_mask == 0; | |
6476 | else | |
6477 | narrow = current_it_mask != 0; | |
6478 | ||
6479 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
6480 | narrow = FALSE; | |
6481 | if (inst.operands[2].shifted) | |
6482 | narrow = FALSE; | |
6483 | if (inst.size_req == 4) | |
6484 | narrow = FALSE; | |
6485 | ||
6486 | if (narrow) | |
a737bd4d | 6487 | { |
c19d1205 | 6488 | if (Rd == Rs) |
a737bd4d | 6489 | { |
c19d1205 ZW |
6490 | inst.instruction = THUMB_OP16 (inst.instruction); |
6491 | inst.instruction |= Rd; | |
6492 | inst.instruction |= Rn << 3; | |
6493 | return; | |
a737bd4d | 6494 | } |
c19d1205 | 6495 | if (Rd == Rn) |
a737bd4d | 6496 | { |
c19d1205 ZW |
6497 | inst.instruction = THUMB_OP16 (inst.instruction); |
6498 | inst.instruction |= Rd; | |
6499 | inst.instruction |= Rs << 3; | |
6500 | return; | |
a737bd4d NC |
6501 | } |
6502 | } | |
c19d1205 ZW |
6503 | |
6504 | /* If we get here, it can't be done in 16 bits. */ | |
6505 | constraint (inst.operands[2].shifted | |
6506 | && inst.operands[2].immisreg, | |
6507 | _("shift must be constant")); | |
6508 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6509 | inst.instruction |= Rd << 8; | |
6510 | inst.instruction |= Rs << 16; | |
6511 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 6512 | } |
b99bd4ef | 6513 | } |
c19d1205 ZW |
6514 | else |
6515 | { | |
6516 | /* On its face this is a lie - the instruction does set the | |
6517 | flags. However, the only supported mnemonic in this mode | |
6518 | says it doesn't. */ | |
6519 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 6520 | |
c19d1205 ZW |
6521 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
6522 | _("unshifted register required")); | |
6523 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
6524 | ||
6525 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6526 | inst.instruction |= Rd; | |
6527 | ||
6528 | if (Rd == Rs) | |
6529 | inst.instruction |= Rn << 3; | |
6530 | else if (Rd == Rn) | |
6531 | inst.instruction |= Rs << 3; | |
6532 | else | |
6533 | constraint (1, _("dest must overlap one source register")); | |
6534 | } | |
a737bd4d NC |
6535 | } |
6536 | ||
62b3e311 PB |
6537 | static void |
6538 | do_t_barrier (void) | |
6539 | { | |
6540 | if (inst.operands[0].present) | |
6541 | { | |
6542 | constraint ((inst.instruction & 0xf0) != 0x40 | |
6543 | && inst.operands[0].imm != 0xf, | |
6544 | "bad barrier type"); | |
6545 | inst.instruction |= inst.operands[0].imm; | |
6546 | } | |
6547 | else | |
6548 | inst.instruction |= 0xf; | |
6549 | } | |
6550 | ||
c19d1205 ZW |
6551 | static void |
6552 | do_t_bfc (void) | |
a737bd4d | 6553 | { |
c19d1205 ZW |
6554 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
6555 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6556 | /* The instruction encoding stores the LSB and MSB, | |
6557 | not the LSB and width. */ | |
6558 | inst.instruction |= inst.operands[0].reg << 8; | |
6559 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; | |
6560 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
6561 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
6562 | } |
6563 | ||
c19d1205 ZW |
6564 | static void |
6565 | do_t_bfi (void) | |
b99bd4ef | 6566 | { |
c19d1205 | 6567 | unsigned int msb; |
b99bd4ef | 6568 | |
c19d1205 ZW |
6569 | /* #0 in second position is alternative syntax for bfc, which is |
6570 | the same instruction but with REG_PC in the Rm field. */ | |
6571 | if (!inst.operands[1].isreg) | |
6572 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 6573 | |
c19d1205 ZW |
6574 | msb = inst.operands[2].imm + inst.operands[3].imm; |
6575 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6576 | /* The instruction encoding stores the LSB and MSB, | |
6577 | not the LSB and width. */ | |
6578 | inst.instruction |= inst.operands[0].reg << 8; | |
6579 | inst.instruction |= inst.operands[1].reg << 16; | |
6580 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
6581 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
6582 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
6583 | } |
6584 | ||
c19d1205 ZW |
6585 | static void |
6586 | do_t_bfx (void) | |
b99bd4ef | 6587 | { |
c19d1205 ZW |
6588 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
6589 | _("bit-field extends past end of register")); | |
6590 | inst.instruction |= inst.operands[0].reg << 8; | |
6591 | inst.instruction |= inst.operands[1].reg << 16; | |
6592 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
6593 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
6594 | inst.instruction |= inst.operands[3].imm - 1; | |
6595 | } | |
b99bd4ef | 6596 | |
c19d1205 ZW |
6597 | /* ARM V5 Thumb BLX (argument parse) |
6598 | BLX <target_addr> which is BLX(1) | |
6599 | BLX <Rm> which is BLX(2) | |
6600 | Unfortunately, there are two different opcodes for this mnemonic. | |
6601 | So, the insns[].value is not used, and the code here zaps values | |
6602 | into inst.instruction. | |
b99bd4ef | 6603 | |
c19d1205 ZW |
6604 | ??? How to take advantage of the additional two bits of displacement |
6605 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 6606 | |
c19d1205 ZW |
6607 | static void |
6608 | do_t_blx (void) | |
6609 | { | |
dfa9f0d5 | 6610 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
c19d1205 ZW |
6611 | if (inst.operands[0].isreg) |
6612 | /* We have a register, so this is BLX(2). */ | |
6613 | inst.instruction |= inst.operands[0].reg << 3; | |
b99bd4ef NC |
6614 | else |
6615 | { | |
c19d1205 | 6616 | /* No register. This must be BLX(1). */ |
2fc8bdac | 6617 | inst.instruction = 0xf000e800; |
39b41c9c PB |
6618 | #ifdef OBJ_ELF |
6619 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
6620 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
6621 | else | |
6622 | #endif | |
6623 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; | |
c19d1205 | 6624 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
6625 | } |
6626 | } | |
6627 | ||
c19d1205 ZW |
6628 | static void |
6629 | do_t_branch (void) | |
b99bd4ef | 6630 | { |
0110f2b8 | 6631 | int opcode; |
dfa9f0d5 PB |
6632 | int cond; |
6633 | ||
6634 | if (current_it_mask) | |
6635 | { | |
6636 | /* Conditional branches inside IT blocks are encoded as unconditional | |
6637 | branches. */ | |
6638 | cond = COND_ALWAYS; | |
6639 | /* A branch must be the last instruction in an IT block. */ | |
6640 | constraint (current_it_mask != 0x10, BAD_BRANCH); | |
6641 | } | |
6642 | else | |
6643 | cond = inst.cond; | |
6644 | ||
6645 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
6646 | opcode = T_MNEM_bcond; |
6647 | else | |
6648 | opcode = inst.instruction; | |
6649 | ||
6650 | if (unified_syntax && inst.size_req == 4) | |
c19d1205 | 6651 | { |
0110f2b8 | 6652 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 6653 | if (cond == COND_ALWAYS) |
0110f2b8 | 6654 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
6655 | else |
6656 | { | |
dfa9f0d5 PB |
6657 | assert (cond != 0xF); |
6658 | inst.instruction |= cond << 22; | |
c19d1205 ZW |
6659 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
6660 | } | |
6661 | } | |
b99bd4ef NC |
6662 | else |
6663 | { | |
0110f2b8 | 6664 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 6665 | if (cond == COND_ALWAYS) |
c19d1205 ZW |
6666 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; |
6667 | else | |
b99bd4ef | 6668 | { |
dfa9f0d5 | 6669 | inst.instruction |= cond << 8; |
c19d1205 | 6670 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 6671 | } |
0110f2b8 PB |
6672 | /* Allow section relaxation. */ |
6673 | if (unified_syntax && inst.size_req != 2) | |
6674 | inst.relax = opcode; | |
b99bd4ef | 6675 | } |
c19d1205 ZW |
6676 | |
6677 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
6678 | } |
6679 | ||
6680 | static void | |
c19d1205 | 6681 | do_t_bkpt (void) |
b99bd4ef | 6682 | { |
dfa9f0d5 PB |
6683 | constraint (inst.cond != COND_ALWAYS, |
6684 | _("instruction is always unconditional")); | |
c19d1205 | 6685 | if (inst.operands[0].present) |
b99bd4ef | 6686 | { |
c19d1205 ZW |
6687 | constraint (inst.operands[0].imm > 255, |
6688 | _("immediate value out of range")); | |
6689 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 6690 | } |
b99bd4ef NC |
6691 | } |
6692 | ||
6693 | static void | |
c19d1205 | 6694 | do_t_branch23 (void) |
b99bd4ef | 6695 | { |
dfa9f0d5 | 6696 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
c19d1205 | 6697 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
6698 | inst.reloc.pc_rel = 1; |
6699 | ||
c19d1205 ZW |
6700 | /* If the destination of the branch is a defined symbol which does not have |
6701 | the THUMB_FUNC attribute, then we must be calling a function which has | |
6702 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
6703 | function and change the branch to refer to that function instead. */ | |
6704 | if ( inst.reloc.exp.X_op == O_symbol | |
6705 | && inst.reloc.exp.X_add_symbol != NULL | |
6706 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
6707 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
6708 | inst.reloc.exp.X_add_symbol = | |
6709 | find_real_start (inst.reloc.exp.X_add_symbol); | |
90e4755a RE |
6710 | } |
6711 | ||
6712 | static void | |
c19d1205 | 6713 | do_t_bx (void) |
90e4755a | 6714 | { |
dfa9f0d5 | 6715 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
c19d1205 ZW |
6716 | inst.instruction |= inst.operands[0].reg << 3; |
6717 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
6718 | should cause the alignment to be checked once it is known. This is | |
6719 | because BX PC only works if the instruction is word aligned. */ | |
6720 | } | |
90e4755a | 6721 | |
c19d1205 ZW |
6722 | static void |
6723 | do_t_bxj (void) | |
6724 | { | |
dfa9f0d5 | 6725 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
c19d1205 ZW |
6726 | if (inst.operands[0].reg == REG_PC) |
6727 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
90e4755a | 6728 | |
c19d1205 | 6729 | inst.instruction |= inst.operands[0].reg << 16; |
90e4755a RE |
6730 | } |
6731 | ||
6732 | static void | |
c19d1205 | 6733 | do_t_clz (void) |
90e4755a | 6734 | { |
c19d1205 ZW |
6735 | inst.instruction |= inst.operands[0].reg << 8; |
6736 | inst.instruction |= inst.operands[1].reg << 16; | |
6737 | inst.instruction |= inst.operands[1].reg; | |
6738 | } | |
90e4755a | 6739 | |
dfa9f0d5 PB |
6740 | static void |
6741 | do_t_cps (void) | |
6742 | { | |
6743 | constraint (current_it_mask, BAD_NOT_IT); | |
6744 | inst.instruction |= inst.operands[0].imm; | |
6745 | } | |
6746 | ||
c19d1205 ZW |
6747 | static void |
6748 | do_t_cpsi (void) | |
6749 | { | |
dfa9f0d5 | 6750 | constraint (current_it_mask, BAD_NOT_IT); |
c19d1205 | 6751 | if (unified_syntax |
62b3e311 PB |
6752 | && (inst.operands[1].present || inst.size_req == 4) |
6753 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 6754 | { |
c19d1205 ZW |
6755 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
6756 | inst.instruction = 0xf3af8000; | |
6757 | inst.instruction |= imod << 9; | |
6758 | inst.instruction |= inst.operands[0].imm << 5; | |
6759 | if (inst.operands[1].present) | |
6760 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 6761 | } |
c19d1205 | 6762 | else |
90e4755a | 6763 | { |
62b3e311 PB |
6764 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
6765 | && (inst.operands[0].imm & 4), | |
6766 | _("selected processor does not support 'A' form " | |
6767 | "of this instruction")); | |
6768 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
6769 | _("Thumb does not support the 2-argument " |
6770 | "form of this instruction")); | |
6771 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 6772 | } |
90e4755a RE |
6773 | } |
6774 | ||
c19d1205 ZW |
6775 | /* THUMB CPY instruction (argument parse). */ |
6776 | ||
90e4755a | 6777 | static void |
c19d1205 | 6778 | do_t_cpy (void) |
90e4755a | 6779 | { |
c19d1205 | 6780 | if (inst.size_req == 4) |
90e4755a | 6781 | { |
c19d1205 ZW |
6782 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
6783 | inst.instruction |= inst.operands[0].reg << 8; | |
6784 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 6785 | } |
c19d1205 | 6786 | else |
90e4755a | 6787 | { |
c19d1205 ZW |
6788 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
6789 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
6790 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 6791 | } |
90e4755a RE |
6792 | } |
6793 | ||
90e4755a | 6794 | static void |
c19d1205 | 6795 | do_t_czb (void) |
90e4755a | 6796 | { |
dfa9f0d5 | 6797 | constraint (current_it_mask, BAD_NOT_IT); |
c19d1205 ZW |
6798 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
6799 | inst.instruction |= inst.operands[0].reg; | |
6800 | inst.reloc.pc_rel = 1; | |
6801 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
6802 | } | |
90e4755a | 6803 | |
62b3e311 PB |
6804 | static void |
6805 | do_t_dbg (void) | |
6806 | { | |
6807 | inst.instruction |= inst.operands[0].imm; | |
6808 | } | |
6809 | ||
6810 | static void | |
6811 | do_t_div (void) | |
6812 | { | |
6813 | if (!inst.operands[1].present) | |
6814 | inst.operands[1].reg = inst.operands[0].reg; | |
6815 | inst.instruction |= inst.operands[0].reg << 8; | |
6816 | inst.instruction |= inst.operands[1].reg << 16; | |
6817 | inst.instruction |= inst.operands[2].reg; | |
6818 | } | |
6819 | ||
c19d1205 ZW |
6820 | static void |
6821 | do_t_hint (void) | |
6822 | { | |
6823 | if (unified_syntax && inst.size_req == 4) | |
6824 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6825 | else | |
6826 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6827 | } | |
90e4755a | 6828 | |
c19d1205 ZW |
6829 | static void |
6830 | do_t_it (void) | |
6831 | { | |
6832 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 6833 | |
dfa9f0d5 | 6834 | constraint (current_it_mask, BAD_NOT_IT); |
e27ec89e PB |
6835 | current_it_mask = (inst.instruction & 0xf) | 0x10; |
6836 | current_cc = cond; | |
6837 | ||
6838 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 6839 | if ((cond & 0x1) == 0x0) |
90e4755a | 6840 | { |
c19d1205 | 6841 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 6842 | |
c19d1205 ZW |
6843 | if ((mask & 0x7) == 0) |
6844 | /* no conversion needed */; | |
6845 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
6846 | mask ^= 0x8; |
6847 | else if ((mask & 0x1) == 0) | |
6848 | mask ^= 0xC; | |
c19d1205 | 6849 | else |
e27ec89e | 6850 | mask ^= 0xE; |
90e4755a | 6851 | |
e27ec89e PB |
6852 | inst.instruction &= 0xfff0; |
6853 | inst.instruction |= mask; | |
c19d1205 | 6854 | } |
90e4755a | 6855 | |
c19d1205 ZW |
6856 | inst.instruction |= cond << 4; |
6857 | } | |
90e4755a | 6858 | |
c19d1205 ZW |
6859 | static void |
6860 | do_t_ldmstm (void) | |
6861 | { | |
6862 | /* This really doesn't seem worth it. */ | |
6863 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
6864 | _("expression too complex")); | |
6865 | constraint (inst.operands[1].writeback, | |
6866 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 6867 | |
c19d1205 ZW |
6868 | if (unified_syntax) |
6869 | { | |
6870 | /* See if we can use a 16-bit instruction. */ | |
6871 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
6872 | && inst.size_req != 4 | |
6873 | && inst.operands[0].reg <= 7 | |
6874 | && !(inst.operands[1].imm & ~0xff) | |
6875 | && (inst.instruction == T_MNEM_stmia | |
6876 | ? inst.operands[0].writeback | |
6877 | : (inst.operands[0].writeback | |
6878 | == !(inst.operands[1].imm & (1 << inst.operands[0].reg))))) | |
90e4755a | 6879 | { |
c19d1205 ZW |
6880 | if (inst.instruction == T_MNEM_stmia |
6881 | && (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6882 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
6883 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6884 | inst.operands[0].reg); | |
90e4755a | 6885 | |
c19d1205 ZW |
6886 | inst.instruction = THUMB_OP16 (inst.instruction); |
6887 | inst.instruction |= inst.operands[0].reg << 8; | |
6888 | inst.instruction |= inst.operands[1].imm; | |
6889 | } | |
6890 | else | |
6891 | { | |
6892 | if (inst.operands[1].imm & (1 << 13)) | |
6893 | as_warn (_("SP should not be in register list")); | |
6894 | if (inst.instruction == T_MNEM_stmia) | |
90e4755a | 6895 | { |
c19d1205 ZW |
6896 | if (inst.operands[1].imm & (1 << 15)) |
6897 | as_warn (_("PC should not be in register list")); | |
6898 | if (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6899 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6900 | inst.operands[0].reg); | |
90e4755a RE |
6901 | } |
6902 | else | |
6903 | { | |
c19d1205 ZW |
6904 | if (inst.operands[1].imm & (1 << 14) |
6905 | && inst.operands[1].imm & (1 << 15)) | |
6906 | as_warn (_("LR and PC should not both be in register list")); | |
6907 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6908 | && inst.operands[0].writeback) | |
6909 | as_warn (_("base register should not be in register list " | |
6910 | "when written back")); | |
90e4755a | 6911 | } |
c19d1205 ZW |
6912 | if (inst.instruction < 0xffff) |
6913 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6914 | inst.instruction |= inst.operands[0].reg << 16; | |
6915 | inst.instruction |= inst.operands[1].imm; | |
6916 | if (inst.operands[0].writeback) | |
6917 | inst.instruction |= WRITE_BACK; | |
90e4755a RE |
6918 | } |
6919 | } | |
c19d1205 | 6920 | else |
90e4755a | 6921 | { |
c19d1205 ZW |
6922 | constraint (inst.operands[0].reg > 7 |
6923 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
6924 | if (inst.instruction == T_MNEM_stmia) | |
f03698e6 | 6925 | { |
c19d1205 ZW |
6926 | if (!inst.operands[0].writeback) |
6927 | as_warn (_("this instruction will write back the base register")); | |
6928 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6929 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
6930 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6931 | inst.operands[0].reg); | |
f03698e6 | 6932 | } |
c19d1205 | 6933 | else |
90e4755a | 6934 | { |
c19d1205 ZW |
6935 | if (!inst.operands[0].writeback |
6936 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
6937 | as_warn (_("this instruction will write back the base register")); | |
6938 | else if (inst.operands[0].writeback | |
6939 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
6940 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
6941 | } |
6942 | ||
c19d1205 ZW |
6943 | inst.instruction = THUMB_OP16 (inst.instruction); |
6944 | inst.instruction |= inst.operands[0].reg << 8; | |
6945 | inst.instruction |= inst.operands[1].imm; | |
6946 | } | |
6947 | } | |
e28cd48c | 6948 | |
c19d1205 ZW |
6949 | static void |
6950 | do_t_ldrex (void) | |
6951 | { | |
6952 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
6953 | || inst.operands[1].postind || inst.operands[1].writeback | |
6954 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
6955 | || inst.operands[1].negative, | |
01cfc07f | 6956 | BAD_ADDR_MODE); |
e28cd48c | 6957 | |
c19d1205 ZW |
6958 | inst.instruction |= inst.operands[0].reg << 12; |
6959 | inst.instruction |= inst.operands[1].reg << 16; | |
6960 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
6961 | } | |
e28cd48c | 6962 | |
c19d1205 ZW |
6963 | static void |
6964 | do_t_ldrexd (void) | |
6965 | { | |
6966 | if (!inst.operands[1].present) | |
1cac9012 | 6967 | { |
c19d1205 ZW |
6968 | constraint (inst.operands[0].reg == REG_LR, |
6969 | _("r14 not allowed as first register " | |
6970 | "when second register is omitted")); | |
6971 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 6972 | } |
c19d1205 ZW |
6973 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
6974 | BAD_OVERLAP); | |
b99bd4ef | 6975 | |
c19d1205 ZW |
6976 | inst.instruction |= inst.operands[0].reg << 12; |
6977 | inst.instruction |= inst.operands[1].reg << 8; | |
6978 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
6979 | } |
6980 | ||
6981 | static void | |
c19d1205 | 6982 | do_t_ldst (void) |
b99bd4ef | 6983 | { |
0110f2b8 PB |
6984 | unsigned long opcode; |
6985 | int Rn; | |
6986 | ||
6987 | opcode = inst.instruction; | |
c19d1205 | 6988 | if (unified_syntax) |
b99bd4ef | 6989 | { |
53365c0d PB |
6990 | if (!inst.operands[1].isreg) |
6991 | { | |
6992 | if (opcode <= 0xffff) | |
6993 | inst.instruction = THUMB_OP32 (opcode); | |
6994 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
6995 | return; | |
6996 | } | |
0110f2b8 PB |
6997 | if (inst.operands[1].isreg |
6998 | && !inst.operands[1].writeback | |
c19d1205 ZW |
6999 | && !inst.operands[1].shifted && !inst.operands[1].postind |
7000 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
7001 | && opcode <= 0xffff |
7002 | && inst.size_req != 4) | |
c19d1205 | 7003 | { |
0110f2b8 PB |
7004 | /* Insn may have a 16-bit form. */ |
7005 | Rn = inst.operands[1].reg; | |
7006 | if (inst.operands[1].immisreg) | |
7007 | { | |
7008 | inst.instruction = THUMB_OP16 (opcode); | |
7009 | /* [Rn, Ri] */ | |
7010 | if (Rn <= 7 && inst.operands[1].imm <= 7) | |
7011 | goto op16; | |
7012 | } | |
7013 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
7014 | && opcode != T_MNEM_ldrsb) | |
7015 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
7016 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
7017 | { | |
7018 | /* [Rn, #const] */ | |
7019 | if (Rn > 7) | |
7020 | { | |
7021 | if (Rn == REG_PC) | |
7022 | { | |
7023 | if (inst.reloc.pc_rel) | |
7024 | opcode = T_MNEM_ldr_pc2; | |
7025 | else | |
7026 | opcode = T_MNEM_ldr_pc; | |
7027 | } | |
7028 | else | |
7029 | { | |
7030 | if (opcode == T_MNEM_ldr) | |
7031 | opcode = T_MNEM_ldr_sp; | |
7032 | else | |
7033 | opcode = T_MNEM_str_sp; | |
7034 | } | |
7035 | inst.instruction = inst.operands[0].reg << 8; | |
7036 | } | |
7037 | else | |
7038 | { | |
7039 | inst.instruction = inst.operands[0].reg; | |
7040 | inst.instruction |= inst.operands[1].reg << 3; | |
7041 | } | |
7042 | inst.instruction |= THUMB_OP16 (opcode); | |
7043 | if (inst.size_req == 2) | |
7044 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
7045 | else | |
7046 | inst.relax = opcode; | |
7047 | return; | |
7048 | } | |
c19d1205 | 7049 | } |
0110f2b8 PB |
7050 | /* Definitely a 32-bit variant. */ |
7051 | inst.instruction = THUMB_OP32 (opcode); | |
c19d1205 ZW |
7052 | inst.instruction |= inst.operands[0].reg << 12; |
7053 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
7054 | return; |
7055 | } | |
7056 | ||
c19d1205 ZW |
7057 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
7058 | ||
7059 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 7060 | { |
c19d1205 ZW |
7061 | /* Only [Rn,Rm] is acceptable. */ |
7062 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
7063 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
7064 | || inst.operands[1].postind || inst.operands[1].shifted | |
7065 | || inst.operands[1].negative, | |
7066 | _("Thumb does not support this addressing mode")); | |
7067 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7068 | goto op16; | |
b99bd4ef | 7069 | } |
c19d1205 ZW |
7070 | |
7071 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7072 | if (!inst.operands[1].isreg) | |
7073 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
7074 | return; | |
b99bd4ef | 7075 | |
c19d1205 ZW |
7076 | constraint (!inst.operands[1].preind |
7077 | || inst.operands[1].shifted | |
7078 | || inst.operands[1].writeback, | |
7079 | _("Thumb does not support this addressing mode")); | |
7080 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 7081 | { |
c19d1205 ZW |
7082 | constraint (inst.instruction & 0x0600, |
7083 | _("byte or halfword not valid for base register")); | |
7084 | constraint (inst.operands[1].reg == REG_PC | |
7085 | && !(inst.instruction & THUMB_LOAD_BIT), | |
7086 | _("r15 based store not allowed")); | |
7087 | constraint (inst.operands[1].immisreg, | |
7088 | _("invalid base register for register offset")); | |
b99bd4ef | 7089 | |
c19d1205 ZW |
7090 | if (inst.operands[1].reg == REG_PC) |
7091 | inst.instruction = T_OPCODE_LDR_PC; | |
7092 | else if (inst.instruction & THUMB_LOAD_BIT) | |
7093 | inst.instruction = T_OPCODE_LDR_SP; | |
7094 | else | |
7095 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 7096 | |
c19d1205 ZW |
7097 | inst.instruction |= inst.operands[0].reg << 8; |
7098 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
7099 | return; | |
7100 | } | |
90e4755a | 7101 | |
c19d1205 ZW |
7102 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
7103 | if (!inst.operands[1].immisreg) | |
7104 | { | |
7105 | /* Immediate offset. */ | |
7106 | inst.instruction |= inst.operands[0].reg; | |
7107 | inst.instruction |= inst.operands[1].reg << 3; | |
7108 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
7109 | return; | |
7110 | } | |
90e4755a | 7111 | |
c19d1205 ZW |
7112 | /* Register offset. */ |
7113 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
7114 | constraint (inst.operands[1].negative, | |
7115 | _("Thumb does not support this addressing mode")); | |
90e4755a | 7116 | |
c19d1205 ZW |
7117 | op16: |
7118 | switch (inst.instruction) | |
7119 | { | |
7120 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
7121 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
7122 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
7123 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
7124 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
7125 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
7126 | case 0x5600 /* ldrsb */: | |
7127 | case 0x5e00 /* ldrsh */: break; | |
7128 | default: abort (); | |
7129 | } | |
90e4755a | 7130 | |
c19d1205 ZW |
7131 | inst.instruction |= inst.operands[0].reg; |
7132 | inst.instruction |= inst.operands[1].reg << 3; | |
7133 | inst.instruction |= inst.operands[1].imm << 6; | |
7134 | } | |
90e4755a | 7135 | |
c19d1205 ZW |
7136 | static void |
7137 | do_t_ldstd (void) | |
7138 | { | |
7139 | if (!inst.operands[1].present) | |
b99bd4ef | 7140 | { |
c19d1205 ZW |
7141 | inst.operands[1].reg = inst.operands[0].reg + 1; |
7142 | constraint (inst.operands[0].reg == REG_LR, | |
7143 | _("r14 not allowed here")); | |
b99bd4ef | 7144 | } |
c19d1205 ZW |
7145 | inst.instruction |= inst.operands[0].reg << 12; |
7146 | inst.instruction |= inst.operands[1].reg << 8; | |
7147 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
7148 | ||
b99bd4ef NC |
7149 | } |
7150 | ||
c19d1205 ZW |
7151 | static void |
7152 | do_t_ldstt (void) | |
7153 | { | |
7154 | inst.instruction |= inst.operands[0].reg << 12; | |
7155 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
7156 | } | |
a737bd4d | 7157 | |
b99bd4ef | 7158 | static void |
c19d1205 | 7159 | do_t_mla (void) |
b99bd4ef | 7160 | { |
c19d1205 ZW |
7161 | inst.instruction |= inst.operands[0].reg << 8; |
7162 | inst.instruction |= inst.operands[1].reg << 16; | |
7163 | inst.instruction |= inst.operands[2].reg; | |
7164 | inst.instruction |= inst.operands[3].reg << 12; | |
7165 | } | |
b99bd4ef | 7166 | |
c19d1205 ZW |
7167 | static void |
7168 | do_t_mlal (void) | |
7169 | { | |
7170 | inst.instruction |= inst.operands[0].reg << 12; | |
7171 | inst.instruction |= inst.operands[1].reg << 8; | |
7172 | inst.instruction |= inst.operands[2].reg << 16; | |
7173 | inst.instruction |= inst.operands[3].reg; | |
7174 | } | |
b99bd4ef | 7175 | |
c19d1205 ZW |
7176 | static void |
7177 | do_t_mov_cmp (void) | |
7178 | { | |
7179 | if (unified_syntax) | |
b99bd4ef | 7180 | { |
c19d1205 ZW |
7181 | int r0off = (inst.instruction == T_MNEM_mov |
7182 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 7183 | unsigned long opcode; |
3d388997 PB |
7184 | bfd_boolean narrow; |
7185 | bfd_boolean low_regs; | |
7186 | ||
7187 | low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); | |
0110f2b8 | 7188 | opcode = inst.instruction; |
3d388997 | 7189 | if (current_it_mask) |
0110f2b8 | 7190 | narrow = opcode != T_MNEM_movs; |
3d388997 | 7191 | else |
0110f2b8 | 7192 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
7193 | if (inst.size_req == 4 |
7194 | || inst.operands[1].shifted) | |
7195 | narrow = FALSE; | |
7196 | ||
c19d1205 ZW |
7197 | if (!inst.operands[1].isreg) |
7198 | { | |
0110f2b8 PB |
7199 | /* Immediate operand. */ |
7200 | if (current_it_mask == 0 && opcode == T_MNEM_mov) | |
7201 | narrow = 0; | |
7202 | if (low_regs && narrow) | |
7203 | { | |
7204 | inst.instruction = THUMB_OP16 (opcode); | |
7205 | inst.instruction |= inst.operands[0].reg << 8; | |
7206 | if (inst.size_req == 2) | |
7207 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
7208 | else | |
7209 | inst.relax = opcode; | |
7210 | } | |
7211 | else | |
7212 | { | |
7213 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7214 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
7215 | inst.instruction |= inst.operands[0].reg << r0off; | |
7216 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
7217 | } | |
c19d1205 | 7218 | } |
3d388997 | 7219 | else if (!narrow) |
c19d1205 ZW |
7220 | { |
7221 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7222 | inst.instruction |= inst.operands[0].reg << r0off; | |
7223 | encode_thumb32_shifted_operand (1); | |
7224 | } | |
7225 | else | |
7226 | switch (inst.instruction) | |
7227 | { | |
7228 | case T_MNEM_mov: | |
7229 | inst.instruction = T_OPCODE_MOV_HR; | |
7230 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
7231 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
7232 | inst.instruction |= inst.operands[1].reg << 3; | |
7233 | break; | |
b99bd4ef | 7234 | |
c19d1205 ZW |
7235 | case T_MNEM_movs: |
7236 | /* We know we have low registers at this point. | |
7237 | Generate ADD Rd, Rs, #0. */ | |
7238 | inst.instruction = T_OPCODE_ADD_I3; | |
7239 | inst.instruction |= inst.operands[0].reg; | |
7240 | inst.instruction |= inst.operands[1].reg << 3; | |
7241 | break; | |
7242 | ||
7243 | case T_MNEM_cmp: | |
3d388997 | 7244 | if (low_regs) |
c19d1205 ZW |
7245 | { |
7246 | inst.instruction = T_OPCODE_CMP_LR; | |
7247 | inst.instruction |= inst.operands[0].reg; | |
7248 | inst.instruction |= inst.operands[1].reg << 3; | |
7249 | } | |
7250 | else | |
7251 | { | |
7252 | inst.instruction = T_OPCODE_CMP_HR; | |
7253 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
7254 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
7255 | inst.instruction |= inst.operands[1].reg << 3; | |
7256 | } | |
7257 | break; | |
7258 | } | |
b99bd4ef NC |
7259 | return; |
7260 | } | |
7261 | ||
c19d1205 ZW |
7262 | inst.instruction = THUMB_OP16 (inst.instruction); |
7263 | if (inst.operands[1].isreg) | |
b99bd4ef | 7264 | { |
c19d1205 | 7265 | if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) |
b99bd4ef | 7266 | { |
c19d1205 ZW |
7267 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
7268 | since a MOV instruction produces unpredictable results. */ | |
7269 | if (inst.instruction == T_OPCODE_MOV_I8) | |
7270 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 7271 | else |
c19d1205 | 7272 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 7273 | |
c19d1205 ZW |
7274 | inst.instruction |= inst.operands[0].reg; |
7275 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7276 | } |
7277 | else | |
7278 | { | |
c19d1205 ZW |
7279 | if (inst.instruction == T_OPCODE_MOV_I8) |
7280 | inst.instruction = T_OPCODE_MOV_HR; | |
7281 | else | |
7282 | inst.instruction = T_OPCODE_CMP_HR; | |
7283 | do_t_cpy (); | |
b99bd4ef NC |
7284 | } |
7285 | } | |
c19d1205 | 7286 | else |
b99bd4ef | 7287 | { |
c19d1205 ZW |
7288 | constraint (inst.operands[0].reg > 7, |
7289 | _("only lo regs allowed with immediate")); | |
7290 | inst.instruction |= inst.operands[0].reg << 8; | |
7291 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
7292 | } | |
7293 | } | |
b99bd4ef | 7294 | |
c19d1205 ZW |
7295 | static void |
7296 | do_t_mov16 (void) | |
7297 | { | |
7298 | inst.instruction |= inst.operands[0].reg << 8; | |
7299 | inst.instruction |= (inst.operands[1].imm & 0xf000) << 4; | |
7300 | inst.instruction |= (inst.operands[1].imm & 0x0800) << 15; | |
7301 | inst.instruction |= (inst.operands[1].imm & 0x0700) << 4; | |
7302 | inst.instruction |= (inst.operands[1].imm & 0x00ff); | |
7303 | } | |
b99bd4ef | 7304 | |
c19d1205 ZW |
7305 | static void |
7306 | do_t_mvn_tst (void) | |
7307 | { | |
7308 | if (unified_syntax) | |
7309 | { | |
7310 | int r0off = (inst.instruction == T_MNEM_mvn | |
7311 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
7312 | bfd_boolean narrow; |
7313 | ||
7314 | if (inst.size_req == 4 | |
7315 | || inst.instruction > 0xffff | |
7316 | || inst.operands[1].shifted | |
7317 | || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7318 | narrow = FALSE; | |
7319 | else if (inst.instruction == T_MNEM_cmn) | |
7320 | narrow = TRUE; | |
7321 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
7322 | narrow = (current_it_mask == 0); | |
7323 | else | |
7324 | narrow = (current_it_mask != 0); | |
7325 | ||
c19d1205 | 7326 | if (!inst.operands[1].isreg) |
b99bd4ef | 7327 | { |
c19d1205 ZW |
7328 | /* For an immediate, we always generate a 32-bit opcode; |
7329 | section relaxation will shrink it later if possible. */ | |
7330 | if (inst.instruction < 0xffff) | |
7331 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7332 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
7333 | inst.instruction |= inst.operands[0].reg << r0off; | |
7334 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 7335 | } |
c19d1205 | 7336 | else |
b99bd4ef | 7337 | { |
c19d1205 | 7338 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 7339 | if (narrow) |
b99bd4ef | 7340 | { |
c19d1205 ZW |
7341 | inst.instruction = THUMB_OP16 (inst.instruction); |
7342 | inst.instruction |= inst.operands[0].reg; | |
7343 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7344 | } |
c19d1205 | 7345 | else |
b99bd4ef | 7346 | { |
c19d1205 ZW |
7347 | constraint (inst.operands[1].shifted |
7348 | && inst.operands[1].immisreg, | |
7349 | _("shift must be constant")); | |
7350 | if (inst.instruction < 0xffff) | |
7351 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7352 | inst.instruction |= inst.operands[0].reg << r0off; | |
7353 | encode_thumb32_shifted_operand (1); | |
b99bd4ef | 7354 | } |
b99bd4ef NC |
7355 | } |
7356 | } | |
7357 | else | |
7358 | { | |
c19d1205 ZW |
7359 | constraint (inst.instruction > 0xffff |
7360 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
7361 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
7362 | _("unshifted register required")); | |
7363 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
7364 | BAD_HIREG); | |
b99bd4ef | 7365 | |
c19d1205 ZW |
7366 | inst.instruction = THUMB_OP16 (inst.instruction); |
7367 | inst.instruction |= inst.operands[0].reg; | |
7368 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7369 | } |
b99bd4ef NC |
7370 | } |
7371 | ||
b05fe5cf | 7372 | static void |
c19d1205 | 7373 | do_t_mrs (void) |
b05fe5cf | 7374 | { |
62b3e311 PB |
7375 | int flags; |
7376 | flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); | |
7377 | if (flags == 0) | |
7378 | { | |
7379 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), | |
7380 | _("selected processor does not support " | |
7381 | "requested special purpose register")); | |
7382 | } | |
7383 | else | |
7384 | { | |
7385 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
7386 | _("selected processor does not support " | |
7387 | "requested special purpose register %x")); | |
7388 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
7389 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
7390 | _("'CPSR' or 'SPSR' expected")); | |
7391 | } | |
7392 | ||
c19d1205 | 7393 | inst.instruction |= inst.operands[0].reg << 8; |
62b3e311 PB |
7394 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
7395 | inst.instruction |= inst.operands[1].imm & 0xff; | |
c19d1205 | 7396 | } |
b05fe5cf | 7397 | |
c19d1205 ZW |
7398 | static void |
7399 | do_t_msr (void) | |
7400 | { | |
62b3e311 PB |
7401 | int flags; |
7402 | ||
c19d1205 ZW |
7403 | constraint (!inst.operands[1].isreg, |
7404 | _("Thumb encoding does not support an immediate here")); | |
62b3e311 PB |
7405 | flags = inst.operands[0].imm; |
7406 | if (flags & ~0xff) | |
7407 | { | |
7408 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), | |
7409 | _("selected processor does not support " | |
7410 | "requested special purpose register")); | |
7411 | } | |
7412 | else | |
7413 | { | |
7414 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), | |
7415 | _("selected processor does not support " | |
7416 | "requested special purpose register")); | |
7417 | flags |= PSR_f; | |
7418 | } | |
7419 | inst.instruction |= (flags & SPSR_BIT) >> 2; | |
7420 | inst.instruction |= (flags & ~SPSR_BIT) >> 8; | |
7421 | inst.instruction |= (flags & 0xff); | |
c19d1205 ZW |
7422 | inst.instruction |= inst.operands[1].reg << 16; |
7423 | } | |
b05fe5cf | 7424 | |
c19d1205 ZW |
7425 | static void |
7426 | do_t_mul (void) | |
7427 | { | |
7428 | if (!inst.operands[2].present) | |
7429 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 7430 | |
c19d1205 ZW |
7431 | /* There is no 32-bit MULS and no 16-bit MUL. */ |
7432 | if (unified_syntax && inst.instruction == T_MNEM_mul) | |
b05fe5cf | 7433 | { |
c19d1205 ZW |
7434 | inst.instruction = THUMB_OP32 (inst.instruction); |
7435 | inst.instruction |= inst.operands[0].reg << 8; | |
7436 | inst.instruction |= inst.operands[1].reg << 16; | |
7437 | inst.instruction |= inst.operands[2].reg << 0; | |
b05fe5cf | 7438 | } |
c19d1205 | 7439 | else |
b05fe5cf | 7440 | { |
c19d1205 ZW |
7441 | constraint (!unified_syntax |
7442 | && inst.instruction == T_MNEM_muls, BAD_THUMB32); | |
7443 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
7444 | BAD_HIREG); | |
b05fe5cf | 7445 | |
c19d1205 ZW |
7446 | inst.instruction = THUMB_OP16 (inst.instruction); |
7447 | inst.instruction |= inst.operands[0].reg; | |
b05fe5cf | 7448 | |
c19d1205 ZW |
7449 | if (inst.operands[0].reg == inst.operands[1].reg) |
7450 | inst.instruction |= inst.operands[2].reg << 3; | |
7451 | else if (inst.operands[0].reg == inst.operands[2].reg) | |
7452 | inst.instruction |= inst.operands[1].reg << 3; | |
7453 | else | |
7454 | constraint (1, _("dest must overlap one source register")); | |
7455 | } | |
7456 | } | |
b05fe5cf | 7457 | |
c19d1205 ZW |
7458 | static void |
7459 | do_t_mull (void) | |
7460 | { | |
7461 | inst.instruction |= inst.operands[0].reg << 12; | |
7462 | inst.instruction |= inst.operands[1].reg << 8; | |
7463 | inst.instruction |= inst.operands[2].reg << 16; | |
7464 | inst.instruction |= inst.operands[3].reg; | |
b05fe5cf | 7465 | |
c19d1205 ZW |
7466 | if (inst.operands[0].reg == inst.operands[1].reg) |
7467 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7468 | } | |
b05fe5cf | 7469 | |
c19d1205 ZW |
7470 | static void |
7471 | do_t_nop (void) | |
7472 | { | |
7473 | if (unified_syntax) | |
7474 | { | |
7475 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 7476 | { |
c19d1205 ZW |
7477 | inst.instruction = THUMB_OP32 (inst.instruction); |
7478 | inst.instruction |= inst.operands[0].imm; | |
7479 | } | |
7480 | else | |
7481 | { | |
7482 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7483 | inst.instruction |= inst.operands[0].imm << 4; | |
7484 | } | |
7485 | } | |
7486 | else | |
7487 | { | |
7488 | constraint (inst.operands[0].present, | |
7489 | _("Thumb does not support NOP with hints")); | |
7490 | inst.instruction = 0x46c0; | |
7491 | } | |
7492 | } | |
b05fe5cf | 7493 | |
c19d1205 ZW |
7494 | static void |
7495 | do_t_neg (void) | |
7496 | { | |
7497 | if (unified_syntax) | |
7498 | { | |
3d388997 PB |
7499 | bfd_boolean narrow; |
7500 | ||
7501 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
7502 | narrow = (current_it_mask == 0); | |
7503 | else | |
7504 | narrow = (current_it_mask != 0); | |
7505 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7506 | narrow = FALSE; | |
7507 | if (inst.size_req == 4) | |
7508 | narrow = FALSE; | |
7509 | ||
7510 | if (!narrow) | |
c19d1205 ZW |
7511 | { |
7512 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7513 | inst.instruction |= inst.operands[0].reg << 8; | |
7514 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
7515 | } |
7516 | else | |
7517 | { | |
c19d1205 ZW |
7518 | inst.instruction = THUMB_OP16 (inst.instruction); |
7519 | inst.instruction |= inst.operands[0].reg; | |
7520 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
7521 | } |
7522 | } | |
7523 | else | |
7524 | { | |
c19d1205 ZW |
7525 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
7526 | BAD_HIREG); | |
7527 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
7528 | ||
7529 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7530 | inst.instruction |= inst.operands[0].reg; | |
7531 | inst.instruction |= inst.operands[1].reg << 3; | |
7532 | } | |
7533 | } | |
7534 | ||
7535 | static void | |
7536 | do_t_pkhbt (void) | |
7537 | { | |
7538 | inst.instruction |= inst.operands[0].reg << 8; | |
7539 | inst.instruction |= inst.operands[1].reg << 16; | |
7540 | inst.instruction |= inst.operands[2].reg; | |
7541 | if (inst.operands[3].present) | |
7542 | { | |
7543 | unsigned int val = inst.reloc.exp.X_add_number; | |
7544 | constraint (inst.reloc.exp.X_op != O_constant, | |
7545 | _("expression too complex")); | |
7546 | inst.instruction |= (val & 0x1c) << 10; | |
7547 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 7548 | } |
c19d1205 | 7549 | } |
b05fe5cf | 7550 | |
c19d1205 ZW |
7551 | static void |
7552 | do_t_pkhtb (void) | |
7553 | { | |
7554 | if (!inst.operands[3].present) | |
7555 | inst.instruction &= ~0x00000020; | |
7556 | do_t_pkhbt (); | |
b05fe5cf ZW |
7557 | } |
7558 | ||
c19d1205 ZW |
7559 | static void |
7560 | do_t_pld (void) | |
7561 | { | |
7562 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
7563 | } | |
b05fe5cf | 7564 | |
c19d1205 ZW |
7565 | static void |
7566 | do_t_push_pop (void) | |
b99bd4ef | 7567 | { |
e9f89963 PB |
7568 | unsigned mask; |
7569 | ||
c19d1205 ZW |
7570 | constraint (inst.operands[0].writeback, |
7571 | _("push/pop do not support {reglist}^")); | |
7572 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
7573 | _("expression too complex")); | |
b99bd4ef | 7574 | |
e9f89963 PB |
7575 | mask = inst.operands[0].imm; |
7576 | if ((mask & ~0xff) == 0) | |
c19d1205 ZW |
7577 | inst.instruction = THUMB_OP16 (inst.instruction); |
7578 | else if ((inst.instruction == T_MNEM_push | |
e9f89963 | 7579 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 7580 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 7581 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 7582 | { |
c19d1205 ZW |
7583 | inst.instruction = THUMB_OP16 (inst.instruction); |
7584 | inst.instruction |= THUMB_PP_PC_LR; | |
e9f89963 | 7585 | mask &= 0xff; |
c19d1205 ZW |
7586 | } |
7587 | else if (unified_syntax) | |
7588 | { | |
e9f89963 PB |
7589 | if (mask & (1 << 13)) |
7590 | inst.error = _("SP not allowed in register list"); | |
c19d1205 | 7591 | if (inst.instruction == T_MNEM_push) |
b99bd4ef | 7592 | { |
e9f89963 PB |
7593 | if (mask & (1 << 15)) |
7594 | inst.error = _("PC not allowed in register list"); | |
c19d1205 ZW |
7595 | } |
7596 | else | |
7597 | { | |
e9f89963 PB |
7598 | if (mask & (1 << 14) |
7599 | && mask & (1 << 15)) | |
7600 | inst.error = _("LR and PC should not both be in register list"); | |
c19d1205 | 7601 | } |
e9f89963 PB |
7602 | if ((mask & (mask - 1)) == 0) |
7603 | { | |
7604 | /* Single register push/pop implemented as str/ldr. */ | |
7605 | if (inst.instruction == T_MNEM_push) | |
7606 | inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */ | |
7607 | else | |
7608 | inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */ | |
7609 | mask = ffs(mask) - 1; | |
7610 | mask <<= 12; | |
7611 | } | |
7612 | else | |
7613 | inst.instruction = THUMB_OP32 (inst.instruction); | |
c19d1205 ZW |
7614 | } |
7615 | else | |
7616 | { | |
7617 | inst.error = _("invalid register list to push/pop instruction"); | |
7618 | return; | |
7619 | } | |
b99bd4ef | 7620 | |
e9f89963 | 7621 | inst.instruction |= mask; |
c19d1205 | 7622 | } |
b99bd4ef | 7623 | |
c19d1205 ZW |
7624 | static void |
7625 | do_t_rbit (void) | |
7626 | { | |
7627 | inst.instruction |= inst.operands[0].reg << 8; | |
7628 | inst.instruction |= inst.operands[1].reg << 16; | |
7629 | } | |
b99bd4ef | 7630 | |
c19d1205 ZW |
7631 | static void |
7632 | do_t_rev (void) | |
7633 | { | |
7634 | if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
7635 | && inst.size_req != 4) | |
7636 | { | |
7637 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7638 | inst.instruction |= inst.operands[0].reg; | |
7639 | inst.instruction |= inst.operands[1].reg << 3; | |
7640 | } | |
7641 | else if (unified_syntax) | |
7642 | { | |
7643 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7644 | inst.instruction |= inst.operands[0].reg << 8; | |
7645 | inst.instruction |= inst.operands[1].reg << 16; | |
7646 | inst.instruction |= inst.operands[1].reg; | |
7647 | } | |
7648 | else | |
7649 | inst.error = BAD_HIREG; | |
7650 | } | |
b99bd4ef | 7651 | |
c19d1205 ZW |
7652 | static void |
7653 | do_t_rsb (void) | |
7654 | { | |
7655 | int Rd, Rs; | |
b99bd4ef | 7656 | |
c19d1205 ZW |
7657 | Rd = inst.operands[0].reg; |
7658 | Rs = (inst.operands[1].present | |
7659 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
7660 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 7661 | |
c19d1205 ZW |
7662 | inst.instruction |= Rd << 8; |
7663 | inst.instruction |= Rs << 16; | |
7664 | if (!inst.operands[2].isreg) | |
7665 | { | |
7666 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
7667 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
7668 | } | |
7669 | else | |
7670 | encode_thumb32_shifted_operand (2); | |
7671 | } | |
b99bd4ef | 7672 | |
c19d1205 ZW |
7673 | static void |
7674 | do_t_setend (void) | |
7675 | { | |
dfa9f0d5 | 7676 | constraint (current_it_mask, BAD_NOT_IT); |
c19d1205 ZW |
7677 | if (inst.operands[0].imm) |
7678 | inst.instruction |= 0x8; | |
7679 | } | |
b99bd4ef | 7680 | |
c19d1205 ZW |
7681 | static void |
7682 | do_t_shift (void) | |
7683 | { | |
7684 | if (!inst.operands[1].present) | |
7685 | inst.operands[1].reg = inst.operands[0].reg; | |
7686 | ||
7687 | if (unified_syntax) | |
7688 | { | |
3d388997 PB |
7689 | bfd_boolean narrow; |
7690 | int shift_kind; | |
7691 | ||
7692 | switch (inst.instruction) | |
7693 | { | |
7694 | case T_MNEM_asr: | |
7695 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
7696 | case T_MNEM_lsl: | |
7697 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
7698 | case T_MNEM_lsr: | |
7699 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
7700 | case T_MNEM_ror: | |
7701 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
7702 | default: abort (); | |
7703 | } | |
7704 | ||
7705 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
7706 | narrow = (current_it_mask == 0); | |
7707 | else | |
7708 | narrow = (current_it_mask != 0); | |
7709 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7710 | narrow = FALSE; | |
7711 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
7712 | narrow = FALSE; | |
7713 | if (inst.operands[2].isreg | |
7714 | && (inst.operands[1].reg != inst.operands[0].reg | |
7715 | || inst.operands[2].reg > 7)) | |
7716 | narrow = FALSE; | |
7717 | if (inst.size_req == 4) | |
7718 | narrow = FALSE; | |
7719 | ||
7720 | if (!narrow) | |
c19d1205 ZW |
7721 | { |
7722 | if (inst.operands[2].isreg) | |
b99bd4ef | 7723 | { |
c19d1205 ZW |
7724 | inst.instruction = THUMB_OP32 (inst.instruction); |
7725 | inst.instruction |= inst.operands[0].reg << 8; | |
7726 | inst.instruction |= inst.operands[1].reg << 16; | |
7727 | inst.instruction |= inst.operands[2].reg; | |
7728 | } | |
7729 | else | |
7730 | { | |
7731 | inst.operands[1].shifted = 1; | |
3d388997 | 7732 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
7733 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
7734 | ? T_MNEM_movs : T_MNEM_mov); | |
7735 | inst.instruction |= inst.operands[0].reg << 8; | |
7736 | encode_thumb32_shifted_operand (1); | |
7737 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
7738 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
7739 | } |
7740 | } | |
7741 | else | |
7742 | { | |
c19d1205 | 7743 | if (inst.operands[2].isreg) |
b99bd4ef | 7744 | { |
3d388997 | 7745 | switch (shift_kind) |
b99bd4ef | 7746 | { |
3d388997 PB |
7747 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
7748 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
7749 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
7750 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 7751 | default: abort (); |
b99bd4ef | 7752 | } |
c19d1205 ZW |
7753 | |
7754 | inst.instruction |= inst.operands[0].reg; | |
7755 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
7756 | } |
7757 | else | |
7758 | { | |
3d388997 | 7759 | switch (shift_kind) |
b99bd4ef | 7760 | { |
3d388997 PB |
7761 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
7762 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
7763 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 7764 | default: abort (); |
b99bd4ef | 7765 | } |
c19d1205 ZW |
7766 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
7767 | inst.instruction |= inst.operands[0].reg; | |
7768 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7769 | } |
7770 | } | |
c19d1205 ZW |
7771 | } |
7772 | else | |
7773 | { | |
7774 | constraint (inst.operands[0].reg > 7 | |
7775 | || inst.operands[1].reg > 7, BAD_HIREG); | |
7776 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 7777 | |
c19d1205 ZW |
7778 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
7779 | { | |
7780 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
7781 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
7782 | _("source1 and dest must be same register")); | |
b99bd4ef | 7783 | |
c19d1205 ZW |
7784 | switch (inst.instruction) |
7785 | { | |
7786 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
7787 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
7788 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
7789 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
7790 | default: abort (); | |
7791 | } | |
7792 | ||
7793 | inst.instruction |= inst.operands[0].reg; | |
7794 | inst.instruction |= inst.operands[2].reg << 3; | |
7795 | } | |
7796 | else | |
b99bd4ef | 7797 | { |
c19d1205 ZW |
7798 | switch (inst.instruction) |
7799 | { | |
7800 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
7801 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
7802 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
7803 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
7804 | default: abort (); | |
7805 | } | |
7806 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
7807 | inst.instruction |= inst.operands[0].reg; | |
7808 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7809 | } |
7810 | } | |
b99bd4ef NC |
7811 | } |
7812 | ||
7813 | static void | |
c19d1205 | 7814 | do_t_simd (void) |
b99bd4ef | 7815 | { |
c19d1205 ZW |
7816 | inst.instruction |= inst.operands[0].reg << 8; |
7817 | inst.instruction |= inst.operands[1].reg << 16; | |
7818 | inst.instruction |= inst.operands[2].reg; | |
7819 | } | |
b99bd4ef | 7820 | |
c19d1205 | 7821 | static void |
3eb17e6b | 7822 | do_t_smc (void) |
c19d1205 ZW |
7823 | { |
7824 | unsigned int value = inst.reloc.exp.X_add_number; | |
7825 | constraint (inst.reloc.exp.X_op != O_constant, | |
7826 | _("expression too complex")); | |
7827 | inst.reloc.type = BFD_RELOC_UNUSED; | |
7828 | inst.instruction |= (value & 0xf000) >> 12; | |
7829 | inst.instruction |= (value & 0x0ff0); | |
7830 | inst.instruction |= (value & 0x000f) << 16; | |
7831 | } | |
b99bd4ef | 7832 | |
c19d1205 ZW |
7833 | static void |
7834 | do_t_ssat (void) | |
7835 | { | |
7836 | inst.instruction |= inst.operands[0].reg << 8; | |
7837 | inst.instruction |= inst.operands[1].imm - 1; | |
7838 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7839 | |
c19d1205 | 7840 | if (inst.operands[3].present) |
b99bd4ef | 7841 | { |
c19d1205 ZW |
7842 | constraint (inst.reloc.exp.X_op != O_constant, |
7843 | _("expression too complex")); | |
b99bd4ef | 7844 | |
c19d1205 | 7845 | if (inst.reloc.exp.X_add_number != 0) |
6189168b | 7846 | { |
c19d1205 ZW |
7847 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
7848 | inst.instruction |= 0x00200000; /* sh bit */ | |
7849 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; | |
7850 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
6189168b | 7851 | } |
c19d1205 | 7852 | inst.reloc.type = BFD_RELOC_UNUSED; |
6189168b | 7853 | } |
b99bd4ef NC |
7854 | } |
7855 | ||
0dd132b6 | 7856 | static void |
c19d1205 | 7857 | do_t_ssat16 (void) |
0dd132b6 | 7858 | { |
c19d1205 ZW |
7859 | inst.instruction |= inst.operands[0].reg << 8; |
7860 | inst.instruction |= inst.operands[1].imm - 1; | |
7861 | inst.instruction |= inst.operands[2].reg << 16; | |
7862 | } | |
0dd132b6 | 7863 | |
c19d1205 ZW |
7864 | static void |
7865 | do_t_strex (void) | |
7866 | { | |
7867 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
7868 | || inst.operands[2].postind || inst.operands[2].writeback | |
7869 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
7870 | || inst.operands[2].negative, | |
01cfc07f | 7871 | BAD_ADDR_MODE); |
0dd132b6 | 7872 | |
c19d1205 ZW |
7873 | inst.instruction |= inst.operands[0].reg << 8; |
7874 | inst.instruction |= inst.operands[1].reg << 12; | |
7875 | inst.instruction |= inst.operands[2].reg << 16; | |
7876 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
7877 | } |
7878 | ||
b99bd4ef | 7879 | static void |
c19d1205 | 7880 | do_t_strexd (void) |
b99bd4ef | 7881 | { |
c19d1205 ZW |
7882 | if (!inst.operands[2].present) |
7883 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 7884 | |
c19d1205 ZW |
7885 | constraint (inst.operands[0].reg == inst.operands[1].reg |
7886 | || inst.operands[0].reg == inst.operands[2].reg | |
7887 | || inst.operands[0].reg == inst.operands[3].reg | |
7888 | || inst.operands[1].reg == inst.operands[2].reg, | |
7889 | BAD_OVERLAP); | |
b99bd4ef | 7890 | |
c19d1205 ZW |
7891 | inst.instruction |= inst.operands[0].reg; |
7892 | inst.instruction |= inst.operands[1].reg << 12; | |
7893 | inst.instruction |= inst.operands[2].reg << 8; | |
7894 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
7895 | } |
7896 | ||
7897 | static void | |
c19d1205 | 7898 | do_t_sxtah (void) |
b99bd4ef | 7899 | { |
c19d1205 ZW |
7900 | inst.instruction |= inst.operands[0].reg << 8; |
7901 | inst.instruction |= inst.operands[1].reg << 16; | |
7902 | inst.instruction |= inst.operands[2].reg; | |
7903 | inst.instruction |= inst.operands[3].imm << 4; | |
7904 | } | |
b99bd4ef | 7905 | |
c19d1205 ZW |
7906 | static void |
7907 | do_t_sxth (void) | |
7908 | { | |
7909 | if (inst.instruction <= 0xffff && inst.size_req != 4 | |
7910 | && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
7911 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) | |
b99bd4ef | 7912 | { |
c19d1205 ZW |
7913 | inst.instruction = THUMB_OP16 (inst.instruction); |
7914 | inst.instruction |= inst.operands[0].reg; | |
7915 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7916 | } |
c19d1205 | 7917 | else if (unified_syntax) |
b99bd4ef | 7918 | { |
c19d1205 ZW |
7919 | if (inst.instruction <= 0xffff) |
7920 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7921 | inst.instruction |= inst.operands[0].reg << 8; | |
7922 | inst.instruction |= inst.operands[1].reg; | |
7923 | inst.instruction |= inst.operands[2].imm << 4; | |
b99bd4ef | 7924 | } |
c19d1205 | 7925 | else |
b99bd4ef | 7926 | { |
c19d1205 ZW |
7927 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
7928 | _("Thumb encoding does not support rotation")); | |
7929 | constraint (1, BAD_HIREG); | |
b99bd4ef | 7930 | } |
c19d1205 | 7931 | } |
b99bd4ef | 7932 | |
c19d1205 ZW |
7933 | static void |
7934 | do_t_swi (void) | |
7935 | { | |
7936 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
7937 | } | |
b99bd4ef | 7938 | |
92e90b6e PB |
7939 | static void |
7940 | do_t_tb (void) | |
7941 | { | |
7942 | int half; | |
7943 | ||
7944 | half = (inst.instruction & 0x10) != 0; | |
dfa9f0d5 PB |
7945 | constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); |
7946 | constraint (inst.operands[0].immisreg, | |
7947 | _("instruction requires register index")); | |
92e90b6e PB |
7948 | constraint (inst.operands[0].imm == 15, |
7949 | _("PC is not a valid index register")); | |
7950 | constraint (!half && inst.operands[0].shifted, | |
7951 | _("instruction does not allow shifted index")); | |
92e90b6e PB |
7952 | inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; |
7953 | } | |
7954 | ||
c19d1205 ZW |
7955 | static void |
7956 | do_t_usat (void) | |
7957 | { | |
7958 | inst.instruction |= inst.operands[0].reg << 8; | |
7959 | inst.instruction |= inst.operands[1].imm; | |
7960 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7961 | |
c19d1205 | 7962 | if (inst.operands[3].present) |
b99bd4ef | 7963 | { |
c19d1205 ZW |
7964 | constraint (inst.reloc.exp.X_op != O_constant, |
7965 | _("expression too complex")); | |
7966 | if (inst.reloc.exp.X_add_number != 0) | |
7967 | { | |
7968 | if (inst.operands[3].shift_kind == SHIFT_ASR) | |
7969 | inst.instruction |= 0x00200000; /* sh bit */ | |
b99bd4ef | 7970 | |
c19d1205 ZW |
7971 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; |
7972 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
7973 | } | |
7974 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 7975 | } |
b99bd4ef NC |
7976 | } |
7977 | ||
7978 | static void | |
c19d1205 | 7979 | do_t_usat16 (void) |
b99bd4ef | 7980 | { |
c19d1205 ZW |
7981 | inst.instruction |= inst.operands[0].reg << 8; |
7982 | inst.instruction |= inst.operands[1].imm; | |
7983 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7984 | } |
c19d1205 ZW |
7985 | \f |
7986 | /* Overall per-instruction processing. */ | |
7987 | ||
7988 | /* We need to be able to fix up arbitrary expressions in some statements. | |
7989 | This is so that we can handle symbols that are an arbitrary distance from | |
7990 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
7991 | which returns part of an address in a form which will be valid for | |
7992 | a data instruction. We do this by pushing the expression into a symbol | |
7993 | in the expr_section, and creating a fix for that. */ | |
b99bd4ef NC |
7994 | |
7995 | static void | |
c19d1205 ZW |
7996 | fix_new_arm (fragS * frag, |
7997 | int where, | |
7998 | short int size, | |
7999 | expressionS * exp, | |
8000 | int pc_rel, | |
8001 | int reloc) | |
b99bd4ef | 8002 | { |
c19d1205 | 8003 | fixS * new_fix; |
b99bd4ef | 8004 | |
c19d1205 | 8005 | switch (exp->X_op) |
b99bd4ef | 8006 | { |
c19d1205 ZW |
8007 | case O_constant: |
8008 | case O_symbol: | |
8009 | case O_add: | |
8010 | case O_subtract: | |
8011 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
8012 | break; | |
b99bd4ef | 8013 | |
c19d1205 ZW |
8014 | default: |
8015 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
8016 | pc_rel, reloc); | |
8017 | break; | |
b99bd4ef NC |
8018 | } |
8019 | ||
c19d1205 ZW |
8020 | /* Mark whether the fix is to a THUMB instruction, or an ARM |
8021 | instruction. */ | |
adbaf948 | 8022 | new_fix->tc_fix_data = thumb_mode; |
b99bd4ef NC |
8023 | } |
8024 | ||
0110f2b8 PB |
8025 | /* Create a frg for an instruction requiring relaxation. */ |
8026 | static void | |
8027 | output_relax_insn (void) | |
8028 | { | |
8029 | char * to; | |
8030 | symbolS *sym; | |
8031 | int offset; | |
8032 | ||
6e1cb1a6 PB |
8033 | #ifdef OBJ_ELF |
8034 | /* The size of the instruction is unknown, so tie the debug info to the | |
8035 | start of the instruction. */ | |
8036 | dwarf2_emit_insn (0); | |
8037 | #endif | |
8038 | ||
0110f2b8 PB |
8039 | switch (inst.reloc.exp.X_op) |
8040 | { | |
8041 | case O_symbol: | |
8042 | sym = inst.reloc.exp.X_add_symbol; | |
8043 | offset = inst.reloc.exp.X_add_number; | |
8044 | break; | |
8045 | case O_constant: | |
8046 | sym = NULL; | |
8047 | offset = inst.reloc.exp.X_add_number; | |
8048 | break; | |
8049 | default: | |
8050 | sym = make_expr_symbol (&inst.reloc.exp); | |
8051 | offset = 0; | |
8052 | break; | |
8053 | } | |
8054 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
8055 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
8056 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
8057 | } |
8058 | ||
8059 | /* Write a 32-bit thumb instruction to buf. */ | |
8060 | static void | |
8061 | put_thumb32_insn (char * buf, unsigned long insn) | |
8062 | { | |
8063 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
8064 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
8065 | } | |
8066 | ||
b99bd4ef | 8067 | static void |
c19d1205 | 8068 | output_inst (const char * str) |
b99bd4ef | 8069 | { |
c19d1205 | 8070 | char * to = NULL; |
b99bd4ef | 8071 | |
c19d1205 | 8072 | if (inst.error) |
b99bd4ef | 8073 | { |
c19d1205 | 8074 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
8075 | return; |
8076 | } | |
0110f2b8 PB |
8077 | if (inst.relax) { |
8078 | output_relax_insn(); | |
8079 | return; | |
8080 | } | |
c19d1205 ZW |
8081 | if (inst.size == 0) |
8082 | return; | |
b99bd4ef | 8083 | |
c19d1205 ZW |
8084 | to = frag_more (inst.size); |
8085 | ||
8086 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 8087 | { |
c19d1205 | 8088 | assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 8089 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 8090 | } |
c19d1205 | 8091 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 8092 | { |
c19d1205 ZW |
8093 | assert (inst.size == (2 * INSN_SIZE)); |
8094 | md_number_to_chars (to, inst.instruction, INSN_SIZE); | |
8095 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 8096 | } |
c19d1205 ZW |
8097 | else |
8098 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 8099 | |
c19d1205 ZW |
8100 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
8101 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
8102 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
8103 | inst.reloc.type); | |
b99bd4ef | 8104 | |
c19d1205 ZW |
8105 | #ifdef OBJ_ELF |
8106 | dwarf2_emit_insn (inst.size); | |
8107 | #endif | |
8108 | } | |
b99bd4ef | 8109 | |
c19d1205 ZW |
8110 | /* Tag values used in struct asm_opcode's tag field. */ |
8111 | enum opcode_tag | |
8112 | { | |
8113 | OT_unconditional, /* Instruction cannot be conditionalized. | |
8114 | The ARM condition field is still 0xE. */ | |
8115 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
8116 | and carries 0xF in its ARM condition field. */ | |
8117 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
8118 | OT_cinfix3, /* Instruction takes a conditional infix, | |
8119 | beginning at character index 3. (In | |
8120 | unified mode, it becomes a suffix.) */ | |
e3cb604e PB |
8121 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
8122 | character index 3, even in unified mode. Used for | |
8123 | legacy instructions where suffix and infix forms | |
8124 | may be ambiguous. */ | |
c19d1205 | 8125 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 8126 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
8127 | OT_odd_infix_unc, /* This is the unconditional variant of an |
8128 | instruction that takes a conditional infix | |
8129 | at an unusual position. In unified mode, | |
8130 | this variant will accept a suffix. */ | |
8131 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
8132 | are the conditional variants of instructions that | |
8133 | take conditional infixes in unusual positions. | |
8134 | The infix appears at character index | |
8135 | (tag - OT_odd_infix_0). These are not accepted | |
8136 | in unified mode. */ | |
8137 | }; | |
b99bd4ef | 8138 | |
c19d1205 ZW |
8139 | /* Subroutine of md_assemble, responsible for looking up the primary |
8140 | opcode from the mnemonic the user wrote. STR points to the | |
8141 | beginning of the mnemonic. | |
8142 | ||
8143 | This is not simply a hash table lookup, because of conditional | |
8144 | variants. Most instructions have conditional variants, which are | |
8145 | expressed with a _conditional affix_ to the mnemonic. If we were | |
8146 | to encode each conditional variant as a literal string in the opcode | |
8147 | table, it would have approximately 20,000 entries. | |
8148 | ||
8149 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
8150 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
8151 | instructions take the affix as an infix, notably the s-variants of | |
8152 | the arithmetic instructions. Of those instructions, all but six | |
8153 | have the infix appear after the third character of the mnemonic. | |
8154 | ||
8155 | Accordingly, the algorithm for looking up primary opcodes given | |
8156 | an identifier is: | |
8157 | ||
8158 | 1. Look up the identifier in the opcode table. | |
8159 | If we find a match, go to step U. | |
8160 | ||
8161 | 2. Look up the last two characters of the identifier in the | |
8162 | conditions table. If we find a match, look up the first N-2 | |
8163 | characters of the identifier in the opcode table. If we | |
8164 | find a match, go to step CE. | |
8165 | ||
8166 | 3. Look up the fourth and fifth characters of the identifier in | |
8167 | the conditions table. If we find a match, extract those | |
8168 | characters from the identifier, and look up the remaining | |
8169 | characters in the opcode table. If we find a match, go | |
8170 | to step CM. | |
8171 | ||
8172 | 4. Fail. | |
8173 | ||
8174 | U. Examine the tag field of the opcode structure, in case this is | |
8175 | one of the six instructions with its conditional infix in an | |
8176 | unusual place. If it is, the tag tells us where to find the | |
8177 | infix; look it up in the conditions table and set inst.cond | |
8178 | accordingly. Otherwise, this is an unconditional instruction. | |
8179 | Again set inst.cond accordingly. Return the opcode structure. | |
8180 | ||
8181 | CE. Examine the tag field to make sure this is an instruction that | |
8182 | should receive a conditional suffix. If it is not, fail. | |
8183 | Otherwise, set inst.cond from the suffix we already looked up, | |
8184 | and return the opcode structure. | |
8185 | ||
8186 | CM. Examine the tag field to make sure this is an instruction that | |
8187 | should receive a conditional infix after the third character. | |
8188 | If it is not, fail. Otherwise, undo the edits to the current | |
8189 | line of input and proceed as for case CE. */ | |
8190 | ||
8191 | static const struct asm_opcode * | |
8192 | opcode_lookup (char **str) | |
8193 | { | |
8194 | char *end, *base; | |
8195 | char *affix; | |
8196 | const struct asm_opcode *opcode; | |
8197 | const struct asm_cond *cond; | |
e3cb604e | 8198 | char save[2]; |
c19d1205 ZW |
8199 | |
8200 | /* Scan up to the end of the mnemonic, which must end in white space, | |
8201 | '.' (in unified mode only), or end of string. */ | |
8202 | for (base = end = *str; *end != '\0'; end++) | |
8203 | if (*end == ' ' || (unified_syntax && *end == '.')) | |
8204 | break; | |
b99bd4ef | 8205 | |
c19d1205 ZW |
8206 | if (end == base) |
8207 | return 0; | |
b99bd4ef | 8208 | |
c19d1205 ZW |
8209 | /* Handle a possible width suffix. */ |
8210 | if (end[0] == '.') | |
b99bd4ef | 8211 | { |
c19d1205 ZW |
8212 | if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0')) |
8213 | inst.size_req = 4; | |
8214 | else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0')) | |
8215 | inst.size_req = 2; | |
8216 | else | |
8217 | return 0; | |
b99bd4ef | 8218 | |
c19d1205 | 8219 | *str = end + 2; |
b99bd4ef | 8220 | } |
c19d1205 ZW |
8221 | else |
8222 | *str = end; | |
b99bd4ef | 8223 | |
c19d1205 ZW |
8224 | /* Look for unaffixed or special-case affixed mnemonic. */ |
8225 | opcode = hash_find_n (arm_ops_hsh, base, end - base); | |
8226 | if (opcode) | |
b99bd4ef | 8227 | { |
c19d1205 ZW |
8228 | /* step U */ |
8229 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 8230 | { |
c19d1205 ZW |
8231 | inst.cond = COND_ALWAYS; |
8232 | return opcode; | |
b99bd4ef | 8233 | } |
b99bd4ef | 8234 | |
c19d1205 ZW |
8235 | if (unified_syntax) |
8236 | as_warn (_("conditional infixes are deprecated in unified syntax")); | |
8237 | affix = base + (opcode->tag - OT_odd_infix_0); | |
8238 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
8239 | assert (cond); | |
b99bd4ef | 8240 | |
c19d1205 ZW |
8241 | inst.cond = cond->value; |
8242 | return opcode; | |
8243 | } | |
b99bd4ef | 8244 | |
c19d1205 ZW |
8245 | /* Cannot have a conditional suffix on a mnemonic of less than two |
8246 | characters. */ | |
8247 | if (end - base < 3) | |
8248 | return 0; | |
b99bd4ef | 8249 | |
c19d1205 ZW |
8250 | /* Look for suffixed mnemonic. */ |
8251 | affix = end - 2; | |
8252 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
8253 | opcode = hash_find_n (arm_ops_hsh, base, affix - base); | |
8254 | if (opcode && cond) | |
8255 | { | |
8256 | /* step CE */ | |
8257 | switch (opcode->tag) | |
8258 | { | |
e3cb604e PB |
8259 | case OT_cinfix3_legacy: |
8260 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
8261 | break; | |
8262 | ||
c19d1205 ZW |
8263 | case OT_cinfix3: |
8264 | case OT_odd_infix_unc: | |
8265 | if (!unified_syntax) | |
e3cb604e | 8266 | return 0; |
c19d1205 ZW |
8267 | /* else fall through */ |
8268 | ||
8269 | case OT_csuffix: | |
8270 | case OT_csuf_or_in3: | |
8271 | inst.cond = cond->value; | |
8272 | return opcode; | |
8273 | ||
8274 | case OT_unconditional: | |
8275 | case OT_unconditionalF: | |
dfa9f0d5 PB |
8276 | if (thumb_mode) |
8277 | { | |
8278 | inst.cond = cond->value; | |
8279 | } | |
8280 | else | |
8281 | { | |
8282 | /* delayed diagnostic */ | |
8283 | inst.error = BAD_COND; | |
8284 | inst.cond = COND_ALWAYS; | |
8285 | } | |
c19d1205 | 8286 | return opcode; |
b99bd4ef | 8287 | |
c19d1205 ZW |
8288 | default: |
8289 | return 0; | |
8290 | } | |
8291 | } | |
b99bd4ef | 8292 | |
c19d1205 ZW |
8293 | /* Cannot have a usual-position infix on a mnemonic of less than |
8294 | six characters (five would be a suffix). */ | |
8295 | if (end - base < 6) | |
8296 | return 0; | |
b99bd4ef | 8297 | |
c19d1205 ZW |
8298 | /* Look for infixed mnemonic in the usual position. */ |
8299 | affix = base + 3; | |
8300 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
e3cb604e PB |
8301 | if (!cond) |
8302 | return 0; | |
8303 | ||
8304 | memcpy (save, affix, 2); | |
8305 | memmove (affix, affix + 2, (end - affix) - 2); | |
8306 | opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); | |
8307 | memmove (affix + 2, affix, (end - affix) - 2); | |
8308 | memcpy (affix, save, 2); | |
8309 | ||
8310 | if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3 | |
8311 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 8312 | { |
c19d1205 | 8313 | /* step CM */ |
e3cb604e | 8314 | if (unified_syntax && opcode->tag == OT_cinfix3) |
c19d1205 ZW |
8315 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
8316 | ||
8317 | inst.cond = cond->value; | |
8318 | return opcode; | |
b99bd4ef NC |
8319 | } |
8320 | ||
c19d1205 | 8321 | return 0; |
b99bd4ef NC |
8322 | } |
8323 | ||
c19d1205 ZW |
8324 | void |
8325 | md_assemble (char *str) | |
b99bd4ef | 8326 | { |
c19d1205 ZW |
8327 | char *p = str; |
8328 | const struct asm_opcode * opcode; | |
b99bd4ef | 8329 | |
c19d1205 ZW |
8330 | /* Align the previous label if needed. */ |
8331 | if (last_label_seen != NULL) | |
b99bd4ef | 8332 | { |
c19d1205 ZW |
8333 | symbol_set_frag (last_label_seen, frag_now); |
8334 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
8335 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
8336 | } |
8337 | ||
c19d1205 ZW |
8338 | memset (&inst, '\0', sizeof (inst)); |
8339 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 8340 | |
c19d1205 ZW |
8341 | opcode = opcode_lookup (&p); |
8342 | if (!opcode) | |
b99bd4ef | 8343 | { |
c19d1205 ZW |
8344 | /* It wasn't an instruction, but it might be a register alias of |
8345 | the form alias .req reg. */ | |
8346 | if (!create_register_alias (str, p)) | |
8347 | as_bad (_("bad instruction `%s'"), str); | |
b99bd4ef | 8348 | |
b99bd4ef NC |
8349 | return; |
8350 | } | |
8351 | ||
c19d1205 | 8352 | if (thumb_mode) |
b99bd4ef | 8353 | { |
e74cfd16 | 8354 | arm_feature_set variant; |
8f06b2d8 PB |
8355 | |
8356 | variant = cpu_variant; | |
8357 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
8358 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
8359 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 8360 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
8361 | if (!opcode->tvariant |
8362 | || (thumb_mode == 1 | |
8363 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 8364 | { |
c19d1205 | 8365 | as_bad (_("selected processor does not support `%s'"), str); |
b99bd4ef NC |
8366 | return; |
8367 | } | |
c19d1205 ZW |
8368 | if (inst.cond != COND_ALWAYS && !unified_syntax |
8369 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 8370 | { |
c19d1205 | 8371 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
8372 | return; |
8373 | } | |
8374 | ||
e27ec89e PB |
8375 | /* Check conditional suffixes. */ |
8376 | if (current_it_mask) | |
8377 | { | |
8378 | int cond; | |
8379 | cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; | |
dfa9f0d5 PB |
8380 | current_it_mask <<= 1; |
8381 | current_it_mask &= 0x1f; | |
8382 | /* The BKPT instruction is unconditional even in an IT block. */ | |
8383 | if (!inst.error | |
8384 | && cond != inst.cond && opcode->tencode != do_t_bkpt) | |
e27ec89e PB |
8385 | { |
8386 | as_bad (_("incorrect condition in IT block")); | |
8387 | return; | |
8388 | } | |
e27ec89e PB |
8389 | } |
8390 | else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) | |
8391 | { | |
8392 | as_bad (_("thumb conditional instrunction not in IT block")); | |
8393 | return; | |
8394 | } | |
8395 | ||
c19d1205 ZW |
8396 | mapping_state (MAP_THUMB); |
8397 | inst.instruction = opcode->tvalue; | |
8398 | ||
8399 | if (!parse_operands (p, opcode->operands)) | |
8400 | opcode->tencode (); | |
8401 | ||
e27ec89e PB |
8402 | /* Clear current_it_mask at the end of an IT block. */ |
8403 | if (current_it_mask == 0x10) | |
8404 | current_it_mask = 0; | |
8405 | ||
0110f2b8 | 8406 | if (!(inst.error || inst.relax)) |
b99bd4ef | 8407 | { |
c19d1205 ZW |
8408 | assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
8409 | inst.size = (inst.instruction > 0xffff ? 4 : 2); | |
8410 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 8411 | { |
c19d1205 | 8412 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
8413 | return; |
8414 | } | |
8415 | } | |
e74cfd16 PB |
8416 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
8417 | *opcode->tvariant); | |
ee065d83 | 8418 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
e74cfd16 | 8419 | set those bits when Thumb-2 32-bit instuctions are seen. ie. |
ee065d83 PB |
8420 | anything other than bl/blx. |
8421 | This is overly pessimistic for relaxable instructions. */ | |
8422 | if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) | |
8423 | || inst.relax) | |
e74cfd16 PB |
8424 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
8425 | arm_ext_v6t2); | |
c19d1205 ZW |
8426 | } |
8427 | else | |
8428 | { | |
8429 | /* Check that this instruction is supported for this CPU. */ | |
62b3e311 PB |
8430 | if (!opcode->avariant || |
8431 | !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) | |
b99bd4ef | 8432 | { |
c19d1205 ZW |
8433 | as_bad (_("selected processor does not support `%s'"), str); |
8434 | return; | |
b99bd4ef | 8435 | } |
c19d1205 | 8436 | if (inst.size_req) |
b99bd4ef | 8437 | { |
c19d1205 ZW |
8438 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
8439 | return; | |
b99bd4ef NC |
8440 | } |
8441 | ||
c19d1205 ZW |
8442 | mapping_state (MAP_ARM); |
8443 | inst.instruction = opcode->avalue; | |
8444 | if (opcode->tag == OT_unconditionalF) | |
8445 | inst.instruction |= 0xF << 28; | |
8446 | else | |
8447 | inst.instruction |= inst.cond << 28; | |
8448 | inst.size = INSN_SIZE; | |
8449 | if (!parse_operands (p, opcode->operands)) | |
8450 | opcode->aencode (); | |
ee065d83 PB |
8451 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
8452 | on a hypothetical non-thumb v5 core. */ | |
e74cfd16 PB |
8453 | if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) |
8454 | || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) | |
8455 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); | |
ee065d83 | 8456 | else |
e74cfd16 PB |
8457 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
8458 | *opcode->avariant); | |
b99bd4ef | 8459 | } |
c19d1205 ZW |
8460 | output_inst (str); |
8461 | } | |
b99bd4ef | 8462 | |
c19d1205 ZW |
8463 | /* Various frobbings of labels and their addresses. */ |
8464 | ||
8465 | void | |
8466 | arm_start_line_hook (void) | |
8467 | { | |
8468 | last_label_seen = NULL; | |
b99bd4ef NC |
8469 | } |
8470 | ||
c19d1205 ZW |
8471 | void |
8472 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 8473 | { |
c19d1205 | 8474 | last_label_seen = sym; |
b99bd4ef | 8475 | |
c19d1205 | 8476 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 8477 | |
c19d1205 ZW |
8478 | #if defined OBJ_COFF || defined OBJ_ELF |
8479 | ARM_SET_INTERWORK (sym, support_interwork); | |
8480 | #endif | |
b99bd4ef | 8481 | |
c19d1205 ZW |
8482 | /* Note - do not allow local symbols (.Lxxx) to be labeled |
8483 | as Thumb functions. This is because these labels, whilst | |
8484 | they exist inside Thumb code, are not the entry points for | |
8485 | possible ARM->Thumb calls. Also, these labels can be used | |
8486 | as part of a computed goto or switch statement. eg gcc | |
8487 | can generate code that looks like this: | |
b99bd4ef | 8488 | |
c19d1205 ZW |
8489 | ldr r2, [pc, .Laaa] |
8490 | lsl r3, r3, #2 | |
8491 | ldr r2, [r3, r2] | |
8492 | mov pc, r2 | |
b99bd4ef | 8493 | |
c19d1205 ZW |
8494 | .Lbbb: .word .Lxxx |
8495 | .Lccc: .word .Lyyy | |
8496 | ..etc... | |
8497 | .Laaa: .word Lbbb | |
b99bd4ef | 8498 | |
c19d1205 ZW |
8499 | The first instruction loads the address of the jump table. |
8500 | The second instruction converts a table index into a byte offset. | |
8501 | The third instruction gets the jump address out of the table. | |
8502 | The fourth instruction performs the jump. | |
b99bd4ef | 8503 | |
c19d1205 ZW |
8504 | If the address stored at .Laaa is that of a symbol which has the |
8505 | Thumb_Func bit set, then the linker will arrange for this address | |
8506 | to have the bottom bit set, which in turn would mean that the | |
8507 | address computation performed by the third instruction would end | |
8508 | up with the bottom bit set. Since the ARM is capable of unaligned | |
8509 | word loads, the instruction would then load the incorrect address | |
8510 | out of the jump table, and chaos would ensue. */ | |
8511 | if (label_is_thumb_function_name | |
8512 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
8513 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 8514 | { |
c19d1205 ZW |
8515 | /* When the address of a Thumb function is taken the bottom |
8516 | bit of that address should be set. This will allow | |
8517 | interworking between Arm and Thumb functions to work | |
8518 | correctly. */ | |
b99bd4ef | 8519 | |
c19d1205 | 8520 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 8521 | |
c19d1205 | 8522 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 8523 | } |
07a53e5c RH |
8524 | |
8525 | #ifdef OBJ_ELF | |
8526 | dwarf2_emit_label (sym); | |
8527 | #endif | |
b99bd4ef NC |
8528 | } |
8529 | ||
c19d1205 ZW |
8530 | int |
8531 | arm_data_in_code (void) | |
b99bd4ef | 8532 | { |
c19d1205 | 8533 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 8534 | { |
c19d1205 ZW |
8535 | *input_line_pointer = '/'; |
8536 | input_line_pointer += 5; | |
8537 | *input_line_pointer = 0; | |
8538 | return 1; | |
b99bd4ef NC |
8539 | } |
8540 | ||
c19d1205 | 8541 | return 0; |
b99bd4ef NC |
8542 | } |
8543 | ||
c19d1205 ZW |
8544 | char * |
8545 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 8546 | { |
c19d1205 | 8547 | int len; |
b99bd4ef | 8548 | |
c19d1205 ZW |
8549 | if (thumb_mode && (len = strlen (name)) > 5 |
8550 | && streq (name + len - 5, "/data")) | |
8551 | *(name + len - 5) = 0; | |
b99bd4ef | 8552 | |
c19d1205 | 8553 | return name; |
b99bd4ef | 8554 | } |
c19d1205 ZW |
8555 | \f |
8556 | /* Table of all register names defined by default. The user can | |
8557 | define additional names with .req. Note that all register names | |
8558 | should appear in both upper and lowercase variants. Some registers | |
8559 | also have mixed-case names. */ | |
b99bd4ef | 8560 | |
c19d1205 ZW |
8561 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE } |
8562 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) | |
8563 | #define REGSET(p,t) \ | |
8564 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
8565 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
8566 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
8567 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
7ed4c4c5 | 8568 | |
c19d1205 | 8569 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 8570 | { |
c19d1205 ZW |
8571 | /* ARM integer registers. */ |
8572 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 8573 | |
c19d1205 ZW |
8574 | /* ATPCS synonyms. */ |
8575 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
8576 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
8577 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 8578 | |
c19d1205 ZW |
8579 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
8580 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
8581 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 8582 | |
c19d1205 ZW |
8583 | /* Well-known aliases. */ |
8584 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
8585 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
8586 | ||
8587 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
8588 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
8589 | ||
8590 | /* Coprocessor numbers. */ | |
8591 | REGSET(p, CP), REGSET(P, CP), | |
8592 | ||
8593 | /* Coprocessor register numbers. The "cr" variants are for backward | |
8594 | compatibility. */ | |
8595 | REGSET(c, CN), REGSET(C, CN), | |
8596 | REGSET(cr, CN), REGSET(CR, CN), | |
8597 | ||
8598 | /* FPA registers. */ | |
8599 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
8600 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
8601 | ||
8602 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
8603 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
8604 | ||
8605 | /* VFP SP registers. */ | |
8606 | REGSET(s,VFS), | |
8607 | REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS), | |
8608 | REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS), | |
8609 | REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS), | |
8610 | REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS), | |
8611 | ||
8612 | REGSET(S,VFS), | |
8613 | REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS), | |
8614 | REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS), | |
8615 | REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS), | |
8616 | REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS), | |
8617 | ||
8618 | /* VFP DP Registers. */ | |
8619 | REGSET(d,VFD), REGSET(D,VFS), | |
8620 | ||
8621 | /* VFP control registers. */ | |
8622 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
8623 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
8624 | ||
8625 | /* Maverick DSP coprocessor registers. */ | |
8626 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
8627 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
8628 | ||
8629 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
8630 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
8631 | REGDEF(dspsc,0,DSPSC), | |
8632 | ||
8633 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
8634 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
8635 | REGDEF(DSPSC,0,DSPSC), | |
8636 | ||
8637 | /* iWMMXt data registers - p0, c0-15. */ | |
8638 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
8639 | ||
8640 | /* iWMMXt control registers - p1, c0-3. */ | |
8641 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
8642 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
8643 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
8644 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
8645 | ||
8646 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
8647 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
8648 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
8649 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
8650 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
8651 | ||
8652 | /* XScale accumulator registers. */ | |
8653 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
8654 | }; | |
8655 | #undef REGDEF | |
8656 | #undef REGNUM | |
8657 | #undef REGSET | |
7ed4c4c5 | 8658 | |
c19d1205 ZW |
8659 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
8660 | within psr_required_here. */ | |
8661 | static const struct asm_psr psrs[] = | |
8662 | { | |
8663 | /* Backward compatibility notation. Note that "all" is no longer | |
8664 | truly all possible PSR bits. */ | |
8665 | {"all", PSR_c | PSR_f}, | |
8666 | {"flg", PSR_f}, | |
8667 | {"ctl", PSR_c}, | |
8668 | ||
8669 | /* Individual flags. */ | |
8670 | {"f", PSR_f}, | |
8671 | {"c", PSR_c}, | |
8672 | {"x", PSR_x}, | |
8673 | {"s", PSR_s}, | |
8674 | /* Combinations of flags. */ | |
8675 | {"fs", PSR_f | PSR_s}, | |
8676 | {"fx", PSR_f | PSR_x}, | |
8677 | {"fc", PSR_f | PSR_c}, | |
8678 | {"sf", PSR_s | PSR_f}, | |
8679 | {"sx", PSR_s | PSR_x}, | |
8680 | {"sc", PSR_s | PSR_c}, | |
8681 | {"xf", PSR_x | PSR_f}, | |
8682 | {"xs", PSR_x | PSR_s}, | |
8683 | {"xc", PSR_x | PSR_c}, | |
8684 | {"cf", PSR_c | PSR_f}, | |
8685 | {"cs", PSR_c | PSR_s}, | |
8686 | {"cx", PSR_c | PSR_x}, | |
8687 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
8688 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
8689 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
8690 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
8691 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
8692 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
8693 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
8694 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
8695 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
8696 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
8697 | {"scf", PSR_s | PSR_c | PSR_f}, | |
8698 | {"scx", PSR_s | PSR_c | PSR_x}, | |
8699 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
8700 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
8701 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
8702 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
8703 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
8704 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
8705 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
8706 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
8707 | {"csf", PSR_c | PSR_s | PSR_f}, | |
8708 | {"csx", PSR_c | PSR_s | PSR_x}, | |
8709 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
8710 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
8711 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
8712 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
8713 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
8714 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
8715 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
8716 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
8717 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
8718 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
8719 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
8720 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
8721 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
8722 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
8723 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
8724 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
8725 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
8726 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
8727 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
8728 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
8729 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
8730 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
8731 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
8732 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
8733 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
8734 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
8735 | }; | |
8736 | ||
62b3e311 PB |
8737 | /* Table of V7M psr names. */ |
8738 | static const struct asm_psr v7m_psrs[] = | |
8739 | { | |
8740 | {"apsr", 0 }, | |
8741 | {"iapsr", 1 }, | |
8742 | {"eapsr", 2 }, | |
8743 | {"psr", 3 }, | |
8744 | {"ipsr", 5 }, | |
8745 | {"epsr", 6 }, | |
8746 | {"iepsr", 7 }, | |
8747 | {"msp", 8 }, | |
8748 | {"psp", 9 }, | |
8749 | {"primask", 16}, | |
8750 | {"basepri", 17}, | |
8751 | {"basepri_max", 18}, | |
8752 | {"faultmask", 19}, | |
8753 | {"control", 20} | |
8754 | }; | |
8755 | ||
c19d1205 ZW |
8756 | /* Table of all shift-in-operand names. */ |
8757 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 8758 | { |
c19d1205 ZW |
8759 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
8760 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
8761 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
8762 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
8763 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
8764 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
8765 | }; | |
b99bd4ef | 8766 | |
c19d1205 ZW |
8767 | /* Table of all explicit relocation names. */ |
8768 | #ifdef OBJ_ELF | |
8769 | static struct reloc_entry reloc_names[] = | |
8770 | { | |
8771 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
8772 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
8773 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
8774 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
8775 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
8776 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
8777 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
8778 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
8779 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
8780 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
8781 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} | |
8782 | }; | |
8783 | #endif | |
b99bd4ef | 8784 | |
c19d1205 ZW |
8785 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
8786 | static const struct asm_cond conds[] = | |
8787 | { | |
8788 | {"eq", 0x0}, | |
8789 | {"ne", 0x1}, | |
8790 | {"cs", 0x2}, {"hs", 0x2}, | |
8791 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
8792 | {"mi", 0x4}, | |
8793 | {"pl", 0x5}, | |
8794 | {"vs", 0x6}, | |
8795 | {"vc", 0x7}, | |
8796 | {"hi", 0x8}, | |
8797 | {"ls", 0x9}, | |
8798 | {"ge", 0xa}, | |
8799 | {"lt", 0xb}, | |
8800 | {"gt", 0xc}, | |
8801 | {"le", 0xd}, | |
8802 | {"al", 0xe} | |
8803 | }; | |
bfae80f2 | 8804 | |
62b3e311 PB |
8805 | static struct asm_barrier_opt barrier_opt_names[] = |
8806 | { | |
8807 | { "sy", 0xf }, | |
8808 | { "un", 0x7 }, | |
8809 | { "st", 0xe }, | |
8810 | { "unst", 0x6 } | |
8811 | }; | |
8812 | ||
c19d1205 ZW |
8813 | /* Table of ARM-format instructions. */ |
8814 | ||
8815 | /* Macros for gluing together operand strings. N.B. In all cases | |
8816 | other than OPS0, the trailing OP_stop comes from default | |
8817 | zero-initialization of the unspecified elements of the array. */ | |
8818 | #define OPS0() { OP_stop, } | |
8819 | #define OPS1(a) { OP_##a, } | |
8820 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
8821 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
8822 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
8823 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
8824 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
8825 | ||
8826 | /* These macros abstract out the exact format of the mnemonic table and | |
8827 | save some repeated characters. */ | |
8828 | ||
8829 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
8830 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
8831 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 8832 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8833 | |
8834 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
8835 | a T_MNEM_xyz enumerator. */ | |
8836 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
8837 | TxCE(mnem, aop, 0x##top, nops, ops, ae, te) | |
8838 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ | |
8839 | TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
8840 | ||
8841 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
8842 | infix after the third character. */ | |
8843 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
8844 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 8845 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8846 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
8847 | TxC3(mnem, aop, 0x##top, nops, ops, ae, te) | |
8848 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ | |
8849 | TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
8850 | ||
8851 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
8852 | appear in the condition table. */ | |
8853 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
8854 | { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
1887dd22 | 8855 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8856 | |
8857 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
8858 | TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ | |
8859 | TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ | |
8860 | TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ | |
8861 | TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ | |
8862 | TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ | |
8863 | TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ | |
8864 | TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ | |
8865 | TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ | |
8866 | TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ | |
8867 | TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ | |
8868 | TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ | |
8869 | TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ | |
8870 | TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ | |
8871 | TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ | |
8872 | TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ | |
8873 | TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ | |
8874 | TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ | |
8875 | TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ | |
8876 | TxCM_(m1, al, m2, op, top, nops, ops, ae, te) | |
8877 | ||
8878 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
8879 | TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) | |
8880 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
8881 | TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) | |
8882 | ||
8883 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
8884 | field is still 0xE. Many of the Thumb variants can be executed |
8885 | conditionally, so this is checked separately. */ | |
c19d1205 ZW |
8886 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
8887 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 8888 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8889 | |
8890 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
8891 | condition code field. */ | |
8892 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
8893 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 8894 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8895 | |
8896 | /* ARM-only variants of all the above. */ | |
6a86118a NC |
8897 | #define CE(mnem, op, nops, ops, ae) \ |
8898 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8899 | ||
8900 | #define C3(mnem, op, nops, ops, ae) \ | |
8901 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8902 | ||
e3cb604e PB |
8903 | /* Legacy mnemonics that always have conditional infix after the third |
8904 | character. */ | |
8905 | #define CL(mnem, op, nops, ops, ae) \ | |
8906 | { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ | |
8907 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8908 | ||
8f06b2d8 PB |
8909 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
8910 | #define cCE(mnem, op, nops, ops, ae) \ | |
8911 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8912 | ||
e3cb604e PB |
8913 | /* Legacy coprocessor instructions where conditional infix and conditional |
8914 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
8915 | not just the potentially ambiguous ones. */ | |
8916 | #define cCL(mnem, op, nops, ops, ae) \ | |
8917 | { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ | |
8918 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8919 | ||
8920 | /* Coprocessor, takes either a suffix or a position-3 infix | |
8921 | (for an FPA corner case). */ | |
8922 | #define C3E(mnem, op, nops, ops, ae) \ | |
8923 | { #mnem, OPS##nops ops, OT_csuf_or_in3, \ | |
8924 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8f06b2d8 | 8925 | |
6a86118a NC |
8926 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
8927 | { #m1 #m2 #m3, OPS##nops ops, \ | |
8928 | sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
8929 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8930 | ||
8931 | #define CM(m1, m2, op, nops, ops, ae) \ | |
8932 | xCM_(m1, , m2, op, nops, ops, ae), \ | |
8933 | xCM_(m1, eq, m2, op, nops, ops, ae), \ | |
8934 | xCM_(m1, ne, m2, op, nops, ops, ae), \ | |
8935 | xCM_(m1, cs, m2, op, nops, ops, ae), \ | |
8936 | xCM_(m1, hs, m2, op, nops, ops, ae), \ | |
8937 | xCM_(m1, cc, m2, op, nops, ops, ae), \ | |
8938 | xCM_(m1, ul, m2, op, nops, ops, ae), \ | |
8939 | xCM_(m1, lo, m2, op, nops, ops, ae), \ | |
8940 | xCM_(m1, mi, m2, op, nops, ops, ae), \ | |
8941 | xCM_(m1, pl, m2, op, nops, ops, ae), \ | |
8942 | xCM_(m1, vs, m2, op, nops, ops, ae), \ | |
8943 | xCM_(m1, vc, m2, op, nops, ops, ae), \ | |
8944 | xCM_(m1, hi, m2, op, nops, ops, ae), \ | |
8945 | xCM_(m1, ls, m2, op, nops, ops, ae), \ | |
8946 | xCM_(m1, ge, m2, op, nops, ops, ae), \ | |
8947 | xCM_(m1, lt, m2, op, nops, ops, ae), \ | |
8948 | xCM_(m1, gt, m2, op, nops, ops, ae), \ | |
8949 | xCM_(m1, le, m2, op, nops, ops, ae), \ | |
8950 | xCM_(m1, al, m2, op, nops, ops, ae) | |
8951 | ||
8952 | #define UE(mnem, op, nops, ops, ae) \ | |
8953 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
8954 | ||
8955 | #define UF(mnem, op, nops, ops, ae) \ | |
8956 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
8957 | ||
c19d1205 ZW |
8958 | #define do_0 0 |
8959 | ||
8960 | /* Thumb-only, unconditional. */ | |
8961 | #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) | |
8962 | ||
c19d1205 | 8963 | static const struct asm_opcode insns[] = |
bfae80f2 | 8964 | { |
e74cfd16 PB |
8965 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
8966 | #define THUMB_VARIANT &arm_ext_v4t | |
c19d1205 ZW |
8967 | tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), |
8968 | tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
8969 | tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
8970 | tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
8971 | tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
8972 | tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
8973 | tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub), | |
8974 | tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub), | |
8975 | tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
8976 | tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
8977 | tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
8978 | tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
8979 | tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
8980 | tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
8981 | tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), | |
8982 | tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), | |
8983 | ||
8984 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
8985 | for setting PSR flag bits. They are obsolete in V6 and do not | |
8986 | have Thumb equivalents. */ | |
8987 | tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
8988 | tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
e3cb604e | 8989 | CL(tstp, 110f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
8990 | tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), |
8991 | tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
e3cb604e | 8992 | CL(cmpp, 150f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
8993 | tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), |
8994 | tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
e3cb604e | 8995 | CL(cmnp, 170f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
8996 | |
8997 | tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), | |
8998 | tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), | |
8999 | tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), | |
9000 | tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), | |
9001 | ||
9002 | tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst), | |
9003 | tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst), | |
9004 | tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst), | |
9005 | tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst), | |
9006 | ||
f5208ef2 | 9007 | tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
c19d1205 ZW |
9008 | tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
9009 | tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
f5208ef2 | 9010 | tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
c19d1205 ZW |
9011 | tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
9012 | tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
9013 | ||
9014 | TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), | |
c16d2bf0 | 9015 | TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), |
0110f2b8 | 9016 | tCE(b, a000000, b, 1, (EXPr), branch, t_branch), |
39b41c9c | 9017 | TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), |
bfae80f2 | 9018 | |
c19d1205 | 9019 | /* Pseudo ops. */ |
e9f89963 | 9020 | tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac ZW |
9021 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
9022 | tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), | |
c19d1205 ZW |
9023 | |
9024 | /* Thumb-compatibility pseudo ops. */ | |
9025 | tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), | |
9026 | tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), | |
9027 | tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), | |
9028 | tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
9029 | tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), | |
2fc8bdac | 9030 | tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), |
c19d1205 ZW |
9031 | tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), |
9032 | tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), | |
9033 | tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), | |
9034 | tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), | |
9035 | tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), | |
9036 | tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), | |
9037 | ||
9038 | #undef THUMB_VARIANT | |
e74cfd16 | 9039 | #define THUMB_VARIANT &arm_ext_v6 |
2fc8bdac | 9040 | TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
9041 | |
9042 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
9043 | #undef THUMB_VARIANT | |
e74cfd16 | 9044 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
9045 | TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
9046 | TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
9047 | TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
9048 | TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
e3cb604e | 9049 | CL(teqp, 130f000, 2, (RR, SH), cmp), |
c19d1205 ZW |
9050 | |
9051 | TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
3e94bf1a | 9052 | TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), |
c19d1205 | 9053 | TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), |
3e94bf1a | 9054 | TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), |
c19d1205 | 9055 | |
9c3c69f2 PB |
9056 | TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
9057 | TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 9058 | |
9c3c69f2 PB |
9059 | TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
9060 | TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
9061 | |
9062 | /* V1 instructions with no Thumb analogue at all. */ | |
9063 | CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), | |
9064 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), | |
9065 | ||
9066 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
9067 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
9068 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
9069 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
9070 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
9071 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
9072 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
9073 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
9074 | ||
9075 | #undef ARM_VARIANT | |
e74cfd16 | 9076 | #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ |
c19d1205 | 9077 | #undef THUMB_VARIANT |
e74cfd16 | 9078 | #define THUMB_VARIANT &arm_ext_v4t |
c19d1205 ZW |
9079 | tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
9080 | tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
9081 | ||
9082 | #undef THUMB_VARIANT | |
e74cfd16 | 9083 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
9084 | TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
9085 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), | |
9086 | ||
9087 | /* Generic coprocessor instructions. */ | |
9088 | TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
9089 | TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
9090 | TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
9091 | TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
9092 | TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
9093 | TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
9094 | TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
9095 | ||
9096 | #undef ARM_VARIANT | |
e74cfd16 | 9097 | #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ |
c19d1205 ZW |
9098 | CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
9099 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), | |
9100 | ||
9101 | #undef ARM_VARIANT | |
e74cfd16 | 9102 | #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ |
c19d1205 ZW |
9103 | TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs), |
9104 | TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr), | |
9105 | ||
9106 | #undef ARM_VARIANT | |
e74cfd16 | 9107 | #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ |
c19d1205 ZW |
9108 | TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
9109 | CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
9110 | TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
9111 | CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
9112 | TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
9113 | CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
9114 | TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
9115 | CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
9116 | ||
9117 | #undef ARM_VARIANT | |
e74cfd16 | 9118 | #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ |
c19d1205 | 9119 | #undef THUMB_VARIANT |
e74cfd16 | 9120 | #define THUMB_VARIANT &arm_ext_v4t |
c19d1205 ZW |
9121 | tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst), |
9122 | tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst), | |
9123 | tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst), | |
9124 | tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst), | |
9125 | tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst), | |
9126 | tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst), | |
9127 | ||
9128 | #undef ARM_VARIANT | |
e74cfd16 | 9129 | #define ARM_VARIANT &arm_ext_v4t_5 |
c19d1205 ZW |
9130 | /* ARM Architecture 4T. */ |
9131 | /* Note: bx (and blx) are required on V5, even if the processor does | |
9132 | not support Thumb. */ | |
9133 | TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), | |
9134 | ||
9135 | #undef ARM_VARIANT | |
e74cfd16 | 9136 | #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ |
c19d1205 | 9137 | #undef THUMB_VARIANT |
e74cfd16 | 9138 | #define THUMB_VARIANT &arm_ext_v5t |
c19d1205 ZW |
9139 | /* Note: blx has 2 variants; the .value coded here is for |
9140 | BLX(2). Only this variant has conditional execution. */ | |
9141 | TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), | |
9142 | TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
9143 | ||
9144 | #undef THUMB_VARIANT | |
e74cfd16 | 9145 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
9146 | TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
9147 | TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
9148 | TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
9149 | TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
9150 | TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
9151 | TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
9152 | TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
9153 | TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
9154 | ||
9155 | #undef ARM_VARIANT | |
e74cfd16 | 9156 | #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ |
c19d1205 ZW |
9157 | TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
9158 | TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
9159 | TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
9160 | TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
9161 | ||
9162 | TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
9163 | TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
9164 | ||
9165 | TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
9166 | TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
9167 | TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
9168 | TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
9169 | ||
9170 | TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9171 | TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9172 | TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9173 | TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9174 | ||
9175 | TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9176 | TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9177 | ||
9178 | TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
9179 | TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
9180 | TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
9181 | TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
9182 | ||
9183 | #undef ARM_VARIANT | |
e74cfd16 | 9184 | #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ |
c19d1205 ZW |
9185 | TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), |
9186 | TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd), | |
9187 | TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd), | |
9188 | ||
9189 | TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
9190 | TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
9191 | ||
9192 | #undef ARM_VARIANT | |
e74cfd16 | 9193 | #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ |
c19d1205 ZW |
9194 | TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
9195 | ||
9196 | #undef ARM_VARIANT | |
e74cfd16 | 9197 | #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ |
c19d1205 | 9198 | #undef THUMB_VARIANT |
e74cfd16 | 9199 | #define THUMB_VARIANT &arm_ext_v6 |
c19d1205 ZW |
9200 | TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
9201 | TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
9202 | tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
9203 | tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
9204 | tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
9205 | tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
9206 | tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
9207 | tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
9208 | tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
9209 | TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), | |
9210 | ||
9211 | #undef THUMB_VARIANT | |
e74cfd16 | 9212 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
9213 | TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), |
9214 | TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
9215 | TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 PB |
9216 | |
9217 | TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), | |
9218 | TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
9219 | ||
9220 | /* ARM V6 not included in V7M (eg. integer SIMD). */ | |
9221 | #undef THUMB_VARIANT | |
9222 | #define THUMB_VARIANT &arm_ext_v6_notm | |
dfa9f0d5 | 9223 | TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
c19d1205 ZW |
9224 | TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), |
9225 | TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
9226 | TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9227 | TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9228 | TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9229 | TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9230 | TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9231 | TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9232 | TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9233 | TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9234 | TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9235 | TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9236 | TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9237 | TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9238 | TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9239 | TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9240 | TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9241 | TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9242 | TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9243 | TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9244 | TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9245 | TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9246 | TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9247 | TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9248 | TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9249 | TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9250 | TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9251 | TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9252 | TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9253 | TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9254 | TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9255 | TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9256 | TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9257 | TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9258 | TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9259 | TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9260 | TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9261 | TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
9262 | TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
9263 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
9264 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
9265 | TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
9266 | TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
9267 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
9268 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
9269 | TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
9270 | TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9271 | TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9272 | TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9273 | TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
9274 | TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9275 | TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9276 | TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
9277 | TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
f1022c90 | 9278 | TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
c19d1205 ZW |
9279 | TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), |
9280 | TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9281 | TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
9282 | TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
9283 | TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9284 | TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9285 | TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
9286 | TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
9287 | TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9288 | TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9289 | TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9290 | TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
9291 | TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9292 | TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9293 | TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9294 | TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9295 | TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9296 | TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9297 | TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs), | |
9298 | UF(srsib, 9cd0500, 1, (I31w), srs), | |
9299 | UF(srsda, 84d0500, 1, (I31w), srs), | |
9300 | TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs), | |
c19d1205 ZW |
9301 | TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
9302 | TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), | |
9303 | TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
9304 | TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
9305 | TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
c19d1205 ZW |
9306 | TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), |
9307 | ||
9308 | #undef ARM_VARIANT | |
e74cfd16 | 9309 | #define ARM_VARIANT &arm_ext_v6k |
c19d1205 | 9310 | #undef THUMB_VARIANT |
e74cfd16 | 9311 | #define THUMB_VARIANT &arm_ext_v6k |
c19d1205 ZW |
9312 | tCE(yield, 320f001, yield, 0, (), noargs, t_hint), |
9313 | tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), | |
9314 | tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), | |
9315 | tCE(sev, 320f004, sev, 0, (), noargs, t_hint), | |
9316 | ||
ebdca51a PB |
9317 | #undef THUMB_VARIANT |
9318 | #define THUMB_VARIANT &arm_ext_v6_notm | |
9319 | TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), | |
9320 | TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), | |
9321 | ||
c19d1205 | 9322 | #undef THUMB_VARIANT |
e74cfd16 | 9323 | #define THUMB_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
9324 | TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), |
9325 | TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
c19d1205 ZW |
9326 | TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), |
9327 | TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
c19d1205 ZW |
9328 | TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
9329 | ||
9330 | #undef ARM_VARIANT | |
e74cfd16 | 9331 | #define ARM_VARIANT &arm_ext_v6z |
3eb17e6b | 9332 | TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 ZW |
9333 | |
9334 | #undef ARM_VARIANT | |
e74cfd16 | 9335 | #define ARM_VARIANT &arm_ext_v6t2 |
c19d1205 ZW |
9336 | TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
9337 | TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
9338 | TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
9339 | TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
9340 | ||
9341 | TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), | |
9342 | TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16), | |
9343 | TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16), | |
9344 | TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
9345 | ||
9346 | TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
9347 | TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
9348 | TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
9349 | TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
9350 | ||
9351 | UT(cbnz, b900, 2, (RR, EXP), t_czb), | |
9352 | UT(cbz, b100, 2, (RR, EXP), t_czb), | |
9353 | /* ARM does not really have an IT instruction. */ | |
9354 | TUE(it, 0, bf08, 1, (COND), it, t_it), | |
9355 | TUE(itt, 0, bf0c, 1, (COND), it, t_it), | |
9356 | TUE(ite, 0, bf04, 1, (COND), it, t_it), | |
9357 | TUE(ittt, 0, bf0e, 1, (COND), it, t_it), | |
9358 | TUE(itet, 0, bf06, 1, (COND), it, t_it), | |
9359 | TUE(itte, 0, bf0a, 1, (COND), it, t_it), | |
9360 | TUE(itee, 0, bf02, 1, (COND), it, t_it), | |
9361 | TUE(itttt, 0, bf0f, 1, (COND), it, t_it), | |
9362 | TUE(itett, 0, bf07, 1, (COND), it, t_it), | |
9363 | TUE(ittet, 0, bf0b, 1, (COND), it, t_it), | |
9364 | TUE(iteet, 0, bf03, 1, (COND), it, t_it), | |
9365 | TUE(ittte, 0, bf0d, 1, (COND), it, t_it), | |
9366 | TUE(itete, 0, bf05, 1, (COND), it, t_it), | |
9367 | TUE(ittee, 0, bf09, 1, (COND), it, t_it), | |
9368 | TUE(iteee, 0, bf01, 1, (COND), it, t_it), | |
9369 | ||
92e90b6e PB |
9370 | /* Thumb2 only instructions. */ |
9371 | #undef ARM_VARIANT | |
e74cfd16 | 9372 | #define ARM_VARIANT NULL |
92e90b6e PB |
9373 | |
9374 | TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
9375 | TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
9376 | TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), | |
9377 | TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), | |
9378 | ||
62b3e311 PB |
9379 | /* Thumb-2 hardware division instructions (R and M profiles only). */ |
9380 | #undef THUMB_VARIANT | |
9381 | #define THUMB_VARIANT &arm_ext_div | |
9382 | TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), | |
9383 | TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), | |
9384 | ||
9385 | /* ARM V7 instructions. */ | |
9386 | #undef ARM_VARIANT | |
9387 | #define ARM_VARIANT &arm_ext_v7 | |
9388 | #undef THUMB_VARIANT | |
9389 | #define THUMB_VARIANT &arm_ext_v7 | |
9390 | TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), | |
9391 | TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
9392 | TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), | |
9393 | TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), | |
9394 | TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), | |
9395 | ||
c19d1205 | 9396 | #undef ARM_VARIANT |
e74cfd16 | 9397 | #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ |
8f06b2d8 PB |
9398 | cCE(wfs, e200110, 1, (RR), rd), |
9399 | cCE(rfs, e300110, 1, (RR), rd), | |
9400 | cCE(wfc, e400110, 1, (RR), rd), | |
9401 | cCE(rfc, e500110, 1, (RR), rd), | |
9402 | ||
e3cb604e PB |
9403 | cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr), |
9404 | cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr), | |
9405 | cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr), | |
9406 | cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr), | |
9407 | ||
9408 | cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr), | |
9409 | cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr), | |
9410 | cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr), | |
9411 | cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr), | |
9412 | ||
9413 | cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), | |
9414 | cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), | |
9415 | cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), | |
9416 | cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), | |
9417 | cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), | |
9418 | cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), | |
9419 | cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), | |
9420 | cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), | |
9421 | cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), | |
9422 | cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), | |
9423 | cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), | |
9424 | cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), | |
9425 | ||
9426 | cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), | |
9427 | cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), | |
9428 | cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), | |
9429 | cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), | |
9430 | cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), | |
9431 | cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), | |
9432 | cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), | |
9433 | cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), | |
9434 | cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), | |
9435 | cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), | |
9436 | cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), | |
9437 | cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), | |
9438 | ||
9439 | cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), | |
9440 | cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), | |
9441 | cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), | |
9442 | cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), | |
9443 | cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), | |
9444 | cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), | |
9445 | cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), | |
9446 | cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), | |
9447 | cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), | |
9448 | cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), | |
9449 | cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), | |
9450 | cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), | |
9451 | ||
9452 | cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), | |
9453 | cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), | |
9454 | cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), | |
9455 | cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), | |
9456 | cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), | |
9457 | cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), | |
9458 | cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), | |
9459 | cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), | |
9460 | cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), | |
9461 | cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), | |
9462 | cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), | |
9463 | cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), | |
9464 | ||
9465 | cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), | |
9466 | cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), | |
9467 | cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), | |
9468 | cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), | |
9469 | cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), | |
9470 | cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), | |
9471 | cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), | |
9472 | cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), | |
9473 | cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), | |
9474 | cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), | |
9475 | cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), | |
9476 | cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), | |
9477 | ||
9478 | cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), | |
9479 | cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), | |
9480 | cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), | |
9481 | cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), | |
9482 | cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), | |
9483 | cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), | |
9484 | cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), | |
9485 | cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), | |
9486 | cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), | |
9487 | cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), | |
9488 | cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), | |
9489 | cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), | |
9490 | ||
9491 | cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), | |
9492 | cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), | |
9493 | cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), | |
9494 | cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), | |
9495 | cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), | |
9496 | cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), | |
9497 | cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), | |
9498 | cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), | |
9499 | cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), | |
9500 | cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), | |
9501 | cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), | |
9502 | cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), | |
9503 | ||
9504 | cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), | |
9505 | cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), | |
9506 | cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), | |
9507 | cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), | |
9508 | cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), | |
9509 | cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), | |
9510 | cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), | |
9511 | cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), | |
9512 | cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), | |
9513 | cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), | |
9514 | cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), | |
9515 | cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), | |
9516 | ||
9517 | cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), | |
9518 | cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), | |
9519 | cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), | |
9520 | cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), | |
9521 | cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), | |
9522 | cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), | |
9523 | cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), | |
9524 | cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), | |
9525 | cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), | |
9526 | cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), | |
9527 | cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), | |
9528 | cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), | |
9529 | ||
9530 | cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), | |
9531 | cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), | |
9532 | cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), | |
9533 | cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), | |
9534 | cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), | |
9535 | cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), | |
9536 | cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), | |
9537 | cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), | |
9538 | cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), | |
9539 | cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), | |
9540 | cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), | |
9541 | cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), | |
9542 | ||
9543 | cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), | |
9544 | cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), | |
9545 | cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), | |
9546 | cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), | |
9547 | cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), | |
9548 | cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), | |
9549 | cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), | |
9550 | cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), | |
9551 | cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), | |
9552 | cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), | |
9553 | cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), | |
9554 | cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), | |
9555 | ||
9556 | cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), | |
9557 | cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), | |
9558 | cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), | |
9559 | cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), | |
9560 | cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), | |
9561 | cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), | |
9562 | cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), | |
9563 | cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), | |
9564 | cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), | |
9565 | cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), | |
9566 | cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), | |
9567 | cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), | |
9568 | ||
9569 | cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), | |
9570 | cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), | |
9571 | cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), | |
9572 | cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), | |
9573 | cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), | |
9574 | cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), | |
9575 | cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), | |
9576 | cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), | |
9577 | cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), | |
9578 | cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), | |
9579 | cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), | |
9580 | cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), | |
9581 | ||
9582 | cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), | |
9583 | cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), | |
9584 | cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), | |
9585 | cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), | |
9586 | cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), | |
9587 | cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), | |
9588 | cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), | |
9589 | cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), | |
9590 | cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), | |
9591 | cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), | |
9592 | cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), | |
9593 | cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), | |
9594 | ||
9595 | cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), | |
9596 | cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), | |
9597 | cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), | |
9598 | cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), | |
9599 | cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), | |
9600 | cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), | |
9601 | cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), | |
9602 | cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), | |
9603 | cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), | |
9604 | cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), | |
9605 | cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), | |
9606 | cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), | |
9607 | ||
9608 | cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), | |
9609 | cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), | |
9610 | cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), | |
9611 | cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), | |
9612 | cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), | |
9613 | cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), | |
9614 | cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), | |
9615 | cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), | |
9616 | cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), | |
9617 | cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), | |
9618 | cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), | |
9619 | cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), | |
9620 | ||
9621 | cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9622 | cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9623 | cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9624 | cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9625 | cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9626 | cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9627 | cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9628 | cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9629 | cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9630 | cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9631 | cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9632 | cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9633 | ||
9634 | cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9635 | cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9636 | cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9637 | cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9638 | cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9639 | cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9640 | cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9641 | cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9642 | cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9643 | cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9644 | cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9645 | cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9646 | ||
9647 | cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9648 | cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9649 | cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9650 | cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9651 | cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9652 | cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9653 | cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9654 | cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9655 | cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9656 | cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9657 | cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9658 | cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9659 | ||
9660 | cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9661 | cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9662 | cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9663 | cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9664 | cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9665 | cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9666 | cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9667 | cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9668 | cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9669 | cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9670 | cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9671 | cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9672 | ||
9673 | cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9674 | cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9675 | cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9676 | cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9677 | cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9678 | cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9679 | cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9680 | cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9681 | cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9682 | cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9683 | cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9684 | cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9685 | ||
9686 | cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9687 | cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9688 | cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9689 | cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9690 | cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9691 | cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9692 | cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9693 | cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9694 | cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9695 | cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9696 | cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9697 | cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9698 | ||
9699 | cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9700 | cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9701 | cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9702 | cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9703 | cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9704 | cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9705 | cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9706 | cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9707 | cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9708 | cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9709 | cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9710 | cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9711 | ||
9712 | cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9713 | cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9714 | cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9715 | cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9716 | cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9717 | cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9718 | cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9719 | cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9720 | cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9721 | cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9722 | cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9723 | cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9724 | ||
9725 | cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9726 | cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9727 | cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9728 | cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9729 | cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9730 | cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9731 | cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9732 | cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9733 | cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9734 | cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9735 | cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9736 | cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9737 | ||
9738 | cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9739 | cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9740 | cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9741 | cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9742 | cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9743 | cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9744 | cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9745 | cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9746 | cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9747 | cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9748 | cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9749 | cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9750 | ||
9751 | cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9752 | cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9753 | cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9754 | cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9755 | cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9756 | cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9757 | cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9758 | cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9759 | cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9760 | cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9761 | cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9762 | cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9763 | ||
9764 | cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9765 | cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9766 | cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9767 | cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9768 | cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9769 | cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9770 | cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9771 | cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9772 | cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9773 | cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9774 | cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9775 | cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9776 | ||
9777 | cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9778 | cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9779 | cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9780 | cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9781 | cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9782 | cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9783 | cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9784 | cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9785 | cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9786 | cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9787 | cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9788 | cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
8f06b2d8 PB |
9789 | |
9790 | cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), | |
c19d1205 | 9791 | C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), |
8f06b2d8 | 9792 | cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), |
c19d1205 ZW |
9793 | C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), |
9794 | ||
e3cb604e PB |
9795 | cCL(flts, e000110, 2, (RF, RR), rn_rd), |
9796 | cCL(fltsp, e000130, 2, (RF, RR), rn_rd), | |
9797 | cCL(fltsm, e000150, 2, (RF, RR), rn_rd), | |
9798 | cCL(fltsz, e000170, 2, (RF, RR), rn_rd), | |
9799 | cCL(fltd, e000190, 2, (RF, RR), rn_rd), | |
9800 | cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), | |
9801 | cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), | |
9802 | cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), | |
9803 | cCL(flte, e080110, 2, (RF, RR), rn_rd), | |
9804 | cCL(fltep, e080130, 2, (RF, RR), rn_rd), | |
9805 | cCL(fltem, e080150, 2, (RF, RR), rn_rd), | |
9806 | cCL(fltez, e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 9807 | |
c19d1205 ZW |
9808 | /* The implementation of the FIX instruction is broken on some |
9809 | assemblers, in that it accepts a precision specifier as well as a | |
9810 | rounding specifier, despite the fact that this is meaningless. | |
9811 | To be more compatible, we accept it as well, though of course it | |
9812 | does not set any bits. */ | |
8f06b2d8 | 9813 | cCE(fix, e100110, 2, (RR, RF), rd_rm), |
e3cb604e PB |
9814 | cCL(fixp, e100130, 2, (RR, RF), rd_rm), |
9815 | cCL(fixm, e100150, 2, (RR, RF), rd_rm), | |
9816 | cCL(fixz, e100170, 2, (RR, RF), rd_rm), | |
9817 | cCL(fixsp, e100130, 2, (RR, RF), rd_rm), | |
9818 | cCL(fixsm, e100150, 2, (RR, RF), rd_rm), | |
9819 | cCL(fixsz, e100170, 2, (RR, RF), rd_rm), | |
9820 | cCL(fixdp, e100130, 2, (RR, RF), rd_rm), | |
9821 | cCL(fixdm, e100150, 2, (RR, RF), rd_rm), | |
9822 | cCL(fixdz, e100170, 2, (RR, RF), rd_rm), | |
9823 | cCL(fixep, e100130, 2, (RR, RF), rd_rm), | |
9824 | cCL(fixem, e100150, 2, (RR, RF), rd_rm), | |
9825 | cCL(fixez, e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 9826 | |
c19d1205 ZW |
9827 | /* Instructions that were new with the real FPA, call them V2. */ |
9828 | #undef ARM_VARIANT | |
e74cfd16 | 9829 | #define ARM_VARIANT &fpu_fpa_ext_v2 |
8f06b2d8 | 9830 | cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
e3cb604e PB |
9831 | cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
9832 | cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
8f06b2d8 | 9833 | cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
e3cb604e PB |
9834 | cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
9835 | cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 ZW |
9836 | |
9837 | #undef ARM_VARIANT | |
e74cfd16 | 9838 | #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ |
c19d1205 | 9839 | /* Moves and type conversions. */ |
8f06b2d8 PB |
9840 | cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
9841 | cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
9842 | cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
9843 | cCE(fmstat, ef1fa10, 0, (), noargs), | |
9844 | cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9845 | cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9846 | cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9847 | cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9848 | cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9849 | cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9850 | cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), | |
9851 | cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
9852 | |
9853 | /* Memory operations. */ | |
8f06b2d8 PB |
9854 | cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst), |
9855 | cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst), | |
9856 | cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9857 | cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9858 | cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9859 | cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9860 | cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9861 | cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9862 | cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9863 | cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9864 | cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9865 | cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9866 | cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9867 | cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9868 | cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9869 | cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9870 | cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9871 | cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 9872 | |
c19d1205 | 9873 | /* Monadic operations. */ |
8f06b2d8 PB |
9874 | cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
9875 | cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9876 | cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
9877 | |
9878 | /* Dyadic operations. */ | |
8f06b2d8 PB |
9879 | cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
9880 | cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9881 | cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9882 | cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9883 | cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9884 | cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9885 | cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9886 | cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9887 | cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 9888 | |
c19d1205 | 9889 | /* Comparisons. */ |
8f06b2d8 PB |
9890 | cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
9891 | cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), | |
9892 | cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9893 | cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 9894 | |
c19d1205 | 9895 | #undef ARM_VARIANT |
e74cfd16 | 9896 | #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ |
c19d1205 | 9897 | /* Moves and type conversions. */ |
8f06b2d8 PB |
9898 | cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm), |
9899 | cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9900 | cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9901 | cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd), | |
9902 | cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd), | |
9903 | cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn), | |
9904 | cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn), | |
9905 | cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9906 | cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9907 | cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9908 | cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9909 | cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9910 | cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 ZW |
9911 | |
9912 | /* Memory operations. */ | |
8f06b2d8 PB |
9913 | cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst), |
9914 | cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst), | |
9915 | cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9916 | cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9917 | cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9918 | cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9919 | cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9920 | cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9921 | cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9922 | cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
b99bd4ef | 9923 | |
c19d1205 | 9924 | /* Monadic operations. */ |
8f06b2d8 PB |
9925 | cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm), |
9926 | cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm), | |
9927 | cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm), | |
c19d1205 ZW |
9928 | |
9929 | /* Dyadic operations. */ | |
8f06b2d8 PB |
9930 | cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm), |
9931 | cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9932 | cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9933 | cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9934 | cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9935 | cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9936 | cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9937 | cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9938 | cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
b99bd4ef | 9939 | |
c19d1205 | 9940 | /* Comparisons. */ |
8f06b2d8 PB |
9941 | cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm), |
9942 | cCE(fcmpzd, eb50b40, 1, (RVD), rd), | |
9943 | cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm), | |
9944 | cCE(fcmpezd, eb50bc0, 1, (RVD), rd), | |
c19d1205 ZW |
9945 | |
9946 | #undef ARM_VARIANT | |
e74cfd16 | 9947 | #define ARM_VARIANT &fpu_vfp_ext_v2 |
8f06b2d8 PB |
9948 | cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
9949 | cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
9950 | cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn), | |
9951 | cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm), | |
c19d1205 ZW |
9952 | |
9953 | #undef ARM_VARIANT | |
e74cfd16 | 9954 | #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ |
8f06b2d8 PB |
9955 | cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
9956 | cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9957 | cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9958 | cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9959 | cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9960 | cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9961 | cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
9962 | cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 ZW |
9963 | |
9964 | #undef ARM_VARIANT | |
e74cfd16 | 9965 | #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ |
8f06b2d8 PB |
9966 | cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), |
9967 | cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), | |
9968 | cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), | |
9969 | cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), | |
9970 | cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), | |
9971 | cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), | |
9972 | cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), | |
9973 | cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), | |
9974 | cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), | |
9975 | cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9976 | cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9977 | cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9978 | cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9979 | cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9980 | cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9981 | cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9982 | cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9983 | cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9984 | cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd), | |
9985 | cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
9986 | cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9987 | cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9988 | cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9989 | cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9990 | cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9991 | cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9992 | cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), | |
9993 | cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), | |
9994 | cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), | |
9995 | cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn), | |
9996 | cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
9997 | cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), | |
9998 | cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), | |
9999 | cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), | |
10000 | cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), | |
10001 | cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), | |
10002 | cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), | |
10003 | cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10004 | cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10005 | cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10006 | cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10007 | cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10008 | cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10009 | cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10010 | cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10011 | cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10012 | cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
10013 | cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10014 | cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10015 | cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10016 | cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10017 | cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10018 | cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10019 | cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10020 | cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10021 | cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10022 | cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10023 | cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10024 | cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10025 | cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10026 | cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10027 | cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10028 | cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10029 | cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10030 | cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10031 | cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10032 | cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
10033 | cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
10034 | cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
10035 | cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
10036 | cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10037 | cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10038 | cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10039 | cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10040 | cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10041 | cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10042 | cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10043 | cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10044 | cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10045 | cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10046 | cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10047 | cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10048 | cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10049 | cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10050 | cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10051 | cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10052 | cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10053 | cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10054 | cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
10055 | cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10056 | cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10057 | cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10058 | cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10059 | cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10060 | cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10061 | cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10062 | cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10063 | cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10064 | cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10065 | cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10066 | cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10067 | cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10068 | cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10069 | cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10070 | cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10071 | cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10072 | cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10073 | cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10074 | cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10075 | cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10076 | cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
10077 | cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10078 | cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10079 | cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10080 | cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10081 | cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10082 | cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10083 | cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10084 | cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10085 | cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10086 | cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10087 | cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10088 | cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10089 | cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10090 | cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10091 | cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10092 | cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10093 | cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10094 | cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
10095 | cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
10096 | cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
10097 | cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
10098 | cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
10099 | cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10100 | cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10101 | cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10102 | cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10103 | cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10104 | cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10105 | cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10106 | cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10107 | cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10108 | cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), | |
10109 | cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), | |
10110 | cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), | |
10111 | cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), | |
10112 | cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), | |
10113 | cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), | |
10114 | cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10115 | cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10116 | cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10117 | cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), | |
10118 | cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), | |
10119 | cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), | |
10120 | cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), | |
10121 | cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), | |
10122 | cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), | |
10123 | cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10124 | cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10125 | cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10126 | cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
10127 | cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 ZW |
10128 | |
10129 | #undef ARM_VARIANT | |
e74cfd16 | 10130 | #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ |
8f06b2d8 PB |
10131 | cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr), |
10132 | cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr), | |
10133 | cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr), | |
10134 | cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr), | |
10135 | cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr), | |
10136 | cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr), | |
10137 | cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr), | |
10138 | cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr), | |
10139 | cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), | |
10140 | cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), | |
10141 | cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), | |
10142 | cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), | |
10143 | cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), | |
10144 | cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), | |
10145 | cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), | |
10146 | cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), | |
10147 | cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), | |
10148 | cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), | |
10149 | cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), | |
10150 | cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), | |
10151 | cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), | |
10152 | cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), | |
10153 | cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), | |
10154 | cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), | |
10155 | cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), | |
10156 | cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), | |
10157 | cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), | |
10158 | cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), | |
10159 | cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
10160 | cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), | |
10161 | cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), | |
10162 | cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), | |
10163 | cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), | |
10164 | cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), | |
10165 | cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), | |
10166 | cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), | |
10167 | cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), | |
10168 | cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), | |
10169 | cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), | |
10170 | cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), | |
10171 | cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), | |
10172 | cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), | |
10173 | cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
10174 | cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
10175 | cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
10176 | cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
10177 | cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
10178 | cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
10179 | cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
10180 | cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
10181 | cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), | |
10182 | cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), | |
10183 | cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), | |
10184 | cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), | |
10185 | cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
10186 | cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
10187 | cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
10188 | cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
10189 | cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
10190 | cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
10191 | cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), | |
10192 | cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), | |
10193 | cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), | |
10194 | cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), | |
10195 | cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
10196 | cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
10197 | cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
10198 | cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
10199 | cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
10200 | cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
10201 | cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
10202 | cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
10203 | cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
10204 | cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
10205 | cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
10206 | cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
10207 | }; |
10208 | #undef ARM_VARIANT | |
10209 | #undef THUMB_VARIANT | |
10210 | #undef TCE | |
10211 | #undef TCM | |
10212 | #undef TUE | |
10213 | #undef TUF | |
10214 | #undef TCC | |
8f06b2d8 | 10215 | #undef cCE |
e3cb604e PB |
10216 | #undef cCL |
10217 | #undef C3E | |
c19d1205 ZW |
10218 | #undef CE |
10219 | #undef CM | |
10220 | #undef UE | |
10221 | #undef UF | |
10222 | #undef UT | |
10223 | #undef OPS0 | |
10224 | #undef OPS1 | |
10225 | #undef OPS2 | |
10226 | #undef OPS3 | |
10227 | #undef OPS4 | |
10228 | #undef OPS5 | |
10229 | #undef OPS6 | |
10230 | #undef do_0 | |
10231 | \f | |
10232 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 10233 | |
c19d1205 ZW |
10234 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
10235 | for use in the a.out file, and stores them in the array pointed to by buf. | |
10236 | This knows about the endian-ness of the target machine and does | |
10237 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
10238 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
10239 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 10240 | |
c19d1205 ZW |
10241 | void |
10242 | md_number_to_chars (char * buf, valueT val, int n) | |
10243 | { | |
10244 | if (target_big_endian) | |
10245 | number_to_chars_bigendian (buf, val, n); | |
10246 | else | |
10247 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
10248 | } |
10249 | ||
c19d1205 ZW |
10250 | static valueT |
10251 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 10252 | { |
c19d1205 ZW |
10253 | valueT result = 0; |
10254 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 10255 | |
c19d1205 | 10256 | if (target_big_endian) |
b99bd4ef | 10257 | { |
c19d1205 ZW |
10258 | while (n--) |
10259 | { | |
10260 | result <<= 8; | |
10261 | result |= (*where++ & 255); | |
10262 | } | |
b99bd4ef | 10263 | } |
c19d1205 | 10264 | else |
b99bd4ef | 10265 | { |
c19d1205 ZW |
10266 | while (n--) |
10267 | { | |
10268 | result <<= 8; | |
10269 | result |= (where[n] & 255); | |
10270 | } | |
bfae80f2 | 10271 | } |
b99bd4ef | 10272 | |
c19d1205 | 10273 | return result; |
bfae80f2 | 10274 | } |
b99bd4ef | 10275 | |
c19d1205 | 10276 | /* MD interface: Sections. */ |
b99bd4ef | 10277 | |
0110f2b8 PB |
10278 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
10279 | 2 bytes. */ | |
10280 | ||
c19d1205 | 10281 | int |
0110f2b8 | 10282 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
10283 | segT segtype ATTRIBUTE_UNUSED) |
10284 | { | |
0110f2b8 PB |
10285 | fragp->fr_var = 2; |
10286 | return 2; | |
10287 | } | |
10288 | ||
10289 | /* Convert a machine dependent frag. */ | |
10290 | ||
10291 | void | |
10292 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
10293 | { | |
10294 | unsigned long insn; | |
10295 | unsigned long old_op; | |
10296 | char *buf; | |
10297 | expressionS exp; | |
10298 | fixS *fixp; | |
10299 | int reloc_type; | |
10300 | int pc_rel; | |
10301 | int opcode; | |
10302 | ||
10303 | buf = fragp->fr_literal + fragp->fr_fix; | |
10304 | ||
10305 | old_op = bfd_get_16(abfd, buf); | |
10306 | if (fragp->fr_symbol) { | |
10307 | exp.X_op = O_symbol; | |
10308 | exp.X_add_symbol = fragp->fr_symbol; | |
10309 | } else { | |
10310 | exp.X_op = O_constant; | |
10311 | } | |
10312 | exp.X_add_number = fragp->fr_offset; | |
10313 | opcode = fragp->fr_subtype; | |
10314 | switch (opcode) | |
10315 | { | |
10316 | case T_MNEM_ldr_pc: | |
10317 | case T_MNEM_ldr_pc2: | |
10318 | case T_MNEM_ldr_sp: | |
10319 | case T_MNEM_str_sp: | |
10320 | case T_MNEM_ldr: | |
10321 | case T_MNEM_ldrb: | |
10322 | case T_MNEM_ldrh: | |
10323 | case T_MNEM_str: | |
10324 | case T_MNEM_strb: | |
10325 | case T_MNEM_strh: | |
10326 | if (fragp->fr_var == 4) | |
10327 | { | |
10328 | insn = THUMB_OP32(opcode); | |
10329 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) | |
10330 | { | |
10331 | insn |= (old_op & 0x700) << 4; | |
10332 | } | |
10333 | else | |
10334 | { | |
10335 | insn |= (old_op & 7) << 12; | |
10336 | insn |= (old_op & 0x38) << 13; | |
10337 | } | |
10338 | insn |= 0x00000c00; | |
10339 | put_thumb32_insn (buf, insn); | |
10340 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
10341 | } | |
10342 | else | |
10343 | { | |
10344 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10345 | } | |
10346 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
10347 | break; | |
10348 | case T_MNEM_adr: | |
10349 | if (fragp->fr_var == 4) | |
10350 | { | |
10351 | insn = THUMB_OP32 (opcode); | |
10352 | insn |= (old_op & 0xf0) << 4; | |
10353 | put_thumb32_insn (buf, insn); | |
10354 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
10355 | } | |
10356 | else | |
10357 | { | |
10358 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
10359 | exp.X_add_number -= 4; | |
10360 | } | |
10361 | pc_rel = 1; | |
10362 | break; | |
10363 | case T_MNEM_mov: | |
10364 | case T_MNEM_movs: | |
10365 | case T_MNEM_cmp: | |
10366 | case T_MNEM_cmn: | |
10367 | if (fragp->fr_var == 4) | |
10368 | { | |
10369 | int r0off = (opcode == T_MNEM_mov | |
10370 | || opcode == T_MNEM_movs) ? 0 : 8; | |
10371 | insn = THUMB_OP32 (opcode); | |
10372 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
10373 | insn |= (old_op & 0x700) << r0off; | |
10374 | put_thumb32_insn (buf, insn); | |
10375 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10376 | } | |
10377 | else | |
10378 | { | |
10379 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
10380 | } | |
10381 | pc_rel = 0; | |
10382 | break; | |
10383 | case T_MNEM_b: | |
10384 | if (fragp->fr_var == 4) | |
10385 | { | |
10386 | insn = THUMB_OP32(opcode); | |
10387 | put_thumb32_insn (buf, insn); | |
10388 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
10389 | } | |
10390 | else | |
10391 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
10392 | pc_rel = 1; | |
10393 | break; | |
10394 | case T_MNEM_bcond: | |
10395 | if (fragp->fr_var == 4) | |
10396 | { | |
10397 | insn = THUMB_OP32(opcode); | |
10398 | insn |= (old_op & 0xf00) << 14; | |
10399 | put_thumb32_insn (buf, insn); | |
10400 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
10401 | } | |
10402 | else | |
10403 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
10404 | pc_rel = 1; | |
10405 | break; | |
10406 | case T_MNEM_add_sp: | |
10407 | case T_MNEM_add_pc: | |
10408 | case T_MNEM_inc_sp: | |
10409 | case T_MNEM_dec_sp: | |
10410 | if (fragp->fr_var == 4) | |
10411 | { | |
10412 | /* ??? Choose between add and addw. */ | |
10413 | insn = THUMB_OP32 (opcode); | |
10414 | insn |= (old_op & 0xf0) << 4; | |
10415 | put_thumb32_insn (buf, insn); | |
10416 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10417 | } | |
10418 | else | |
10419 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
10420 | pc_rel = 0; | |
10421 | break; | |
10422 | ||
10423 | case T_MNEM_addi: | |
10424 | case T_MNEM_addis: | |
10425 | case T_MNEM_subi: | |
10426 | case T_MNEM_subis: | |
10427 | if (fragp->fr_var == 4) | |
10428 | { | |
10429 | insn = THUMB_OP32 (opcode); | |
10430 | insn |= (old_op & 0xf0) << 4; | |
10431 | insn |= (old_op & 0xf) << 16; | |
10432 | put_thumb32_insn (buf, insn); | |
10433 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
10434 | } | |
10435 | else | |
10436 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
10437 | pc_rel = 0; | |
10438 | break; | |
10439 | default: | |
10440 | abort(); | |
10441 | } | |
10442 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
10443 | reloc_type); | |
10444 | fixp->fx_file = fragp->fr_file; | |
10445 | fixp->fx_line = fragp->fr_line; | |
10446 | fragp->fr_fix += fragp->fr_var; | |
10447 | } | |
10448 | ||
10449 | /* Return the size of a relaxable immediate operand instruction. | |
10450 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
10451 | static int | |
10452 | relax_immediate (fragS *fragp, int size, int shift) | |
10453 | { | |
10454 | offsetT offset; | |
10455 | offsetT mask; | |
10456 | offsetT low; | |
10457 | ||
10458 | /* ??? Should be able to do better than this. */ | |
10459 | if (fragp->fr_symbol) | |
10460 | return 4; | |
10461 | ||
10462 | low = (1 << shift) - 1; | |
10463 | mask = (1 << (shift + size)) - (1 << shift); | |
10464 | offset = fragp->fr_offset; | |
10465 | /* Force misaligned offsets to 32-bit variant. */ | |
10466 | if (offset & low) | |
10467 | return -4; | |
10468 | if (offset & ~mask) | |
10469 | return 4; | |
10470 | return 2; | |
10471 | } | |
10472 | ||
10473 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative | |
10474 | load. */ | |
10475 | static int | |
10476 | relax_adr (fragS *fragp, asection *sec) | |
10477 | { | |
10478 | addressT addr; | |
10479 | offsetT val; | |
10480 | ||
10481 | /* Assume worst case for symbols not known to be in the same section. */ | |
10482 | if (!S_IS_DEFINED(fragp->fr_symbol) | |
10483 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) | |
10484 | return 4; | |
10485 | ||
10486 | val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset; | |
10487 | addr = fragp->fr_address + fragp->fr_fix; | |
10488 | addr = (addr + 4) & ~3; | |
10489 | /* Fix the insn as the 4-byte version if the target address is not | |
10490 | sufficiently aligned. This is prevents an infinite loop when two | |
10491 | instructions have contradictory range/alignment requirements. */ | |
10492 | if (val & 3) | |
10493 | return -4; | |
10494 | val -= addr; | |
10495 | if (val < 0 || val > 1020) | |
10496 | return 4; | |
10497 | return 2; | |
10498 | } | |
10499 | ||
10500 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
10501 | static int | |
10502 | relax_addsub (fragS *fragp, asection *sec) | |
10503 | { | |
10504 | char *buf; | |
10505 | int op; | |
10506 | ||
10507 | buf = fragp->fr_literal + fragp->fr_fix; | |
10508 | op = bfd_get_16(sec->owner, buf); | |
10509 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
10510 | return relax_immediate (fragp, 8, 0); | |
10511 | else | |
10512 | return relax_immediate (fragp, 3, 0); | |
10513 | } | |
10514 | ||
10515 | ||
10516 | /* Return the size of a relaxable branch instruction. BITS is the | |
10517 | size of the offset field in the narrow instruction. */ | |
10518 | ||
10519 | static int | |
10520 | relax_branch (fragS *fragp, asection *sec, int bits) | |
10521 | { | |
10522 | addressT addr; | |
10523 | offsetT val; | |
10524 | offsetT limit; | |
10525 | ||
10526 | /* Assume worst case for symbols not known to be in the same section. */ | |
10527 | if (!S_IS_DEFINED(fragp->fr_symbol) | |
10528 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) | |
10529 | return 4; | |
10530 | ||
10531 | val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset; | |
10532 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
10533 | val -= addr; | |
10534 | ||
10535 | /* Offset is a signed value *2 */ | |
10536 | limit = 1 << bits; | |
10537 | if (val >= limit || val < -limit) | |
10538 | return 4; | |
10539 | return 2; | |
10540 | } | |
10541 | ||
10542 | ||
10543 | /* Relax a machine dependent frag. This returns the amount by which | |
10544 | the current size of the frag should change. */ | |
10545 | ||
10546 | int | |
10547 | arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
10548 | { | |
10549 | int oldsize; | |
10550 | int newsize; | |
10551 | ||
10552 | oldsize = fragp->fr_var; | |
10553 | switch (fragp->fr_subtype) | |
10554 | { | |
10555 | case T_MNEM_ldr_pc2: | |
10556 | newsize = relax_adr(fragp, sec); | |
10557 | break; | |
10558 | case T_MNEM_ldr_pc: | |
10559 | case T_MNEM_ldr_sp: | |
10560 | case T_MNEM_str_sp: | |
10561 | newsize = relax_immediate(fragp, 8, 2); | |
10562 | break; | |
10563 | case T_MNEM_ldr: | |
10564 | case T_MNEM_str: | |
10565 | newsize = relax_immediate(fragp, 5, 2); | |
10566 | break; | |
10567 | case T_MNEM_ldrh: | |
10568 | case T_MNEM_strh: | |
10569 | newsize = relax_immediate(fragp, 5, 1); | |
10570 | break; | |
10571 | case T_MNEM_ldrb: | |
10572 | case T_MNEM_strb: | |
10573 | newsize = relax_immediate(fragp, 5, 0); | |
10574 | break; | |
10575 | case T_MNEM_adr: | |
10576 | newsize = relax_adr(fragp, sec); | |
10577 | break; | |
10578 | case T_MNEM_mov: | |
10579 | case T_MNEM_movs: | |
10580 | case T_MNEM_cmp: | |
10581 | case T_MNEM_cmn: | |
10582 | newsize = relax_immediate(fragp, 8, 0); | |
10583 | break; | |
10584 | case T_MNEM_b: | |
10585 | newsize = relax_branch(fragp, sec, 11); | |
10586 | break; | |
10587 | case T_MNEM_bcond: | |
10588 | newsize = relax_branch(fragp, sec, 8); | |
10589 | break; | |
10590 | case T_MNEM_add_sp: | |
10591 | case T_MNEM_add_pc: | |
10592 | newsize = relax_immediate (fragp, 8, 2); | |
10593 | break; | |
10594 | case T_MNEM_inc_sp: | |
10595 | case T_MNEM_dec_sp: | |
10596 | newsize = relax_immediate (fragp, 7, 2); | |
10597 | break; | |
10598 | case T_MNEM_addi: | |
10599 | case T_MNEM_addis: | |
10600 | case T_MNEM_subi: | |
10601 | case T_MNEM_subis: | |
10602 | newsize = relax_addsub (fragp, sec); | |
10603 | break; | |
10604 | default: | |
10605 | abort(); | |
10606 | } | |
10607 | if (newsize < 0) | |
10608 | { | |
10609 | fragp->fr_var = -newsize; | |
10610 | md_convert_frag (sec->owner, sec, fragp); | |
10611 | frag_wane(fragp); | |
10612 | return -(newsize + oldsize); | |
10613 | } | |
10614 | fragp->fr_var = newsize; | |
10615 | return newsize - oldsize; | |
c19d1205 | 10616 | } |
b99bd4ef | 10617 | |
c19d1205 | 10618 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 10619 | |
c19d1205 ZW |
10620 | valueT |
10621 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
10622 | valueT size) | |
10623 | { | |
10624 | #ifdef OBJ_ELF | |
10625 | return size; | |
10626 | #else | |
10627 | /* Round all sects to multiple of 4. */ | |
10628 | return (size + 3) & ~3; | |
10629 | #endif | |
bfae80f2 | 10630 | } |
b99bd4ef | 10631 | |
c19d1205 ZW |
10632 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
10633 | of an rs_align_code fragment. */ | |
10634 | ||
10635 | void | |
10636 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 10637 | { |
c19d1205 ZW |
10638 | static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; |
10639 | static char const thumb_noop[2] = { 0xc0, 0x46 }; | |
10640 | static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; | |
10641 | static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; | |
10642 | ||
10643 | int bytes, fix, noop_size; | |
10644 | char * p; | |
10645 | const char * noop; | |
bfae80f2 | 10646 | |
c19d1205 | 10647 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
10648 | return; |
10649 | ||
c19d1205 ZW |
10650 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
10651 | p = fragP->fr_literal + fragP->fr_fix; | |
10652 | fix = 0; | |
bfae80f2 | 10653 | |
c19d1205 ZW |
10654 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
10655 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 10656 | |
c19d1205 | 10657 | if (fragP->tc_frag_data) |
a737bd4d | 10658 | { |
c19d1205 ZW |
10659 | if (target_big_endian) |
10660 | noop = thumb_bigend_noop; | |
10661 | else | |
10662 | noop = thumb_noop; | |
10663 | noop_size = sizeof (thumb_noop); | |
7ed4c4c5 NC |
10664 | } |
10665 | else | |
10666 | { | |
c19d1205 ZW |
10667 | if (target_big_endian) |
10668 | noop = arm_bigend_noop; | |
10669 | else | |
10670 | noop = arm_noop; | |
10671 | noop_size = sizeof (arm_noop); | |
7ed4c4c5 | 10672 | } |
a737bd4d | 10673 | |
c19d1205 | 10674 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 10675 | { |
c19d1205 ZW |
10676 | fix = bytes & (noop_size - 1); |
10677 | memset (p, 0, fix); | |
10678 | p += fix; | |
10679 | bytes -= fix; | |
a737bd4d | 10680 | } |
a737bd4d | 10681 | |
c19d1205 | 10682 | while (bytes >= noop_size) |
a737bd4d | 10683 | { |
c19d1205 ZW |
10684 | memcpy (p, noop, noop_size); |
10685 | p += noop_size; | |
10686 | bytes -= noop_size; | |
10687 | fix += noop_size; | |
a737bd4d NC |
10688 | } |
10689 | ||
c19d1205 ZW |
10690 | fragP->fr_fix += fix; |
10691 | fragP->fr_var = noop_size; | |
a737bd4d NC |
10692 | } |
10693 | ||
c19d1205 ZW |
10694 | /* Called from md_do_align. Used to create an alignment |
10695 | frag in a code section. */ | |
10696 | ||
10697 | void | |
10698 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 10699 | { |
c19d1205 | 10700 | char * p; |
7ed4c4c5 | 10701 | |
c19d1205 ZW |
10702 | /* We assume that there will never be a requirement |
10703 | to support alignments greater than 32 bytes. */ | |
10704 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) | |
10705 | as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); | |
bfae80f2 | 10706 | |
c19d1205 ZW |
10707 | p = frag_var (rs_align_code, |
10708 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
10709 | 1, | |
10710 | (relax_substateT) max, | |
10711 | (symbolS *) NULL, | |
10712 | (offsetT) n, | |
10713 | (char *) NULL); | |
10714 | *p = 0; | |
10715 | } | |
bfae80f2 | 10716 | |
c19d1205 | 10717 | /* Perform target specific initialisation of a frag. */ |
bfae80f2 | 10718 | |
c19d1205 ZW |
10719 | void |
10720 | arm_init_frag (fragS * fragP) | |
10721 | { | |
10722 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
10723 | fragP->tc_frag_data = thumb_mode; | |
bfae80f2 RE |
10724 | } |
10725 | ||
c19d1205 ZW |
10726 | #ifdef OBJ_ELF |
10727 | /* When we change sections we need to issue a new mapping symbol. */ | |
10728 | ||
10729 | void | |
10730 | arm_elf_change_section (void) | |
bfae80f2 | 10731 | { |
c19d1205 ZW |
10732 | flagword flags; |
10733 | segment_info_type *seginfo; | |
bfae80f2 | 10734 | |
c19d1205 ZW |
10735 | /* Link an unlinked unwind index table section to the .text section. */ |
10736 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
10737 | && elf_linked_to_section (now_seg) == NULL) | |
10738 | elf_linked_to_section (now_seg) = text_section; | |
10739 | ||
10740 | if (!SEG_NORMAL (now_seg)) | |
bfae80f2 RE |
10741 | return; |
10742 | ||
c19d1205 ZW |
10743 | flags = bfd_get_section_flags (stdoutput, now_seg); |
10744 | ||
10745 | /* We can ignore sections that only contain debug info. */ | |
10746 | if ((flags & SEC_ALLOC) == 0) | |
10747 | return; | |
bfae80f2 | 10748 | |
c19d1205 ZW |
10749 | seginfo = seg_info (now_seg); |
10750 | mapstate = seginfo->tc_segment_info_data.mapstate; | |
10751 | marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; | |
bfae80f2 RE |
10752 | } |
10753 | ||
c19d1205 ZW |
10754 | int |
10755 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 10756 | { |
c19d1205 ZW |
10757 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
10758 | return SHT_ARM_EXIDX; | |
e45d0630 | 10759 | |
c19d1205 ZW |
10760 | return -1; |
10761 | } | |
10762 | \f | |
10763 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 10764 | |
c19d1205 | 10765 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 10766 | |
c19d1205 | 10767 | /* Cenerate and deferred unwind frame offset. */ |
e45d0630 | 10768 | |
bfae80f2 | 10769 | static void |
c19d1205 | 10770 | flush_pending_unwind (void) |
bfae80f2 | 10771 | { |
c19d1205 | 10772 | offsetT offset; |
bfae80f2 | 10773 | |
c19d1205 ZW |
10774 | offset = unwind.pending_offset; |
10775 | unwind.pending_offset = 0; | |
10776 | if (offset != 0) | |
10777 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
10778 | } |
10779 | ||
c19d1205 ZW |
10780 | /* Add an opcode to this list for this function. Two-byte opcodes should |
10781 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
10782 | order. */ | |
10783 | ||
bfae80f2 | 10784 | static void |
c19d1205 | 10785 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 10786 | { |
c19d1205 ZW |
10787 | /* Add any deferred stack adjustment. */ |
10788 | if (unwind.pending_offset) | |
10789 | flush_pending_unwind (); | |
bfae80f2 | 10790 | |
c19d1205 | 10791 | unwind.sp_restored = 0; |
bfae80f2 | 10792 | |
c19d1205 | 10793 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 10794 | { |
c19d1205 ZW |
10795 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
10796 | if (unwind.opcodes) | |
10797 | unwind.opcodes = xrealloc (unwind.opcodes, | |
10798 | unwind.opcode_alloc); | |
10799 | else | |
10800 | unwind.opcodes = xmalloc (unwind.opcode_alloc); | |
bfae80f2 | 10801 | } |
c19d1205 | 10802 | while (length > 0) |
bfae80f2 | 10803 | { |
c19d1205 ZW |
10804 | length--; |
10805 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
10806 | op >>= 8; | |
10807 | unwind.opcode_count++; | |
bfae80f2 | 10808 | } |
bfae80f2 RE |
10809 | } |
10810 | ||
c19d1205 ZW |
10811 | /* Add unwind opcodes to adjust the stack pointer. */ |
10812 | ||
bfae80f2 | 10813 | static void |
c19d1205 | 10814 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 10815 | { |
c19d1205 | 10816 | valueT op; |
bfae80f2 | 10817 | |
c19d1205 | 10818 | if (offset > 0x200) |
bfae80f2 | 10819 | { |
c19d1205 ZW |
10820 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
10821 | char bytes[5]; | |
10822 | int n; | |
10823 | valueT o; | |
bfae80f2 | 10824 | |
c19d1205 ZW |
10825 | /* Long form: 0xb2, uleb128. */ |
10826 | /* This might not fit in a word so add the individual bytes, | |
10827 | remembering the list is built in reverse order. */ | |
10828 | o = (valueT) ((offset - 0x204) >> 2); | |
10829 | if (o == 0) | |
10830 | add_unwind_opcode (0, 1); | |
bfae80f2 | 10831 | |
c19d1205 ZW |
10832 | /* Calculate the uleb128 encoding of the offset. */ |
10833 | n = 0; | |
10834 | while (o) | |
10835 | { | |
10836 | bytes[n] = o & 0x7f; | |
10837 | o >>= 7; | |
10838 | if (o) | |
10839 | bytes[n] |= 0x80; | |
10840 | n++; | |
10841 | } | |
10842 | /* Add the insn. */ | |
10843 | for (; n; n--) | |
10844 | add_unwind_opcode (bytes[n - 1], 1); | |
10845 | add_unwind_opcode (0xb2, 1); | |
10846 | } | |
10847 | else if (offset > 0x100) | |
bfae80f2 | 10848 | { |
c19d1205 ZW |
10849 | /* Two short opcodes. */ |
10850 | add_unwind_opcode (0x3f, 1); | |
10851 | op = (offset - 0x104) >> 2; | |
10852 | add_unwind_opcode (op, 1); | |
bfae80f2 | 10853 | } |
c19d1205 ZW |
10854 | else if (offset > 0) |
10855 | { | |
10856 | /* Short opcode. */ | |
10857 | op = (offset - 4) >> 2; | |
10858 | add_unwind_opcode (op, 1); | |
10859 | } | |
10860 | else if (offset < 0) | |
bfae80f2 | 10861 | { |
c19d1205 ZW |
10862 | offset = -offset; |
10863 | while (offset > 0x100) | |
bfae80f2 | 10864 | { |
c19d1205 ZW |
10865 | add_unwind_opcode (0x7f, 1); |
10866 | offset -= 0x100; | |
bfae80f2 | 10867 | } |
c19d1205 ZW |
10868 | op = ((offset - 4) >> 2) | 0x40; |
10869 | add_unwind_opcode (op, 1); | |
bfae80f2 | 10870 | } |
bfae80f2 RE |
10871 | } |
10872 | ||
c19d1205 ZW |
10873 | /* Finish the list of unwind opcodes for this function. */ |
10874 | static void | |
10875 | finish_unwind_opcodes (void) | |
bfae80f2 | 10876 | { |
c19d1205 | 10877 | valueT op; |
bfae80f2 | 10878 | |
c19d1205 | 10879 | if (unwind.fp_used) |
bfae80f2 | 10880 | { |
c19d1205 ZW |
10881 | /* Adjust sp as neccessary. */ |
10882 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; | |
10883 | flush_pending_unwind (); | |
bfae80f2 | 10884 | |
c19d1205 ZW |
10885 | /* After restoring sp from the frame pointer. */ |
10886 | op = 0x90 | unwind.fp_reg; | |
10887 | add_unwind_opcode (op, 1); | |
10888 | } | |
10889 | else | |
10890 | flush_pending_unwind (); | |
bfae80f2 RE |
10891 | } |
10892 | ||
bfae80f2 | 10893 | |
c19d1205 ZW |
10894 | /* Start an exception table entry. If idx is nonzero this is an index table |
10895 | entry. */ | |
bfae80f2 RE |
10896 | |
10897 | static void | |
c19d1205 | 10898 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 10899 | { |
c19d1205 ZW |
10900 | const char * text_name; |
10901 | const char * prefix; | |
10902 | const char * prefix_once; | |
10903 | const char * group_name; | |
10904 | size_t prefix_len; | |
10905 | size_t text_len; | |
10906 | char * sec_name; | |
10907 | size_t sec_name_len; | |
10908 | int type; | |
10909 | int flags; | |
10910 | int linkonce; | |
bfae80f2 | 10911 | |
c19d1205 | 10912 | if (idx) |
bfae80f2 | 10913 | { |
c19d1205 ZW |
10914 | prefix = ELF_STRING_ARM_unwind; |
10915 | prefix_once = ELF_STRING_ARM_unwind_once; | |
10916 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 10917 | } |
c19d1205 | 10918 | else |
bfae80f2 | 10919 | { |
c19d1205 ZW |
10920 | prefix = ELF_STRING_ARM_unwind_info; |
10921 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
10922 | type = SHT_PROGBITS; | |
bfae80f2 RE |
10923 | } |
10924 | ||
c19d1205 ZW |
10925 | text_name = segment_name (text_seg); |
10926 | if (streq (text_name, ".text")) | |
10927 | text_name = ""; | |
10928 | ||
10929 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
10930 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 10931 | { |
c19d1205 ZW |
10932 | prefix = prefix_once; |
10933 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
10934 | } |
10935 | ||
c19d1205 ZW |
10936 | prefix_len = strlen (prefix); |
10937 | text_len = strlen (text_name); | |
10938 | sec_name_len = prefix_len + text_len; | |
10939 | sec_name = xmalloc (sec_name_len + 1); | |
10940 | memcpy (sec_name, prefix, prefix_len); | |
10941 | memcpy (sec_name + prefix_len, text_name, text_len); | |
10942 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 10943 | |
c19d1205 ZW |
10944 | flags = SHF_ALLOC; |
10945 | linkonce = 0; | |
10946 | group_name = 0; | |
bfae80f2 | 10947 | |
c19d1205 ZW |
10948 | /* Handle COMDAT group. */ |
10949 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 10950 | { |
c19d1205 ZW |
10951 | group_name = elf_group_name (text_seg); |
10952 | if (group_name == NULL) | |
10953 | { | |
10954 | as_bad ("Group section `%s' has no group signature", | |
10955 | segment_name (text_seg)); | |
10956 | ignore_rest_of_line (); | |
10957 | return; | |
10958 | } | |
10959 | flags |= SHF_GROUP; | |
10960 | linkonce = 1; | |
bfae80f2 RE |
10961 | } |
10962 | ||
c19d1205 | 10963 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 10964 | |
c19d1205 ZW |
10965 | /* Set the setion link for index tables. */ |
10966 | if (idx) | |
10967 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
10968 | } |
10969 | ||
bfae80f2 | 10970 | |
c19d1205 ZW |
10971 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
10972 | personality routine data. Returns zero, or the index table value for | |
10973 | and inline entry. */ | |
10974 | ||
10975 | static valueT | |
10976 | create_unwind_entry (int have_data) | |
bfae80f2 | 10977 | { |
c19d1205 ZW |
10978 | int size; |
10979 | addressT where; | |
10980 | char *ptr; | |
10981 | /* The current word of data. */ | |
10982 | valueT data; | |
10983 | /* The number of bytes left in this word. */ | |
10984 | int n; | |
bfae80f2 | 10985 | |
c19d1205 | 10986 | finish_unwind_opcodes (); |
bfae80f2 | 10987 | |
c19d1205 ZW |
10988 | /* Remember the current text section. */ |
10989 | unwind.saved_seg = now_seg; | |
10990 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 10991 | |
c19d1205 | 10992 | start_unwind_section (now_seg, 0); |
bfae80f2 | 10993 | |
c19d1205 | 10994 | if (unwind.personality_routine == NULL) |
bfae80f2 | 10995 | { |
c19d1205 ZW |
10996 | if (unwind.personality_index == -2) |
10997 | { | |
10998 | if (have_data) | |
10999 | as_bad (_("handerdata in cantunwind frame")); | |
11000 | return 1; /* EXIDX_CANTUNWIND. */ | |
11001 | } | |
bfae80f2 | 11002 | |
c19d1205 ZW |
11003 | /* Use a default personality routine if none is specified. */ |
11004 | if (unwind.personality_index == -1) | |
11005 | { | |
11006 | if (unwind.opcode_count > 3) | |
11007 | unwind.personality_index = 1; | |
11008 | else | |
11009 | unwind.personality_index = 0; | |
11010 | } | |
bfae80f2 | 11011 | |
c19d1205 ZW |
11012 | /* Space for the personality routine entry. */ |
11013 | if (unwind.personality_index == 0) | |
11014 | { | |
11015 | if (unwind.opcode_count > 3) | |
11016 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 11017 | |
c19d1205 ZW |
11018 | if (!have_data) |
11019 | { | |
11020 | /* All the data is inline in the index table. */ | |
11021 | data = 0x80; | |
11022 | n = 3; | |
11023 | while (unwind.opcode_count > 0) | |
11024 | { | |
11025 | unwind.opcode_count--; | |
11026 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
11027 | n--; | |
11028 | } | |
bfae80f2 | 11029 | |
c19d1205 ZW |
11030 | /* Pad with "finish" opcodes. */ |
11031 | while (n--) | |
11032 | data = (data << 8) | 0xb0; | |
bfae80f2 | 11033 | |
c19d1205 ZW |
11034 | return data; |
11035 | } | |
11036 | size = 0; | |
11037 | } | |
11038 | else | |
11039 | /* We get two opcodes "free" in the first word. */ | |
11040 | size = unwind.opcode_count - 2; | |
11041 | } | |
11042 | else | |
11043 | /* An extra byte is required for the opcode count. */ | |
11044 | size = unwind.opcode_count + 1; | |
bfae80f2 | 11045 | |
c19d1205 ZW |
11046 | size = (size + 3) >> 2; |
11047 | if (size > 0xff) | |
11048 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 11049 | |
c19d1205 ZW |
11050 | frag_align (2, 0, 0); |
11051 | record_alignment (now_seg, 2); | |
11052 | unwind.table_entry = expr_build_dot (); | |
11053 | ||
11054 | /* Allocate the table entry. */ | |
11055 | ptr = frag_more ((size << 2) + 4); | |
11056 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 11057 | |
c19d1205 | 11058 | switch (unwind.personality_index) |
bfae80f2 | 11059 | { |
c19d1205 ZW |
11060 | case -1: |
11061 | /* ??? Should this be a PLT generating relocation? */ | |
11062 | /* Custom personality routine. */ | |
11063 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
11064 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 11065 | |
c19d1205 ZW |
11066 | where += 4; |
11067 | ptr += 4; | |
bfae80f2 | 11068 | |
c19d1205 ZW |
11069 | /* Set the first byte to the number of additional words. */ |
11070 | data = size - 1; | |
11071 | n = 3; | |
11072 | break; | |
bfae80f2 | 11073 | |
c19d1205 ZW |
11074 | /* ABI defined personality routines. */ |
11075 | case 0: | |
11076 | /* Three opcodes bytes are packed into the first word. */ | |
11077 | data = 0x80; | |
11078 | n = 3; | |
11079 | break; | |
bfae80f2 | 11080 | |
c19d1205 ZW |
11081 | case 1: |
11082 | case 2: | |
11083 | /* The size and first two opcode bytes go in the first word. */ | |
11084 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
11085 | n = 2; | |
11086 | break; | |
bfae80f2 | 11087 | |
c19d1205 ZW |
11088 | default: |
11089 | /* Should never happen. */ | |
11090 | abort (); | |
11091 | } | |
bfae80f2 | 11092 | |
c19d1205 ZW |
11093 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
11094 | time. */ | |
11095 | while (unwind.opcode_count > 0) | |
11096 | { | |
11097 | if (n == 0) | |
11098 | { | |
11099 | md_number_to_chars (ptr, data, 4); | |
11100 | ptr += 4; | |
11101 | n = 4; | |
11102 | data = 0; | |
11103 | } | |
11104 | unwind.opcode_count--; | |
11105 | n--; | |
11106 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
11107 | } | |
11108 | ||
11109 | /* Finish off the last word. */ | |
11110 | if (n < 4) | |
11111 | { | |
11112 | /* Pad with "finish" opcodes. */ | |
11113 | while (n--) | |
11114 | data = (data << 8) | 0xb0; | |
11115 | ||
11116 | md_number_to_chars (ptr, data, 4); | |
11117 | } | |
11118 | ||
11119 | if (!have_data) | |
11120 | { | |
11121 | /* Add an empty descriptor if there is no user-specified data. */ | |
11122 | ptr = frag_more (4); | |
11123 | md_number_to_chars (ptr, 0, 4); | |
11124 | } | |
11125 | ||
11126 | return 0; | |
bfae80f2 RE |
11127 | } |
11128 | ||
c19d1205 ZW |
11129 | /* Convert REGNAME to a DWARF-2 register number. */ |
11130 | ||
11131 | int | |
11132 | tc_arm_regname_to_dw2regnum (const char *regname) | |
bfae80f2 | 11133 | { |
c19d1205 ZW |
11134 | int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN); |
11135 | ||
11136 | if (reg == FAIL) | |
11137 | return -1; | |
11138 | ||
11139 | return reg; | |
bfae80f2 RE |
11140 | } |
11141 | ||
c19d1205 ZW |
11142 | /* Initialize the DWARF-2 unwind information for this procedure. */ |
11143 | ||
11144 | void | |
11145 | tc_arm_frame_initial_instructions (void) | |
bfae80f2 | 11146 | { |
c19d1205 | 11147 | cfi_add_CFA_def_cfa (REG_SP, 0); |
bfae80f2 | 11148 | } |
c19d1205 | 11149 | #endif /* OBJ_ELF */ |
bfae80f2 | 11150 | |
bfae80f2 | 11151 | |
c19d1205 | 11152 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 11153 | |
2fc8bdac ZW |
11154 | /* Return the address within the segment that a PC-relative fixup is |
11155 | relative to. For ARM, PC-relative fixups applied to instructions | |
11156 | are generally relative to the location of the fixup plus 8 bytes. | |
11157 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
11158 | require special handling. */ | |
bfae80f2 | 11159 | |
c19d1205 | 11160 | long |
2fc8bdac | 11161 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 11162 | { |
2fc8bdac ZW |
11163 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
11164 | ||
11165 | /* If this is pc-relative and we are going to emit a relocation | |
11166 | then we just want to put out any pipeline compensation that the linker | |
11167 | will need. Otherwise we want to use the calculated base. */ | |
11168 | if (fixP->fx_pcrel | |
11169 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11170 | || arm_force_relocation (fixP))) | |
11171 | base = 0; | |
bfae80f2 | 11172 | |
c19d1205 | 11173 | switch (fixP->fx_r_type) |
bfae80f2 | 11174 | { |
2fc8bdac ZW |
11175 | /* PC relative addressing on the Thumb is slightly odd as the |
11176 | bottom two bits of the PC are forced to zero for the | |
11177 | calculation. This happens *after* application of the | |
11178 | pipeline offset. However, Thumb adrl already adjusts for | |
11179 | this, so we need not do it again. */ | |
c19d1205 | 11180 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 11181 | return base & ~3; |
c19d1205 ZW |
11182 | |
11183 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
11184 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 11185 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 11186 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 11187 | return (base + 4) & ~3; |
c19d1205 | 11188 | |
2fc8bdac ZW |
11189 | /* Thumb branches are simply offset by +4. */ |
11190 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
11191 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
11192 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
11193 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
11194 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
11195 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
11196 | case BFD_RELOC_THUMB_PCREL_BLX: | |
11197 | return base + 4; | |
bfae80f2 | 11198 | |
2fc8bdac ZW |
11199 | /* ARM mode branches are offset by +8. However, the Windows CE |
11200 | loader expects the relocation not to take this into account. */ | |
11201 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
39b41c9c PB |
11202 | case BFD_RELOC_ARM_PCREL_CALL: |
11203 | case BFD_RELOC_ARM_PCREL_JUMP: | |
2fc8bdac ZW |
11204 | case BFD_RELOC_ARM_PCREL_BLX: |
11205 | case BFD_RELOC_ARM_PLT32: | |
c19d1205 | 11206 | #ifdef TE_WINCE |
2fc8bdac | 11207 | return base; |
c19d1205 | 11208 | #else |
2fc8bdac | 11209 | return base + 8; |
c19d1205 | 11210 | #endif |
2fc8bdac ZW |
11211 | |
11212 | /* ARM mode loads relative to PC are also offset by +8. Unlike | |
11213 | branches, the Windows CE loader *does* expect the relocation | |
11214 | to take this into account. */ | |
11215 | case BFD_RELOC_ARM_OFFSET_IMM: | |
11216 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
11217 | case BFD_RELOC_ARM_HWLITERAL: | |
11218 | case BFD_RELOC_ARM_LITERAL: | |
11219 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
11220 | return base + 8; | |
11221 | ||
11222 | ||
11223 | /* Other PC-relative relocations are un-offset. */ | |
11224 | default: | |
11225 | return base; | |
11226 | } | |
bfae80f2 RE |
11227 | } |
11228 | ||
c19d1205 ZW |
11229 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
11230 | Otherwise we have no need to default values of symbols. */ | |
11231 | ||
11232 | symbolS * | |
11233 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 11234 | { |
c19d1205 ZW |
11235 | #ifdef OBJ_ELF |
11236 | if (name[0] == '_' && name[1] == 'G' | |
11237 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
11238 | { | |
11239 | if (!GOT_symbol) | |
11240 | { | |
11241 | if (symbol_find (name)) | |
11242 | as_bad ("GOT already in the symbol table"); | |
bfae80f2 | 11243 | |
c19d1205 ZW |
11244 | GOT_symbol = symbol_new (name, undefined_section, |
11245 | (valueT) 0, & zero_address_frag); | |
11246 | } | |
bfae80f2 | 11247 | |
c19d1205 | 11248 | return GOT_symbol; |
bfae80f2 | 11249 | } |
c19d1205 | 11250 | #endif |
bfae80f2 | 11251 | |
c19d1205 | 11252 | return 0; |
bfae80f2 RE |
11253 | } |
11254 | ||
55cf6793 | 11255 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
11256 | computed as two separate immediate values, added together. We |
11257 | already know that this value cannot be computed by just one ARM | |
11258 | instruction. */ | |
11259 | ||
11260 | static unsigned int | |
11261 | validate_immediate_twopart (unsigned int val, | |
11262 | unsigned int * highpart) | |
bfae80f2 | 11263 | { |
c19d1205 ZW |
11264 | unsigned int a; |
11265 | unsigned int i; | |
bfae80f2 | 11266 | |
c19d1205 ZW |
11267 | for (i = 0; i < 32; i += 2) |
11268 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
11269 | { | |
11270 | if (a & 0xff00) | |
11271 | { | |
11272 | if (a & ~ 0xffff) | |
11273 | continue; | |
11274 | * highpart = (a >> 8) | ((i + 24) << 7); | |
11275 | } | |
11276 | else if (a & 0xff0000) | |
11277 | { | |
11278 | if (a & 0xff000000) | |
11279 | continue; | |
11280 | * highpart = (a >> 16) | ((i + 16) << 7); | |
11281 | } | |
11282 | else | |
11283 | { | |
11284 | assert (a & 0xff000000); | |
11285 | * highpart = (a >> 24) | ((i + 8) << 7); | |
11286 | } | |
bfae80f2 | 11287 | |
c19d1205 ZW |
11288 | return (a & 0xff) | (i << 7); |
11289 | } | |
bfae80f2 | 11290 | |
c19d1205 | 11291 | return FAIL; |
bfae80f2 RE |
11292 | } |
11293 | ||
c19d1205 ZW |
11294 | static int |
11295 | validate_offset_imm (unsigned int val, int hwse) | |
11296 | { | |
11297 | if ((hwse && val > 255) || val > 4095) | |
11298 | return FAIL; | |
11299 | return val; | |
11300 | } | |
bfae80f2 | 11301 | |
55cf6793 | 11302 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
11303 | negative immediate constant by altering the instruction. A bit of |
11304 | a hack really. | |
11305 | MOV <-> MVN | |
11306 | AND <-> BIC | |
11307 | ADC <-> SBC | |
11308 | by inverting the second operand, and | |
11309 | ADD <-> SUB | |
11310 | CMP <-> CMN | |
11311 | by negating the second operand. */ | |
bfae80f2 | 11312 | |
c19d1205 ZW |
11313 | static int |
11314 | negate_data_op (unsigned long * instruction, | |
11315 | unsigned long value) | |
bfae80f2 | 11316 | { |
c19d1205 ZW |
11317 | int op, new_inst; |
11318 | unsigned long negated, inverted; | |
bfae80f2 | 11319 | |
c19d1205 ZW |
11320 | negated = encode_arm_immediate (-value); |
11321 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 11322 | |
c19d1205 ZW |
11323 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
11324 | switch (op) | |
bfae80f2 | 11325 | { |
c19d1205 ZW |
11326 | /* First negates. */ |
11327 | case OPCODE_SUB: /* ADD <-> SUB */ | |
11328 | new_inst = OPCODE_ADD; | |
11329 | value = negated; | |
11330 | break; | |
bfae80f2 | 11331 | |
c19d1205 ZW |
11332 | case OPCODE_ADD: |
11333 | new_inst = OPCODE_SUB; | |
11334 | value = negated; | |
11335 | break; | |
bfae80f2 | 11336 | |
c19d1205 ZW |
11337 | case OPCODE_CMP: /* CMP <-> CMN */ |
11338 | new_inst = OPCODE_CMN; | |
11339 | value = negated; | |
11340 | break; | |
bfae80f2 | 11341 | |
c19d1205 ZW |
11342 | case OPCODE_CMN: |
11343 | new_inst = OPCODE_CMP; | |
11344 | value = negated; | |
11345 | break; | |
bfae80f2 | 11346 | |
c19d1205 ZW |
11347 | /* Now Inverted ops. */ |
11348 | case OPCODE_MOV: /* MOV <-> MVN */ | |
11349 | new_inst = OPCODE_MVN; | |
11350 | value = inverted; | |
11351 | break; | |
bfae80f2 | 11352 | |
c19d1205 ZW |
11353 | case OPCODE_MVN: |
11354 | new_inst = OPCODE_MOV; | |
11355 | value = inverted; | |
11356 | break; | |
bfae80f2 | 11357 | |
c19d1205 ZW |
11358 | case OPCODE_AND: /* AND <-> BIC */ |
11359 | new_inst = OPCODE_BIC; | |
11360 | value = inverted; | |
11361 | break; | |
bfae80f2 | 11362 | |
c19d1205 ZW |
11363 | case OPCODE_BIC: |
11364 | new_inst = OPCODE_AND; | |
11365 | value = inverted; | |
11366 | break; | |
bfae80f2 | 11367 | |
c19d1205 ZW |
11368 | case OPCODE_ADC: /* ADC <-> SBC */ |
11369 | new_inst = OPCODE_SBC; | |
11370 | value = inverted; | |
11371 | break; | |
bfae80f2 | 11372 | |
c19d1205 ZW |
11373 | case OPCODE_SBC: |
11374 | new_inst = OPCODE_ADC; | |
11375 | value = inverted; | |
11376 | break; | |
bfae80f2 | 11377 | |
c19d1205 ZW |
11378 | /* We cannot do anything. */ |
11379 | default: | |
11380 | return FAIL; | |
b99bd4ef NC |
11381 | } |
11382 | ||
c19d1205 ZW |
11383 | if (value == (unsigned) FAIL) |
11384 | return FAIL; | |
11385 | ||
11386 | *instruction &= OPCODE_MASK; | |
11387 | *instruction |= new_inst << DATA_OP_SHIFT; | |
11388 | return value; | |
b99bd4ef NC |
11389 | } |
11390 | ||
ef8d22e6 PB |
11391 | /* Like negate_data_op, but for Thumb-2. */ |
11392 | ||
11393 | static unsigned int | |
11394 | thumb32_negate_data_op (offsetT *instruction, offsetT value) | |
11395 | { | |
11396 | int op, new_inst; | |
11397 | int rd; | |
11398 | offsetT negated, inverted; | |
11399 | ||
11400 | negated = encode_thumb32_immediate (-value); | |
11401 | inverted = encode_thumb32_immediate (~value); | |
11402 | ||
11403 | rd = (*instruction >> 8) & 0xf; | |
11404 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
11405 | switch (op) | |
11406 | { | |
11407 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
11408 | case T2_OPCODE_SUB: | |
11409 | new_inst = T2_OPCODE_ADD; | |
11410 | value = negated; | |
11411 | break; | |
11412 | ||
11413 | case T2_OPCODE_ADD: | |
11414 | new_inst = T2_OPCODE_SUB; | |
11415 | value = negated; | |
11416 | break; | |
11417 | ||
11418 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
11419 | case T2_OPCODE_ORR: | |
11420 | new_inst = T2_OPCODE_ORN; | |
11421 | value = inverted; | |
11422 | break; | |
11423 | ||
11424 | case T2_OPCODE_ORN: | |
11425 | new_inst = T2_OPCODE_ORR; | |
11426 | value = inverted; | |
11427 | break; | |
11428 | ||
11429 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
11430 | case T2_OPCODE_AND: | |
11431 | new_inst = T2_OPCODE_BIC; | |
11432 | if (rd == 15) | |
11433 | value = FAIL; | |
11434 | else | |
11435 | value = inverted; | |
11436 | break; | |
11437 | ||
11438 | case T2_OPCODE_BIC: | |
11439 | new_inst = T2_OPCODE_AND; | |
11440 | value = inverted; | |
11441 | break; | |
11442 | ||
11443 | /* ADC <-> SBC */ | |
11444 | case T2_OPCODE_ADC: | |
11445 | new_inst = T2_OPCODE_SBC; | |
11446 | value = inverted; | |
11447 | break; | |
11448 | ||
11449 | case T2_OPCODE_SBC: | |
11450 | new_inst = T2_OPCODE_ADC; | |
11451 | value = inverted; | |
11452 | break; | |
11453 | ||
11454 | /* We cannot do anything. */ | |
11455 | default: | |
11456 | return FAIL; | |
11457 | } | |
11458 | ||
11459 | if (value == FAIL) | |
11460 | return FAIL; | |
11461 | ||
11462 | *instruction &= T2_OPCODE_MASK; | |
11463 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
11464 | return value; | |
11465 | } | |
11466 | ||
8f06b2d8 PB |
11467 | /* Read a 32-bit thumb instruction from buf. */ |
11468 | static unsigned long | |
11469 | get_thumb32_insn (char * buf) | |
11470 | { | |
11471 | unsigned long insn; | |
11472 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
11473 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
11474 | ||
11475 | return insn; | |
11476 | } | |
11477 | ||
c19d1205 | 11478 | void |
55cf6793 | 11479 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
11480 | valueT * valP, |
11481 | segT seg) | |
11482 | { | |
11483 | offsetT value = * valP; | |
11484 | offsetT newval; | |
11485 | unsigned int newimm; | |
11486 | unsigned long temp; | |
11487 | int sign; | |
11488 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 11489 | |
c19d1205 | 11490 | assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 11491 | |
c19d1205 ZW |
11492 | /* Note whether this will delete the relocation. */ |
11493 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
11494 | fixP->fx_done = 1; | |
b99bd4ef | 11495 | |
adbaf948 ZW |
11496 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
11497 | consistency with the behavior on 32-bit hosts. Remember value | |
11498 | for emit_reloc. */ | |
11499 | value &= 0xffffffff; | |
11500 | value ^= 0x80000000; | |
11501 | value -= 0x80000000; | |
11502 | ||
11503 | *valP = value; | |
c19d1205 | 11504 | fixP->fx_addnumber = value; |
b99bd4ef | 11505 | |
adbaf948 ZW |
11506 | /* Same treatment for fixP->fx_offset. */ |
11507 | fixP->fx_offset &= 0xffffffff; | |
11508 | fixP->fx_offset ^= 0x80000000; | |
11509 | fixP->fx_offset -= 0x80000000; | |
11510 | ||
c19d1205 | 11511 | switch (fixP->fx_r_type) |
b99bd4ef | 11512 | { |
c19d1205 ZW |
11513 | case BFD_RELOC_NONE: |
11514 | /* This will need to go in the object file. */ | |
11515 | fixP->fx_done = 0; | |
11516 | break; | |
b99bd4ef | 11517 | |
c19d1205 ZW |
11518 | case BFD_RELOC_ARM_IMMEDIATE: |
11519 | /* We claim that this fixup has been processed here, | |
11520 | even if in fact we generate an error because we do | |
11521 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
11522 | fixP->fx_done = 1; | |
b99bd4ef | 11523 | |
c19d1205 ZW |
11524 | if (fixP->fx_addsy |
11525 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
b99bd4ef | 11526 | { |
c19d1205 ZW |
11527 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11528 | _("undefined symbol %s used as an immediate value"), | |
11529 | S_GET_NAME (fixP->fx_addsy)); | |
11530 | break; | |
b99bd4ef NC |
11531 | } |
11532 | ||
c19d1205 ZW |
11533 | newimm = encode_arm_immediate (value); |
11534 | temp = md_chars_to_number (buf, INSN_SIZE); | |
11535 | ||
11536 | /* If the instruction will fail, see if we can fix things up by | |
11537 | changing the opcode. */ | |
11538 | if (newimm == (unsigned int) FAIL | |
11539 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 11540 | { |
c19d1205 ZW |
11541 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11542 | _("invalid constant (%lx) after fixup"), | |
11543 | (unsigned long) value); | |
11544 | break; | |
b99bd4ef | 11545 | } |
b99bd4ef | 11546 | |
c19d1205 ZW |
11547 | newimm |= (temp & 0xfffff000); |
11548 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
11549 | break; | |
b99bd4ef | 11550 | |
c19d1205 ZW |
11551 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
11552 | { | |
11553 | unsigned int highpart = 0; | |
11554 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 11555 | |
c19d1205 ZW |
11556 | newimm = encode_arm_immediate (value); |
11557 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 11558 | |
c19d1205 ZW |
11559 | /* If the instruction will fail, see if we can fix things up by |
11560 | changing the opcode. */ | |
11561 | if (newimm == (unsigned int) FAIL | |
11562 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
11563 | { | |
11564 | /* No ? OK - try using two ADD instructions to generate | |
11565 | the value. */ | |
11566 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 11567 | |
c19d1205 ZW |
11568 | /* Yes - then make sure that the second instruction is |
11569 | also an add. */ | |
11570 | if (newimm != (unsigned int) FAIL) | |
11571 | newinsn = temp; | |
11572 | /* Still No ? Try using a negated value. */ | |
11573 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
11574 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
11575 | /* Otherwise - give up. */ | |
11576 | else | |
11577 | { | |
11578 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11579 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
11580 | (long) value); | |
11581 | break; | |
11582 | } | |
b99bd4ef | 11583 | |
c19d1205 ZW |
11584 | /* Replace the first operand in the 2nd instruction (which |
11585 | is the PC) with the destination register. We have | |
11586 | already added in the PC in the first instruction and we | |
11587 | do not want to do it again. */ | |
11588 | newinsn &= ~ 0xf0000; | |
11589 | newinsn |= ((newinsn & 0x0f000) << 4); | |
11590 | } | |
b99bd4ef | 11591 | |
c19d1205 ZW |
11592 | newimm |= (temp & 0xfffff000); |
11593 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 11594 | |
c19d1205 ZW |
11595 | highpart |= (newinsn & 0xfffff000); |
11596 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
11597 | } | |
11598 | break; | |
b99bd4ef | 11599 | |
c19d1205 | 11600 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
11601 | if (!fixP->fx_done && seg->use_rela_p) |
11602 | value = 0; | |
11603 | ||
c19d1205 ZW |
11604 | case BFD_RELOC_ARM_LITERAL: |
11605 | sign = value >= 0; | |
b99bd4ef | 11606 | |
c19d1205 ZW |
11607 | if (value < 0) |
11608 | value = - value; | |
b99bd4ef | 11609 | |
c19d1205 | 11610 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 11611 | { |
c19d1205 ZW |
11612 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
11613 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11614 | _("invalid literal constant: pool needs to be closer")); | |
11615 | else | |
11616 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11617 | _("bad immediate value for offset (%ld)"), | |
11618 | (long) value); | |
11619 | break; | |
f03698e6 RE |
11620 | } |
11621 | ||
c19d1205 ZW |
11622 | newval = md_chars_to_number (buf, INSN_SIZE); |
11623 | newval &= 0xff7ff000; | |
11624 | newval |= value | (sign ? INDEX_UP : 0); | |
11625 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11626 | break; | |
b99bd4ef | 11627 | |
c19d1205 ZW |
11628 | case BFD_RELOC_ARM_OFFSET_IMM8: |
11629 | case BFD_RELOC_ARM_HWLITERAL: | |
11630 | sign = value >= 0; | |
b99bd4ef | 11631 | |
c19d1205 ZW |
11632 | if (value < 0) |
11633 | value = - value; | |
b99bd4ef | 11634 | |
c19d1205 | 11635 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 11636 | { |
c19d1205 ZW |
11637 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
11638 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11639 | _("invalid literal constant: pool needs to be closer")); | |
11640 | else | |
11641 | as_bad (_("bad immediate value for half-word offset (%ld)"), | |
11642 | (long) value); | |
11643 | break; | |
b99bd4ef NC |
11644 | } |
11645 | ||
c19d1205 ZW |
11646 | newval = md_chars_to_number (buf, INSN_SIZE); |
11647 | newval &= 0xff7ff0f0; | |
11648 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
11649 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11650 | break; | |
b99bd4ef | 11651 | |
c19d1205 ZW |
11652 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
11653 | if (value < 0 || value > 1020 || value % 4 != 0) | |
11654 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11655 | _("bad immediate value for offset (%ld)"), (long) value); | |
11656 | value /= 4; | |
b99bd4ef | 11657 | |
c19d1205 | 11658 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
11659 | newval |= value; |
11660 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
11661 | break; | |
b99bd4ef | 11662 | |
c19d1205 ZW |
11663 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
11664 | /* This is a complicated relocation used for all varieties of Thumb32 | |
11665 | load/store instruction with immediate offset: | |
11666 | ||
11667 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
11668 | *4, optional writeback(W) | |
11669 | (doubleword load/store) | |
11670 | ||
11671 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
11672 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
11673 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
11674 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
11675 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
11676 | ||
11677 | Uppercase letters indicate bits that are already encoded at | |
11678 | this point. Lowercase letters are our problem. For the | |
11679 | second block of instructions, the secondary opcode nybble | |
11680 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
11681 | a PC-relative operation. */ | |
11682 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11683 | newval <<= 16; | |
11684 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 11685 | |
c19d1205 | 11686 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 11687 | { |
c19d1205 ZW |
11688 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
11689 | if (value >= 0) | |
11690 | newval |= (1 << 23); | |
11691 | else | |
11692 | value = -value; | |
11693 | if (value % 4 != 0) | |
11694 | { | |
11695 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11696 | _("offset not a multiple of 4")); | |
11697 | break; | |
11698 | } | |
11699 | value /= 4; | |
216d22bc | 11700 | if (value > 0xff) |
c19d1205 ZW |
11701 | { |
11702 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11703 | _("offset out of range")); | |
11704 | break; | |
11705 | } | |
11706 | newval &= ~0xff; | |
b99bd4ef | 11707 | } |
c19d1205 | 11708 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 11709 | { |
c19d1205 ZW |
11710 | /* PC-relative, 12-bit offset. */ |
11711 | if (value >= 0) | |
11712 | newval |= (1 << 23); | |
11713 | else | |
11714 | value = -value; | |
216d22bc | 11715 | if (value > 0xfff) |
c19d1205 ZW |
11716 | { |
11717 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11718 | _("offset out of range")); | |
11719 | break; | |
11720 | } | |
11721 | newval &= ~0xfff; | |
b99bd4ef | 11722 | } |
c19d1205 | 11723 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 11724 | { |
c19d1205 ZW |
11725 | /* Writeback: 8-bit, +/- offset. */ |
11726 | if (value >= 0) | |
11727 | newval |= (1 << 9); | |
11728 | else | |
11729 | value = -value; | |
216d22bc | 11730 | if (value > 0xff) |
c19d1205 ZW |
11731 | { |
11732 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11733 | _("offset out of range")); | |
11734 | break; | |
11735 | } | |
11736 | newval &= ~0xff; | |
b99bd4ef | 11737 | } |
c19d1205 | 11738 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 11739 | { |
c19d1205 | 11740 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 11741 | if (value < 0 || value > 0xff) |
b99bd4ef | 11742 | { |
c19d1205 ZW |
11743 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11744 | _("offset out of range")); | |
11745 | break; | |
b99bd4ef | 11746 | } |
c19d1205 ZW |
11747 | newval &= ~0xff; |
11748 | newval |= value; | |
b99bd4ef NC |
11749 | } |
11750 | else | |
b99bd4ef | 11751 | { |
c19d1205 ZW |
11752 | /* Positive 12-bit or negative 8-bit offset. */ |
11753 | int limit; | |
11754 | if (value >= 0) | |
b99bd4ef | 11755 | { |
c19d1205 ZW |
11756 | newval |= (1 << 23); |
11757 | limit = 0xfff; | |
11758 | } | |
11759 | else | |
11760 | { | |
11761 | value = -value; | |
11762 | limit = 0xff; | |
11763 | } | |
11764 | if (value > limit) | |
11765 | { | |
11766 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11767 | _("offset out of range")); | |
11768 | break; | |
b99bd4ef | 11769 | } |
c19d1205 | 11770 | newval &= ~limit; |
b99bd4ef | 11771 | } |
b99bd4ef | 11772 | |
c19d1205 ZW |
11773 | newval |= value; |
11774 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
11775 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
11776 | break; | |
404ff6b5 | 11777 | |
c19d1205 ZW |
11778 | case BFD_RELOC_ARM_SHIFT_IMM: |
11779 | newval = md_chars_to_number (buf, INSN_SIZE); | |
11780 | if (((unsigned long) value) > 32 | |
11781 | || (value == 32 | |
11782 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
11783 | { | |
11784 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11785 | _("shift expression is too large")); | |
11786 | break; | |
11787 | } | |
404ff6b5 | 11788 | |
c19d1205 ZW |
11789 | if (value == 0) |
11790 | /* Shifts of zero must be done as lsl. */ | |
11791 | newval &= ~0x60; | |
11792 | else if (value == 32) | |
11793 | value = 0; | |
11794 | newval &= 0xfffff07f; | |
11795 | newval |= (value & 0x1f) << 7; | |
11796 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11797 | break; | |
404ff6b5 | 11798 | |
c19d1205 | 11799 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
92e90b6e | 11800 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 11801 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
11802 | /* We claim that this fixup has been processed here, |
11803 | even if in fact we generate an error because we do | |
11804 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
11805 | fixP->fx_done = 1; | |
404ff6b5 | 11806 | |
c19d1205 ZW |
11807 | if (fixP->fx_addsy |
11808 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
11809 | { | |
11810 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11811 | _("undefined symbol %s used as an immediate value"), | |
11812 | S_GET_NAME (fixP->fx_addsy)); | |
11813 | break; | |
11814 | } | |
404ff6b5 | 11815 | |
c19d1205 ZW |
11816 | newval = md_chars_to_number (buf, THUMB_SIZE); |
11817 | newval <<= 16; | |
11818 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 11819 | |
e9f89963 PB |
11820 | /* FUTURE: Implement analogue of negate_data_op for T32. */ |
11821 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE) | |
ef8d22e6 PB |
11822 | { |
11823 | newimm = encode_thumb32_immediate (value); | |
11824 | if (newimm == (unsigned int) FAIL) | |
11825 | newimm = thumb32_negate_data_op (&newval, value); | |
11826 | } | |
e9f89963 | 11827 | else |
92e90b6e | 11828 | { |
e9f89963 PB |
11829 | /* 12 bit immediate for addw/subw. */ |
11830 | if (value < 0) | |
11831 | { | |
11832 | value = -value; | |
11833 | newval ^= 0x00a00000; | |
11834 | } | |
92e90b6e PB |
11835 | if (value > 0xfff) |
11836 | newimm = (unsigned int) FAIL; | |
11837 | else | |
11838 | newimm = value; | |
11839 | } | |
cc8a6dd0 | 11840 | |
c19d1205 | 11841 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 11842 | { |
c19d1205 ZW |
11843 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11844 | _("invalid constant (%lx) after fixup"), | |
11845 | (unsigned long) value); | |
11846 | break; | |
3631a3c8 NC |
11847 | } |
11848 | ||
c19d1205 ZW |
11849 | newval |= (newimm & 0x800) << 15; |
11850 | newval |= (newimm & 0x700) << 4; | |
11851 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 11852 | |
c19d1205 ZW |
11853 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
11854 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
11855 | break; | |
a737bd4d | 11856 | |
3eb17e6b | 11857 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
11858 | if (((unsigned long) value) > 0xffff) |
11859 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 11860 | _("invalid smc expression")); |
2fc8bdac | 11861 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
11862 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
11863 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11864 | break; | |
a737bd4d | 11865 | |
c19d1205 | 11866 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 11867 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
11868 | { |
11869 | if (((unsigned long) value) > 0xff) | |
11870 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11871 | _("invalid swi expression")); | |
2fc8bdac | 11872 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
11873 | newval |= value; |
11874 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11875 | } | |
11876 | else | |
11877 | { | |
11878 | if (((unsigned long) value) > 0x00ffffff) | |
11879 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11880 | _("invalid swi expression")); | |
2fc8bdac | 11881 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
11882 | newval |= value; |
11883 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11884 | } | |
11885 | break; | |
a737bd4d | 11886 | |
c19d1205 ZW |
11887 | case BFD_RELOC_ARM_MULTI: |
11888 | if (((unsigned long) value) > 0xffff) | |
11889 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11890 | _("invalid expression in load/store multiple")); | |
11891 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
11892 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11893 | break; | |
a737bd4d | 11894 | |
c19d1205 | 11895 | #ifdef OBJ_ELF |
39b41c9c PB |
11896 | case BFD_RELOC_ARM_PCREL_CALL: |
11897 | newval = md_chars_to_number (buf, INSN_SIZE); | |
11898 | if ((newval & 0xf0000000) == 0xf0000000) | |
11899 | temp = 1; | |
11900 | else | |
11901 | temp = 3; | |
11902 | goto arm_branch_common; | |
11903 | ||
11904 | case BFD_RELOC_ARM_PCREL_JUMP: | |
2fc8bdac | 11905 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 11906 | #endif |
39b41c9c PB |
11907 | case BFD_RELOC_ARM_PCREL_BRANCH: |
11908 | temp = 3; | |
11909 | goto arm_branch_common; | |
a737bd4d | 11910 | |
39b41c9c PB |
11911 | case BFD_RELOC_ARM_PCREL_BLX: |
11912 | temp = 1; | |
11913 | arm_branch_common: | |
c19d1205 | 11914 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
11915 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
11916 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
11917 | also be be clear. */ | |
11918 | if (value & temp) | |
c19d1205 | 11919 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
11920 | _("misaligned branch destination")); |
11921 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
11922 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
11923 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11924 | _("branch out of range")); | |
a737bd4d | 11925 | |
2fc8bdac | 11926 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11927 | { |
2fc8bdac ZW |
11928 | newval = md_chars_to_number (buf, INSN_SIZE); |
11929 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
11930 | /* Set the H bit on BLX instructions. */ |
11931 | if (temp == 1) | |
11932 | { | |
11933 | if (value & 2) | |
11934 | newval |= 0x01000000; | |
11935 | else | |
11936 | newval &= ~0x01000000; | |
11937 | } | |
2fc8bdac | 11938 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 11939 | } |
c19d1205 | 11940 | break; |
a737bd4d | 11941 | |
c19d1205 | 11942 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */ |
2fc8bdac ZW |
11943 | /* CZB can only branch forward. */ |
11944 | if (value & ~0x7e) | |
11945 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11946 | _("branch out of range")); | |
a737bd4d | 11947 | |
2fc8bdac ZW |
11948 | if (fixP->fx_done || !seg->use_rela_p) |
11949 | { | |
11950 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
080eb7fe | 11951 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); |
2fc8bdac ZW |
11952 | md_number_to_chars (buf, newval, THUMB_SIZE); |
11953 | } | |
c19d1205 | 11954 | break; |
a737bd4d | 11955 | |
c19d1205 | 11956 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
11957 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
11958 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11959 | _("branch out of range")); | |
a737bd4d | 11960 | |
2fc8bdac ZW |
11961 | if (fixP->fx_done || !seg->use_rela_p) |
11962 | { | |
11963 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11964 | newval |= (value & 0x1ff) >> 1; | |
11965 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11966 | } | |
c19d1205 | 11967 | break; |
a737bd4d | 11968 | |
c19d1205 | 11969 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
11970 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
11971 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11972 | _("branch out of range")); | |
a737bd4d | 11973 | |
2fc8bdac ZW |
11974 | if (fixP->fx_done || !seg->use_rela_p) |
11975 | { | |
11976 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11977 | newval |= (value & 0xfff) >> 1; | |
11978 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11979 | } | |
c19d1205 | 11980 | break; |
a737bd4d | 11981 | |
c19d1205 | 11982 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
2fc8bdac ZW |
11983 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
11984 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11985 | _("conditional branch out of range")); | |
404ff6b5 | 11986 | |
2fc8bdac ZW |
11987 | if (fixP->fx_done || !seg->use_rela_p) |
11988 | { | |
11989 | offsetT newval2; | |
11990 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 11991 | |
2fc8bdac ZW |
11992 | S = (value & 0x00100000) >> 20; |
11993 | J2 = (value & 0x00080000) >> 19; | |
11994 | J1 = (value & 0x00040000) >> 18; | |
11995 | hi = (value & 0x0003f000) >> 12; | |
11996 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 11997 | |
2fc8bdac ZW |
11998 | newval = md_chars_to_number (buf, THUMB_SIZE); |
11999 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
12000 | newval |= (S << 10) | hi; | |
12001 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
12002 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12003 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
12004 | } | |
c19d1205 | 12005 | break; |
6c43fab6 | 12006 | |
c19d1205 ZW |
12007 | case BFD_RELOC_THUMB_PCREL_BLX: |
12008 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
2fc8bdac ZW |
12009 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
12010 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12011 | _("branch out of range")); | |
404ff6b5 | 12012 | |
2fc8bdac ZW |
12013 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
12014 | /* For a BLX instruction, make sure that the relocation is rounded up | |
12015 | to a word boundary. This follows the semantics of the instruction | |
12016 | which specifies that bit 1 of the target address will come from bit | |
12017 | 1 of the base address. */ | |
12018 | value = (value + 1) & ~ 1; | |
404ff6b5 | 12019 | |
2fc8bdac | 12020 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 12021 | { |
2fc8bdac ZW |
12022 | offsetT newval2; |
12023 | ||
12024 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
12025 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
12026 | newval |= (value & 0x7fffff) >> 12; | |
12027 | newval2 |= (value & 0xfff) >> 1; | |
12028 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12029 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
c19d1205 | 12030 | } |
c19d1205 | 12031 | break; |
404ff6b5 | 12032 | |
c19d1205 | 12033 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
12034 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
12035 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12036 | _("branch out of range")); | |
6c43fab6 | 12037 | |
2fc8bdac ZW |
12038 | if (fixP->fx_done || !seg->use_rela_p) |
12039 | { | |
12040 | offsetT newval2; | |
12041 | addressT S, I1, I2, lo, hi; | |
6c43fab6 | 12042 | |
2fc8bdac ZW |
12043 | S = (value & 0x01000000) >> 24; |
12044 | I1 = (value & 0x00800000) >> 23; | |
12045 | I2 = (value & 0x00400000) >> 22; | |
12046 | hi = (value & 0x003ff000) >> 12; | |
12047 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 12048 | |
2fc8bdac ZW |
12049 | I1 = !(I1 ^ S); |
12050 | I2 = !(I2 ^ S); | |
a737bd4d | 12051 | |
2fc8bdac ZW |
12052 | newval = md_chars_to_number (buf, THUMB_SIZE); |
12053 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
12054 | newval |= (S << 10) | hi; | |
12055 | newval2 |= (I1 << 13) | (I2 << 11) | lo; | |
12056 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12057 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
12058 | } | |
12059 | break; | |
a737bd4d | 12060 | |
2fc8bdac ZW |
12061 | case BFD_RELOC_8: |
12062 | if (fixP->fx_done || !seg->use_rela_p) | |
12063 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 12064 | break; |
a737bd4d | 12065 | |
c19d1205 | 12066 | case BFD_RELOC_16: |
2fc8bdac | 12067 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 12068 | md_number_to_chars (buf, value, 2); |
c19d1205 | 12069 | break; |
a737bd4d | 12070 | |
c19d1205 ZW |
12071 | #ifdef OBJ_ELF |
12072 | case BFD_RELOC_ARM_TLS_GD32: | |
12073 | case BFD_RELOC_ARM_TLS_LE32: | |
12074 | case BFD_RELOC_ARM_TLS_IE32: | |
12075 | case BFD_RELOC_ARM_TLS_LDM32: | |
12076 | case BFD_RELOC_ARM_TLS_LDO32: | |
12077 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12078 | /* fall through */ | |
6c43fab6 | 12079 | |
c19d1205 ZW |
12080 | case BFD_RELOC_ARM_GOT32: |
12081 | case BFD_RELOC_ARM_GOTOFF: | |
12082 | case BFD_RELOC_ARM_TARGET2: | |
2fc8bdac ZW |
12083 | if (fixP->fx_done || !seg->use_rela_p) |
12084 | md_number_to_chars (buf, 0, 4); | |
c19d1205 ZW |
12085 | break; |
12086 | #endif | |
6c43fab6 | 12087 | |
c19d1205 ZW |
12088 | case BFD_RELOC_RVA: |
12089 | case BFD_RELOC_32: | |
12090 | case BFD_RELOC_ARM_TARGET1: | |
12091 | case BFD_RELOC_ARM_ROSEGREL32: | |
12092 | case BFD_RELOC_ARM_SBREL32: | |
12093 | case BFD_RELOC_32_PCREL: | |
2fc8bdac | 12094 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 12095 | md_number_to_chars (buf, value, 4); |
c19d1205 | 12096 | break; |
6c43fab6 | 12097 | |
c19d1205 ZW |
12098 | #ifdef OBJ_ELF |
12099 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 12100 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
12101 | { |
12102 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
12103 | if ((value ^ (value >> 1)) & 0x40000000) | |
12104 | { | |
12105 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12106 | _("rel31 relocation overflow")); | |
12107 | } | |
12108 | newval |= value & 0x7fffffff; | |
12109 | md_number_to_chars (buf, newval, 4); | |
12110 | } | |
12111 | break; | |
c19d1205 | 12112 | #endif |
a737bd4d | 12113 | |
c19d1205 | 12114 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 12115 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
12116 | if (value < -1023 || value > 1023 || (value & 3)) |
12117 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12118 | _("co-processor offset out of range")); | |
12119 | cp_off_common: | |
12120 | sign = value >= 0; | |
12121 | if (value < 0) | |
12122 | value = -value; | |
8f06b2d8 PB |
12123 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
12124 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
12125 | newval = md_chars_to_number (buf, INSN_SIZE); | |
12126 | else | |
12127 | newval = get_thumb32_insn (buf); | |
12128 | newval &= 0xff7fff00; | |
c19d1205 ZW |
12129 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
12130 | if (value == 0) | |
12131 | newval &= ~WRITE_BACK; | |
8f06b2d8 PB |
12132 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
12133 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
12134 | md_number_to_chars (buf, newval, INSN_SIZE); | |
12135 | else | |
12136 | put_thumb32_insn (buf, newval); | |
c19d1205 | 12137 | break; |
a737bd4d | 12138 | |
c19d1205 | 12139 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 12140 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
12141 | if (value < -255 || value > 255) |
12142 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12143 | _("co-processor offset out of range")); | |
12144 | goto cp_off_common; | |
6c43fab6 | 12145 | |
c19d1205 ZW |
12146 | case BFD_RELOC_ARM_THUMB_OFFSET: |
12147 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
12148 | /* Exactly what ranges, and where the offset is inserted depends | |
12149 | on the type of instruction, we can establish this from the | |
12150 | top 4 bits. */ | |
12151 | switch (newval >> 12) | |
12152 | { | |
12153 | case 4: /* PC load. */ | |
12154 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
12155 | forced to zero for these loads; md_pcrel_from has already | |
12156 | compensated for this. */ | |
12157 | if (value & 3) | |
12158 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12159 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
12160 | (((unsigned long) fixP->fx_frag->fr_address |
12161 | + (unsigned long) fixP->fx_where) & ~3) | |
12162 | + (unsigned long) value); | |
a737bd4d | 12163 | |
c19d1205 ZW |
12164 | if (value & ~0x3fc) |
12165 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12166 | _("invalid offset, value too big (0x%08lX)"), | |
12167 | (long) value); | |
a737bd4d | 12168 | |
c19d1205 ZW |
12169 | newval |= value >> 2; |
12170 | break; | |
a737bd4d | 12171 | |
c19d1205 ZW |
12172 | case 9: /* SP load/store. */ |
12173 | if (value & ~0x3fc) | |
12174 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12175 | _("invalid offset, value too big (0x%08lX)"), | |
12176 | (long) value); | |
12177 | newval |= value >> 2; | |
12178 | break; | |
6c43fab6 | 12179 | |
c19d1205 ZW |
12180 | case 6: /* Word load/store. */ |
12181 | if (value & ~0x7c) | |
12182 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12183 | _("invalid offset, value too big (0x%08lX)"), | |
12184 | (long) value); | |
12185 | newval |= value << 4; /* 6 - 2. */ | |
12186 | break; | |
a737bd4d | 12187 | |
c19d1205 ZW |
12188 | case 7: /* Byte load/store. */ |
12189 | if (value & ~0x1f) | |
12190 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12191 | _("invalid offset, value too big (0x%08lX)"), | |
12192 | (long) value); | |
12193 | newval |= value << 6; | |
12194 | break; | |
a737bd4d | 12195 | |
c19d1205 ZW |
12196 | case 8: /* Halfword load/store. */ |
12197 | if (value & ~0x3e) | |
12198 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12199 | _("invalid offset, value too big (0x%08lX)"), | |
12200 | (long) value); | |
12201 | newval |= value << 5; /* 6 - 1. */ | |
12202 | break; | |
a737bd4d | 12203 | |
c19d1205 ZW |
12204 | default: |
12205 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12206 | "Unable to process relocation for thumb opcode: %lx", | |
12207 | (unsigned long) newval); | |
12208 | break; | |
12209 | } | |
12210 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12211 | break; | |
a737bd4d | 12212 | |
c19d1205 ZW |
12213 | case BFD_RELOC_ARM_THUMB_ADD: |
12214 | /* This is a complicated relocation, since we use it for all of | |
12215 | the following immediate relocations: | |
a737bd4d | 12216 | |
c19d1205 ZW |
12217 | 3bit ADD/SUB |
12218 | 8bit ADD/SUB | |
12219 | 9bit ADD/SUB SP word-aligned | |
12220 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 12221 | |
c19d1205 ZW |
12222 | The type of instruction being processed is encoded in the |
12223 | instruction field: | |
a737bd4d | 12224 | |
c19d1205 ZW |
12225 | 0x8000 SUB |
12226 | 0x00F0 Rd | |
12227 | 0x000F Rs | |
12228 | */ | |
12229 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
12230 | { | |
12231 | int rd = (newval >> 4) & 0xf; | |
12232 | int rs = newval & 0xf; | |
12233 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 12234 | |
c19d1205 ZW |
12235 | /* Check for HI regs, only very restricted cases allowed: |
12236 | Adjusting SP, and using PC or SP to get an address. */ | |
12237 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
12238 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
12239 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12240 | _("invalid Hi register with immediate")); | |
a737bd4d | 12241 | |
c19d1205 ZW |
12242 | /* If value is negative, choose the opposite instruction. */ |
12243 | if (value < 0) | |
12244 | { | |
12245 | value = -value; | |
12246 | subtract = !subtract; | |
12247 | if (value < 0) | |
12248 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12249 | _("immediate value out of range")); | |
12250 | } | |
a737bd4d | 12251 | |
c19d1205 ZW |
12252 | if (rd == REG_SP) |
12253 | { | |
12254 | if (value & ~0x1fc) | |
12255 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12256 | _("invalid immediate for stack address calculation")); | |
12257 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
12258 | newval |= value >> 2; | |
12259 | } | |
12260 | else if (rs == REG_PC || rs == REG_SP) | |
12261 | { | |
12262 | if (subtract || value & ~0x3fc) | |
12263 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12264 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
12265 | (unsigned long) value); | |
12266 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
12267 | newval |= rd << 8; | |
12268 | newval |= value >> 2; | |
12269 | } | |
12270 | else if (rs == rd) | |
12271 | { | |
12272 | if (value & ~0xff) | |
12273 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12274 | _("immediate value out of range")); | |
12275 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
12276 | newval |= (rd << 8) | value; | |
12277 | } | |
12278 | else | |
12279 | { | |
12280 | if (value & ~0x7) | |
12281 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12282 | _("immediate value out of range")); | |
12283 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
12284 | newval |= rd | (rs << 3) | (value << 6); | |
12285 | } | |
12286 | } | |
12287 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12288 | break; | |
a737bd4d | 12289 | |
c19d1205 ZW |
12290 | case BFD_RELOC_ARM_THUMB_IMM: |
12291 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
12292 | if (value < 0 || value > 255) | |
12293 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12294 | _("invalid immediate: %ld is too large"), | |
12295 | (long) value); | |
12296 | newval |= value; | |
12297 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12298 | break; | |
a737bd4d | 12299 | |
c19d1205 ZW |
12300 | case BFD_RELOC_ARM_THUMB_SHIFT: |
12301 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
12302 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
12303 | temp = newval & 0xf800; | |
12304 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
12305 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12306 | _("invalid shift value: %ld"), (long) value); | |
12307 | /* Shifts of zero must be encoded as LSL. */ | |
12308 | if (value == 0) | |
12309 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
12310 | /* Shifts of 32 are encoded as zero. */ | |
12311 | else if (value == 32) | |
12312 | value = 0; | |
12313 | newval |= value << 6; | |
12314 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
12315 | break; | |
a737bd4d | 12316 | |
c19d1205 ZW |
12317 | case BFD_RELOC_VTABLE_INHERIT: |
12318 | case BFD_RELOC_VTABLE_ENTRY: | |
12319 | fixP->fx_done = 0; | |
12320 | return; | |
6c43fab6 | 12321 | |
c19d1205 ZW |
12322 | case BFD_RELOC_UNUSED: |
12323 | default: | |
12324 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12325 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
12326 | } | |
6c43fab6 RE |
12327 | } |
12328 | ||
c19d1205 ZW |
12329 | /* Translate internal representation of relocation info to BFD target |
12330 | format. */ | |
a737bd4d | 12331 | |
c19d1205 | 12332 | arelent * |
00a97672 | 12333 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 12334 | { |
c19d1205 ZW |
12335 | arelent * reloc; |
12336 | bfd_reloc_code_real_type code; | |
a737bd4d | 12337 | |
c19d1205 | 12338 | reloc = xmalloc (sizeof (arelent)); |
a737bd4d | 12339 | |
c19d1205 ZW |
12340 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
12341 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
12342 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 12343 | |
2fc8bdac | 12344 | if (fixp->fx_pcrel) |
00a97672 RS |
12345 | { |
12346 | if (section->use_rela_p) | |
12347 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
12348 | else | |
12349 | fixp->fx_offset = reloc->address; | |
12350 | } | |
c19d1205 | 12351 | reloc->addend = fixp->fx_offset; |
a737bd4d | 12352 | |
c19d1205 | 12353 | switch (fixp->fx_r_type) |
a737bd4d | 12354 | { |
c19d1205 ZW |
12355 | case BFD_RELOC_8: |
12356 | if (fixp->fx_pcrel) | |
12357 | { | |
12358 | code = BFD_RELOC_8_PCREL; | |
12359 | break; | |
12360 | } | |
a737bd4d | 12361 | |
c19d1205 ZW |
12362 | case BFD_RELOC_16: |
12363 | if (fixp->fx_pcrel) | |
12364 | { | |
12365 | code = BFD_RELOC_16_PCREL; | |
12366 | break; | |
12367 | } | |
6c43fab6 | 12368 | |
c19d1205 ZW |
12369 | case BFD_RELOC_32: |
12370 | if (fixp->fx_pcrel) | |
12371 | { | |
12372 | code = BFD_RELOC_32_PCREL; | |
12373 | break; | |
12374 | } | |
a737bd4d | 12375 | |
c19d1205 ZW |
12376 | case BFD_RELOC_NONE: |
12377 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
12378 | case BFD_RELOC_ARM_PCREL_BLX: | |
12379 | case BFD_RELOC_RVA: | |
12380 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
12381 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
12382 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
12383 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
12384 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
12385 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
12386 | case BFD_RELOC_THUMB_PCREL_BLX: | |
12387 | case BFD_RELOC_VTABLE_ENTRY: | |
12388 | case BFD_RELOC_VTABLE_INHERIT: | |
12389 | code = fixp->fx_r_type; | |
12390 | break; | |
a737bd4d | 12391 | |
c19d1205 ZW |
12392 | case BFD_RELOC_ARM_LITERAL: |
12393 | case BFD_RELOC_ARM_HWLITERAL: | |
12394 | /* If this is called then the a literal has | |
12395 | been referenced across a section boundary. */ | |
12396 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12397 | _("literal referenced across section boundary")); | |
12398 | return NULL; | |
a737bd4d | 12399 | |
c19d1205 ZW |
12400 | #ifdef OBJ_ELF |
12401 | case BFD_RELOC_ARM_GOT32: | |
12402 | case BFD_RELOC_ARM_GOTOFF: | |
12403 | case BFD_RELOC_ARM_PLT32: | |
12404 | case BFD_RELOC_ARM_TARGET1: | |
12405 | case BFD_RELOC_ARM_ROSEGREL32: | |
12406 | case BFD_RELOC_ARM_SBREL32: | |
12407 | case BFD_RELOC_ARM_PREL31: | |
12408 | case BFD_RELOC_ARM_TARGET2: | |
12409 | case BFD_RELOC_ARM_TLS_LE32: | |
12410 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
12411 | case BFD_RELOC_ARM_PCREL_CALL: |
12412 | case BFD_RELOC_ARM_PCREL_JUMP: | |
c19d1205 ZW |
12413 | code = fixp->fx_r_type; |
12414 | break; | |
a737bd4d | 12415 | |
c19d1205 ZW |
12416 | case BFD_RELOC_ARM_TLS_GD32: |
12417 | case BFD_RELOC_ARM_TLS_IE32: | |
12418 | case BFD_RELOC_ARM_TLS_LDM32: | |
12419 | /* BFD will include the symbol's address in the addend. | |
12420 | But we don't want that, so subtract it out again here. */ | |
12421 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
12422 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
12423 | code = fixp->fx_r_type; | |
12424 | break; | |
12425 | #endif | |
a737bd4d | 12426 | |
c19d1205 ZW |
12427 | case BFD_RELOC_ARM_IMMEDIATE: |
12428 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12429 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
12430 | return NULL; | |
a737bd4d | 12431 | |
c19d1205 ZW |
12432 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
12433 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12434 | _("ADRL used for a symbol not defined in the same file")); | |
12435 | return NULL; | |
a737bd4d | 12436 | |
c19d1205 | 12437 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
12438 | if (section->use_rela_p) |
12439 | { | |
12440 | code = fixp->fx_r_type; | |
12441 | break; | |
12442 | } | |
12443 | ||
c19d1205 ZW |
12444 | if (fixp->fx_addsy != NULL |
12445 | && !S_IS_DEFINED (fixp->fx_addsy) | |
12446 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 12447 | { |
c19d1205 ZW |
12448 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12449 | _("undefined local label `%s'"), | |
12450 | S_GET_NAME (fixp->fx_addsy)); | |
12451 | return NULL; | |
a737bd4d NC |
12452 | } |
12453 | ||
c19d1205 ZW |
12454 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12455 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
12456 | return NULL; | |
a737bd4d | 12457 | |
c19d1205 ZW |
12458 | default: |
12459 | { | |
12460 | char * type; | |
6c43fab6 | 12461 | |
c19d1205 ZW |
12462 | switch (fixp->fx_r_type) |
12463 | { | |
12464 | case BFD_RELOC_NONE: type = "NONE"; break; | |
12465 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
12466 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 12467 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
12468 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
12469 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
12470 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
8f06b2d8 | 12471 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
12472 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
12473 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
12474 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
12475 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
12476 | default: type = _("<unknown>"); break; | |
12477 | } | |
12478 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12479 | _("cannot represent %s relocation in this object file format"), | |
12480 | type); | |
12481 | return NULL; | |
12482 | } | |
a737bd4d | 12483 | } |
6c43fab6 | 12484 | |
c19d1205 ZW |
12485 | #ifdef OBJ_ELF |
12486 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
12487 | && GOT_symbol | |
12488 | && fixp->fx_addsy == GOT_symbol) | |
12489 | { | |
12490 | code = BFD_RELOC_ARM_GOTPC; | |
12491 | reloc->addend = fixp->fx_offset = reloc->address; | |
12492 | } | |
12493 | #endif | |
6c43fab6 | 12494 | |
c19d1205 | 12495 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 12496 | |
c19d1205 ZW |
12497 | if (reloc->howto == NULL) |
12498 | { | |
12499 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12500 | _("cannot represent %s relocation in this object file format"), | |
12501 | bfd_get_reloc_code_name (code)); | |
12502 | return NULL; | |
12503 | } | |
6c43fab6 | 12504 | |
c19d1205 ZW |
12505 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
12506 | vtable entry to be used in the relocation's section offset. */ | |
12507 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12508 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 12509 | |
c19d1205 | 12510 | return reloc; |
6c43fab6 RE |
12511 | } |
12512 | ||
c19d1205 | 12513 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 12514 | |
c19d1205 ZW |
12515 | void |
12516 | cons_fix_new_arm (fragS * frag, | |
12517 | int where, | |
12518 | int size, | |
12519 | expressionS * exp) | |
6c43fab6 | 12520 | { |
c19d1205 ZW |
12521 | bfd_reloc_code_real_type type; |
12522 | int pcrel = 0; | |
6c43fab6 | 12523 | |
c19d1205 ZW |
12524 | /* Pick a reloc. |
12525 | FIXME: @@ Should look at CPU word size. */ | |
12526 | switch (size) | |
12527 | { | |
12528 | case 1: | |
12529 | type = BFD_RELOC_8; | |
12530 | break; | |
12531 | case 2: | |
12532 | type = BFD_RELOC_16; | |
12533 | break; | |
12534 | case 4: | |
12535 | default: | |
12536 | type = BFD_RELOC_32; | |
12537 | break; | |
12538 | case 8: | |
12539 | type = BFD_RELOC_64; | |
12540 | break; | |
12541 | } | |
6c43fab6 | 12542 | |
c19d1205 ZW |
12543 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
12544 | } | |
6c43fab6 | 12545 | |
c19d1205 ZW |
12546 | #if defined OBJ_COFF || defined OBJ_ELF |
12547 | void | |
12548 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 12549 | { |
c19d1205 ZW |
12550 | /* If the destination of the branch is a defined symbol which does not have |
12551 | the THUMB_FUNC attribute, then we must be calling a function which has | |
12552 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
12553 | function and change the branch to refer to that function instead. */ | |
12554 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
12555 | && fixP->fx_addsy != NULL | |
12556 | && S_IS_DEFINED (fixP->fx_addsy) | |
12557 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 12558 | { |
c19d1205 | 12559 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 12560 | } |
c19d1205 ZW |
12561 | } |
12562 | #endif | |
6c43fab6 | 12563 | |
c19d1205 ZW |
12564 | int |
12565 | arm_force_relocation (struct fix * fixp) | |
12566 | { | |
12567 | #if defined (OBJ_COFF) && defined (TE_PE) | |
12568 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
12569 | return 1; | |
12570 | #endif | |
6c43fab6 | 12571 | |
c19d1205 ZW |
12572 | /* Resolve these relocations even if the symbol is extern or weak. */ |
12573 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
12574 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 PB |
12575 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
12576 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
12577 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
12578 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 12579 | return 0; |
a737bd4d | 12580 | |
c19d1205 | 12581 | return generic_force_reloc (fixp); |
404ff6b5 AH |
12582 | } |
12583 | ||
c19d1205 ZW |
12584 | #ifdef OBJ_COFF |
12585 | /* This is a little hack to help the gas/arm/adrl.s test. It prevents | |
12586 | local labels from being added to the output symbol table when they | |
12587 | are used with the ADRL pseudo op. The ADRL relocation should always | |
12588 | be resolved before the binbary is emitted, so it is safe to say that | |
12589 | it is adjustable. */ | |
404ff6b5 | 12590 | |
c19d1205 ZW |
12591 | bfd_boolean |
12592 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 12593 | { |
c19d1205 ZW |
12594 | if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE) |
12595 | return 1; | |
12596 | return 0; | |
404ff6b5 | 12597 | } |
c19d1205 | 12598 | #endif |
404ff6b5 | 12599 | |
c19d1205 ZW |
12600 | #ifdef OBJ_ELF |
12601 | /* Relocations against Thumb function names must be left unadjusted, | |
12602 | so that the linker can use this information to correctly set the | |
12603 | bottom bit of their addresses. The MIPS version of this function | |
12604 | also prevents relocations that are mips-16 specific, but I do not | |
12605 | know why it does this. | |
404ff6b5 | 12606 | |
c19d1205 ZW |
12607 | FIXME: |
12608 | There is one other problem that ought to be addressed here, but | |
12609 | which currently is not: Taking the address of a label (rather | |
12610 | than a function) and then later jumping to that address. Such | |
12611 | addresses also ought to have their bottom bit set (assuming that | |
12612 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 12613 | |
c19d1205 ZW |
12614 | bfd_boolean |
12615 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 12616 | { |
c19d1205 ZW |
12617 | if (fixP->fx_addsy == NULL) |
12618 | return 1; | |
404ff6b5 | 12619 | |
c19d1205 ZW |
12620 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
12621 | && fixP->fx_subsy == NULL) | |
12622 | return 0; | |
a737bd4d | 12623 | |
c19d1205 ZW |
12624 | /* We need the symbol name for the VTABLE entries. */ |
12625 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12626 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12627 | return 0; | |
404ff6b5 | 12628 | |
c19d1205 ZW |
12629 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
12630 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
12631 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
12632 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
12633 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
12634 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
12635 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
12636 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
12637 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
12638 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
12639 | return 0; | |
a737bd4d | 12640 | |
c19d1205 | 12641 | return 1; |
a737bd4d | 12642 | } |
404ff6b5 | 12643 | |
c19d1205 ZW |
12644 | const char * |
12645 | elf32_arm_target_format (void) | |
404ff6b5 | 12646 | { |
c19d1205 ZW |
12647 | #ifdef TE_SYMBIAN |
12648 | return (target_big_endian | |
12649 | ? "elf32-bigarm-symbian" | |
12650 | : "elf32-littlearm-symbian"); | |
12651 | #elif defined (TE_VXWORKS) | |
12652 | return (target_big_endian | |
12653 | ? "elf32-bigarm-vxworks" | |
12654 | : "elf32-littlearm-vxworks"); | |
12655 | #else | |
12656 | if (target_big_endian) | |
12657 | return "elf32-bigarm"; | |
12658 | else | |
12659 | return "elf32-littlearm"; | |
12660 | #endif | |
404ff6b5 AH |
12661 | } |
12662 | ||
c19d1205 ZW |
12663 | void |
12664 | armelf_frob_symbol (symbolS * symp, | |
12665 | int * puntp) | |
404ff6b5 | 12666 | { |
c19d1205 ZW |
12667 | elf_frob_symbol (symp, puntp); |
12668 | } | |
12669 | #endif | |
404ff6b5 | 12670 | |
c19d1205 | 12671 | /* MD interface: Finalization. */ |
a737bd4d | 12672 | |
c19d1205 ZW |
12673 | /* A good place to do this, although this was probably not intended |
12674 | for this kind of use. We need to dump the literal pool before | |
12675 | references are made to a null symbol pointer. */ | |
a737bd4d | 12676 | |
c19d1205 ZW |
12677 | void |
12678 | arm_cleanup (void) | |
12679 | { | |
12680 | literal_pool * pool; | |
a737bd4d | 12681 | |
c19d1205 ZW |
12682 | for (pool = list_of_pools; pool; pool = pool->next) |
12683 | { | |
12684 | /* Put it at the end of the relevent section. */ | |
12685 | subseg_set (pool->section, pool->sub_section); | |
12686 | #ifdef OBJ_ELF | |
12687 | arm_elf_change_section (); | |
12688 | #endif | |
12689 | s_ltorg (0); | |
12690 | } | |
404ff6b5 AH |
12691 | } |
12692 | ||
c19d1205 ZW |
12693 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
12694 | ARM ones. */ | |
404ff6b5 | 12695 | |
c19d1205 ZW |
12696 | void |
12697 | arm_adjust_symtab (void) | |
404ff6b5 | 12698 | { |
c19d1205 ZW |
12699 | #ifdef OBJ_COFF |
12700 | symbolS * sym; | |
404ff6b5 | 12701 | |
c19d1205 ZW |
12702 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
12703 | { | |
12704 | if (ARM_IS_THUMB (sym)) | |
12705 | { | |
12706 | if (THUMB_IS_FUNC (sym)) | |
12707 | { | |
12708 | /* Mark the symbol as a Thumb function. */ | |
12709 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
12710 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
12711 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 12712 | |
c19d1205 ZW |
12713 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
12714 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
12715 | else | |
12716 | as_bad (_("%s: unexpected function type: %d"), | |
12717 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
12718 | } | |
12719 | else switch (S_GET_STORAGE_CLASS (sym)) | |
12720 | { | |
12721 | case C_EXT: | |
12722 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
12723 | break; | |
12724 | case C_STAT: | |
12725 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
12726 | break; | |
12727 | case C_LABEL: | |
12728 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
12729 | break; | |
12730 | default: | |
12731 | /* Do nothing. */ | |
12732 | break; | |
12733 | } | |
12734 | } | |
a737bd4d | 12735 | |
c19d1205 ZW |
12736 | if (ARM_IS_INTERWORK (sym)) |
12737 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 12738 | } |
c19d1205 ZW |
12739 | #endif |
12740 | #ifdef OBJ_ELF | |
12741 | symbolS * sym; | |
12742 | char bind; | |
404ff6b5 | 12743 | |
c19d1205 | 12744 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 12745 | { |
c19d1205 ZW |
12746 | if (ARM_IS_THUMB (sym)) |
12747 | { | |
12748 | elf_symbol_type * elf_sym; | |
404ff6b5 | 12749 | |
c19d1205 ZW |
12750 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
12751 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 12752 | |
c19d1205 ZW |
12753 | if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name)) |
12754 | { | |
12755 | /* If it's a .thumb_func, declare it as so, | |
12756 | otherwise tag label as .code 16. */ | |
12757 | if (THUMB_IS_FUNC (sym)) | |
12758 | elf_sym->internal_elf_sym.st_info = | |
12759 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
12760 | else | |
12761 | elf_sym->internal_elf_sym.st_info = | |
12762 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
12763 | } | |
12764 | } | |
12765 | } | |
12766 | #endif | |
404ff6b5 AH |
12767 | } |
12768 | ||
c19d1205 | 12769 | /* MD interface: Initialization. */ |
404ff6b5 | 12770 | |
a737bd4d | 12771 | static void |
c19d1205 | 12772 | set_constant_flonums (void) |
a737bd4d | 12773 | { |
c19d1205 | 12774 | int i; |
404ff6b5 | 12775 | |
c19d1205 ZW |
12776 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
12777 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
12778 | abort (); | |
a737bd4d | 12779 | } |
404ff6b5 | 12780 | |
c19d1205 ZW |
12781 | void |
12782 | md_begin (void) | |
a737bd4d | 12783 | { |
c19d1205 ZW |
12784 | unsigned mach; |
12785 | unsigned int i; | |
404ff6b5 | 12786 | |
c19d1205 ZW |
12787 | if ( (arm_ops_hsh = hash_new ()) == NULL |
12788 | || (arm_cond_hsh = hash_new ()) == NULL | |
12789 | || (arm_shift_hsh = hash_new ()) == NULL | |
12790 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 12791 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 12792 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
12793 | || (arm_reloc_hsh = hash_new ()) == NULL |
12794 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
12795 | as_fatal (_("virtual memory exhausted")); |
12796 | ||
12797 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
12798 | hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); | |
12799 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) | |
12800 | hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); | |
12801 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) | |
12802 | hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); | |
12803 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) | |
12804 | hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); | |
62b3e311 PB |
12805 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
12806 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i)); | |
c19d1205 ZW |
12807 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
12808 | hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); | |
62b3e311 PB |
12809 | for (i = 0; |
12810 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
12811 | i++) | |
12812 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, | |
12813 | (PTR) (barrier_opt_names + i)); | |
c19d1205 ZW |
12814 | #ifdef OBJ_ELF |
12815 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
12816 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); | |
12817 | #endif | |
12818 | ||
12819 | set_constant_flonums (); | |
404ff6b5 | 12820 | |
c19d1205 ZW |
12821 | /* Set the cpu variant based on the command-line options. We prefer |
12822 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
12823 | -mfpu= over any other way of setting the floating point unit. | |
12824 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 12825 | if (legacy_cpu) |
404ff6b5 | 12826 | { |
e74cfd16 | 12827 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
12828 | as_bad (_("use of old and new-style options to set CPU type")); |
12829 | ||
12830 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 12831 | } |
e74cfd16 | 12832 | else if (!mcpu_cpu_opt) |
c19d1205 | 12833 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 12834 | |
e74cfd16 | 12835 | if (legacy_fpu) |
c19d1205 | 12836 | { |
e74cfd16 | 12837 | if (mfpu_opt) |
c19d1205 | 12838 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
12839 | |
12840 | mfpu_opt = legacy_fpu; | |
12841 | } | |
e74cfd16 | 12842 | else if (!mfpu_opt) |
03b1477f | 12843 | { |
c19d1205 | 12844 | #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) |
39c2da32 RE |
12845 | /* Some environments specify a default FPU. If they don't, infer it |
12846 | from the processor. */ | |
e74cfd16 | 12847 | if (mcpu_fpu_opt) |
03b1477f RE |
12848 | mfpu_opt = mcpu_fpu_opt; |
12849 | else | |
12850 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 12851 | #else |
e74cfd16 | 12852 | mfpu_opt = &fpu_default; |
39c2da32 | 12853 | #endif |
03b1477f RE |
12854 | } |
12855 | ||
e74cfd16 | 12856 | if (!mfpu_opt) |
03b1477f | 12857 | { |
e74cfd16 PB |
12858 | if (!mcpu_cpu_opt) |
12859 | mfpu_opt = &fpu_default; | |
12860 | else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) | |
12861 | mfpu_opt = &fpu_arch_vfp_v2; | |
03b1477f | 12862 | else |
e74cfd16 | 12863 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
12864 | } |
12865 | ||
ee065d83 | 12866 | #ifdef CPU_DEFAULT |
e74cfd16 | 12867 | if (!mcpu_cpu_opt) |
ee065d83 | 12868 | { |
e74cfd16 PB |
12869 | mcpu_cpu_opt = &cpu_default; |
12870 | selected_cpu = cpu_default; | |
ee065d83 | 12871 | } |
e74cfd16 PB |
12872 | #else |
12873 | if (mcpu_cpu_opt) | |
12874 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 12875 | else |
e74cfd16 | 12876 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 12877 | #endif |
03b1477f | 12878 | |
e74cfd16 | 12879 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 12880 | |
e74cfd16 | 12881 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 12882 | |
f17c130b | 12883 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 12884 | { |
7cc69913 NC |
12885 | unsigned int flags = 0; |
12886 | ||
12887 | #if defined OBJ_ELF | |
12888 | flags = meabi_flags; | |
d507cf36 PB |
12889 | |
12890 | switch (meabi_flags) | |
33a392fb | 12891 | { |
d507cf36 | 12892 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 12893 | #endif |
d507cf36 PB |
12894 | /* Set the flags in the private structure. */ |
12895 | if (uses_apcs_26) flags |= F_APCS26; | |
12896 | if (support_interwork) flags |= F_INTERWORK; | |
12897 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 12898 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 12899 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
12900 | flags |= F_SOFT_FLOAT; |
12901 | ||
d507cf36 PB |
12902 | switch (mfloat_abi_opt) |
12903 | { | |
12904 | case ARM_FLOAT_ABI_SOFT: | |
12905 | case ARM_FLOAT_ABI_SOFTFP: | |
12906 | flags |= F_SOFT_FLOAT; | |
12907 | break; | |
33a392fb | 12908 | |
d507cf36 PB |
12909 | case ARM_FLOAT_ABI_HARD: |
12910 | if (flags & F_SOFT_FLOAT) | |
12911 | as_bad (_("hard-float conflicts with specified fpu")); | |
12912 | break; | |
12913 | } | |
03b1477f | 12914 | |
e74cfd16 PB |
12915 | /* Using pure-endian doubles (even if soft-float). */ |
12916 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 12917 | flags |= F_VFP_FLOAT; |
f17c130b | 12918 | |
fde78edd | 12919 | #if defined OBJ_ELF |
e74cfd16 | 12920 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 12921 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
12922 | break; |
12923 | ||
8cb51566 | 12924 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 12925 | case EF_ARM_EABI_VER5: |
c19d1205 | 12926 | /* No additional flags to set. */ |
d507cf36 PB |
12927 | break; |
12928 | ||
12929 | default: | |
12930 | abort (); | |
12931 | } | |
7cc69913 | 12932 | #endif |
b99bd4ef NC |
12933 | bfd_set_private_flags (stdoutput, flags); |
12934 | ||
12935 | /* We have run out flags in the COFF header to encode the | |
12936 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 12937 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
12938 | if (atpcs) |
12939 | { | |
12940 | asection * sec; | |
12941 | ||
12942 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
12943 | ||
12944 | if (sec != NULL) | |
12945 | { | |
12946 | bfd_set_section_flags | |
12947 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
12948 | bfd_set_section_size (stdoutput, sec, 0); | |
12949 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
12950 | } | |
12951 | } | |
7cc69913 | 12952 | } |
f17c130b | 12953 | #endif |
b99bd4ef NC |
12954 | |
12955 | /* Record the CPU type as well. */ | |
e74cfd16 | 12956 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) |
e16bb312 | 12957 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 12958 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 12959 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 12960 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 12961 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 12962 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 12963 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 12964 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 12965 | { |
e74cfd16 | 12966 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
12967 | mach = bfd_mach_arm_5T; |
12968 | else | |
12969 | mach = bfd_mach_arm_5; | |
12970 | } | |
e74cfd16 | 12971 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 12972 | { |
e74cfd16 | 12973 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
12974 | mach = bfd_mach_arm_4T; |
12975 | else | |
12976 | mach = bfd_mach_arm_4; | |
12977 | } | |
e74cfd16 | 12978 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 12979 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
12980 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
12981 | mach = bfd_mach_arm_3; | |
12982 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
12983 | mach = bfd_mach_arm_2a; | |
12984 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
12985 | mach = bfd_mach_arm_2; | |
12986 | else | |
12987 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
12988 | |
12989 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
12990 | } | |
12991 | ||
c19d1205 | 12992 | /* Command line processing. */ |
b99bd4ef | 12993 | |
c19d1205 ZW |
12994 | /* md_parse_option |
12995 | Invocation line includes a switch not recognized by the base assembler. | |
12996 | See if it's a processor-specific option. | |
b99bd4ef | 12997 | |
c19d1205 ZW |
12998 | This routine is somewhat complicated by the need for backwards |
12999 | compatibility (since older releases of gcc can't be changed). | |
13000 | The new options try to make the interface as compatible as | |
13001 | possible with GCC. | |
b99bd4ef | 13002 | |
c19d1205 | 13003 | New options (supported) are: |
b99bd4ef | 13004 | |
c19d1205 ZW |
13005 | -mcpu=<cpu name> Assemble for selected processor |
13006 | -march=<architecture name> Assemble for selected architecture | |
13007 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
13008 | -EB/-mbig-endian Big-endian | |
13009 | -EL/-mlittle-endian Little-endian | |
13010 | -k Generate PIC code | |
13011 | -mthumb Start in Thumb mode | |
13012 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 13013 | |
c19d1205 | 13014 | For now we will also provide support for: |
b99bd4ef | 13015 | |
c19d1205 ZW |
13016 | -mapcs-32 32-bit Program counter |
13017 | -mapcs-26 26-bit Program counter | |
13018 | -macps-float Floats passed in FP registers | |
13019 | -mapcs-reentrant Reentrant code | |
13020 | -matpcs | |
13021 | (sometime these will probably be replaced with -mapcs=<list of options> | |
13022 | and -matpcs=<list of options>) | |
b99bd4ef | 13023 | |
c19d1205 ZW |
13024 | The remaining options are only supported for back-wards compatibility. |
13025 | Cpu variants, the arm part is optional: | |
13026 | -m[arm]1 Currently not supported. | |
13027 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
13028 | -m[arm]3 Arm 3 processor | |
13029 | -m[arm]6[xx], Arm 6 processors | |
13030 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
13031 | -m[arm]8[10] Arm 8 processors | |
13032 | -m[arm]9[20][tdmi] Arm 9 processors | |
13033 | -mstrongarm[110[0]] StrongARM processors | |
13034 | -mxscale XScale processors | |
13035 | -m[arm]v[2345[t[e]]] Arm architectures | |
13036 | -mall All (except the ARM1) | |
13037 | FP variants: | |
13038 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
13039 | -mfpe-old (No float load/store multiples) | |
13040 | -mvfpxd VFP Single precision | |
13041 | -mvfp All VFP | |
13042 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 13043 | |
c19d1205 ZW |
13044 | The following CPU names are recognized: |
13045 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
13046 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
13047 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
13048 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
13049 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
13050 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
13051 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 13052 | |
c19d1205 | 13053 | */ |
b99bd4ef | 13054 | |
c19d1205 | 13055 | const char * md_shortopts = "m:k"; |
b99bd4ef | 13056 | |
c19d1205 ZW |
13057 | #ifdef ARM_BI_ENDIAN |
13058 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
13059 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 13060 | #else |
c19d1205 ZW |
13061 | #if TARGET_BYTES_BIG_ENDIAN |
13062 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 13063 | #else |
c19d1205 ZW |
13064 | #define OPTION_EL (OPTION_MD_BASE + 1) |
13065 | #endif | |
b99bd4ef | 13066 | #endif |
b99bd4ef | 13067 | |
c19d1205 | 13068 | struct option md_longopts[] = |
b99bd4ef | 13069 | { |
c19d1205 ZW |
13070 | #ifdef OPTION_EB |
13071 | {"EB", no_argument, NULL, OPTION_EB}, | |
13072 | #endif | |
13073 | #ifdef OPTION_EL | |
13074 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 13075 | #endif |
c19d1205 ZW |
13076 | {NULL, no_argument, NULL, 0} |
13077 | }; | |
b99bd4ef | 13078 | |
c19d1205 | 13079 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 13080 | |
c19d1205 | 13081 | struct arm_option_table |
b99bd4ef | 13082 | { |
c19d1205 ZW |
13083 | char *option; /* Option name to match. */ |
13084 | char *help; /* Help information. */ | |
13085 | int *var; /* Variable to change. */ | |
13086 | int value; /* What to change it to. */ | |
13087 | char *deprecated; /* If non-null, print this message. */ | |
13088 | }; | |
b99bd4ef | 13089 | |
c19d1205 ZW |
13090 | struct arm_option_table arm_opts[] = |
13091 | { | |
13092 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
13093 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
13094 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
13095 | &support_interwork, 1, NULL}, | |
13096 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
13097 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
13098 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
13099 | 1, NULL}, | |
13100 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
13101 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
13102 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
13103 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
13104 | NULL}, | |
b99bd4ef | 13105 | |
c19d1205 ZW |
13106 | /* These are recognized by the assembler, but have no affect on code. */ |
13107 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
13108 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
e74cfd16 PB |
13109 | {NULL, NULL, NULL, 0, NULL} |
13110 | }; | |
13111 | ||
13112 | struct arm_legacy_option_table | |
13113 | { | |
13114 | char *option; /* Option name to match. */ | |
13115 | const arm_feature_set **var; /* Variable to change. */ | |
13116 | const arm_feature_set value; /* What to change it to. */ | |
13117 | char *deprecated; /* If non-null, print this message. */ | |
13118 | }; | |
b99bd4ef | 13119 | |
e74cfd16 PB |
13120 | const struct arm_legacy_option_table arm_legacy_opts[] = |
13121 | { | |
c19d1205 ZW |
13122 | /* DON'T add any new processors to this list -- we want the whole list |
13123 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
13124 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
13125 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
13126 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
13127 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
13128 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
13129 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
13130 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
13131 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
13132 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
13133 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
13134 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
13135 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
13136 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
13137 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
13138 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
13139 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
13140 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
13141 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
13142 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
13143 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
13144 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
13145 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
13146 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
13147 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
13148 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
13149 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
13150 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
13151 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
13152 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
13153 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
13154 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
13155 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
13156 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
13157 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
13158 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
13159 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
13160 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
13161 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
13162 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
13163 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
13164 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
13165 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
13166 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
13167 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
13168 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
13169 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
13170 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
13171 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
13172 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
13173 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
13174 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
13175 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
13176 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
13177 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
13178 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
13179 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
13180 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
13181 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
13182 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
13183 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
13184 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
13185 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
13186 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
13187 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
13188 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
13189 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
13190 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
13191 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
13192 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
13193 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 13194 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 13195 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 13196 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 13197 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 13198 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
13199 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
13200 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
13201 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 13202 | |
c19d1205 | 13203 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
13204 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
13205 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
13206 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
13207 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
13208 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
13209 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
13210 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
13211 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
13212 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
13213 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
13214 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
13215 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
13216 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
13217 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
13218 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
13219 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
13220 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
13221 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 13222 | |
c19d1205 | 13223 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
13224 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
13225 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
13226 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
13227 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 13228 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 13229 | |
e74cfd16 | 13230 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 13231 | }; |
7ed4c4c5 | 13232 | |
c19d1205 | 13233 | struct arm_cpu_option_table |
7ed4c4c5 | 13234 | { |
c19d1205 | 13235 | char *name; |
e74cfd16 | 13236 | const arm_feature_set value; |
c19d1205 ZW |
13237 | /* For some CPUs we assume an FPU unless the user explicitly sets |
13238 | -mfpu=... */ | |
e74cfd16 | 13239 | const arm_feature_set default_fpu; |
ee065d83 PB |
13240 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
13241 | case. */ | |
13242 | const char *canonical_name; | |
c19d1205 | 13243 | }; |
7ed4c4c5 | 13244 | |
c19d1205 ZW |
13245 | /* This list should, at a minimum, contain all the cpu names |
13246 | recognized by GCC. */ | |
e74cfd16 | 13247 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 13248 | { |
ee065d83 PB |
13249 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
13250 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
13251 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
13252 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
13253 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
13254 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13255 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13256 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13257 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13258 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13259 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13260 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
13261 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13262 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
13263 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13264 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
13265 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13266 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13267 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13268 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13269 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13270 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13271 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13272 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13273 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13274 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13275 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13276 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
13277 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13278 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13279 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13280 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
13281 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
13282 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
13283 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
13284 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
13285 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
13286 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
13287 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13288 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
13289 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13290 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13291 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
13292 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
13293 | /* For V5 or later processors we default to using VFP; but the user |
13294 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
13295 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
13296 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13297 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
13298 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
13299 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
13300 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
13301 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
13302 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13303 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
13304 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
13305 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13306 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13307 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
13308 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
13309 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13310 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
13311 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
13312 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13313 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
13314 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
13315 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
13316 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, | |
13317 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
13318 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
13319 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
13320 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, | |
13321 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, | |
13322 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, | |
13323 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
13324 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
13325 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
62b3e311 PB |
13326 | {"cortex-a8", ARM_ARCH_V7A, FPU_ARCH_VFP_V2, NULL}, |
13327 | {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, | |
13328 | {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, | |
c19d1205 | 13329 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 13330 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 13331 | /* ??? iwmmxt is not a processor. */ |
ee065d83 PB |
13332 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
13333 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, | |
c19d1205 | 13334 | /* Maverick */ |
e74cfd16 PB |
13335 | {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
13336 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} | |
c19d1205 | 13337 | }; |
7ed4c4c5 | 13338 | |
c19d1205 | 13339 | struct arm_arch_option_table |
7ed4c4c5 | 13340 | { |
c19d1205 | 13341 | char *name; |
e74cfd16 PB |
13342 | const arm_feature_set value; |
13343 | const arm_feature_set default_fpu; | |
c19d1205 | 13344 | }; |
7ed4c4c5 | 13345 | |
c19d1205 ZW |
13346 | /* This list should, at a minimum, contain all the architecture names |
13347 | recognized by GCC. */ | |
e74cfd16 | 13348 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
13349 | { |
13350 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
13351 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
13352 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
13353 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
13354 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
13355 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
13356 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
13357 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
13358 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
13359 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
13360 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
13361 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
13362 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
13363 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
13364 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
13365 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
13366 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
13367 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
13368 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
13369 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
13370 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
13371 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
13372 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
13373 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
13374 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
13375 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
62b3e311 PB |
13376 | {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, |
13377 | {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, | |
13378 | {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
13379 | {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c19d1205 ZW |
13380 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, |
13381 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
e74cfd16 | 13382 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 13383 | }; |
7ed4c4c5 | 13384 | |
c19d1205 | 13385 | /* ISA extensions in the co-processor space. */ |
e74cfd16 | 13386 | struct arm_option_cpu_value_table |
c19d1205 ZW |
13387 | { |
13388 | char *name; | |
e74cfd16 | 13389 | const arm_feature_set value; |
c19d1205 | 13390 | }; |
7ed4c4c5 | 13391 | |
e74cfd16 | 13392 | static const struct arm_option_cpu_value_table arm_extensions[] = |
c19d1205 | 13393 | { |
e74cfd16 PB |
13394 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, |
13395 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, | |
13396 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, | |
13397 | {NULL, ARM_ARCH_NONE} | |
c19d1205 | 13398 | }; |
7ed4c4c5 | 13399 | |
c19d1205 ZW |
13400 | /* This list should, at a minimum, contain all the fpu names |
13401 | recognized by GCC. */ | |
e74cfd16 | 13402 | static const struct arm_option_cpu_value_table arm_fpus[] = |
c19d1205 ZW |
13403 | { |
13404 | {"softfpa", FPU_NONE}, | |
13405 | {"fpe", FPU_ARCH_FPE}, | |
13406 | {"fpe2", FPU_ARCH_FPE}, | |
13407 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
13408 | {"fpa", FPU_ARCH_FPA}, | |
13409 | {"fpa10", FPU_ARCH_FPA}, | |
13410 | {"fpa11", FPU_ARCH_FPA}, | |
13411 | {"arm7500fe", FPU_ARCH_FPA}, | |
13412 | {"softvfp", FPU_ARCH_VFP}, | |
13413 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
13414 | {"vfp", FPU_ARCH_VFP_V2}, | |
13415 | {"vfp9", FPU_ARCH_VFP_V2}, | |
13416 | {"vfp10", FPU_ARCH_VFP_V2}, | |
13417 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
13418 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
13419 | {"arm1020t", FPU_ARCH_VFP_V1}, | |
13420 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
13421 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
13422 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
13423 | {"maverick", FPU_ARCH_MAVERICK}, | |
e74cfd16 PB |
13424 | {NULL, ARM_ARCH_NONE} |
13425 | }; | |
13426 | ||
13427 | struct arm_option_value_table | |
13428 | { | |
13429 | char *name; | |
13430 | long value; | |
c19d1205 | 13431 | }; |
7ed4c4c5 | 13432 | |
e74cfd16 | 13433 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
13434 | { |
13435 | {"hard", ARM_FLOAT_ABI_HARD}, | |
13436 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
13437 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 13438 | {NULL, 0} |
c19d1205 | 13439 | }; |
7ed4c4c5 | 13440 | |
c19d1205 | 13441 | #ifdef OBJ_ELF |
3a4a14e9 | 13442 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 13443 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
13444 | { |
13445 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
13446 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 13447 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 13448 | {NULL, 0} |
c19d1205 ZW |
13449 | }; |
13450 | #endif | |
7ed4c4c5 | 13451 | |
c19d1205 ZW |
13452 | struct arm_long_option_table |
13453 | { | |
13454 | char * option; /* Substring to match. */ | |
13455 | char * help; /* Help information. */ | |
13456 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
13457 | char * deprecated; /* If non-null, print this message. */ | |
13458 | }; | |
7ed4c4c5 NC |
13459 | |
13460 | static int | |
e74cfd16 | 13461 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 13462 | { |
e74cfd16 PB |
13463 | arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); |
13464 | ||
13465 | /* Copy the feature set, so that we can modify it. */ | |
13466 | *ext_set = **opt_p; | |
13467 | *opt_p = ext_set; | |
13468 | ||
c19d1205 | 13469 | while (str != NULL && *str != 0) |
7ed4c4c5 | 13470 | { |
e74cfd16 | 13471 | const struct arm_option_cpu_value_table * opt; |
c19d1205 ZW |
13472 | char * ext; |
13473 | int optlen; | |
7ed4c4c5 | 13474 | |
c19d1205 ZW |
13475 | if (*str != '+') |
13476 | { | |
13477 | as_bad (_("invalid architectural extension")); | |
13478 | return 0; | |
13479 | } | |
7ed4c4c5 | 13480 | |
c19d1205 ZW |
13481 | str++; |
13482 | ext = strchr (str, '+'); | |
7ed4c4c5 | 13483 | |
c19d1205 ZW |
13484 | if (ext != NULL) |
13485 | optlen = ext - str; | |
13486 | else | |
13487 | optlen = strlen (str); | |
7ed4c4c5 | 13488 | |
c19d1205 ZW |
13489 | if (optlen == 0) |
13490 | { | |
13491 | as_bad (_("missing architectural extension")); | |
13492 | return 0; | |
13493 | } | |
7ed4c4c5 | 13494 | |
c19d1205 ZW |
13495 | for (opt = arm_extensions; opt->name != NULL; opt++) |
13496 | if (strncmp (opt->name, str, optlen) == 0) | |
13497 | { | |
e74cfd16 | 13498 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); |
c19d1205 ZW |
13499 | break; |
13500 | } | |
7ed4c4c5 | 13501 | |
c19d1205 ZW |
13502 | if (opt->name == NULL) |
13503 | { | |
13504 | as_bad (_("unknown architectural extnsion `%s'"), str); | |
13505 | return 0; | |
13506 | } | |
7ed4c4c5 | 13507 | |
c19d1205 ZW |
13508 | str = ext; |
13509 | }; | |
7ed4c4c5 | 13510 | |
c19d1205 ZW |
13511 | return 1; |
13512 | } | |
7ed4c4c5 | 13513 | |
c19d1205 ZW |
13514 | static int |
13515 | arm_parse_cpu (char * str) | |
7ed4c4c5 | 13516 | { |
e74cfd16 | 13517 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
13518 | char * ext = strchr (str, '+'); |
13519 | int optlen; | |
7ed4c4c5 | 13520 | |
c19d1205 ZW |
13521 | if (ext != NULL) |
13522 | optlen = ext - str; | |
7ed4c4c5 | 13523 | else |
c19d1205 | 13524 | optlen = strlen (str); |
7ed4c4c5 | 13525 | |
c19d1205 | 13526 | if (optlen == 0) |
7ed4c4c5 | 13527 | { |
c19d1205 ZW |
13528 | as_bad (_("missing cpu name `%s'"), str); |
13529 | return 0; | |
7ed4c4c5 NC |
13530 | } |
13531 | ||
c19d1205 ZW |
13532 | for (opt = arm_cpus; opt->name != NULL; opt++) |
13533 | if (strncmp (opt->name, str, optlen) == 0) | |
13534 | { | |
e74cfd16 PB |
13535 | mcpu_cpu_opt = &opt->value; |
13536 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 PB |
13537 | if (opt->canonical_name) |
13538 | strcpy(selected_cpu_name, opt->canonical_name); | |
13539 | else | |
13540 | { | |
13541 | int i; | |
13542 | for (i = 0; i < optlen; i++) | |
13543 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
13544 | selected_cpu_name[i] = 0; | |
13545 | } | |
7ed4c4c5 | 13546 | |
c19d1205 ZW |
13547 | if (ext != NULL) |
13548 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 13549 | |
c19d1205 ZW |
13550 | return 1; |
13551 | } | |
7ed4c4c5 | 13552 | |
c19d1205 ZW |
13553 | as_bad (_("unknown cpu `%s'"), str); |
13554 | return 0; | |
7ed4c4c5 NC |
13555 | } |
13556 | ||
c19d1205 ZW |
13557 | static int |
13558 | arm_parse_arch (char * str) | |
7ed4c4c5 | 13559 | { |
e74cfd16 | 13560 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
13561 | char *ext = strchr (str, '+'); |
13562 | int optlen; | |
7ed4c4c5 | 13563 | |
c19d1205 ZW |
13564 | if (ext != NULL) |
13565 | optlen = ext - str; | |
7ed4c4c5 | 13566 | else |
c19d1205 | 13567 | optlen = strlen (str); |
7ed4c4c5 | 13568 | |
c19d1205 | 13569 | if (optlen == 0) |
7ed4c4c5 | 13570 | { |
c19d1205 ZW |
13571 | as_bad (_("missing architecture name `%s'"), str); |
13572 | return 0; | |
7ed4c4c5 NC |
13573 | } |
13574 | ||
c19d1205 ZW |
13575 | for (opt = arm_archs; opt->name != NULL; opt++) |
13576 | if (streq (opt->name, str)) | |
13577 | { | |
e74cfd16 PB |
13578 | march_cpu_opt = &opt->value; |
13579 | march_fpu_opt = &opt->default_fpu; | |
ee065d83 | 13580 | strcpy(selected_cpu_name, opt->name); |
7ed4c4c5 | 13581 | |
c19d1205 ZW |
13582 | if (ext != NULL) |
13583 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 13584 | |
c19d1205 ZW |
13585 | return 1; |
13586 | } | |
13587 | ||
13588 | as_bad (_("unknown architecture `%s'\n"), str); | |
13589 | return 0; | |
7ed4c4c5 | 13590 | } |
eb043451 | 13591 | |
c19d1205 ZW |
13592 | static int |
13593 | arm_parse_fpu (char * str) | |
13594 | { | |
e74cfd16 | 13595 | const struct arm_option_cpu_value_table * opt; |
b99bd4ef | 13596 | |
c19d1205 ZW |
13597 | for (opt = arm_fpus; opt->name != NULL; opt++) |
13598 | if (streq (opt->name, str)) | |
13599 | { | |
e74cfd16 | 13600 | mfpu_opt = &opt->value; |
c19d1205 ZW |
13601 | return 1; |
13602 | } | |
b99bd4ef | 13603 | |
c19d1205 ZW |
13604 | as_bad (_("unknown floating point format `%s'\n"), str); |
13605 | return 0; | |
13606 | } | |
13607 | ||
13608 | static int | |
13609 | arm_parse_float_abi (char * str) | |
b99bd4ef | 13610 | { |
e74cfd16 | 13611 | const struct arm_option_value_table * opt; |
b99bd4ef | 13612 | |
c19d1205 ZW |
13613 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
13614 | if (streq (opt->name, str)) | |
13615 | { | |
13616 | mfloat_abi_opt = opt->value; | |
13617 | return 1; | |
13618 | } | |
cc8a6dd0 | 13619 | |
c19d1205 ZW |
13620 | as_bad (_("unknown floating point abi `%s'\n"), str); |
13621 | return 0; | |
13622 | } | |
b99bd4ef | 13623 | |
c19d1205 ZW |
13624 | #ifdef OBJ_ELF |
13625 | static int | |
13626 | arm_parse_eabi (char * str) | |
13627 | { | |
e74cfd16 | 13628 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 13629 | |
c19d1205 ZW |
13630 | for (opt = arm_eabis; opt->name != NULL; opt++) |
13631 | if (streq (opt->name, str)) | |
13632 | { | |
13633 | meabi_flags = opt->value; | |
13634 | return 1; | |
13635 | } | |
13636 | as_bad (_("unknown EABI `%s'\n"), str); | |
13637 | return 0; | |
13638 | } | |
13639 | #endif | |
cc8a6dd0 | 13640 | |
c19d1205 ZW |
13641 | struct arm_long_option_table arm_long_opts[] = |
13642 | { | |
13643 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
13644 | arm_parse_cpu, NULL}, | |
13645 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
13646 | arm_parse_arch, NULL}, | |
13647 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
13648 | arm_parse_fpu, NULL}, | |
13649 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
13650 | arm_parse_float_abi, NULL}, | |
13651 | #ifdef OBJ_ELF | |
13652 | {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), | |
13653 | arm_parse_eabi, NULL}, | |
13654 | #endif | |
13655 | {NULL, NULL, 0, NULL} | |
13656 | }; | |
cc8a6dd0 | 13657 | |
c19d1205 ZW |
13658 | int |
13659 | md_parse_option (int c, char * arg) | |
13660 | { | |
13661 | struct arm_option_table *opt; | |
e74cfd16 | 13662 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 13663 | struct arm_long_option_table *lopt; |
b99bd4ef | 13664 | |
c19d1205 | 13665 | switch (c) |
b99bd4ef | 13666 | { |
c19d1205 ZW |
13667 | #ifdef OPTION_EB |
13668 | case OPTION_EB: | |
13669 | target_big_endian = 1; | |
13670 | break; | |
13671 | #endif | |
cc8a6dd0 | 13672 | |
c19d1205 ZW |
13673 | #ifdef OPTION_EL |
13674 | case OPTION_EL: | |
13675 | target_big_endian = 0; | |
13676 | break; | |
13677 | #endif | |
b99bd4ef | 13678 | |
c19d1205 ZW |
13679 | case 'a': |
13680 | /* Listing option. Just ignore these, we don't support additional | |
13681 | ones. */ | |
13682 | return 0; | |
b99bd4ef | 13683 | |
c19d1205 ZW |
13684 | default: |
13685 | for (opt = arm_opts; opt->option != NULL; opt++) | |
13686 | { | |
13687 | if (c == opt->option[0] | |
13688 | && ((arg == NULL && opt->option[1] == 0) | |
13689 | || streq (arg, opt->option + 1))) | |
13690 | { | |
13691 | #if WARN_DEPRECATED | |
13692 | /* If the option is deprecated, tell the user. */ | |
13693 | if (opt->deprecated != NULL) | |
13694 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
13695 | arg ? arg : "", _(opt->deprecated)); | |
13696 | #endif | |
b99bd4ef | 13697 | |
c19d1205 ZW |
13698 | if (opt->var != NULL) |
13699 | *opt->var = opt->value; | |
cc8a6dd0 | 13700 | |
c19d1205 ZW |
13701 | return 1; |
13702 | } | |
13703 | } | |
b99bd4ef | 13704 | |
e74cfd16 PB |
13705 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
13706 | { | |
13707 | if (c == fopt->option[0] | |
13708 | && ((arg == NULL && fopt->option[1] == 0) | |
13709 | || streq (arg, fopt->option + 1))) | |
13710 | { | |
13711 | #if WARN_DEPRECATED | |
13712 | /* If the option is deprecated, tell the user. */ | |
13713 | if (fopt->deprecated != NULL) | |
13714 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
13715 | arg ? arg : "", _(fopt->deprecated)); | |
13716 | #endif | |
13717 | ||
13718 | if (fopt->var != NULL) | |
13719 | *fopt->var = &fopt->value; | |
13720 | ||
13721 | return 1; | |
13722 | } | |
13723 | } | |
13724 | ||
c19d1205 ZW |
13725 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
13726 | { | |
13727 | /* These options are expected to have an argument. */ | |
13728 | if (c == lopt->option[0] | |
13729 | && arg != NULL | |
13730 | && strncmp (arg, lopt->option + 1, | |
13731 | strlen (lopt->option + 1)) == 0) | |
13732 | { | |
13733 | #if WARN_DEPRECATED | |
13734 | /* If the option is deprecated, tell the user. */ | |
13735 | if (lopt->deprecated != NULL) | |
13736 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, | |
13737 | _(lopt->deprecated)); | |
13738 | #endif | |
b99bd4ef | 13739 | |
c19d1205 ZW |
13740 | /* Call the sup-option parser. */ |
13741 | return lopt->func (arg + strlen (lopt->option) - 1); | |
13742 | } | |
13743 | } | |
a737bd4d | 13744 | |
c19d1205 ZW |
13745 | return 0; |
13746 | } | |
a394c00f | 13747 | |
c19d1205 ZW |
13748 | return 1; |
13749 | } | |
a394c00f | 13750 | |
c19d1205 ZW |
13751 | void |
13752 | md_show_usage (FILE * fp) | |
a394c00f | 13753 | { |
c19d1205 ZW |
13754 | struct arm_option_table *opt; |
13755 | struct arm_long_option_table *lopt; | |
a394c00f | 13756 | |
c19d1205 | 13757 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 13758 | |
c19d1205 ZW |
13759 | for (opt = arm_opts; opt->option != NULL; opt++) |
13760 | if (opt->help != NULL) | |
13761 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 13762 | |
c19d1205 ZW |
13763 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
13764 | if (lopt->help != NULL) | |
13765 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 13766 | |
c19d1205 ZW |
13767 | #ifdef OPTION_EB |
13768 | fprintf (fp, _("\ | |
13769 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
13770 | #endif |
13771 | ||
c19d1205 ZW |
13772 | #ifdef OPTION_EL |
13773 | fprintf (fp, _("\ | |
13774 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 13775 | #endif |
c19d1205 | 13776 | } |
ee065d83 PB |
13777 | |
13778 | ||
13779 | #ifdef OBJ_ELF | |
62b3e311 PB |
13780 | typedef struct |
13781 | { | |
13782 | int val; | |
13783 | arm_feature_set flags; | |
13784 | } cpu_arch_ver_table; | |
13785 | ||
13786 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
13787 | least features first. */ | |
13788 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
13789 | { | |
13790 | {1, ARM_ARCH_V4}, | |
13791 | {2, ARM_ARCH_V4T}, | |
13792 | {3, ARM_ARCH_V5}, | |
13793 | {4, ARM_ARCH_V5TE}, | |
13794 | {5, ARM_ARCH_V5TEJ}, | |
13795 | {6, ARM_ARCH_V6}, | |
13796 | {7, ARM_ARCH_V6Z}, | |
13797 | {8, ARM_ARCH_V6K}, | |
13798 | {9, ARM_ARCH_V6T2}, | |
13799 | {10, ARM_ARCH_V7A}, | |
13800 | {10, ARM_ARCH_V7R}, | |
13801 | {10, ARM_ARCH_V7M}, | |
13802 | {0, ARM_ARCH_NONE} | |
13803 | }; | |
13804 | ||
ee065d83 PB |
13805 | /* Set the public EABI object attributes. */ |
13806 | static void | |
13807 | aeabi_set_public_attributes (void) | |
13808 | { | |
13809 | int arch; | |
e74cfd16 | 13810 | arm_feature_set flags; |
62b3e311 PB |
13811 | arm_feature_set tmp; |
13812 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
13813 | |
13814 | /* Choose the architecture based on the capabilities of the requested cpu | |
13815 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
13816 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
13817 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
13818 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
62b3e311 PB |
13819 | |
13820 | tmp = flags; | |
13821 | arch = 0; | |
13822 | for (p = cpu_arch_ver; p->val; p++) | |
13823 | { | |
13824 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
13825 | { | |
13826 | arch = p->val; | |
13827 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
13828 | } | |
13829 | } | |
ee065d83 PB |
13830 | |
13831 | /* Tag_CPU_name. */ | |
13832 | if (selected_cpu_name[0]) | |
13833 | { | |
13834 | char *p; | |
13835 | ||
13836 | p = selected_cpu_name; | |
13837 | if (strncmp(p, "armv", 4) == 0) | |
13838 | { | |
13839 | int i; | |
13840 | ||
13841 | p += 4; | |
13842 | for (i = 0; p[i]; i++) | |
13843 | p[i] = TOUPPER (p[i]); | |
13844 | } | |
13845 | elf32_arm_add_eabi_attr_string (stdoutput, 5, p); | |
13846 | } | |
13847 | /* Tag_CPU_arch. */ | |
13848 | elf32_arm_add_eabi_attr_int (stdoutput, 6, arch); | |
62b3e311 PB |
13849 | /* Tag_CPU_arch_profile. */ |
13850 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
13851 | elf32_arm_add_eabi_attr_int (stdoutput, 7, 'A'); | |
13852 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) | |
13853 | elf32_arm_add_eabi_attr_int (stdoutput, 7, 'R'); | |
13854 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)) | |
13855 | elf32_arm_add_eabi_attr_int (stdoutput, 7, 'M'); | |
ee065d83 | 13856 | /* Tag_ARM_ISA_use. */ |
e74cfd16 | 13857 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) |
ee065d83 PB |
13858 | elf32_arm_add_eabi_attr_int (stdoutput, 8, 1); |
13859 | /* Tag_THUMB_ISA_use. */ | |
e74cfd16 | 13860 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) |
ee065d83 | 13861 | elf32_arm_add_eabi_attr_int (stdoutput, 9, |
e74cfd16 | 13862 | ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); |
ee065d83 | 13863 | /* Tag_VFP_arch. */ |
e74cfd16 PB |
13864 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2) |
13865 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2)) | |
ee065d83 | 13866 | elf32_arm_add_eabi_attr_int (stdoutput, 10, 2); |
e74cfd16 PB |
13867 | else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1) |
13868 | || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1)) | |
ee065d83 PB |
13869 | elf32_arm_add_eabi_attr_int (stdoutput, 10, 1); |
13870 | /* Tag_WMMX_arch. */ | |
e74cfd16 PB |
13871 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) |
13872 | || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) | |
ee065d83 PB |
13873 | elf32_arm_add_eabi_attr_int (stdoutput, 11, 1); |
13874 | } | |
13875 | ||
13876 | /* Add the .ARM.attributes section. */ | |
13877 | void | |
13878 | arm_md_end (void) | |
13879 | { | |
13880 | segT s; | |
13881 | char *p; | |
13882 | addressT addr; | |
13883 | offsetT size; | |
13884 | ||
13885 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) | |
13886 | return; | |
13887 | ||
13888 | aeabi_set_public_attributes (); | |
13889 | size = elf32_arm_eabi_attr_size (stdoutput); | |
13890 | s = subseg_new (".ARM.attributes", 0); | |
13891 | bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA); | |
13892 | addr = frag_now_fix (); | |
13893 | p = frag_more (size); | |
13894 | elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size); | |
13895 | } | |
13896 | ||
13897 | ||
13898 | /* Parse a .cpu directive. */ | |
13899 | ||
13900 | static void | |
13901 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
13902 | { | |
e74cfd16 | 13903 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
13904 | char *name; |
13905 | char saved_char; | |
13906 | ||
13907 | name = input_line_pointer; | |
13908 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
13909 | input_line_pointer++; | |
13910 | saved_char = *input_line_pointer; | |
13911 | *input_line_pointer = 0; | |
13912 | ||
13913 | /* Skip the first "all" entry. */ | |
13914 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
13915 | if (streq (opt->name, name)) | |
13916 | { | |
e74cfd16 PB |
13917 | mcpu_cpu_opt = &opt->value; |
13918 | selected_cpu = opt->value; | |
ee065d83 PB |
13919 | if (opt->canonical_name) |
13920 | strcpy(selected_cpu_name, opt->canonical_name); | |
13921 | else | |
13922 | { | |
13923 | int i; | |
13924 | for (i = 0; opt->name[i]; i++) | |
13925 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
13926 | selected_cpu_name[i] = 0; | |
13927 | } | |
e74cfd16 | 13928 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
13929 | *input_line_pointer = saved_char; |
13930 | demand_empty_rest_of_line (); | |
13931 | return; | |
13932 | } | |
13933 | as_bad (_("unknown cpu `%s'"), name); | |
13934 | *input_line_pointer = saved_char; | |
13935 | ignore_rest_of_line (); | |
13936 | } | |
13937 | ||
13938 | ||
13939 | /* Parse a .arch directive. */ | |
13940 | ||
13941 | static void | |
13942 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
13943 | { | |
e74cfd16 | 13944 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
13945 | char saved_char; |
13946 | char *name; | |
13947 | ||
13948 | name = input_line_pointer; | |
13949 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
13950 | input_line_pointer++; | |
13951 | saved_char = *input_line_pointer; | |
13952 | *input_line_pointer = 0; | |
13953 | ||
13954 | /* Skip the first "all" entry. */ | |
13955 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
13956 | if (streq (opt->name, name)) | |
13957 | { | |
e74cfd16 PB |
13958 | mcpu_cpu_opt = &opt->value; |
13959 | selected_cpu = opt->value; | |
ee065d83 | 13960 | strcpy(selected_cpu_name, opt->name); |
e74cfd16 | 13961 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
13962 | *input_line_pointer = saved_char; |
13963 | demand_empty_rest_of_line (); | |
13964 | return; | |
13965 | } | |
13966 | ||
13967 | as_bad (_("unknown architecture `%s'\n"), name); | |
13968 | *input_line_pointer = saved_char; | |
13969 | ignore_rest_of_line (); | |
13970 | } | |
13971 | ||
13972 | ||
13973 | /* Parse a .fpu directive. */ | |
13974 | ||
13975 | static void | |
13976 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
13977 | { | |
e74cfd16 | 13978 | const struct arm_option_cpu_value_table *opt; |
ee065d83 PB |
13979 | char saved_char; |
13980 | char *name; | |
13981 | ||
13982 | name = input_line_pointer; | |
13983 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
13984 | input_line_pointer++; | |
13985 | saved_char = *input_line_pointer; | |
13986 | *input_line_pointer = 0; | |
13987 | ||
13988 | for (opt = arm_fpus; opt->name != NULL; opt++) | |
13989 | if (streq (opt->name, name)) | |
13990 | { | |
e74cfd16 PB |
13991 | mfpu_opt = &opt->value; |
13992 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
13993 | *input_line_pointer = saved_char; |
13994 | demand_empty_rest_of_line (); | |
13995 | return; | |
13996 | } | |
13997 | ||
13998 | as_bad (_("unknown floating point format `%s'\n"), name); | |
13999 | *input_line_pointer = saved_char; | |
14000 | ignore_rest_of_line (); | |
14001 | } | |
14002 | #endif /* OBJ_ELF */ | |
14003 |