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e23eba97 | 1 | /* tc-riscv.c -- RISC-V assembler |
d87bef3a | 2 | Copyright (C) 2011-2023 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of GAS. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "as.h" | |
24 | #include "config.h" | |
25 | #include "subsegs.h" | |
26 | #include "safe-ctype.h" | |
27 | ||
28 | #include "itbl-ops.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
31 | ||
1080bf78 | 32 | #include "bfd/elfxx-riscv.h" |
e23eba97 NC |
33 | #include "elf/riscv.h" |
34 | #include "opcode/riscv.h" | |
35 | ||
36 | #include <stdint.h> | |
37 | ||
38 | /* Information about an instruction, including its format, operands | |
39 | and fixups. */ | |
40 | struct riscv_cl_insn | |
41 | { | |
42 | /* The opcode's entry in riscv_opcodes. */ | |
43 | const struct riscv_opcode *insn_mo; | |
44 | ||
634001bb TO |
45 | /* The encoded instruction bits |
46 | (first bits enough to extract instruction length on a long opcode). */ | |
e23eba97 NC |
47 | insn_t insn_opcode; |
48 | ||
634001bb TO |
49 | /* The long encoded instruction bits ([0] is non-zero on a long opcode). */ |
50 | char insn_long_opcode[RISCV_MAX_INSN_LEN]; | |
51 | ||
e23eba97 NC |
52 | /* The frag that contains the instruction. */ |
53 | struct frag *frag; | |
54 | ||
55 | /* The offset into FRAG of the first instruction byte. */ | |
56 | long where; | |
57 | ||
58 | /* The relocs associated with the instruction, if any. */ | |
59 | fixS *fixp; | |
60 | }; | |
61 | ||
3d73d29e NC |
62 | /* All RISC-V CSR belong to one of these classes. */ |
63 | enum riscv_csr_class | |
64 | { | |
65 | CSR_CLASS_NONE, | |
66 | ||
67 | CSR_CLASS_I, | |
65e4a99a NC |
68 | CSR_CLASS_I_32, /* rv32 only */ |
69 | CSR_CLASS_F, /* f-ext only */ | |
70 | CSR_CLASS_ZKR, /* zkr only */ | |
71 | CSR_CLASS_V, /* rvv only */ | |
c625f4ed NC |
72 | CSR_CLASS_DEBUG, /* debug CSR */ |
73 | CSR_CLASS_H, /* hypervisor */ | |
74 | CSR_CLASS_H_32, /* hypervisor, rv32 only */ | |
ac8df5a1 CM |
75 | CSR_CLASS_SMAIA, /* Smaia */ |
76 | CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */ | |
a303646f TO |
77 | CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */ |
78 | CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */ | |
6af47b08 | 79 | CSR_CLASS_SMSTATEEN, /* Smstateen only */ |
6af47b08 | 80 | CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ |
ac8df5a1 CM |
81 | CSR_CLASS_SSAIA, /* Ssaia */ |
82 | CSR_CLASS_SSAIA_AND_H, /* Ssaia with H */ | |
83 | CSR_CLASS_SSAIA_32, /* Ssaia, rv32 only */ | |
84 | CSR_CLASS_SSAIA_AND_H_32, /* Ssaia with H, rv32 only */ | |
15253318 TO |
85 | CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */ |
86 | CSR_CLASS_SSSTATEEN_AND_H, /* S[ms]stateen only (with H) */ | |
87 | CSR_CLASS_SSSTATEEN_AND_H_32, /* S[ms]stateen RV32 only (with H) */ | |
713f3708 TO |
88 | CSR_CLASS_SSCOFPMF, /* Sscofpmf only */ |
89 | CSR_CLASS_SSCOFPMF_32, /* Sscofpmf RV32 only */ | |
766077c1 TO |
90 | CSR_CLASS_SSTC, /* Sstc only */ |
91 | CSR_CLASS_SSTC_AND_H, /* Sstc only (with H) */ | |
92 | CSR_CLASS_SSTC_32, /* Sstc RV32 only */ | |
93 | CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */ | |
3d73d29e NC |
94 | }; |
95 | ||
96 | /* This structure holds all restricted conditions for a CSR. */ | |
97 | struct riscv_csr_extra | |
98 | { | |
99 | /* Class to which this CSR belongs. Used to decide whether or | |
100 | not this CSR is legal in the current -march context. */ | |
101 | enum riscv_csr_class csr_class; | |
102 | ||
103 | /* CSR may have differnet numbers in the previous priv spec. */ | |
104 | unsigned address; | |
105 | ||
106 | /* Record the CSR is defined/valid in which versions. */ | |
107 | enum riscv_spec_class define_version; | |
108 | ||
109 | /* Record the CSR is aborted/invalid from which versions. If it isn't | |
a63375ac | 110 | aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */ |
3d73d29e NC |
111 | enum riscv_spec_class abort_version; |
112 | ||
113 | /* The CSR may have more than one setting. */ | |
114 | struct riscv_csr_extra *next; | |
115 | }; | |
116 | ||
e4028336 PN |
117 | /* This structure contains information about errors that occur within the |
118 | riscv_ip function */ | |
119 | struct riscv_ip_error | |
120 | { | |
121 | /* General error message */ | |
122 | const char* msg; | |
123 | ||
124 | /* Statement that caused the error */ | |
125 | char* statement; | |
126 | ||
127 | /* Missing extension that needs to be enabled */ | |
128 | const char* missing_ext; | |
129 | }; | |
130 | ||
e23eba97 NC |
131 | #ifndef DEFAULT_ARCH |
132 | #define DEFAULT_ARCH "riscv64" | |
133 | #endif | |
134 | ||
2dc8dd17 JW |
135 | #ifndef DEFAULT_RISCV_ATTR |
136 | #define DEFAULT_RISCV_ATTR 0 | |
137 | #endif | |
138 | ||
8f595e9b | 139 | /* Let riscv_after_parse_args set the default value according to xlen. */ |
8f595e9b NC |
140 | #ifndef DEFAULT_RISCV_ARCH_WITH_EXT |
141 | #define DEFAULT_RISCV_ARCH_WITH_EXT NULL | |
142 | #endif | |
143 | ||
dcd709e0 | 144 | /* Need to sync the version with RISC-V compiler. */ |
8f595e9b | 145 | #ifndef DEFAULT_RISCV_ISA_SPEC |
aed44286 | 146 | #define DEFAULT_RISCV_ISA_SPEC "20191213" |
8f595e9b NC |
147 | #endif |
148 | ||
149 | #ifndef DEFAULT_RISCV_PRIV_SPEC | |
150 | #define DEFAULT_RISCV_PRIV_SPEC "1.11" | |
151 | #endif | |
152 | ||
e23eba97 | 153 | static const char default_arch[] = DEFAULT_ARCH; |
8f595e9b | 154 | static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT; |
3d73d29e NC |
155 | static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE; |
156 | static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; | |
e23eba97 | 157 | |
dcd709e0 NC |
158 | static unsigned xlen = 0; /* The width of an x-register. */ |
159 | static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */ | |
5b7c81bd | 160 | static bool rve_abi = false; |
1942a048 NC |
161 | enum float_abi |
162 | { | |
6e1605e4 NC |
163 | FLOAT_ABI_DEFAULT = -1, |
164 | FLOAT_ABI_SOFT, | |
165 | FLOAT_ABI_SINGLE, | |
166 | FLOAT_ABI_DOUBLE, | |
167 | FLOAT_ABI_QUAD | |
168 | }; | |
169 | static enum float_abi float_abi = FLOAT_ABI_DEFAULT; | |
e23eba97 | 170 | |
2922d21d | 171 | #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") |
e23eba97 NC |
172 | #define ADD32_INSN (xlen == 64 ? "addiw" : "addi") |
173 | ||
174 | static unsigned elf_flags = 0; | |
175 | ||
7a29ee29 JB |
176 | static bool probing_insn_operands; |
177 | ||
dcd709e0 NC |
178 | /* Set the default_isa_spec. Return 0 if the spec isn't supported. |
179 | Otherwise, return 1. */ | |
8f595e9b NC |
180 | |
181 | static int | |
182 | riscv_set_default_isa_spec (const char *s) | |
183 | { | |
3d73d29e NC |
184 | enum riscv_spec_class class = ISA_SPEC_CLASS_NONE; |
185 | RISCV_GET_ISA_SPEC_CLASS (s, class); | |
186 | if (class == ISA_SPEC_CLASS_NONE) | |
8f595e9b | 187 | { |
b800637e NC |
188 | as_bad ("unknown default ISA spec `%s' set by " |
189 | "-misa-spec or --with-isa-spec", s); | |
8f595e9b NC |
190 | return 0; |
191 | } | |
192 | else | |
193 | default_isa_spec = class; | |
194 | return 1; | |
195 | } | |
196 | ||
dcd709e0 NC |
197 | /* Set the default_priv_spec. Find the privileged elf attributes when |
198 | the input string is NULL. Return 0 if the spec isn't supported. | |
199 | Otherwise, return 1. */ | |
8f595e9b NC |
200 | |
201 | static int | |
202 | riscv_set_default_priv_spec (const char *s) | |
203 | { | |
3d73d29e | 204 | enum riscv_spec_class class = PRIV_SPEC_CLASS_NONE; |
8f595e9b NC |
205 | unsigned major, minor, revision; |
206 | obj_attribute *attr; | |
8f595e9b | 207 | |
3d73d29e NC |
208 | RISCV_GET_PRIV_SPEC_CLASS (s, class); |
209 | if (class != PRIV_SPEC_CLASS_NONE) | |
8f595e9b NC |
210 | { |
211 | default_priv_spec = class; | |
212 | return 1; | |
213 | } | |
214 | ||
215 | if (s != NULL) | |
216 | { | |
b800637e NC |
217 | as_bad (_("unknown default privileged spec `%s' set by " |
218 | "-mpriv-spec or --with-priv-spec"), s); | |
8f595e9b NC |
219 | return 0; |
220 | } | |
221 | ||
dcd709e0 | 222 | /* Set the default_priv_spec by the privileged elf attributes. */ |
8f595e9b NC |
223 | attr = elf_known_obj_attributes_proc (stdoutput); |
224 | major = (unsigned) attr[Tag_RISCV_priv_spec].i; | |
225 | minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i; | |
226 | revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i; | |
3d73d29e NC |
227 | /* Version 0.0.0 is the default value and meningless. */ |
228 | if (major == 0 && minor == 0 && revision == 0) | |
229 | return 1; | |
8f595e9b | 230 | |
3d73d29e NC |
231 | riscv_get_priv_spec_class_from_numbers (major, minor, revision, &class); |
232 | if (class != PRIV_SPEC_CLASS_NONE) | |
233 | { | |
8f595e9b | 234 | default_priv_spec = class; |
8f595e9b NC |
235 | return 1; |
236 | } | |
237 | ||
dcd709e0 | 238 | /* Still can not find the privileged spec class. */ |
b800637e NC |
239 | as_bad (_("unknown default privileged spec `%d.%d.%d' set by " |
240 | "privileged elf attributes"), major, minor, revision); | |
8f595e9b NC |
241 | return 0; |
242 | } | |
243 | ||
e23eba97 | 244 | /* This is the set of options which the .option pseudo-op may modify. */ |
e23eba97 NC |
245 | struct riscv_set_options |
246 | { | |
247 | int pic; /* Generate position-independent code. */ | |
248 | int rvc; /* Generate RVC code. */ | |
45f76423 | 249 | int relax; /* Emit relocs the linker is allowed to relax. */ |
dcd709e0 | 250 | int arch_attr; /* Emit architecture and privileged elf attributes. */ |
2ca89224 | 251 | int csr_check; /* Enable the CSR checking. */ |
e23eba97 NC |
252 | }; |
253 | ||
254 | static struct riscv_set_options riscv_opts = | |
255 | { | |
dcd709e0 NC |
256 | 0, /* pic */ |
257 | 0, /* rvc */ | |
dcd709e0 | 258 | 1, /* relax */ |
2dc8dd17 | 259 | DEFAULT_RISCV_ATTR, /* arch_attr */ |
dcd709e0 | 260 | 0, /* csr_check */ |
e23eba97 NC |
261 | }; |
262 | ||
437e2ff1 NC |
263 | /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag |
264 | for elf_flags once we have enabled c extension. */ | |
265 | ||
e23eba97 | 266 | static void |
5b7c81bd | 267 | riscv_set_rvc (bool rvc_value) |
e23eba97 NC |
268 | { |
269 | if (rvc_value) | |
270 | elf_flags |= EF_RISCV_RVC; | |
271 | ||
272 | riscv_opts.rvc = rvc_value; | |
273 | } | |
274 | ||
96462b01 S |
275 | /* Turn on the tso flag for elf_flags once we have enabled ztso extension. */ |
276 | ||
277 | static void | |
0242db99 | 278 | riscv_set_tso (void) |
96462b01 S |
279 | { |
280 | elf_flags |= EF_RISCV_TSO; | |
281 | } | |
282 | ||
f5cb31a8 JB |
283 | /* The linked list hanging off of .subsets_list records all enabled extensions, |
284 | which are parsed from the architecture string. The architecture string can | |
285 | be set by the -march option, the elf architecture attributes, and the | |
286 | --with-arch configure option. */ | |
f786c359 | 287 | static riscv_parse_subset_t riscv_rps_as = |
43135d3b | 288 | { |
d3ffd7f7 NC |
289 | NULL, /* subset_list, we will set it later once |
290 | riscv_opts_stack is created or updated. */ | |
f786c359 NC |
291 | as_bad, /* error_handler. */ |
292 | &xlen, /* xlen. */ | |
293 | &default_isa_spec, /* isa_spec. */ | |
294 | true, /* check_unknown_prefixed_ext. */ | |
295 | }; | |
43135d3b | 296 | |
40f1a1a4 NC |
297 | /* Update the architecture string in the subset_list. */ |
298 | ||
299 | static void | |
300 | riscv_reset_subsets_list_arch_str (void) | |
301 | { | |
302 | riscv_subset_list_t *subsets = riscv_rps_as.subset_list; | |
303 | if (subsets->arch_str != NULL) | |
304 | free ((void *) subsets->arch_str); | |
305 | subsets->arch_str = riscv_arch_str (xlen, subsets); | |
306 | } | |
307 | ||
d3ffd7f7 NC |
308 | /* This structure is used to hold a stack of .option values. */ |
309 | struct riscv_option_stack | |
310 | { | |
311 | struct riscv_option_stack *next; | |
312 | struct riscv_set_options options; | |
313 | riscv_subset_list_t *subset_list; | |
314 | }; | |
315 | ||
316 | static struct riscv_option_stack *riscv_opts_stack = NULL; | |
317 | ||
2922d21d | 318 | /* Set which ISA and extensions are available. */ |
e23eba97 | 319 | |
e23eba97 | 320 | static void |
2922d21d | 321 | riscv_set_arch (const char *s) |
e23eba97 | 322 | { |
c9f27991 NC |
323 | if (s != NULL && strcmp (s, "") == 0) |
324 | { | |
325 | as_bad (_("the architecture string of -march and elf architecture " | |
326 | "attributes cannot be empty")); | |
327 | return; | |
328 | } | |
7f999549 | 329 | |
f5cb31a8 | 330 | if (riscv_rps_as.subset_list == NULL) |
d3ffd7f7 | 331 | { |
f5cb31a8 JB |
332 | riscv_rps_as.subset_list = XNEW (riscv_subset_list_t); |
333 | riscv_rps_as.subset_list->head = NULL; | |
334 | riscv_rps_as.subset_list->tail = NULL; | |
40f1a1a4 | 335 | riscv_rps_as.subset_list->arch_str = NULL; |
d3ffd7f7 | 336 | } |
f5cb31a8 | 337 | riscv_release_subset_list (riscv_rps_as.subset_list); |
f786c359 | 338 | riscv_parse_subset (&riscv_rps_as, s); |
40f1a1a4 | 339 | riscv_reset_subsets_list_arch_str (); |
28b2963f | 340 | |
28b2963f | 341 | riscv_set_rvc (false); |
b5c37946 SJ |
342 | if (riscv_subset_supports (&riscv_rps_as, "c") |
343 | || riscv_subset_supports (&riscv_rps_as, "zca")) | |
28b2963f | 344 | riscv_set_rvc (true); |
96462b01 S |
345 | |
346 | if (riscv_subset_supports (&riscv_rps_as, "ztso")) | |
347 | riscv_set_tso (); | |
e23eba97 NC |
348 | } |
349 | ||
dcd709e0 | 350 | /* Indicate -mabi option is explictly set. */ |
5b7c81bd | 351 | static bool explicit_mabi = false; |
6e1605e4 | 352 | |
437e2ff1 NC |
353 | /* Set the abi information. */ |
354 | ||
6e1605e4 | 355 | static void |
5b7c81bd | 356 | riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve) |
6e1605e4 NC |
357 | { |
358 | abi_xlen = new_xlen; | |
359 | float_abi = new_float_abi; | |
360 | rve_abi = rve; | |
361 | } | |
362 | ||
dcd709e0 NC |
363 | /* If the -mabi option isn't set, then set the abi according to the |
364 | ISA string. Otherwise, check if there is any conflict. */ | |
6e1605e4 NC |
365 | |
366 | static void | |
367 | riscv_set_abi_by_arch (void) | |
368 | { | |
369 | if (!explicit_mabi) | |
370 | { | |
f786c359 | 371 | if (riscv_subset_supports (&riscv_rps_as, "q")) |
5b7c81bd | 372 | riscv_set_abi (xlen, FLOAT_ABI_QUAD, false); |
f786c359 | 373 | else if (riscv_subset_supports (&riscv_rps_as, "d")) |
5b7c81bd | 374 | riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false); |
f786c359 | 375 | else if (riscv_subset_supports (&riscv_rps_as, "e")) |
5d0ed830 | 376 | riscv_set_abi (xlen, FLOAT_ABI_SOFT, true); |
6e1605e4 | 377 | else |
5b7c81bd | 378 | riscv_set_abi (xlen, FLOAT_ABI_SOFT, false); |
6e1605e4 NC |
379 | } |
380 | else | |
381 | { | |
382 | gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT); | |
383 | if (abi_xlen > xlen) | |
384 | as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); | |
385 | else if (abi_xlen < xlen) | |
386 | as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); | |
5d0ed830 | 387 | |
f786c359 | 388 | if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) |
5d0ed830 NC |
389 | as_bad ("only the ilp32e ABI is supported for e extension"); |
390 | ||
391 | if (float_abi == FLOAT_ABI_SINGLE | |
f786c359 | 392 | && !riscv_subset_supports (&riscv_rps_as, "f")) |
5d0ed830 NC |
393 | as_bad ("ilp32f/lp64f ABI can't be used when f extension " |
394 | "isn't supported"); | |
395 | else if (float_abi == FLOAT_ABI_DOUBLE | |
f786c359 | 396 | && !riscv_subset_supports (&riscv_rps_as, "d")) |
5d0ed830 NC |
397 | as_bad ("ilp32d/lp64d ABI can't be used when d extension " |
398 | "isn't supported"); | |
399 | else if (float_abi == FLOAT_ABI_QUAD | |
f786c359 | 400 | && !riscv_subset_supports (&riscv_rps_as, "q")) |
5d0ed830 NC |
401 | as_bad ("ilp32q/lp64q ABI can't be used when q extension " |
402 | "isn't supported"); | |
6e1605e4 NC |
403 | } |
404 | ||
405 | /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */ | |
406 | elf_flags &= ~EF_RISCV_FLOAT_ABI; | |
407 | elf_flags |= float_abi << 1; | |
408 | ||
409 | if (rve_abi) | |
410 | elf_flags |= EF_RISCV_RVE; | |
411 | } | |
412 | ||
e23eba97 | 413 | /* Handle of the OPCODE hash table. */ |
629310ab | 414 | static htab_t op_hash = NULL; |
e23eba97 | 415 | |
0e35537d | 416 | /* Handle of the type of .insn hash table. */ |
629310ab | 417 | static htab_t insn_type_hash = NULL; |
0e35537d | 418 | |
e23eba97 | 419 | /* This array holds the chars that always start a comment. If the |
dcd709e0 | 420 | pre-processor is disabled, these aren't very useful. */ |
e23eba97 NC |
421 | const char comment_chars[] = "#"; |
422 | ||
423 | /* This array holds the chars that only start a comment at the beginning of | |
424 | a line. If the line seems to have the form '# 123 filename' | |
dcd709e0 NC |
425 | .line and .file directives will appear in the pre-processed output |
426 | ||
427 | Note that input_file.c hand checks for '#' at the beginning of the | |
e23eba97 | 428 | first line of the input file. This is because the compiler outputs |
dcd709e0 NC |
429 | #NO_APP at the beginning of its output. |
430 | ||
431 | Also note that C style comments are always supported. */ | |
e23eba97 NC |
432 | const char line_comment_chars[] = "#"; |
433 | ||
434 | /* This array holds machine specific line separator characters. */ | |
435 | const char line_separator_chars[] = ";"; | |
436 | ||
dcd709e0 | 437 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
e23eba97 NC |
438 | const char EXP_CHARS[] = "eE"; |
439 | ||
dcd709e0 NC |
440 | /* Chars that mean this number is a floating point constant. |
441 | As in 0f12.456 or 0d1.2345e12. */ | |
035784e3 | 442 | const char FLT_CHARS[] = "rRsSfFdDxXpPhH"; |
e23eba97 | 443 | |
2dc8dd17 | 444 | /* Indicate we are already assemble any instructions or not. */ |
5b7c81bd | 445 | static bool start_assemble = false; |
2dc8dd17 | 446 | |
f9a6a8f0 | 447 | /* Indicate ELF attributes are explicitly set. */ |
5b7c81bd | 448 | static bool explicit_attr = false; |
2dc8dd17 | 449 | |
f9a6a8f0 | 450 | /* Indicate CSR or priv instructions are explicitly used. */ |
5b7c81bd | 451 | static bool explicit_priv_attr = false; |
3fc6c3dc | 452 | |
6eb099ae | 453 | static char *expr_parse_end; |
437e2ff1 | 454 | |
e23eba97 NC |
455 | /* Macros for encoding relaxation state for RVC branches and far jumps. */ |
456 | #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ | |
457 | ((relax_substateT) \ | |
458 | (0xc0000000 \ | |
459 | | ((uncond) ? 1 : 0) \ | |
460 | | ((rvc) ? 2 : 0) \ | |
461 | | ((length) << 2))) | |
462 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) | |
463 | #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) | |
464 | #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) | |
465 | #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) | |
466 | ||
467 | /* Is the given value a sign-extended 32-bit value? */ | |
468 | #define IS_SEXT_32BIT_NUM(x) \ | |
469 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
470 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
471 | ||
472 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ | |
473 | #define IS_ZEXT_32BIT_NUM(x) \ | |
474 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
475 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
476 | ||
477 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
478 | INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ | |
479 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
480 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
481 | ||
8b7419c4 CM |
482 | #define INSERT_IMM(n, s, INSN, VALUE) \ |
483 | INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s) | |
484 | ||
e23eba97 NC |
485 | /* Determine if an instruction matches an opcode. */ |
486 | #define OPCODE_MATCHES(OPCODE, OP) \ | |
487 | (((OPCODE) & MASK_##OP) == MATCH_##OP) | |
488 | ||
9b9b1092 NC |
489 | /* Create a new mapping symbol for the transition to STATE. */ |
490 | ||
491 | static void | |
492 | make_mapping_symbol (enum riscv_seg_mstate state, | |
493 | valueT value, | |
40f1a1a4 | 494 | fragS *frag, |
d918451a NC |
495 | const char *arch_str, |
496 | bool odd_data_padding) | |
9b9b1092 NC |
497 | { |
498 | const char *name; | |
615d4f41 | 499 | char *buff = NULL; |
9b9b1092 NC |
500 | switch (state) |
501 | { | |
502 | case MAP_DATA: | |
503 | name = "$d"; | |
504 | break; | |
505 | case MAP_INSN: | |
d918451a | 506 | if (arch_str != NULL) |
40f1a1a4 | 507 | { |
d918451a | 508 | size_t size = strlen (arch_str) + 3; /* "$x" + '\0' */ |
40f1a1a4 | 509 | buff = xmalloc (size); |
d918451a | 510 | snprintf (buff, size, "$x%s", arch_str); |
40f1a1a4 NC |
511 | name = buff; |
512 | } | |
513 | else | |
514 | name = "$x"; | |
9b9b1092 NC |
515 | break; |
516 | default: | |
517 | abort (); | |
518 | } | |
519 | ||
520 | symbolS *symbol = symbol_new (name, now_seg, frag, value); | |
521 | symbol_get_bfdsym (symbol)->flags |= (BSF_NO_FLAGS | BSF_LOCAL); | |
d918451a | 522 | if (arch_str != NULL) |
40f1a1a4 NC |
523 | { |
524 | /* Store current $x+arch into tc_segment_info. */ | |
525 | seg_info (now_seg)->tc_segment_info_data.arch_map_symbol = symbol; | |
526 | xfree ((void *) buff); | |
527 | } | |
9b9b1092 NC |
528 | |
529 | /* If .fill or other data filling directive generates zero sized data, | |
40f1a1a4 NC |
530 | then mapping symbol for the following code will have the same value. |
531 | ||
532 | Please see gas/testsuite/gas/riscv/mapping.s: .text.zero.fill.first | |
533 | and .text.zero.fill.last. */ | |
534 | symbolS *first = frag->tc_frag_data.first_map_symbol; | |
535 | symbolS *last = frag->tc_frag_data.last_map_symbol; | |
d918451a | 536 | symbolS *removed = NULL; |
9b9b1092 NC |
537 | if (value == 0) |
538 | { | |
40f1a1a4 | 539 | if (first != NULL) |
9b9b1092 | 540 | { |
40f1a1a4 NC |
541 | know (S_GET_VALUE (first) == S_GET_VALUE (symbol) |
542 | && first == last); | |
9b9b1092 | 543 | /* Remove the old one. */ |
d918451a | 544 | removed = first; |
9b9b1092 NC |
545 | } |
546 | frag->tc_frag_data.first_map_symbol = symbol; | |
547 | } | |
40f1a1a4 | 548 | else if (last != NULL) |
9b9b1092 NC |
549 | { |
550 | /* The mapping symbols should be added in offset order. */ | |
40f1a1a4 | 551 | know (S_GET_VALUE (last) <= S_GET_VALUE (symbol)); |
9b9b1092 | 552 | /* Remove the old one. */ |
40f1a1a4 | 553 | if (S_GET_VALUE (last) == S_GET_VALUE (symbol)) |
d918451a | 554 | removed = last; |
9b9b1092 NC |
555 | } |
556 | frag->tc_frag_data.last_map_symbol = symbol; | |
d918451a NC |
557 | |
558 | if (removed == NULL) | |
559 | return; | |
560 | ||
561 | if (odd_data_padding) | |
562 | { | |
563 | /* If the removed mapping symbol is $x+arch, then add it back to | |
564 | the next $x. */ | |
565 | const char *str = strncmp (S_GET_NAME (removed), "$xrv", 4) == 0 | |
566 | ? S_GET_NAME (removed) + 2 : NULL; | |
567 | make_mapping_symbol (MAP_INSN, frag->fr_fix + 1, frag, str, | |
568 | false/* odd_data_padding */); | |
569 | } | |
570 | symbol_remove (removed, &symbol_rootP, &symbol_lastP); | |
9b9b1092 NC |
571 | } |
572 | ||
573 | /* Set the mapping state for frag_now. */ | |
574 | ||
575 | void | |
576 | riscv_mapping_state (enum riscv_seg_mstate to_state, | |
40f1a1a4 | 577 | int max_chars, |
3190ebcb | 578 | bool fr_align_code) |
9b9b1092 NC |
579 | { |
580 | enum riscv_seg_mstate from_state = | |
581 | seg_info (now_seg)->tc_segment_info_data.map_state; | |
40f1a1a4 | 582 | bool reset_seg_arch_str = false; |
9b9b1092 NC |
583 | |
584 | if (!SEG_NORMAL (now_seg) | |
40f1a1a4 | 585 | /* For now we only add the mapping symbols to text sections. |
9b9b1092 NC |
586 | Therefore, the dis-assembler only show the actual contents |
587 | distribution for text. Other sections will be shown as | |
588 | data without the details. */ | |
589 | || !subseg_text_p (now_seg)) | |
590 | return; | |
591 | ||
592 | /* The mapping symbol should be emitted if not in the right | |
40f1a1a4 NC |
593 | mapping state. */ |
594 | symbolS *seg_arch_symbol = | |
595 | seg_info (now_seg)->tc_segment_info_data.arch_map_symbol; | |
596 | if (to_state == MAP_INSN && seg_arch_symbol == 0) | |
597 | { | |
598 | /* Always add $x+arch at the first instruction of section. */ | |
599 | reset_seg_arch_str = true; | |
600 | } | |
601 | else if (seg_arch_symbol != 0 | |
602 | && to_state == MAP_INSN | |
3190ebcb | 603 | && !fr_align_code |
40f1a1a4 NC |
604 | && strcmp (riscv_rps_as.subset_list->arch_str, |
605 | S_GET_NAME (seg_arch_symbol) + 2) != 0) | |
606 | { | |
607 | reset_seg_arch_str = true; | |
40f1a1a4 NC |
608 | } |
609 | else if (from_state == to_state) | |
9b9b1092 NC |
610 | return; |
611 | ||
612 | valueT value = (valueT) (frag_now_fix () - max_chars); | |
613 | seg_info (now_seg)->tc_segment_info_data.map_state = to_state; | |
d918451a NC |
614 | const char *arch_str = reset_seg_arch_str |
615 | ? riscv_rps_as.subset_list->arch_str : NULL; | |
616 | make_mapping_symbol (to_state, value, frag_now, arch_str, | |
617 | false/* odd_data_padding */); | |
9b9b1092 NC |
618 | } |
619 | ||
620 | /* Add the odd bytes of paddings for riscv_handle_align. */ | |
621 | ||
622 | static void | |
623 | riscv_add_odd_padding_symbol (fragS *frag) | |
624 | { | |
625 | /* If there was already a mapping symbol, it should be | |
40f1a1a4 NC |
626 | removed in the make_mapping_symbol. |
627 | ||
d918451a NC |
628 | Please see gas/testsuite/gas/riscv/mapping.s: .text.odd.align.*. */ |
629 | make_mapping_symbol (MAP_DATA, frag->fr_fix, frag, | |
630 | NULL/* arch_str */, true/* odd_data_padding */); | |
9b9b1092 NC |
631 | } |
632 | ||
633 | /* Remove any excess mapping symbols generated for alignment frags in | |
634 | SEC. We may have created a mapping symbol before a zero byte | |
635 | alignment; remove it if there's a mapping symbol after the | |
636 | alignment. */ | |
637 | ||
638 | static void | |
639 | riscv_check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, | |
640 | asection *sec, | |
641 | void *dummy ATTRIBUTE_UNUSED) | |
642 | { | |
643 | segment_info_type *seginfo = seg_info (sec); | |
644 | fragS *fragp; | |
645 | ||
646 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
647 | return; | |
648 | ||
649 | for (fragp = seginfo->frchainP->frch_root; | |
650 | fragp != NULL; | |
651 | fragp = fragp->fr_next) | |
652 | { | |
653 | symbolS *last = fragp->tc_frag_data.last_map_symbol; | |
654 | fragS *next = fragp->fr_next; | |
655 | ||
656 | if (last == NULL || next == NULL) | |
657 | continue; | |
658 | ||
659 | /* Check the last mapping symbol if it is at the boundary of | |
660 | fragment. */ | |
661 | if (S_GET_VALUE (last) < next->fr_address) | |
662 | continue; | |
663 | know (S_GET_VALUE (last) == next->fr_address); | |
664 | ||
665 | do | |
666 | { | |
40f1a1a4 NC |
667 | symbolS *next_first = next->tc_frag_data.first_map_symbol; |
668 | if (next_first != NULL) | |
9b9b1092 NC |
669 | { |
670 | /* The last mapping symbol overlaps with another one | |
40f1a1a4 NC |
671 | which at the start of the next frag. |
672 | ||
673 | Please see the gas/testsuite/gas/riscv/mapping.s: | |
674 | .text.zero.fill.align.A and .text.zero.fill.align.B. */ | |
d918451a NC |
675 | know (S_GET_VALUE (last) == S_GET_VALUE (next_first)); |
676 | symbolS *removed = last; | |
677 | if (strncmp (S_GET_NAME (last), "$xrv", 4) == 0 | |
678 | && strcmp (S_GET_NAME (next_first), "$x") == 0) | |
679 | removed = next_first; | |
680 | symbol_remove (removed, &symbol_rootP, &symbol_lastP); | |
9b9b1092 NC |
681 | break; |
682 | } | |
683 | ||
684 | if (next->fr_next == NULL) | |
685 | { | |
40f1a1a4 NC |
686 | /* The last mapping symbol is at the end of the section. |
687 | ||
688 | Please see the gas/testsuite/gas/riscv/mapping.s: | |
689 | .text.last.section. */ | |
9b9b1092 NC |
690 | know (next->fr_fix == 0 && next->fr_var == 0); |
691 | symbol_remove (last, &symbol_rootP, &symbol_lastP); | |
692 | break; | |
693 | } | |
694 | ||
695 | /* Since we may have empty frags without any mapping symbols, | |
696 | keep looking until the non-empty frag. */ | |
697 | if (next->fr_address != next->fr_next->fr_address) | |
698 | break; | |
699 | ||
700 | next = next->fr_next; | |
701 | } | |
702 | while (next != NULL); | |
703 | } | |
704 | } | |
705 | ||
e23eba97 NC |
706 | /* The default target format to use. */ |
707 | ||
708 | const char * | |
709 | riscv_target_format (void) | |
710 | { | |
fbc09e7a MC |
711 | if (target_big_endian) |
712 | return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv"; | |
713 | else | |
714 | return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; | |
e23eba97 NC |
715 | } |
716 | ||
717 | /* Return the length of instruction INSN. */ | |
718 | ||
719 | static inline unsigned int | |
720 | insn_length (const struct riscv_cl_insn *insn) | |
721 | { | |
722 | return riscv_insn_length (insn->insn_opcode); | |
723 | } | |
724 | ||
725 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
726 | ||
727 | static void | |
728 | create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) | |
729 | { | |
730 | insn->insn_mo = mo; | |
731 | insn->insn_opcode = mo->match; | |
634001bb | 732 | insn->insn_long_opcode[0] = 0; |
e23eba97 NC |
733 | insn->frag = NULL; |
734 | insn->where = 0; | |
735 | insn->fixp = NULL; | |
736 | } | |
737 | ||
738 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
739 | ||
740 | static void | |
741 | install_insn (const struct riscv_cl_insn *insn) | |
742 | { | |
743 | char *f = insn->frag->fr_literal + insn->where; | |
634001bb TO |
744 | if (insn->insn_long_opcode[0] != 0) |
745 | memcpy (f, insn->insn_long_opcode, insn_length (insn)); | |
746 | else | |
747 | number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); | |
e23eba97 NC |
748 | } |
749 | ||
750 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
751 | and install the opcode in the new location. */ | |
752 | ||
753 | static void | |
754 | move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) | |
755 | { | |
756 | insn->frag = frag; | |
757 | insn->where = where; | |
758 | if (insn->fixp != NULL) | |
759 | { | |
760 | insn->fixp->fx_frag = frag; | |
761 | insn->fixp->fx_where = where; | |
762 | } | |
763 | install_insn (insn); | |
764 | } | |
765 | ||
766 | /* Add INSN to the end of the output. */ | |
767 | ||
768 | static void | |
769 | add_fixed_insn (struct riscv_cl_insn *insn) | |
770 | { | |
771 | char *f = frag_more (insn_length (insn)); | |
772 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
773 | } | |
774 | ||
775 | static void | |
776 | add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, | |
777 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
778 | { | |
779 | frag_grow (max_chars); | |
780 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
781 | frag_var (rs_machine_dependent, max_chars, var, | |
782 | subtype, symbol, offset, NULL); | |
783 | } | |
784 | ||
785 | /* Compute the length of a branch sequence, and adjust the stored length | |
786 | accordingly. If FRAGP is NULL, the worst-case length is returned. */ | |
787 | ||
788 | static unsigned | |
789 | relaxed_branch_length (fragS *fragp, asection *sec, int update) | |
790 | { | |
791 | int jump, rvc, length = 8; | |
792 | ||
793 | if (!fragp) | |
794 | return length; | |
795 | ||
796 | jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); | |
797 | rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); | |
798 | length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); | |
799 | ||
800 | /* Assume jumps are in range; the linker will catch any that aren't. */ | |
801 | length = jump ? 4 : 8; | |
802 | ||
803 | if (fragp->fr_symbol != NULL | |
804 | && S_IS_DEFINED (fragp->fr_symbol) | |
01156111 | 805 | && !S_IS_WEAK (fragp->fr_symbol) |
e23eba97 NC |
806 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
807 | { | |
808 | offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
809 | bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; | |
810 | val -= fragp->fr_address + fragp->fr_fix; | |
811 | ||
812 | if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) | |
813 | length = 2; | |
814 | else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) | |
815 | length = 4; | |
816 | else if (!jump && rvc) | |
817 | length = 6; | |
818 | } | |
819 | ||
820 | if (update) | |
821 | fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); | |
822 | ||
823 | return length; | |
824 | } | |
825 | ||
0e35537d JW |
826 | /* Information about an opcode name, mnemonics and its value. */ |
827 | struct opcode_name_t | |
828 | { | |
829 | const char *name; | |
830 | unsigned int val; | |
831 | }; | |
832 | ||
833 | /* List for all supported opcode name. */ | |
834 | static const struct opcode_name_t opcode_name_list[] = | |
835 | { | |
836 | {"C0", 0x0}, | |
837 | {"C1", 0x1}, | |
838 | {"C2", 0x2}, | |
839 | ||
840 | {"LOAD", 0x03}, | |
841 | {"LOAD_FP", 0x07}, | |
842 | {"CUSTOM_0", 0x0b}, | |
843 | {"MISC_MEM", 0x0f}, | |
844 | {"OP_IMM", 0x13}, | |
845 | {"AUIPC", 0x17}, | |
846 | {"OP_IMM_32", 0x1b}, | |
847 | /* 48b 0x1f. */ | |
848 | ||
849 | {"STORE", 0x23}, | |
850 | {"STORE_FP", 0x27}, | |
851 | {"CUSTOM_1", 0x2b}, | |
852 | {"AMO", 0x2f}, | |
853 | {"OP", 0x33}, | |
854 | {"LUI", 0x37}, | |
855 | {"OP_32", 0x3b}, | |
856 | /* 64b 0x3f. */ | |
857 | ||
858 | {"MADD", 0x43}, | |
859 | {"MSUB", 0x47}, | |
860 | {"NMADD", 0x4f}, | |
861 | {"NMSUB", 0x4b}, | |
862 | {"OP_FP", 0x53}, | |
f8ad70a1 | 863 | {"OP_V", 0x57}, |
0e35537d JW |
864 | {"CUSTOM_2", 0x5b}, |
865 | /* 48b 0x5f. */ | |
866 | ||
867 | {"BRANCH", 0x63}, | |
868 | {"JALR", 0x67}, | |
869 | /*reserved 0x5b. */ | |
870 | {"JAL", 0x6f}, | |
871 | {"SYSTEM", 0x73}, | |
872 | /*reserved 0x77. */ | |
873 | {"CUSTOM_3", 0x7b}, | |
874 | /* >80b 0x7f. */ | |
875 | ||
876 | {NULL, 0} | |
877 | }; | |
878 | ||
879 | /* Hash table for lookup opcode name. */ | |
629310ab | 880 | static htab_t opcode_names_hash = NULL; |
0e35537d JW |
881 | |
882 | /* Initialization for hash table of opcode name. */ | |
dcd709e0 | 883 | |
0e35537d JW |
884 | static void |
885 | init_opcode_names_hash (void) | |
886 | { | |
0e35537d JW |
887 | const struct opcode_name_t *opcode; |
888 | ||
889 | for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode) | |
fe0e921f | 890 | if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL) |
b800637e | 891 | as_fatal (_("internal: duplicate %s"), opcode->name); |
0e35537d JW |
892 | } |
893 | ||
dcd709e0 NC |
894 | /* Find `s` is a valid opcode name or not, return the opcode name info |
895 | if found. */ | |
896 | ||
0e35537d JW |
897 | static const struct opcode_name_t * |
898 | opcode_name_lookup (char **s) | |
899 | { | |
900 | char *e; | |
901 | char save_c; | |
902 | struct opcode_name_t *o; | |
903 | ||
904 | /* Find end of name. */ | |
905 | e = *s; | |
906 | if (is_name_beginner (*e)) | |
907 | ++e; | |
908 | while (is_part_of_name (*e)) | |
909 | ++e; | |
910 | ||
911 | /* Terminate name. */ | |
912 | save_c = *e; | |
913 | *e = '\0'; | |
914 | ||
629310ab | 915 | o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s); |
0e35537d JW |
916 | |
917 | /* Advance to next token if one was recognized. */ | |
918 | if (o) | |
919 | *s = e; | |
920 | ||
921 | *e = save_c; | |
6eb099ae | 922 | expr_parse_end = e; |
0e35537d JW |
923 | |
924 | return o; | |
925 | } | |
926 | ||
437e2ff1 | 927 | /* All RISC-V registers belong to one of these classes. */ |
e23eba97 NC |
928 | enum reg_class |
929 | { | |
930 | RCLASS_GPR, | |
931 | RCLASS_FPR, | |
65e4a99a NC |
932 | RCLASS_VECR, |
933 | RCLASS_VECM, | |
8f595e9b NC |
934 | RCLASS_MAX, |
935 | ||
936 | RCLASS_CSR | |
e23eba97 NC |
937 | }; |
938 | ||
629310ab ML |
939 | static htab_t reg_names_hash = NULL; |
940 | static htab_t csr_extra_hash = NULL; | |
e23eba97 NC |
941 | |
942 | #define ENCODE_REG_HASH(cls, n) \ | |
943 | ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) | |
944 | #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) | |
945 | #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) | |
946 | ||
947 | static void | |
948 | hash_reg_name (enum reg_class class, const char *name, unsigned n) | |
949 | { | |
950 | void *hash = ENCODE_REG_HASH (class, n); | |
fe0e921f | 951 | if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL) |
b800637e | 952 | as_fatal (_("internal: duplicate %s"), name); |
e23eba97 NC |
953 | } |
954 | ||
955 | static void | |
02a63525 | 956 | hash_reg_names (enum reg_class class, const char names[][NRC], unsigned n) |
e23eba97 NC |
957 | { |
958 | unsigned i; | |
959 | ||
960 | for (i = 0; i < n; i++) | |
961 | hash_reg_name (class, names[i], i); | |
962 | } | |
963 | ||
8f595e9b | 964 | /* Init hash table csr_extra_hash to handle CSR. */ |
dcd709e0 | 965 | |
8f595e9b NC |
966 | static void |
967 | riscv_init_csr_hash (const char *name, | |
3d73d29e NC |
968 | unsigned address, |
969 | enum riscv_csr_class class, | |
970 | enum riscv_spec_class define_version, | |
971 | enum riscv_spec_class abort_version) | |
8f595e9b NC |
972 | { |
973 | struct riscv_csr_extra *entry, *pre_entry; | |
5b7c81bd | 974 | bool need_enrty = true; |
8f595e9b NC |
975 | |
976 | pre_entry = NULL; | |
629310ab | 977 | entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name); |
8f595e9b NC |
978 | while (need_enrty && entry != NULL) |
979 | { | |
980 | if (entry->csr_class == class | |
1942a048 NC |
981 | && entry->address == address |
982 | && entry->define_version == define_version | |
983 | && entry->abort_version == abort_version) | |
5b7c81bd | 984 | need_enrty = false; |
8f595e9b NC |
985 | pre_entry = entry; |
986 | entry = entry->next; | |
987 | } | |
1942a048 | 988 | |
dcd709e0 | 989 | /* Duplicate CSR. */ |
8f595e9b NC |
990 | if (!need_enrty) |
991 | return; | |
bd0cf5a6 | 992 | |
7bfc4db2 | 993 | entry = notes_alloc (sizeof (*entry)); |
8f595e9b NC |
994 | entry->csr_class = class; |
995 | entry->address = address; | |
996 | entry->define_version = define_version; | |
997 | entry->abort_version = abort_version; | |
5c505568 | 998 | entry->next = NULL; |
8f595e9b | 999 | |
8f595e9b | 1000 | if (pre_entry == NULL) |
fe0e921f | 1001 | str_hash_insert (csr_extra_hash, name, entry, 0); |
8f595e9b NC |
1002 | else |
1003 | pre_entry->next = entry; | |
1004 | } | |
bd0cf5a6 | 1005 | |
dcd709e0 NC |
1006 | /* Return the CSR address after checking the ISA dependency and |
1007 | the privileged spec version. | |
1008 | ||
1009 | There are one warning and two errors for CSR, | |
1010 | ||
1011 | Invalid CSR: the CSR was defined, but isn't allowed for the current ISA | |
1012 | or the privileged spec, report warning only if -mcsr-check is set. | |
1013 | Unknown CSR: the CSR has never been defined, report error. | |
1014 | Improper CSR: the CSR number over the range (> 0xfff), report error. */ | |
bd0cf5a6 | 1015 | |
08ccfccf NC |
1016 | static unsigned int |
1017 | riscv_csr_address (const char *csr_name, | |
1018 | struct riscv_csr_extra *entry) | |
bd0cf5a6 | 1019 | { |
08ccfccf NC |
1020 | struct riscv_csr_extra *saved_entry = entry; |
1021 | enum riscv_csr_class csr_class = entry->csr_class; | |
df0a549e | 1022 | bool need_check_version = false; |
39590abd TO |
1023 | bool is_rv32_only = false; |
1024 | bool is_h_required = false; | |
df0a549e | 1025 | const char* extension = NULL; |
8f595e9b | 1026 | |
8f595e9b | 1027 | switch (csr_class) |
bd0cf5a6 | 1028 | { |
08ccfccf | 1029 | case CSR_CLASS_I_32: |
39590abd | 1030 | is_rv32_only = true; |
df0a549e PN |
1031 | /* Fall through. */ |
1032 | case CSR_CLASS_I: | |
1033 | need_check_version = true; | |
1034 | extension = "i"; | |
08ccfccf | 1035 | break; |
c625f4ed | 1036 | case CSR_CLASS_H_32: |
39590abd | 1037 | is_rv32_only = true; |
c625f4ed NC |
1038 | /* Fall through. */ |
1039 | case CSR_CLASS_H: | |
1040 | extension = "h"; | |
1041 | break; | |
8f595e9b | 1042 | case CSR_CLASS_F: |
df0a549e | 1043 | extension = "f"; |
8f595e9b | 1044 | break; |
3d1cafa0 | 1045 | case CSR_CLASS_ZKR: |
df0a549e | 1046 | extension = "zkr"; |
3d1cafa0 | 1047 | break; |
65e4a99a | 1048 | case CSR_CLASS_V: |
1daabcc7 | 1049 | extension = "zve32x"; |
65e4a99a | 1050 | break; |
ac8df5a1 CM |
1051 | case CSR_CLASS_SMAIA_32: |
1052 | is_rv32_only = true; | |
1053 | /* Fall through. */ | |
1054 | case CSR_CLASS_SMAIA: | |
1055 | extension = "smaia"; | |
1056 | break; | |
a303646f TO |
1057 | case CSR_CLASS_SMCNTRPMF_32: |
1058 | is_rv32_only = true; | |
1059 | /* Fall through. */ | |
1060 | case CSR_CLASS_SMCNTRPMF: | |
1061 | need_check_version = true; | |
1062 | extension = "smcntrpmf"; | |
1063 | break; | |
6af47b08 | 1064 | case CSR_CLASS_SMSTATEEN_32: |
c509db05 TO |
1065 | is_rv32_only = true; |
1066 | /* Fall through. */ | |
1067 | case CSR_CLASS_SMSTATEEN: | |
6af47b08 TO |
1068 | extension = "smstateen"; |
1069 | break; | |
ac8df5a1 CM |
1070 | case CSR_CLASS_SSAIA: |
1071 | case CSR_CLASS_SSAIA_AND_H: | |
1072 | case CSR_CLASS_SSAIA_32: | |
1073 | case CSR_CLASS_SSAIA_AND_H_32: | |
1074 | is_rv32_only = (csr_class == CSR_CLASS_SSAIA_32 | |
1075 | || csr_class == CSR_CLASS_SSAIA_AND_H_32); | |
1076 | is_h_required = (csr_class == CSR_CLASS_SSAIA_AND_H | |
1077 | || csr_class == CSR_CLASS_SSAIA_AND_H_32); | |
1078 | extension = "ssaia"; | |
1079 | break; | |
15253318 | 1080 | case CSR_CLASS_SSSTATEEN_AND_H_32: |
c509db05 TO |
1081 | is_rv32_only = true; |
1082 | /* Fall through. */ | |
1083 | case CSR_CLASS_SSSTATEEN_AND_H: | |
1084 | is_h_required = true; | |
1085 | /* Fall through. */ | |
1086 | case CSR_CLASS_SSSTATEEN: | |
15253318 TO |
1087 | extension = "ssstateen"; |
1088 | break; | |
713f3708 TO |
1089 | case CSR_CLASS_SSCOFPMF_32: |
1090 | is_rv32_only = true; | |
1091 | /* Fall through. */ | |
1092 | case CSR_CLASS_SSCOFPMF: | |
1093 | extension = "sscofpmf"; | |
1094 | break; | |
766077c1 TO |
1095 | case CSR_CLASS_SSTC: |
1096 | case CSR_CLASS_SSTC_AND_H: | |
1097 | case CSR_CLASS_SSTC_32: | |
1098 | case CSR_CLASS_SSTC_AND_H_32: | |
1099 | is_rv32_only = (csr_class == CSR_CLASS_SSTC_32 | |
1100 | || csr_class == CSR_CLASS_SSTC_AND_H_32); | |
1101 | is_h_required = (csr_class == CSR_CLASS_SSTC_AND_H | |
1102 | || csr_class == CSR_CLASS_SSTC_AND_H_32); | |
1103 | extension = "sstc"; | |
1104 | break; | |
08ccfccf | 1105 | case CSR_CLASS_DEBUG: |
8f595e9b NC |
1106 | break; |
1107 | default: | |
1108 | as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class); | |
bd0cf5a6 NC |
1109 | } |
1110 | ||
df0a549e PN |
1111 | if (riscv_opts.csr_check) |
1112 | { | |
39590abd | 1113 | if (is_rv32_only && xlen != 32) |
df0a549e | 1114 | as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name); |
39590abd TO |
1115 | if (is_h_required && !riscv_subset_supports (&riscv_rps_as, "h")) |
1116 | as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name); | |
df0a549e PN |
1117 | |
1118 | if (extension != NULL | |
1119 | && !riscv_subset_supports (&riscv_rps_as, extension)) | |
1120 | as_warn (_("invalid CSR `%s', needs `%s' extension"), | |
1121 | csr_name, extension); | |
1122 | } | |
8f595e9b NC |
1123 | |
1124 | while (entry != NULL) | |
bd0cf5a6 | 1125 | { |
08ccfccf NC |
1126 | if (!need_check_version |
1127 | || (default_priv_spec >= entry->define_version | |
1128 | && default_priv_spec < entry->abort_version)) | |
8f595e9b | 1129 | { |
dcd709e0 | 1130 | /* Find the CSR according to the specific version. */ |
08ccfccf | 1131 | return entry->address; |
8f595e9b NC |
1132 | } |
1133 | entry = entry->next; | |
1134 | } | |
bd0cf5a6 | 1135 | |
dcd709e0 NC |
1136 | /* Can not find the CSR address from the chosen privileged version, |
1137 | so use the newly defined value. */ | |
8f595e9b NC |
1138 | if (riscv_opts.csr_check) |
1139 | { | |
3d73d29e NC |
1140 | const char *priv_name = NULL; |
1141 | RISCV_GET_PRIV_SPEC_NAME (priv_name, default_priv_spec); | |
8f595e9b | 1142 | if (priv_name != NULL) |
b800637e | 1143 | as_warn (_("invalid CSR `%s' for the privileged spec `%s'"), |
8f595e9b | 1144 | csr_name, priv_name); |
bd0cf5a6 | 1145 | } |
08ccfccf NC |
1146 | |
1147 | return saved_entry->address; | |
bd0cf5a6 NC |
1148 | } |
1149 | ||
dcd709e0 NC |
1150 | /* Return -1 if the CSR has never been defined. Otherwise, return |
1151 | the address. */ | |
bd0cf5a6 | 1152 | |
8f595e9b | 1153 | static unsigned int |
bd0cf5a6 NC |
1154 | reg_csr_lookup_internal (const char *s) |
1155 | { | |
1156 | struct riscv_csr_extra *r = | |
629310ab | 1157 | (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s); |
bd0cf5a6 NC |
1158 | |
1159 | if (r == NULL) | |
8f595e9b | 1160 | return -1U; |
bd0cf5a6 | 1161 | |
08ccfccf | 1162 | return riscv_csr_address (s, r); |
bd0cf5a6 NC |
1163 | } |
1164 | ||
e23eba97 NC |
1165 | static unsigned int |
1166 | reg_lookup_internal (const char *s, enum reg_class class) | |
1167 | { | |
8f595e9b NC |
1168 | void *r; |
1169 | ||
1170 | if (class == RCLASS_CSR) | |
1171 | return reg_csr_lookup_internal (s); | |
e23eba97 | 1172 | |
629310ab | 1173 | r = str_hash_find (reg_names_hash, s); |
e23eba97 NC |
1174 | if (r == NULL || DECODE_REG_CLASS (r) != class) |
1175 | return -1; | |
7f999549 | 1176 | |
f786c359 | 1177 | if (riscv_subset_supports (&riscv_rps_as, "e") |
edc77c59 NC |
1178 | && class == RCLASS_GPR |
1179 | && DECODE_REG_NUM (r) > 15) | |
7f999549 JW |
1180 | return -1; |
1181 | ||
e23eba97 NC |
1182 | return DECODE_REG_NUM (r); |
1183 | } | |
1184 | ||
5b7c81bd | 1185 | static bool |
e23eba97 NC |
1186 | reg_lookup (char **s, enum reg_class class, unsigned int *regnop) |
1187 | { | |
1188 | char *e; | |
1189 | char save_c; | |
1190 | int reg = -1; | |
1191 | ||
1192 | /* Find end of name. */ | |
1193 | e = *s; | |
1194 | if (is_name_beginner (*e)) | |
1195 | ++e; | |
1196 | while (is_part_of_name (*e)) | |
1197 | ++e; | |
1198 | ||
1199 | /* Terminate name. */ | |
1200 | save_c = *e; | |
1201 | *e = '\0'; | |
1202 | ||
1203 | /* Look for the register. Advance to next token if one was recognized. */ | |
1204 | if ((reg = reg_lookup_internal (*s, class)) >= 0) | |
1205 | *s = e; | |
1206 | ||
1207 | *e = save_c; | |
1208 | if (regnop) | |
1209 | *regnop = reg; | |
1210 | return reg >= 0; | |
1211 | } | |
1212 | ||
5b7c81bd | 1213 | static bool |
e23eba97 NC |
1214 | arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) |
1215 | { | |
1216 | const char *p = strchr (*s, ','); | |
1217 | size_t i, len = p ? (size_t)(p - *s) : strlen (*s); | |
1218 | ||
bfb218e3 | 1219 | if (len == 0) |
5b7c81bd | 1220 | return false; |
bfb218e3 | 1221 | |
e23eba97 | 1222 | for (i = 0; i < size; i++) |
207cc92d LX |
1223 | if (array[i] != NULL && strncmp (array[i], *s, len) == 0 |
1224 | && array[i][len] == '\0') | |
e23eba97 NC |
1225 | { |
1226 | *regnop = i; | |
1227 | *s += len; | |
5b7c81bd | 1228 | return true; |
e23eba97 NC |
1229 | } |
1230 | ||
5b7c81bd | 1231 | return false; |
e23eba97 NC |
1232 | } |
1233 | ||
1f3fc45b CM |
1234 | static bool |
1235 | flt_lookup (float f, const float *array, size_t size, unsigned *regnop) | |
1236 | { | |
1237 | size_t i; | |
1238 | ||
1239 | for (i = 0; i < size; i++) | |
1240 | if (array[i] == f) | |
1241 | { | |
1242 | *regnop = i; | |
1243 | return true; | |
1244 | } | |
1245 | ||
1246 | return false; | |
1247 | } | |
1248 | ||
437e2ff1 | 1249 | #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) |
8b7419c4 CM |
1250 | #define USE_IMM(n, s) \ |
1251 | (used_bits |= ((insn_t)((1ull<<n)-1) << (s))) | |
437e2ff1 | 1252 | |
e23eba97 NC |
1253 | /* For consistency checking, verify that all bits are specified either |
1254 | by the match/mask part of the instruction definition, or by the | |
83029f7f TO |
1255 | operand list. The `length` could be the actual instruction length or |
1256 | 0 for auto-detection. */ | |
0e35537d | 1257 | |
5b7c81bd | 1258 | static bool |
0e35537d | 1259 | validate_riscv_insn (const struct riscv_opcode *opc, int length) |
e23eba97 | 1260 | { |
437e2ff1 | 1261 | const char *oparg, *opargStart; |
e23eba97 | 1262 | insn_t used_bits = opc->mask; |
0e35537d JW |
1263 | int insn_width; |
1264 | insn_t required_bits; | |
1265 | ||
1266 | if (length == 0) | |
83029f7f TO |
1267 | length = riscv_insn_length (opc->match); |
1268 | /* We don't support instructions longer than 64-bits yet. */ | |
1269 | if (length > 8) | |
1270 | length = 8; | |
1271 | insn_width = 8 * length; | |
0e35537d | 1272 | |
83029f7f | 1273 | required_bits = ((insn_t)~0ULL) >> (64 - insn_width); |
e23eba97 NC |
1274 | |
1275 | if ((used_bits & opc->match) != (opc->match & required_bits)) | |
1276 | { | |
1277 | as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), | |
1278 | opc->name, opc->args); | |
5b7c81bd | 1279 | return false; |
e23eba97 NC |
1280 | } |
1281 | ||
437e2ff1 NC |
1282 | for (oparg = opc->args; *oparg; ++oparg) |
1283 | { | |
1284 | opargStart = oparg; | |
1285 | switch (*oparg) | |
1286 | { | |
1287 | case 'C': /* RVC */ | |
1288 | switch (*++oparg) | |
1289 | { | |
1290 | case 'U': break; /* CRS1, constrained to equal RD. */ | |
1291 | case 'c': break; /* CRS1, constrained to equal sp. */ | |
1292 | case 'T': /* CRS2, floating point. */ | |
1293 | case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; | |
1294 | case 'S': /* CRS1S, floating point. */ | |
1295 | case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; | |
1296 | case 'w': break; /* CRS1S, constrained to equal RD. */ | |
1297 | case 'D': /* CRS2S, floating point. */ | |
1298 | case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
1299 | case 'x': break; /* CRS2S, constrained to equal RD. */ | |
1300 | case 'z': break; /* CRS2S, constrained to be x0. */ | |
1301 | case '>': /* CITYPE immediate, compressed shift. */ | |
1302 | case 'u': /* CITYPE immediate, compressed lui. */ | |
1303 | case 'v': /* CITYPE immediate, li to compressed lui. */ | |
1304 | case 'o': /* CITYPE immediate, allow zero. */ | |
1305 | case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break; | |
1306 | case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break; | |
1307 | case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break; | |
1308 | case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break; | |
1309 | case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break; | |
1310 | case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break; | |
1311 | case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break; | |
1312 | case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break; | |
1313 | case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break; | |
1314 | /* CLTYPE and CSTYPE have the same immediate encoding. */ | |
1315 | case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break; | |
1316 | case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break; | |
1317 | case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break; | |
1318 | case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break; | |
1319 | case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break; | |
1320 | case 'F': /* Compressed funct for .insn directive. */ | |
1321 | switch (*++oparg) | |
1322 | { | |
65e4a99a NC |
1323 | case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break; |
1324 | case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; | |
1325 | case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; | |
1326 | case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break; | |
1327 | default: | |
1328 | goto unknown_validate_operand; | |
437e2ff1 NC |
1329 | } |
1330 | break; | |
0e35537d | 1331 | default: |
437e2ff1 NC |
1332 | goto unknown_validate_operand; |
1333 | } | |
a63375ac | 1334 | break; /* end RVC */ |
65e4a99a NC |
1335 | case 'V': /* RVV */ |
1336 | switch (*++oparg) | |
1337 | { | |
1338 | case 'd': | |
1339 | case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break; | |
1340 | case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break; | |
1341 | case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break; | |
1342 | case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1343 | case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1); | |
1344 | USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1345 | case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD); | |
1346 | USE_BITS (OP_MASK_VS1, OP_SH_VS1); | |
1347 | USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1348 | case '0': break; | |
1349 | case 'b': used_bits |= ENCODE_RVV_VB_IMM (-1U); break; | |
1350 | case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break; | |
1351 | case 'i': | |
1352 | case 'j': | |
1353 | case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break; | |
c8cb3734 | 1354 | case 'l': used_bits |= ENCODE_RVV_VI_UIMM6 (-1U); break; |
65e4a99a | 1355 | case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break; |
c1ecdee7 TO |
1356 | case 'M': break; /* Macro operand, must be a mask register. */ |
1357 | case 'T': break; /* Macro operand, must be a vector register. */ | |
65e4a99a NC |
1358 | default: |
1359 | goto unknown_validate_operand; | |
1360 | } | |
a63375ac | 1361 | break; /* end RVV */ |
437e2ff1 NC |
1362 | case ',': break; |
1363 | case '(': break; | |
1364 | case ')': break; | |
1365 | case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; | |
1366 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
1367 | case 'A': break; /* Macro operand, must be symbol. */ | |
1368 | case 'B': break; /* Macro operand, must be symbol or constant. */ | |
c1ecdee7 | 1369 | case 'c': break; /* Macro operand, must be symbol or constant. */ |
437e2ff1 NC |
1370 | case 'I': break; /* Macro operand, must be constant. */ |
1371 | case 'D': /* RD, floating point. */ | |
1372 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
3d1cafa0 | 1373 | case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break; |
1374 | case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break; | |
437e2ff1 NC |
1375 | case 'Z': /* RS1, CSR number. */ |
1376 | case 'S': /* RS1, floating point. */ | |
1377 | case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
1378 | case 'U': /* RS1 and RS2 are the same, floating point. */ | |
1379 | USE_BITS (OP_MASK_RS1, OP_SH_RS1); | |
1380 | /* Fall through. */ | |
1381 | case 'T': /* RS2, floating point. */ | |
1382 | case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
1383 | case 'R': /* RS3, floating point. */ | |
1384 | case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; | |
1385 | case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; | |
1386 | case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; | |
1387 | case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; | |
1388 | case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; | |
1389 | case 'o': /* ITYPE immediate, load displacement. */ | |
1390 | case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; | |
1391 | case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; | |
1392 | case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; | |
1393 | case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; | |
1394 | case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; | |
1395 | case 'z': break; /* Zero immediate. */ | |
1396 | case '[': break; /* Unused operand. */ | |
1397 | case ']': break; /* Unused operand. */ | |
1398 | case '0': break; /* AMO displacement, must to zero. */ | |
1399 | case '1': break; /* Relaxation operand. */ | |
1400 | case 'F': /* Funct for .insn directive. */ | |
1401 | switch (*++oparg) | |
1402 | { | |
6de11ff6 NC |
1403 | case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; |
1404 | case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; | |
1405 | case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; | |
1406 | default: | |
1407 | goto unknown_validate_operand; | |
437e2ff1 NC |
1408 | } |
1409 | break; | |
1410 | case 'O': /* Opcode for .insn directive. */ | |
1411 | switch (*++oparg) | |
1412 | { | |
6de11ff6 NC |
1413 | case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; |
1414 | case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; | |
1415 | default: | |
1416 | goto unknown_validate_operand; | |
437e2ff1 NC |
1417 | } |
1418 | break; | |
6de11ff6 | 1419 | case 'W': /* Various operands for standard z extensions. */ |
54bca63b TO |
1420 | switch (*++oparg) |
1421 | { | |
1422 | case 'i': | |
1423 | switch (*++oparg) | |
1424 | { | |
1425 | case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break; | |
1426 | default: | |
1427 | goto unknown_validate_operand; | |
1428 | } | |
1429 | break; | |
1f3fc45b CM |
1430 | case 'f': |
1431 | switch (*++oparg) | |
1432 | { | |
1433 | case 'v': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
1434 | default: | |
1435 | goto unknown_validate_operand; | |
1436 | } | |
1437 | break; | |
b5c37946 SJ |
1438 | case 'c': |
1439 | switch (*++oparg) | |
1440 | { | |
1441 | /* byte immediate operators, load/store byte insns. */ | |
1442 | case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break; | |
1443 | /* halfword immediate operators, load/store halfword insns. */ | |
1444 | case 'b': used_bits |= ENCODE_ZCB_BYTE_UIMM (-1U); break; | |
1445 | case 'f': break; | |
1446 | default: | |
1447 | goto unknown_validate_operand; | |
1448 | } | |
1449 | break; | |
54bca63b TO |
1450 | default: |
1451 | goto unknown_validate_operand; | |
1452 | } | |
1453 | break; | |
6de11ff6 NC |
1454 | case 'X': /* Vendor-specific operands. */ |
1455 | switch (*++oparg) | |
1456 | { | |
1457 | case 't': /* Vendor-specific (T-head) operands. */ | |
8b7419c4 | 1458 | { |
6de11ff6 NC |
1459 | size_t n; |
1460 | size_t s; | |
1461 | switch (*++oparg) | |
1462 | { | |
1463 | case 'l': /* Integer immediate, literal. */ | |
1464 | oparg += strcspn(oparg, ",") - 1; | |
1465 | break; | |
1466 | case 's': /* Integer immediate, 'XtsN@S' ... N-bit signed immediate at bit S. */ | |
1467 | goto use_imm; | |
1468 | case 'u': /* Integer immediate, 'XtuN@S' ... N-bit unsigned immediate at bit S. */ | |
1469 | goto use_imm; | |
1470 | use_imm: | |
1471 | n = strtol (oparg + 1, (char **)&oparg, 10); | |
1472 | if (*oparg != '@') | |
1473 | goto unknown_validate_operand; | |
1474 | s = strtol (oparg + 1, (char **)&oparg, 10); | |
1475 | oparg--; | |
1476 | ||
1477 | USE_IMM (n, s); | |
1478 | break; | |
1479 | default: | |
8b7419c4 | 1480 | goto unknown_validate_operand; |
6de11ff6 | 1481 | } |
8b7419c4 | 1482 | } |
6de11ff6 NC |
1483 | break; |
1484 | default: | |
1485 | goto unknown_validate_operand; | |
1486 | } | |
8b7419c4 | 1487 | break; |
437e2ff1 NC |
1488 | default: |
1489 | unknown_validate_operand: | |
1490 | as_bad (_("internal: bad RISC-V opcode " | |
1491 | "(unknown operand type `%s'): %s %s"), | |
1492 | opargStart, opc->name, opc->args); | |
1493 | return false; | |
1494 | } | |
1495 | } | |
1496 | ||
e23eba97 NC |
1497 | if (used_bits != required_bits) |
1498 | { | |
b800637e | 1499 | as_bad (_("internal: bad RISC-V opcode " |
6b84c098 TO |
1500 | "(bits %#llx undefined or invalid): %s %s"), |
1501 | (unsigned long long)(used_bits ^ required_bits), | |
e23eba97 | 1502 | opc->name, opc->args); |
5b7c81bd | 1503 | return false; |
e23eba97 | 1504 | } |
5b7c81bd | 1505 | return true; |
e23eba97 NC |
1506 | } |
1507 | ||
437e2ff1 NC |
1508 | #undef USE_BITS |
1509 | ||
e23eba97 NC |
1510 | struct percent_op_match |
1511 | { | |
1512 | const char *str; | |
1513 | bfd_reloc_code_real_type reloc; | |
1514 | }; | |
1515 | ||
dcd709e0 NC |
1516 | /* Common hash table initialization function for instruction and .insn |
1517 | directive. */ | |
1518 | ||
629310ab | 1519 | static htab_t |
0e35537d | 1520 | init_opcode_hash (const struct riscv_opcode *opcodes, |
5b7c81bd | 1521 | bool insn_directive_p) |
e23eba97 NC |
1522 | { |
1523 | int i = 0; | |
0e35537d | 1524 | int length; |
629310ab | 1525 | htab_t hash = str_htab_create (); |
0e35537d | 1526 | while (opcodes[i].name) |
e23eba97 | 1527 | { |
0e35537d | 1528 | const char *name = opcodes[i].name; |
fe0e921f | 1529 | if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL) |
b800637e | 1530 | as_fatal (_("internal: duplicate %s"), name); |
e23eba97 NC |
1531 | |
1532 | do | |
1533 | { | |
0e35537d | 1534 | if (opcodes[i].pinfo != INSN_MACRO) |
e23eba97 | 1535 | { |
0e35537d JW |
1536 | if (insn_directive_p) |
1537 | length = ((name[0] == 'c') ? 2 : 4); | |
1538 | else | |
dcd709e0 | 1539 | length = 0; /* Let assembler determine the length. */ |
0e35537d | 1540 | if (!validate_riscv_insn (&opcodes[i], length)) |
b800637e NC |
1541 | as_fatal (_("internal: broken assembler. " |
1542 | "No assembly attempted")); | |
e23eba97 | 1543 | } |
0e35537d JW |
1544 | else |
1545 | gas_assert (!insn_directive_p); | |
e23eba97 NC |
1546 | ++i; |
1547 | } | |
0e35537d | 1548 | while (opcodes[i].name && !strcmp (opcodes[i].name, name)); |
e23eba97 NC |
1549 | } |
1550 | ||
0e35537d JW |
1551 | return hash; |
1552 | } | |
1553 | ||
1554 | /* This function is called once, at assembler startup time. It should set up | |
1555 | all the tables, etc. that the MD part of the assembler will need. */ | |
1556 | ||
1557 | void | |
1558 | md_begin (void) | |
1559 | { | |
1560 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
1561 | ||
1562 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
b800637e | 1563 | as_warn (_("could not set architecture and machine")); |
0e35537d | 1564 | |
5b7c81bd AM |
1565 | op_hash = init_opcode_hash (riscv_opcodes, false); |
1566 | insn_type_hash = init_opcode_hash (riscv_insn_types, true); | |
0e35537d | 1567 | |
629310ab | 1568 | reg_names_hash = str_htab_create (); |
e23eba97 NC |
1569 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); |
1570 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); | |
1571 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); | |
1572 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); | |
65e4a99a NC |
1573 | hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR); |
1574 | hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM); | |
b9c04e5a JW |
1575 | /* Add "fp" as an alias for "s0". */ |
1576 | hash_reg_name (RCLASS_GPR, "fp", 8); | |
1577 | ||
bd0cf5a6 | 1578 | /* Create and insert CSR hash tables. */ |
629310ab | 1579 | csr_extra_hash = str_htab_create (); |
8f595e9b NC |
1580 | #define DECLARE_CSR(name, num, class, define_version, abort_version) \ |
1581 | riscv_init_csr_hash (#name, num, class, define_version, abort_version); | |
1582 | #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \ | |
1583 | DECLARE_CSR(name, num, class, define_version, abort_version); | |
e23eba97 NC |
1584 | #include "opcode/riscv-opc.h" |
1585 | #undef DECLARE_CSR | |
1586 | ||
629310ab | 1587 | opcode_names_hash = str_htab_create (); |
bd0cf5a6 NC |
1588 | init_opcode_names_hash (); |
1589 | ||
e23eba97 NC |
1590 | /* Set the default alignment for the text section. */ |
1591 | record_alignment (text_section, riscv_opts.rvc ? 1 : 2); | |
1592 | } | |
1593 | ||
45f76423 AW |
1594 | static insn_t |
1595 | riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) | |
1596 | { | |
1597 | switch (reloc_type) | |
1598 | { | |
1599 | case BFD_RELOC_32: | |
1600 | return value; | |
1601 | ||
1602 | case BFD_RELOC_RISCV_HI20: | |
1603 | return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); | |
1604 | ||
1605 | case BFD_RELOC_RISCV_LO12_S: | |
1606 | return ENCODE_STYPE_IMM (value); | |
1607 | ||
1608 | case BFD_RELOC_RISCV_LO12_I: | |
1609 | return ENCODE_ITYPE_IMM (value); | |
1610 | ||
1611 | default: | |
1612 | abort (); | |
1613 | } | |
1614 | } | |
1615 | ||
e23eba97 NC |
1616 | /* Output an instruction. IP is the instruction information. |
1617 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1618 | RELOC_TYPE. */ | |
1619 | ||
1620 | static void | |
1621 | append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, | |
1622 | bfd_reloc_code_real_type reloc_type) | |
1623 | { | |
1624 | dwarf2_emit_insn (0); | |
1625 | ||
1626 | if (reloc_type != BFD_RELOC_UNUSED) | |
1627 | { | |
1628 | reloc_howto_type *howto; | |
1629 | ||
1d65abb5 | 1630 | gas_assert (address_expr); |
e23eba97 NC |
1631 | if (reloc_type == BFD_RELOC_12_PCREL |
1632 | || reloc_type == BFD_RELOC_RISCV_JMP) | |
1633 | { | |
1634 | int j = reloc_type == BFD_RELOC_RISCV_JMP; | |
8c07e983 | 1635 | int best_case = insn_length (ip); |
e23eba97 | 1636 | unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); |
743f5cfc JW |
1637 | |
1638 | if (now_seg == absolute_section) | |
1639 | { | |
1640 | as_bad (_("relaxable branches not supported in absolute section")); | |
1641 | return; | |
1642 | } | |
1643 | ||
e23eba97 NC |
1644 | add_relaxed_insn (ip, worst_case, best_case, |
1645 | RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), | |
1646 | address_expr->X_add_symbol, | |
1647 | address_expr->X_add_number); | |
1648 | return; | |
1649 | } | |
45f76423 | 1650 | else |
e23eba97 | 1651 | { |
45f76423 AW |
1652 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type); |
1653 | if (howto == NULL) | |
579f0281 | 1654 | as_bad (_("internal: unsupported RISC-V relocation number %d"), |
b800637e | 1655 | reloc_type); |
e23eba97 | 1656 | |
45f76423 AW |
1657 | ip->fixp = fix_new_exp (ip->frag, ip->where, |
1658 | bfd_get_reloc_size (howto), | |
5b7c81bd | 1659 | address_expr, false, reloc_type); |
e23eba97 | 1660 | |
45f76423 | 1661 | ip->fixp->fx_tcbit = riscv_opts.relax; |
e23eba97 | 1662 | } |
e23eba97 NC |
1663 | } |
1664 | ||
e23eba97 | 1665 | add_fixed_insn (ip); |
f77bb6c5 JW |
1666 | |
1667 | /* We need to start a new frag after any instruction that can be | |
1668 | optimized away or compressed by the linker during relaxation, to prevent | |
1669 | the assembler from computing static offsets across such an instruction. | |
1670 | This is necessary to get correct EH info. */ | |
b1b11e92 | 1671 | if (reloc_type == BFD_RELOC_RISCV_HI20 |
f77bb6c5 JW |
1672 | || reloc_type == BFD_RELOC_RISCV_PCREL_HI20 |
1673 | || reloc_type == BFD_RELOC_RISCV_TPREL_HI20 | |
1674 | || reloc_type == BFD_RELOC_RISCV_TPREL_ADD) | |
1675 | { | |
1676 | frag_wane (frag_now); | |
1677 | frag_new (0); | |
1678 | } | |
e23eba97 NC |
1679 | } |
1680 | ||
1681 | /* Build an instruction created by a macro expansion. This is passed | |
dcd709e0 NC |
1682 | a pointer to the count of instructions created so far, an expression, |
1683 | the name of the instruction to build, an operand format string, and | |
1684 | corresponding arguments. */ | |
e23eba97 NC |
1685 | |
1686 | static void | |
1687 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) | |
1688 | { | |
1689 | const struct riscv_opcode *mo; | |
1690 | struct riscv_cl_insn insn; | |
1691 | bfd_reloc_code_real_type r; | |
1692 | va_list args; | |
437e2ff1 | 1693 | const char *fmtStart; |
e23eba97 NC |
1694 | |
1695 | va_start (args, fmt); | |
1696 | ||
1697 | r = BFD_RELOC_UNUSED; | |
629310ab | 1698 | mo = (struct riscv_opcode *) str_hash_find (op_hash, name); |
e23eba97 NC |
1699 | gas_assert (mo); |
1700 | ||
1701 | /* Find a non-RVC variant of the instruction. append_insn will compress | |
1702 | it if possible. */ | |
1703 | while (riscv_insn_length (mo->match) < 4) | |
1704 | mo++; | |
1705 | gas_assert (strcmp (name, mo->name) == 0); | |
1706 | ||
1707 | create_insn (&insn, mo); | |
437e2ff1 | 1708 | for (;; ++fmt) |
e23eba97 | 1709 | { |
437e2ff1 NC |
1710 | fmtStart = fmt; |
1711 | switch (*fmt) | |
e23eba97 | 1712 | { |
65e4a99a NC |
1713 | case 'V': /* RVV */ |
1714 | switch (*++fmt) | |
1715 | { | |
1716 | case 'd': | |
1717 | INSERT_OPERAND (VD, insn, va_arg (args, int)); | |
1718 | continue; | |
1719 | case 's': | |
1720 | INSERT_OPERAND (VS1, insn, va_arg (args, int)); | |
1721 | continue; | |
1722 | case 't': | |
1723 | INSERT_OPERAND (VS2, insn, va_arg (args, int)); | |
1724 | continue; | |
1725 | case 'm': | |
1726 | { | |
1727 | int reg = va_arg (args, int); | |
1728 | if (reg == -1) | |
1729 | { | |
1730 | INSERT_OPERAND (VMASK, insn, 1); | |
1731 | continue; | |
1732 | } | |
1733 | else if (reg == 0) | |
1734 | { | |
1735 | INSERT_OPERAND (VMASK, insn, 0); | |
1736 | continue; | |
1737 | } | |
1738 | else | |
1739 | goto unknown_macro_argument; | |
1740 | } | |
1741 | default: | |
1742 | goto unknown_macro_argument; | |
1743 | } | |
1744 | break; | |
1745 | ||
e23eba97 NC |
1746 | case 'd': |
1747 | INSERT_OPERAND (RD, insn, va_arg (args, int)); | |
1748 | continue; | |
e23eba97 NC |
1749 | case 's': |
1750 | INSERT_OPERAND (RS1, insn, va_arg (args, int)); | |
1751 | continue; | |
e23eba97 NC |
1752 | case 't': |
1753 | INSERT_OPERAND (RS2, insn, va_arg (args, int)); | |
1754 | continue; | |
1755 | ||
e23eba97 NC |
1756 | case 'j': |
1757 | case 'u': | |
1758 | case 'q': | |
1759 | gas_assert (ep != NULL); | |
1760 | r = va_arg (args, int); | |
1761 | continue; | |
1762 | ||
1763 | case '\0': | |
1764 | break; | |
1765 | case ',': | |
1766 | continue; | |
1767 | default: | |
65e4a99a | 1768 | unknown_macro_argument: |
437e2ff1 | 1769 | as_fatal (_("internal: invalid macro argument `%s'"), fmtStart); |
e23eba97 NC |
1770 | } |
1771 | break; | |
1772 | } | |
1773 | va_end (args); | |
1774 | gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1775 | ||
1776 | append_insn (&insn, ep, r); | |
1777 | } | |
1778 | ||
db3b6ecc KC |
1779 | /* Build an instruction created by a macro expansion. Like md_assemble but |
1780 | accept a printf-style format string and arguments. */ | |
1781 | ||
1782 | static void | |
1783 | md_assemblef (const char *format, ...) | |
1784 | { | |
1785 | char *buf = NULL; | |
1786 | va_list ap; | |
1787 | int r; | |
1788 | ||
1789 | va_start (ap, format); | |
1790 | ||
1791 | r = vasprintf (&buf, format, ap); | |
1792 | ||
1793 | if (r < 0) | |
b800637e | 1794 | as_fatal (_("internal: vasprintf failed")); |
db3b6ecc KC |
1795 | |
1796 | md_assemble (buf); | |
1797 | free(buf); | |
1798 | ||
1799 | va_end (ap); | |
1800 | } | |
1801 | ||
e23eba97 NC |
1802 | /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits |
1803 | unset. */ | |
dcd709e0 | 1804 | |
e23eba97 NC |
1805 | static void |
1806 | normalize_constant_expr (expressionS *ex) | |
1807 | { | |
1808 | if (xlen > 32) | |
1809 | return; | |
1810 | if ((ex->X_op == O_constant || ex->X_op == O_symbol) | |
1811 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
1812 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
1813 | - 0x80000000); | |
1814 | } | |
1815 | ||
ca2fd32c JW |
1816 | /* Fail if an expression EX is not a constant. IP is the instruction using EX. |
1817 | MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */ | |
e23eba97 NC |
1818 | |
1819 | static void | |
ca2fd32c | 1820 | check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex, |
5b7c81bd | 1821 | bool maybe_csr) |
e23eba97 NC |
1822 | { |
1823 | if (ex->X_op == O_big) | |
1824 | as_bad (_("unsupported large constant")); | |
ca2fd32c JW |
1825 | else if (maybe_csr && ex->X_op == O_symbol) |
1826 | as_bad (_("unknown CSR `%s'"), | |
1827 | S_GET_NAME (ex->X_add_symbol)); | |
e23eba97 | 1828 | else if (ex->X_op != O_constant) |
b800637e | 1829 | as_bad (_("instruction %s requires absolute expression"), |
e23eba97 NC |
1830 | ip->insn_mo->name); |
1831 | normalize_constant_expr (ex); | |
1832 | } | |
1833 | ||
1834 | static symbolS * | |
1835 | make_internal_label (void) | |
1836 | { | |
e01e1cee AM |
1837 | return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now, |
1838 | frag_now_fix ()); | |
e23eba97 NC |
1839 | } |
1840 | ||
1841 | /* Load an entry from the GOT. */ | |
dcd709e0 | 1842 | |
e23eba97 NC |
1843 | static void |
1844 | pcrel_access (int destreg, int tempreg, expressionS *ep, | |
1845 | const char *lo_insn, const char *lo_pattern, | |
1846 | bfd_reloc_code_real_type hi_reloc, | |
1847 | bfd_reloc_code_real_type lo_reloc) | |
1848 | { | |
1849 | expressionS ep2; | |
1850 | ep2.X_op = O_symbol; | |
1851 | ep2.X_add_symbol = make_internal_label (); | |
1852 | ep2.X_add_number = 0; | |
1853 | ||
1854 | macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); | |
1855 | macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); | |
1856 | } | |
1857 | ||
1858 | static void | |
1859 | pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1860 | bfd_reloc_code_real_type hi_reloc, | |
1861 | bfd_reloc_code_real_type lo_reloc) | |
1862 | { | |
1863 | pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); | |
1864 | } | |
1865 | ||
1866 | static void | |
1867 | pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1868 | bfd_reloc_code_real_type hi_reloc, | |
1869 | bfd_reloc_code_real_type lo_reloc) | |
1870 | { | |
1871 | pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); | |
1872 | } | |
1873 | ||
1874 | /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ | |
dcd709e0 | 1875 | |
e23eba97 NC |
1876 | static void |
1877 | riscv_call (int destreg, int tempreg, expressionS *ep, | |
1878 | bfd_reloc_code_real_type reloc) | |
1879 | { | |
b1b11e92 AM |
1880 | /* Ensure the jalr is emitted to the same frag as the auipc. */ |
1881 | frag_grow (8); | |
e23eba97 NC |
1882 | macro_build (ep, "auipc", "d,u", tempreg, reloc); |
1883 | macro_build (NULL, "jalr", "d,s", destreg, tempreg); | |
b1b11e92 AM |
1884 | /* See comment at end of append_insn. */ |
1885 | frag_wane (frag_now); | |
1886 | frag_new (0); | |
e23eba97 NC |
1887 | } |
1888 | ||
1889 | /* Load an integer constant into a register. */ | |
1890 | ||
1891 | static void | |
1892 | load_const (int reg, expressionS *ep) | |
1893 | { | |
1894 | int shift = RISCV_IMM_BITS; | |
4f7cc141 | 1895 | bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1); |
e23eba97 | 1896 | expressionS upper = *ep, lower = *ep; |
4f7cc141 | 1897 | lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign; |
e23eba97 NC |
1898 | upper.X_add_number -= lower.X_add_number; |
1899 | ||
1900 | if (ep->X_op != O_constant) | |
1901 | { | |
1902 | as_bad (_("unsupported large constant")); | |
1903 | return; | |
1904 | } | |
1905 | ||
1d65abb5 | 1906 | if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) |
e23eba97 NC |
1907 | { |
1908 | /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ | |
1909 | while (((upper.X_add_number >> shift) & 1) == 0) | |
1910 | shift++; | |
1911 | ||
1912 | upper.X_add_number = (int64_t) upper.X_add_number >> shift; | |
1d65abb5 | 1913 | load_const (reg, &upper); |
e23eba97 | 1914 | |
db3b6ecc | 1915 | md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift); |
e23eba97 | 1916 | if (lower.X_add_number != 0) |
b8281767 AM |
1917 | md_assemblef ("addi x%d, x%d, %" PRId64, reg, reg, |
1918 | (int64_t) lower.X_add_number); | |
e23eba97 NC |
1919 | } |
1920 | else | |
1921 | { | |
1922 | /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ | |
1923 | int hi_reg = 0; | |
1924 | ||
1925 | if (upper.X_add_number != 0) | |
1926 | { | |
db3b6ecc KC |
1927 | /* Discard low part and zero-extend upper immediate. */ |
1928 | upper_imm = ((uint32_t)upper.X_add_number >> shift); | |
1929 | ||
b8281767 | 1930 | md_assemblef ("lui x%d, 0x%" PRIx64, reg, (uint64_t) upper_imm); |
e23eba97 NC |
1931 | hi_reg = reg; |
1932 | } | |
1933 | ||
1934 | if (lower.X_add_number != 0 || hi_reg == 0) | |
b8281767 AM |
1935 | md_assemblef ("%s x%d, x%d, %" PRId64, ADD32_INSN, reg, hi_reg, |
1936 | (int64_t) lower.X_add_number); | |
e23eba97 NC |
1937 | } |
1938 | } | |
1939 | ||
c2137f55 NC |
1940 | /* Zero extend and sign extend byte/half-word/word. */ |
1941 | ||
1942 | static void | |
5b7c81bd | 1943 | riscv_ext (int destreg, int srcreg, unsigned shift, bool sign) |
c2137f55 NC |
1944 | { |
1945 | if (sign) | |
1946 | { | |
1947 | md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift); | |
1948 | md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift); | |
1949 | } | |
1950 | else | |
1951 | { | |
1952 | md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift); | |
1953 | md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift); | |
1954 | } | |
1955 | } | |
1956 | ||
65e4a99a NC |
1957 | /* Expand RISC-V Vector macros into one or more instructions. */ |
1958 | ||
1959 | static void | |
1960 | vector_macro (struct riscv_cl_insn *ip) | |
1961 | { | |
1962 | int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD; | |
1963 | int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1; | |
1964 | int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2; | |
1965 | int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK; | |
1966 | int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6; | |
d4868004 | 1967 | const char *vmslt_vx = ip->insn_mo->match ? "vmsltu.vx" : "vmslt.vx"; |
65e4a99a NC |
1968 | int mask = ip->insn_mo->mask; |
1969 | ||
1970 | switch (mask) | |
1971 | { | |
1972 | case M_VMSGE: | |
1973 | if (vm) | |
1974 | { | |
1975 | /* Unmasked. */ | |
d4868004 | 1976 | macro_build (NULL, vmslt_vx, "Vd,Vt,sVm", vd, vs2, vs1, -1); |
65e4a99a NC |
1977 | macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd); |
1978 | break; | |
1979 | } | |
1980 | if (vtemp != 0) | |
1981 | { | |
1982 | /* Masked. Have vtemp to avoid overlap constraints. */ | |
1983 | if (vd == vm) | |
1984 | { | |
d4868004 | 1985 | macro_build (NULL, vmslt_vx, "Vd,Vt,sVm", vtemp, vs2, vs1, -1); |
65e4a99a NC |
1986 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); |
1987 | } | |
1988 | else | |
1989 | { | |
1990 | /* Preserve the value of vd if not updating by vm. */ | |
d4868004 | 1991 | macro_build (NULL, vmslt_vx, "Vd,Vt,sVm", vtemp, vs2, vs1, -1); |
65e4a99a NC |
1992 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); |
1993 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); | |
1994 | macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); | |
1995 | } | |
1996 | } | |
1997 | else if (vd != vm) | |
1998 | { | |
1999 | /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */ | |
d4868004 | 2000 | macro_build (NULL, vmslt_vx, "Vd,Vt,sVm", vd, vs2, vs1, vm); |
65e4a99a NC |
2001 | macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm); |
2002 | } | |
2003 | else | |
2004 | as_bad (_("must provide temp if destination overlaps mask")); | |
2005 | break; | |
2006 | ||
2007 | default: | |
2008 | break; | |
2009 | } | |
2010 | } | |
2011 | ||
e23eba97 | 2012 | /* Expand RISC-V assembly macros into one or more instructions. */ |
2652cfad | 2013 | |
e23eba97 NC |
2014 | static void |
2015 | macro (struct riscv_cl_insn *ip, expressionS *imm_expr, | |
2016 | bfd_reloc_code_real_type *imm_reloc) | |
2017 | { | |
2018 | int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; | |
2019 | int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; | |
2020 | int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; | |
2021 | int mask = ip->insn_mo->mask; | |
2022 | ||
2023 | switch (mask) | |
2024 | { | |
2025 | case M_LI: | |
2026 | load_const (rd, imm_expr); | |
2027 | break; | |
2028 | ||
2029 | case M_LA: | |
2030 | case M_LLA: | |
ec2260af | 2031 | case M_LGA: |
e23eba97 NC |
2032 | /* Load the address of a symbol into a register. */ |
2033 | if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) | |
2034 | as_bad (_("offset too large")); | |
2035 | ||
2036 | if (imm_expr->X_op == O_constant) | |
2037 | load_const (rd, imm_expr); | |
ec2260af JW |
2038 | /* Global PIC symbol. */ |
2039 | else if ((riscv_opts.pic && mask == M_LA) | |
2040 | || mask == M_LGA) | |
e23eba97 NC |
2041 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, |
2042 | BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
ec2260af JW |
2043 | /* Local PIC symbol, or any non-PIC symbol. */ |
2044 | else | |
e23eba97 NC |
2045 | pcrel_load (rd, rd, imm_expr, "addi", |
2046 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2047 | break; | |
2048 | ||
2049 | case M_LA_TLS_GD: | |
2050 | pcrel_load (rd, rd, imm_expr, "addi", | |
2051 | BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2052 | break; | |
2053 | ||
2054 | case M_LA_TLS_IE: | |
2055 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
2056 | BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2057 | break; | |
2058 | ||
2059 | case M_LB: | |
2060 | pcrel_load (rd, rd, imm_expr, "lb", | |
2061 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2062 | break; | |
2063 | ||
2064 | case M_LBU: | |
2065 | pcrel_load (rd, rd, imm_expr, "lbu", | |
2066 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2067 | break; | |
2068 | ||
2069 | case M_LH: | |
2070 | pcrel_load (rd, rd, imm_expr, "lh", | |
2071 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2072 | break; | |
2073 | ||
2074 | case M_LHU: | |
2075 | pcrel_load (rd, rd, imm_expr, "lhu", | |
2076 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2077 | break; | |
2078 | ||
2079 | case M_LW: | |
2080 | pcrel_load (rd, rd, imm_expr, "lw", | |
2081 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2082 | break; | |
2083 | ||
2084 | case M_LWU: | |
2085 | pcrel_load (rd, rd, imm_expr, "lwu", | |
2086 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2087 | break; | |
2088 | ||
2089 | case M_LD: | |
2090 | pcrel_load (rd, rd, imm_expr, "ld", | |
2091 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2092 | break; | |
2093 | ||
2094 | case M_FLW: | |
2095 | pcrel_load (rd, rs1, imm_expr, "flw", | |
2096 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2097 | break; | |
2098 | ||
2099 | case M_FLD: | |
2100 | pcrel_load (rd, rs1, imm_expr, "fld", | |
2101 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2102 | break; | |
2103 | ||
2104 | case M_SB: | |
2105 | pcrel_store (rs2, rs1, imm_expr, "sb", | |
2106 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2107 | break; | |
2108 | ||
2109 | case M_SH: | |
2110 | pcrel_store (rs2, rs1, imm_expr, "sh", | |
2111 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2112 | break; | |
2113 | ||
2114 | case M_SW: | |
2115 | pcrel_store (rs2, rs1, imm_expr, "sw", | |
2116 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2117 | break; | |
2118 | ||
2119 | case M_SD: | |
2120 | pcrel_store (rs2, rs1, imm_expr, "sd", | |
2121 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2122 | break; | |
2123 | ||
2124 | case M_FSW: | |
2125 | pcrel_store (rs2, rs1, imm_expr, "fsw", | |
2126 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2127 | break; | |
2128 | ||
2129 | case M_FSD: | |
2130 | pcrel_store (rs2, rs1, imm_expr, "fsd", | |
2131 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2132 | break; | |
2133 | ||
2134 | case M_CALL: | |
2135 | riscv_call (rd, rs1, imm_expr, *imm_reloc); | |
2136 | break; | |
2137 | ||
c2137f55 | 2138 | case M_ZEXTH: |
5b7c81bd | 2139 | riscv_ext (rd, rs1, xlen - 16, false); |
c2137f55 NC |
2140 | break; |
2141 | ||
2142 | case M_ZEXTW: | |
5b7c81bd | 2143 | riscv_ext (rd, rs1, xlen - 32, false); |
c2137f55 NC |
2144 | break; |
2145 | ||
2146 | case M_SEXTB: | |
5b7c81bd | 2147 | riscv_ext (rd, rs1, xlen - 8, true); |
c2137f55 NC |
2148 | break; |
2149 | ||
2150 | case M_SEXTH: | |
5b7c81bd | 2151 | riscv_ext (rd, rs1, xlen - 16, true); |
c2137f55 NC |
2152 | break; |
2153 | ||
65e4a99a | 2154 | case M_VMSGE: |
65e4a99a NC |
2155 | vector_macro (ip); |
2156 | break; | |
2157 | ||
035784e3 NC |
2158 | case M_FLH: |
2159 | pcrel_load (rd, rs1, imm_expr, "flh", | |
2160 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2161 | break; | |
2162 | case M_FSH: | |
2163 | pcrel_store (rs2, rs1, imm_expr, "fsh", | |
2164 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2165 | break; | |
2166 | ||
e23eba97 | 2167 | default: |
b800637e | 2168 | as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name); |
e23eba97 NC |
2169 | break; |
2170 | } | |
2171 | } | |
2172 | ||
2173 | static const struct percent_op_match percent_op_utype[] = | |
2174 | { | |
85bd4bfb JB |
2175 | {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, |
2176 | {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, | |
2177 | {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, | |
2178 | {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, | |
2179 | {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, | |
2180 | {"hi", BFD_RELOC_RISCV_HI20}, | |
e23eba97 NC |
2181 | {0, 0} |
2182 | }; | |
2183 | ||
2184 | static const struct percent_op_match percent_op_itype[] = | |
2185 | { | |
85bd4bfb JB |
2186 | {"lo", BFD_RELOC_RISCV_LO12_I}, |
2187 | {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, | |
2188 | {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, | |
e23eba97 NC |
2189 | {0, 0} |
2190 | }; | |
2191 | ||
2192 | static const struct percent_op_match percent_op_stype[] = | |
2193 | { | |
85bd4bfb JB |
2194 | {"lo", BFD_RELOC_RISCV_LO12_S}, |
2195 | {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, | |
2196 | {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, | |
e23eba97 NC |
2197 | {0, 0} |
2198 | }; | |
2199 | ||
2200 | static const struct percent_op_match percent_op_rtype[] = | |
2201 | { | |
85bd4bfb | 2202 | {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, |
e23eba97 NC |
2203 | {0, 0} |
2204 | }; | |
2205 | ||
f50fabe4 JW |
2206 | static const struct percent_op_match percent_op_null[] = |
2207 | { | |
2208 | {0, 0} | |
2209 | }; | |
2210 | ||
e23eba97 NC |
2211 | /* Return true if *STR points to a relocation operator. When returning true, |
2212 | move *STR over the operator and store its relocation code in *RELOC. | |
2213 | Leave both *STR and *RELOC alone when returning false. */ | |
2214 | ||
5b7c81bd | 2215 | static bool |
e23eba97 NC |
2216 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc, |
2217 | const struct percent_op_match *percent_op) | |
2218 | { | |
2219 | for ( ; percent_op->str; percent_op++) | |
85bd4bfb | 2220 | if (strncasecmp (*str + 1, percent_op->str, strlen (percent_op->str)) == 0) |
e23eba97 | 2221 | { |
85bd4bfb | 2222 | size_t len = 1 + strlen (percent_op->str); |
e23eba97 | 2223 | |
654dfab0 JB |
2224 | while (ISSPACE ((*str)[len])) |
2225 | ++len; | |
2226 | if ((*str)[len] != '(') | |
e23eba97 NC |
2227 | continue; |
2228 | ||
85bd4bfb | 2229 | *str += len; |
e23eba97 NC |
2230 | *reloc = percent_op->reloc; |
2231 | ||
2232 | /* Check whether the output BFD supports this relocation. | |
2233 | If not, issue an error and fall back on something safe. */ | |
45f76423 AW |
2234 | if (*reloc != BFD_RELOC_UNUSED |
2235 | && !bfd_reloc_type_lookup (stdoutput, *reloc)) | |
e23eba97 | 2236 | { |
b800637e NC |
2237 | as_bad ("internal: relocation %s isn't supported by the " |
2238 | "current ABI", percent_op->str); | |
e23eba97 NC |
2239 | *reloc = BFD_RELOC_UNUSED; |
2240 | } | |
5b7c81bd | 2241 | return true; |
e23eba97 | 2242 | } |
5b7c81bd | 2243 | return false; |
e23eba97 NC |
2244 | } |
2245 | ||
2246 | static void | |
2247 | my_getExpression (expressionS *ep, char *str) | |
2248 | { | |
2249 | char *save_in; | |
2250 | ||
2251 | save_in = input_line_pointer; | |
2252 | input_line_pointer = str; | |
2253 | expression (ep); | |
6eb099ae | 2254 | expr_parse_end = input_line_pointer; |
e23eba97 NC |
2255 | input_line_pointer = save_in; |
2256 | } | |
2257 | ||
2258 | /* Parse string STR as a 16-bit relocatable operand. Store the | |
2259 | expression in *EP and the relocation, if any, in RELOC. | |
2260 | Return the number of relocation operators used (0 or 1). | |
2261 | ||
6eb099ae AM |
2262 | On exit, EXPR_PARSE_END points to the first character after the |
2263 | expression. */ | |
e23eba97 NC |
2264 | |
2265 | static size_t | |
2266 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
2267 | char *str, const struct percent_op_match *percent_op) | |
2268 | { | |
2269 | size_t reloc_index; | |
7a29ee29 JB |
2270 | unsigned crux_depth, str_depth; |
2271 | bool orig_probing = probing_insn_operands; | |
e23eba97 NC |
2272 | char *crux; |
2273 | ||
e23eba97 | 2274 | /* Search for the start of the main expression. |
dcd709e0 NC |
2275 | |
2276 | End the loop with CRUX pointing to the start of the main expression and | |
2277 | with CRUX_DEPTH containing the number of open brackets at that point. */ | |
e23eba97 NC |
2278 | reloc_index = -1; |
2279 | str_depth = 0; | |
2280 | do | |
2281 | { | |
2282 | reloc_index++; | |
2283 | crux = str; | |
2284 | crux_depth = str_depth; | |
2285 | ||
2286 | /* Skip over whitespace and brackets, keeping count of the number | |
2287 | of brackets. */ | |
2288 | while (*str == ' ' || *str == '\t' || *str == '(') | |
2289 | if (*str++ == '(') | |
2290 | str_depth++; | |
2291 | } | |
2292 | while (*str == '%' | |
2293 | && reloc_index < 1 | |
2294 | && parse_relocation (&str, reloc, percent_op)); | |
2295 | ||
a5e756e6 JB |
2296 | if (*str == '%') |
2297 | { | |
2298 | /* expression() will choke on anything looking like an (unrecognized) | |
2299 | relocation specifier. Don't even call it, avoiding multiple (and | |
2300 | perhaps redundant) error messages; our caller will issue one. */ | |
2301 | ep->X_op = O_illegal; | |
2302 | return 0; | |
2303 | } | |
2304 | ||
7a29ee29 JB |
2305 | /* Anything inside parentheses or subject to a relocation operator cannot |
2306 | be a register and hence can be treated the same as operands to | |
2307 | directives (other than .insn). */ | |
2308 | if (str_depth || reloc_index) | |
2309 | probing_insn_operands = false; | |
2310 | ||
e23eba97 | 2311 | my_getExpression (ep, crux); |
6eb099ae | 2312 | str = expr_parse_end; |
e23eba97 | 2313 | |
7a29ee29 JB |
2314 | probing_insn_operands = orig_probing; |
2315 | ||
e23eba97 NC |
2316 | /* Match every open bracket. */ |
2317 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) | |
2318 | if (*str++ == ')') | |
2319 | crux_depth--; | |
2320 | ||
2321 | if (crux_depth > 0) | |
2322 | as_bad ("unclosed '('"); | |
2323 | ||
6eb099ae | 2324 | expr_parse_end = str; |
e23eba97 NC |
2325 | |
2326 | return reloc_index; | |
2327 | } | |
2328 | ||
0e35537d | 2329 | /* Parse opcode name, could be an mnemonics or number. */ |
dcd709e0 | 2330 | |
0e35537d JW |
2331 | static size_t |
2332 | my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
408ab016 | 2333 | char *str) |
0e35537d JW |
2334 | { |
2335 | const struct opcode_name_t *o = opcode_name_lookup (&str); | |
2336 | ||
2337 | if (o != NULL) | |
2338 | { | |
2339 | ep->X_op = O_constant; | |
2340 | ep->X_add_number = o->val; | |
2341 | return 0; | |
2342 | } | |
2343 | ||
408ab016 | 2344 | return my_getSmallExpression (ep, reloc, str, percent_op_null); |
0e35537d JW |
2345 | } |
2346 | ||
65e4a99a | 2347 | /* Parse string STR as a vsetvli operand. Store the expression in *EP. |
6eb099ae AM |
2348 | On exit, EXPR_PARSE_END points to the first character after the |
2349 | expression. */ | |
65e4a99a NC |
2350 | |
2351 | static void | |
2352 | my_getVsetvliExpression (expressionS *ep, char *str) | |
2353 | { | |
2354 | unsigned int vsew_value = 0, vlmul_value = 0; | |
2355 | unsigned int vta_value = 0, vma_value = 0; | |
2356 | bfd_boolean vsew_found = FALSE, vlmul_found = FALSE; | |
2357 | bfd_boolean vta_found = FALSE, vma_found = FALSE; | |
2358 | ||
2359 | if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value)) | |
2360 | { | |
2361 | if (*str == ',') | |
2362 | ++str; | |
2363 | if (vsew_found) | |
2364 | as_bad (_("multiple vsew constants")); | |
2365 | vsew_found = TRUE; | |
2366 | } | |
2367 | if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value)) | |
2368 | { | |
2369 | if (*str == ',') | |
2370 | ++str; | |
2371 | if (vlmul_found) | |
2372 | as_bad (_("multiple vlmul constants")); | |
2373 | vlmul_found = TRUE; | |
2374 | } | |
2375 | if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value)) | |
2376 | { | |
2377 | if (*str == ',') | |
2378 | ++str; | |
2379 | if (vta_found) | |
2380 | as_bad (_("multiple vta constants")); | |
2381 | vta_found = TRUE; | |
2382 | } | |
2383 | if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value)) | |
2384 | { | |
2385 | if (*str == ',') | |
2386 | ++str; | |
2387 | if (vma_found) | |
2388 | as_bad (_("multiple vma constants")); | |
2389 | vma_found = TRUE; | |
2390 | } | |
2391 | ||
2392 | if (vsew_found || vlmul_found || vta_found || vma_found) | |
2393 | { | |
2394 | ep->X_op = O_constant; | |
2395 | ep->X_add_number = (vlmul_value << OP_SH_VLMUL) | |
2396 | | (vsew_value << OP_SH_VSEW) | |
2397 | | (vta_value << OP_SH_VTA) | |
2398 | | (vma_value << OP_SH_VMA); | |
6eb099ae | 2399 | expr_parse_end = str; |
65e4a99a NC |
2400 | } |
2401 | else | |
2402 | { | |
2403 | my_getExpression (ep, str); | |
6eb099ae | 2404 | str = expr_parse_end; |
65e4a99a NC |
2405 | } |
2406 | } | |
2407 | ||
f0531ed6 | 2408 | /* Detect and handle implicitly zero load-store offsets. For example, |
437e2ff1 | 2409 | "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such |
f0531ed6 JW |
2410 | an implicit offset was detected. */ |
2411 | ||
5b7c81bd | 2412 | static bool |
89424b1d | 2413 | riscv_handle_implicit_zero_offset (expressionS *ep, const char *s) |
f0531ed6 JW |
2414 | { |
2415 | /* Check whether there is only a single bracketed expression left. | |
2416 | If so, it must be the base register and the constant must be zero. */ | |
2417 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
2418 | { | |
89424b1d MR |
2419 | ep->X_op = O_constant; |
2420 | ep->X_add_number = 0; | |
5b7c81bd | 2421 | return true; |
f0531ed6 JW |
2422 | } |
2423 | ||
5b7c81bd | 2424 | return false; |
f0531ed6 JW |
2425 | } |
2426 | ||
54b2aec1 | 2427 | /* All RISC-V CSR instructions belong to one of these classes. */ |
54b2aec1 NC |
2428 | enum csr_insn_type |
2429 | { | |
2430 | INSN_NOT_CSR, | |
2431 | INSN_CSRRW, | |
2432 | INSN_CSRRS, | |
2433 | INSN_CSRRC | |
2434 | }; | |
2435 | ||
2436 | /* Return which CSR instruction is checking. */ | |
2437 | ||
2438 | static enum csr_insn_type | |
2439 | riscv_csr_insn_type (insn_t insn) | |
2440 | { | |
2441 | if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0 | |
2442 | || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0) | |
2443 | return INSN_CSRRW; | |
2444 | else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0 | |
2445 | || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0) | |
2446 | return INSN_CSRRS; | |
2447 | else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0 | |
2448 | || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0) | |
2449 | return INSN_CSRRC; | |
2450 | else | |
2451 | return INSN_NOT_CSR; | |
2452 | } | |
2453 | ||
2454 | /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write | |
2455 | CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of | |
2456 | CSR address is 0x3. */ | |
2457 | ||
5b7c81bd | 2458 | static bool |
54b2aec1 NC |
2459 | riscv_csr_read_only_check (insn_t insn) |
2460 | { | |
2461 | int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR; | |
2462 | int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1; | |
2463 | int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3); | |
2464 | enum csr_insn_type csr_insn = riscv_csr_insn_type (insn); | |
2465 | ||
2466 | if (readonly | |
2467 | && (((csr_insn == INSN_CSRRS | |
2468 | || csr_insn == INSN_CSRRC) | |
2469 | && rs1 != 0) | |
2470 | || csr_insn == INSN_CSRRW)) | |
5b7c81bd | 2471 | return false; |
54b2aec1 | 2472 | |
5b7c81bd | 2473 | return true; |
54b2aec1 NC |
2474 | } |
2475 | ||
437e2ff1 | 2476 | /* Return true if it is a privileged instruction. Otherwise, return false. |
1a79004f NC |
2477 | |
2478 | uret is actually a N-ext instruction. So it is better to regard it as | |
2479 | an user instruction rather than the priv instruction. | |
2480 | ||
2481 | hret is used to return from traps in H-mode. H-mode is removed since | |
2482 | the v1.10 priv spec, but probably be added in the new hypervisor spec. | |
2483 | Therefore, hret should be controlled by the hypervisor spec rather than | |
2484 | priv spec in the future. | |
2485 | ||
2486 | dret is defined in the debug spec, so it should be checked in the future, | |
2487 | too. */ | |
2488 | ||
5b7c81bd | 2489 | static bool |
1a79004f NC |
2490 | riscv_is_priv_insn (insn_t insn) |
2491 | { | |
2492 | return (((insn ^ MATCH_SRET) & MASK_SRET) == 0 | |
2493 | || ((insn ^ MATCH_MRET) & MASK_MRET) == 0 | |
2494 | || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0 | |
2495 | || ((insn ^ MATCH_WFI) & MASK_WFI) == 0 | |
2496 | /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to | |
dcd709e0 | 2497 | check it here to keep the compatible. */ |
1a79004f NC |
2498 | || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0); |
2499 | } | |
2500 | ||
7a29ee29 JB |
2501 | static symbolS *deferred_sym_rootP; |
2502 | static symbolS *deferred_sym_lastP; | |
2503 | /* Since symbols can't easily be freed, try to recycle ones which weren't | |
2504 | committed. */ | |
2505 | static symbolS *orphan_sym_rootP; | |
2506 | static symbolS *orphan_sym_lastP; | |
2507 | ||
e23eba97 NC |
2508 | /* This routine assembles an instruction into its binary format. As a |
2509 | side effect, it sets the global variable imm_reloc to the type of | |
2510 | relocation to do if one of the operands is an address expression. */ | |
2511 | ||
e4028336 | 2512 | static struct riscv_ip_error |
e23eba97 | 2513 | riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, |
629310ab | 2514 | bfd_reloc_code_real_type *imm_reloc, htab_t hash) |
e23eba97 | 2515 | { |
437e2ff1 NC |
2516 | /* The operand string defined in the riscv_opcodes. */ |
2517 | const char *oparg, *opargStart; | |
2518 | /* The parsed operands from assembly. */ | |
2519 | char *asarg, *asargStart; | |
2520 | char save_c = 0; | |
e23eba97 | 2521 | struct riscv_opcode *insn; |
e23eba97 | 2522 | unsigned int regno; |
e23eba97 | 2523 | const struct percent_op_match *p; |
e4028336 PN |
2524 | struct riscv_ip_error error; |
2525 | error.msg = "unrecognized opcode"; | |
2526 | error.statement = str; | |
2527 | error.missing_ext = NULL; | |
54b2aec1 | 2528 | /* Indicate we are assembling instruction with CSR. */ |
5b7c81bd | 2529 | bool insn_with_csr = false; |
e23eba97 NC |
2530 | |
2531 | /* Parse the name of the instruction. Terminate the string if whitespace | |
629310ab | 2532 | is found so that str_hash_find only sees the name part of the string. */ |
437e2ff1 NC |
2533 | for (asarg = str; *asarg!= '\0'; ++asarg) |
2534 | if (ISSPACE (*asarg)) | |
e23eba97 | 2535 | { |
437e2ff1 NC |
2536 | save_c = *asarg; |
2537 | *asarg++ = '\0'; | |
e23eba97 NC |
2538 | break; |
2539 | } | |
2540 | ||
629310ab | 2541 | insn = (struct riscv_opcode *) str_hash_find (hash, str); |
e23eba97 | 2542 | |
7a29ee29 JB |
2543 | probing_insn_operands = true; |
2544 | ||
437e2ff1 | 2545 | asargStart = asarg; |
e23eba97 NC |
2546 | for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) |
2547 | { | |
1080bf78 JW |
2548 | if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement)) |
2549 | continue; | |
2550 | ||
f786c359 | 2551 | if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) |
e4028336 PN |
2552 | { |
2553 | error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, | |
2554 | insn->insn_class); | |
2555 | continue; | |
2556 | } | |
e23eba97 | 2557 | |
65e4a99a | 2558 | /* Reset error message of the previous round. */ |
e4028336 PN |
2559 | error.msg = _("illegal operands"); |
2560 | error.missing_ext = NULL; | |
7a29ee29 JB |
2561 | |
2562 | /* Purge deferred symbols from the previous round, if any. */ | |
2563 | while (deferred_sym_rootP) | |
2564 | { | |
2565 | symbolS *sym = deferred_sym_rootP; | |
2566 | ||
2567 | symbol_remove (sym, &deferred_sym_rootP, &deferred_sym_lastP); | |
2568 | symbol_append (sym, orphan_sym_lastP, &orphan_sym_rootP, | |
2569 | &orphan_sym_lastP); | |
2570 | } | |
2571 | ||
e23eba97 | 2572 | create_insn (ip, insn); |
e23eba97 NC |
2573 | |
2574 | imm_expr->X_op = O_absent; | |
2575 | *imm_reloc = BFD_RELOC_UNUSED; | |
b33e94cf | 2576 | p = percent_op_null; |
e23eba97 | 2577 | |
437e2ff1 | 2578 | for (oparg = insn->args;; ++oparg) |
e23eba97 | 2579 | { |
437e2ff1 NC |
2580 | opargStart = oparg; |
2581 | asarg += strspn (asarg, " \t"); | |
2582 | switch (*oparg) | |
e23eba97 | 2583 | { |
dcd709e0 | 2584 | case '\0': /* End of args. */ |
e23eba97 NC |
2585 | if (insn->pinfo != INSN_MACRO) |
2586 | { | |
2587 | if (!insn->match_func (insn, ip->insn_opcode)) | |
2588 | break; | |
0e35537d JW |
2589 | |
2590 | /* For .insn, insn->match and insn->mask are 0. */ | |
2591 | if (riscv_insn_length ((insn->match == 0 && insn->mask == 0) | |
2592 | ? ip->insn_opcode | |
2593 | : insn->match) == 2 | |
2594 | && !riscv_opts.rvc) | |
e23eba97 | 2595 | break; |
54b2aec1 | 2596 | |
1a79004f | 2597 | if (riscv_is_priv_insn (ip->insn_opcode)) |
5b7c81bd | 2598 | explicit_priv_attr = true; |
1a79004f | 2599 | |
54b2aec1 NC |
2600 | /* Check if we write a read-only CSR by the CSR |
2601 | instruction. */ | |
2602 | if (insn_with_csr | |
2603 | && riscv_opts.csr_check | |
2604 | && !riscv_csr_read_only_check (ip->insn_opcode)) | |
2605 | { | |
2606 | /* Restore the character in advance, since we want to | |
2607 | report the detailed warning message here. */ | |
2608 | if (save_c) | |
437e2ff1 | 2609 | *(asargStart - 1) = save_c; |
b800637e | 2610 | as_warn (_("read-only CSR is written `%s'"), str); |
5b7c81bd | 2611 | insn_with_csr = false; |
54b2aec1 | 2612 | } |
65e4a99a NC |
2613 | |
2614 | /* The (segmant) load and store with EEW 64 cannot be used | |
2615 | when zve32x is enabled. */ | |
2616 | if (ip->insn_mo->pinfo & INSN_V_EEW64 | |
2617 | && riscv_subset_supports (&riscv_rps_as, "zve32x") | |
2618 | && !riscv_subset_supports (&riscv_rps_as, "zve64x")) | |
2619 | { | |
e4028336 | 2620 | error.msg = _("illegal opcode for zve32x"); |
65e4a99a NC |
2621 | break; |
2622 | } | |
e23eba97 | 2623 | } |
437e2ff1 | 2624 | if (*asarg != '\0') |
e23eba97 | 2625 | break; |
7a29ee29 | 2626 | |
e23eba97 | 2627 | /* Successful assembly. */ |
e4028336 | 2628 | error.msg = NULL; |
5b7c81bd | 2629 | insn_with_csr = false; |
7a29ee29 JB |
2630 | |
2631 | /* Commit deferred symbols, if any. */ | |
2632 | while (deferred_sym_rootP) | |
2633 | { | |
2634 | symbolS *sym = deferred_sym_rootP; | |
2635 | ||
2636 | symbol_remove (sym, &deferred_sym_rootP, | |
2637 | &deferred_sym_lastP); | |
2638 | symbol_append (sym, symbol_lastP, &symbol_rootP, | |
2639 | &symbol_lastP); | |
2640 | symbol_table_insert (sym); | |
2641 | } | |
e23eba97 NC |
2642 | goto out; |
2643 | ||
2644 | case 'C': /* RVC */ | |
437e2ff1 | 2645 | switch (*++oparg) |
e23eba97 | 2646 | { |
dcd709e0 | 2647 | case 's': /* RS1 x8-x15. */ |
437e2ff1 | 2648 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2649 | || !(regno >= 8 && regno <= 15)) |
2650 | break; | |
2651 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
2652 | continue; | |
2653 | case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ | |
437e2ff1 | 2654 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2655 | || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) |
2656 | break; | |
2657 | continue; | |
dcd709e0 | 2658 | case 't': /* RS2 x8-x15. */ |
437e2ff1 | 2659 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2660 | || !(regno >= 8 && regno <= 15)) |
2661 | break; | |
2662 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
2663 | continue; | |
2664 | case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ | |
437e2ff1 | 2665 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2666 | || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) |
2667 | break; | |
2668 | continue; | |
2669 | case 'U': /* RS1, constrained to equal RD. */ | |
437e2ff1 | 2670 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2671 | || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) |
2672 | break; | |
2673 | continue; | |
2674 | case 'V': /* RS2 */ | |
437e2ff1 | 2675 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no)) |
e23eba97 NC |
2676 | break; |
2677 | INSERT_OPERAND (CRS2, *ip, regno); | |
2678 | continue; | |
2679 | case 'c': /* RS1, constrained to equal sp. */ | |
437e2ff1 | 2680 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2681 | || regno != X_SP) |
2682 | break; | |
2683 | continue; | |
dcd709e0 | 2684 | case 'z': /* RS2, constrained to equal x0. */ |
437e2ff1 | 2685 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
ca0bc150 JW |
2686 | || regno != 0) |
2687 | break; | |
2688 | continue; | |
768589d1 | 2689 | case '>': /* Shift amount, 0 - (XLEN-1). */ |
437e2ff1 | 2690 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2691 | || imm_expr->X_op != O_constant |
768589d1 | 2692 | || (unsigned long) imm_expr->X_add_number >= xlen) |
e23eba97 | 2693 | break; |
5a9f5403 | 2694 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
dc1e8a47 | 2695 | rvc_imm_done: |
6eb099ae | 2696 | asarg = expr_parse_end; |
e23eba97 NC |
2697 | imm_expr->X_op = O_absent; |
2698 | continue; | |
5a9f5403 | 2699 | case '5': |
437e2ff1 | 2700 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2701 | || imm_expr->X_op != O_constant |
5a9f5403 | 2702 | || imm_expr->X_add_number < 0 |
169ec512 | 2703 | || imm_expr->X_add_number >= 32 |
5a9f5403 | 2704 | || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2705 | break; |
0257c2ff | 2706 | ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number); |
e23eba97 | 2707 | goto rvc_imm_done; |
5a9f5403 | 2708 | case '6': |
437e2ff1 | 2709 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d | 2710 | || imm_expr->X_op != O_constant |
0e35537d | 2711 | || imm_expr->X_add_number < 0 |
5a9f5403 NC |
2712 | || imm_expr->X_add_number >= 64 |
2713 | || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number)) | |
0e35537d | 2714 | break; |
0257c2ff | 2715 | ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number); |
0e35537d | 2716 | goto rvc_imm_done; |
5a9f5403 | 2717 | case '8': |
437e2ff1 | 2718 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2719 | || imm_expr->X_op != O_constant |
5a9f5403 NC |
2720 | || imm_expr->X_add_number < 0 |
2721 | || imm_expr->X_add_number >= 256 | |
2722 | || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number)) | |
e23eba97 | 2723 | break; |
0257c2ff | 2724 | ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2725 | goto rvc_imm_done; |
2726 | case 'j': | |
437e2ff1 | 2727 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 NC |
2728 | || imm_expr->X_op != O_constant |
2729 | || imm_expr->X_add_number == 0 | |
5a9f5403 | 2730 | || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2731 | break; |
5a9f5403 | 2732 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2733 | goto rvc_imm_done; |
2734 | case 'k': | |
437e2ff1 | 2735 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2736 | continue; |
437e2ff1 | 2737 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2738 | || imm_expr->X_op != O_constant |
5a9f5403 | 2739 | || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2740 | break; |
5a9f5403 | 2741 | ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2742 | goto rvc_imm_done; |
2743 | case 'l': | |
437e2ff1 | 2744 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2745 | continue; |
437e2ff1 | 2746 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2747 | || imm_expr->X_op != O_constant |
5a9f5403 | 2748 | || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2749 | break; |
5a9f5403 | 2750 | ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2751 | goto rvc_imm_done; |
2752 | case 'm': | |
437e2ff1 | 2753 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2754 | continue; |
437e2ff1 | 2755 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2756 | || imm_expr->X_op != O_constant |
5a9f5403 | 2757 | || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2758 | break; |
2759 | ip->insn_opcode |= | |
5a9f5403 | 2760 | ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2761 | goto rvc_imm_done; |
2762 | case 'n': | |
437e2ff1 | 2763 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2764 | continue; |
437e2ff1 | 2765 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2766 | || imm_expr->X_op != O_constant |
5a9f5403 | 2767 | || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2768 | break; |
2769 | ip->insn_opcode |= | |
5a9f5403 | 2770 | ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number); |
e23eba97 | 2771 | goto rvc_imm_done; |
b416fe87 | 2772 | case 'o': |
437e2ff1 | 2773 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
b416fe87 | 2774 | || imm_expr->X_op != O_constant |
21a186f2 JW |
2775 | /* C.addiw, c.li, and c.andi allow zero immediate. |
2776 | C.addi allows zero immediate as hint. Otherwise this | |
2777 | is same as 'j'. */ | |
5a9f5403 | 2778 | || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number)) |
b416fe87 | 2779 | break; |
5a9f5403 | 2780 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
b416fe87 | 2781 | goto rvc_imm_done; |
e23eba97 | 2782 | case 'K': |
437e2ff1 | 2783 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2784 | || imm_expr->X_op != O_constant |
169ec512 | 2785 | || imm_expr->X_add_number == 0 |
5a9f5403 | 2786 | || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2787 | break; |
2788 | ip->insn_opcode |= | |
5a9f5403 | 2789 | ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2790 | goto rvc_imm_done; |
2791 | case 'L': | |
437e2ff1 | 2792 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2793 | || imm_expr->X_op != O_constant |
5a9f5403 | 2794 | || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2795 | break; |
2796 | ip->insn_opcode |= | |
5a9f5403 | 2797 | ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2798 | goto rvc_imm_done; |
2799 | case 'M': | |
437e2ff1 | 2800 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2801 | continue; |
437e2ff1 | 2802 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2803 | || imm_expr->X_op != O_constant |
5a9f5403 | 2804 | || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2805 | break; |
2806 | ip->insn_opcode |= | |
5a9f5403 | 2807 | ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2808 | goto rvc_imm_done; |
2809 | case 'N': | |
437e2ff1 | 2810 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2811 | continue; |
437e2ff1 | 2812 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2813 | || imm_expr->X_op != O_constant |
5a9f5403 | 2814 | || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2815 | break; |
2816 | ip->insn_opcode |= | |
5a9f5403 | 2817 | ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2818 | goto rvc_imm_done; |
2819 | case 'u': | |
2820 | p = percent_op_utype; | |
437e2ff1 | 2821 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 | 2822 | break; |
dc1e8a47 | 2823 | rvc_lui: |
e23eba97 NC |
2824 | if (imm_expr->X_op != O_constant |
2825 | || imm_expr->X_add_number <= 0 | |
2826 | || imm_expr->X_add_number >= RISCV_BIGIMM_REACH | |
2827 | || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 | |
2828 | && (imm_expr->X_add_number < | |
2829 | RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) | |
2830 | break; | |
5a9f5403 | 2831 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2832 | goto rvc_imm_done; |
2833 | case 'v': | |
437e2ff1 | 2834 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 NC |
2835 | || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) |
2836 | || ((int32_t)imm_expr->X_add_number | |
2837 | != imm_expr->X_add_number)) | |
2838 | break; | |
2839 | imm_expr->X_add_number = | |
2840 | ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; | |
2841 | goto rvc_lui; | |
2842 | case 'p': | |
2843 | goto branch; | |
2844 | case 'a': | |
2845 | goto jump; | |
0e35537d | 2846 | case 'S': /* Floating-point RS1 x8-x15. */ |
437e2ff1 | 2847 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no) |
0e35537d JW |
2848 | || !(regno >= 8 && regno <= 15)) |
2849 | break; | |
2850 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
2851 | continue; | |
e23eba97 | 2852 | case 'D': /* Floating-point RS2 x8-x15. */ |
437e2ff1 | 2853 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no) |
e23eba97 NC |
2854 | || !(regno >= 8 && regno <= 15)) |
2855 | break; | |
2856 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
2857 | continue; | |
2858 | case 'T': /* Floating-point RS2. */ | |
437e2ff1 | 2859 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no)) |
e23eba97 NC |
2860 | break; |
2861 | INSERT_OPERAND (CRS2, *ip, regno); | |
2862 | continue; | |
0e35537d | 2863 | case 'F': |
437e2ff1 | 2864 | switch (*++oparg) |
0e35537d | 2865 | { |
4765cd61 | 2866 | case '6': |
437e2ff1 | 2867 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
4765cd61 JW |
2868 | || imm_expr->X_op != O_constant |
2869 | || imm_expr->X_add_number < 0 | |
2870 | || imm_expr->X_add_number >= 64) | |
2871 | { | |
b800637e | 2872 | as_bad (_("bad value for compressed funct6 " |
b215cdf5 | 2873 | "field, value must be 0...63")); |
4765cd61 JW |
2874 | break; |
2875 | } | |
4765cd61 JW |
2876 | INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number); |
2877 | imm_expr->X_op = O_absent; | |
6eb099ae | 2878 | asarg = expr_parse_end; |
4765cd61 | 2879 | continue; |
1942a048 | 2880 | |
0e35537d | 2881 | case '4': |
437e2ff1 | 2882 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
2883 | || imm_expr->X_op != O_constant |
2884 | || imm_expr->X_add_number < 0 | |
2885 | || imm_expr->X_add_number >= 16) | |
2886 | { | |
b800637e NC |
2887 | as_bad (_("bad value for compressed funct4 " |
2888 | "field, value must be 0...15")); | |
0e35537d JW |
2889 | break; |
2890 | } | |
0e35537d JW |
2891 | INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number); |
2892 | imm_expr->X_op = O_absent; | |
6eb099ae | 2893 | asarg = expr_parse_end; |
0e35537d | 2894 | continue; |
1942a048 | 2895 | |
0e35537d | 2896 | case '3': |
437e2ff1 | 2897 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
2898 | || imm_expr->X_op != O_constant |
2899 | || imm_expr->X_add_number < 0 | |
2900 | || imm_expr->X_add_number >= 8) | |
2901 | { | |
b800637e NC |
2902 | as_bad (_("bad value for compressed funct3 " |
2903 | "field, value must be 0...7")); | |
0e35537d JW |
2904 | break; |
2905 | } | |
2906 | INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number); | |
2907 | imm_expr->X_op = O_absent; | |
6eb099ae | 2908 | asarg = expr_parse_end; |
0e35537d | 2909 | continue; |
1942a048 | 2910 | |
4765cd61 | 2911 | case '2': |
437e2ff1 | 2912 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
4765cd61 JW |
2913 | || imm_expr->X_op != O_constant |
2914 | || imm_expr->X_add_number < 0 | |
2915 | || imm_expr->X_add_number >= 4) | |
2916 | { | |
b800637e NC |
2917 | as_bad (_("bad value for compressed funct2 " |
2918 | "field, value must be 0...3")); | |
4765cd61 JW |
2919 | break; |
2920 | } | |
2921 | INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number); | |
2922 | imm_expr->X_op = O_absent; | |
6eb099ae | 2923 | asarg = expr_parse_end; |
4765cd61 | 2924 | continue; |
1942a048 | 2925 | |
0e35537d | 2926 | default: |
437e2ff1 | 2927 | goto unknown_riscv_ip_operand; |
0e35537d JW |
2928 | } |
2929 | break; | |
2930 | ||
e23eba97 | 2931 | default: |
437e2ff1 | 2932 | goto unknown_riscv_ip_operand; |
e23eba97 | 2933 | } |
a63375ac | 2934 | break; /* end RVC */ |
e23eba97 | 2935 | |
65e4a99a NC |
2936 | case 'V': /* RVV */ |
2937 | switch (*++oparg) | |
2938 | { | |
2939 | case 'd': /* VD */ | |
2940 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2941 | break; | |
2942 | INSERT_OPERAND (VD, *ip, regno); | |
2943 | continue; | |
2944 | ||
2945 | case 'e': /* AMO VD */ | |
2946 | if (reg_lookup (&asarg, RCLASS_GPR, ®no) && regno == 0) | |
2947 | INSERT_OPERAND (VWD, *ip, 0); | |
2948 | else if (reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2949 | { | |
2950 | INSERT_OPERAND (VWD, *ip, 1); | |
2951 | INSERT_OPERAND (VD, *ip, regno); | |
2952 | } | |
2953 | else | |
2954 | break; | |
2955 | continue; | |
2956 | ||
2957 | case 'f': /* AMO VS3 */ | |
2958 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2959 | break; | |
2960 | if (!EXTRACT_OPERAND (VWD, ip->insn_opcode)) | |
2961 | INSERT_OPERAND (VD, *ip, regno); | |
2962 | else | |
2963 | { | |
2964 | /* VS3 must match VD. */ | |
2965 | if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno) | |
2966 | break; | |
2967 | } | |
2968 | continue; | |
2969 | ||
2970 | case 's': /* VS1 */ | |
2971 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2972 | break; | |
2973 | INSERT_OPERAND (VS1, *ip, regno); | |
2974 | continue; | |
2975 | ||
2976 | case 't': /* VS2 */ | |
2977 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2978 | break; | |
2979 | INSERT_OPERAND (VS2, *ip, regno); | |
2980 | continue; | |
2981 | ||
2982 | case 'u': /* VS1 == VS2 */ | |
2983 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2984 | break; | |
2985 | INSERT_OPERAND (VS1, *ip, regno); | |
2986 | INSERT_OPERAND (VS2, *ip, regno); | |
2987 | continue; | |
2988 | ||
2989 | case 'v': /* VD == VS1 == VS2 */ | |
2990 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2991 | break; | |
2992 | INSERT_OPERAND (VD, *ip, regno); | |
2993 | INSERT_OPERAND (VS1, *ip, regno); | |
2994 | INSERT_OPERAND (VS2, *ip, regno); | |
2995 | continue; | |
2996 | ||
2997 | /* The `V0` is carry-in register for v[m]adc and v[m]sbc, | |
2998 | and is used to choose vs1/rs1/frs1/imm or vs2 for | |
2999 | v[f]merge. It use the same encoding as the vector mask | |
3000 | register. */ | |
3001 | case '0': | |
3002 | if (reg_lookup (&asarg, RCLASS_VECR, ®no) && regno == 0) | |
3003 | continue; | |
3004 | break; | |
3005 | ||
3006 | case 'b': /* vtypei for vsetivli */ | |
3007 | my_getVsetvliExpression (imm_expr, asarg); | |
3008 | check_absolute_expr (ip, imm_expr, FALSE); | |
3009 | if (!VALID_RVV_VB_IMM (imm_expr->X_add_number)) | |
3010 | as_bad (_("bad value for vsetivli immediate field, " | |
3011 | "value must be 0..1023")); | |
3012 | ip->insn_opcode | |
3013 | |= ENCODE_RVV_VB_IMM (imm_expr->X_add_number); | |
3014 | imm_expr->X_op = O_absent; | |
6eb099ae | 3015 | asarg = expr_parse_end; |
65e4a99a NC |
3016 | continue; |
3017 | ||
3018 | case 'c': /* vtypei for vsetvli */ | |
3019 | my_getVsetvliExpression (imm_expr, asarg); | |
3020 | check_absolute_expr (ip, imm_expr, FALSE); | |
3021 | if (!VALID_RVV_VC_IMM (imm_expr->X_add_number)) | |
3022 | as_bad (_("bad value for vsetvli immediate field, " | |
3023 | "value must be 0..2047")); | |
3024 | ip->insn_opcode | |
3025 | |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number); | |
3026 | imm_expr->X_op = O_absent; | |
6eb099ae | 3027 | asarg = expr_parse_end; |
65e4a99a NC |
3028 | continue; |
3029 | ||
3030 | case 'i': /* vector arith signed immediate */ | |
3031 | my_getExpression (imm_expr, asarg); | |
3032 | check_absolute_expr (ip, imm_expr, FALSE); | |
3033 | if (imm_expr->X_add_number > 15 | |
3034 | || imm_expr->X_add_number < -16) | |
3035 | as_bad (_("bad value for vector immediate field, " | |
3036 | "value must be -16...15")); | |
3037 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number); | |
3038 | imm_expr->X_op = O_absent; | |
6eb099ae | 3039 | asarg = expr_parse_end; |
65e4a99a NC |
3040 | continue; |
3041 | ||
3042 | case 'j': /* vector arith unsigned immediate */ | |
3043 | my_getExpression (imm_expr, asarg); | |
3044 | check_absolute_expr (ip, imm_expr, FALSE); | |
3045 | if (imm_expr->X_add_number < 0 | |
3046 | || imm_expr->X_add_number >= 32) | |
3047 | as_bad (_("bad value for vector immediate field, " | |
3048 | "value must be 0...31")); | |
3049 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number); | |
3050 | imm_expr->X_op = O_absent; | |
6eb099ae | 3051 | asarg = expr_parse_end; |
65e4a99a NC |
3052 | continue; |
3053 | ||
3054 | case 'k': /* vector arith signed immediate, minus 1 */ | |
3055 | my_getExpression (imm_expr, asarg); | |
3056 | check_absolute_expr (ip, imm_expr, FALSE); | |
3057 | if (imm_expr->X_add_number > 16 | |
3058 | || imm_expr->X_add_number < -15) | |
3059 | as_bad (_("bad value for vector immediate field, " | |
3060 | "value must be -15...16")); | |
3061 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1); | |
3062 | imm_expr->X_op = O_absent; | |
6eb099ae | 3063 | asarg = expr_parse_end; |
65e4a99a NC |
3064 | continue; |
3065 | ||
c8cb3734 CM |
3066 | case 'l': /* 6-bit vector arith unsigned immediate */ |
3067 | my_getExpression (imm_expr, asarg); | |
3068 | check_absolute_expr (ip, imm_expr, FALSE); | |
3069 | if (imm_expr->X_add_number < 0 | |
3070 | || imm_expr->X_add_number >= 64) | |
3071 | as_bad (_("bad value for vector immediate field, " | |
3072 | "value must be 0...63")); | |
3073 | ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 (imm_expr->X_add_number); | |
3074 | imm_expr->X_op = O_absent; | |
3075 | asarg = expr_parse_end; | |
3076 | continue; | |
3077 | ||
65e4a99a NC |
3078 | case 'm': /* optional vector mask */ |
3079 | if (*asarg == '\0') | |
3080 | { | |
3081 | INSERT_OPERAND (VMASK, *ip, 1); | |
3082 | continue; | |
3083 | } | |
3084 | else if (*asarg == ',' && asarg++ | |
3085 | && reg_lookup (&asarg, RCLASS_VECM, ®no) | |
3086 | && regno == 0) | |
3087 | { | |
3088 | INSERT_OPERAND (VMASK, *ip, 0); | |
3089 | continue; | |
3090 | } | |
3091 | break; | |
3092 | ||
3093 | case 'M': /* required vector mask */ | |
3094 | if (reg_lookup (&asarg, RCLASS_VECM, ®no) && regno == 0) | |
3095 | { | |
3096 | INSERT_OPERAND (VMASK, *ip, 0); | |
3097 | continue; | |
3098 | } | |
3099 | break; | |
3100 | ||
3101 | case 'T': /* vector macro temporary register */ | |
3102 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no) || regno == 0) | |
3103 | break; | |
3104 | /* Store it in the FUNCT6 field as we don't have anyplace | |
3105 | else to store it. */ | |
3106 | INSERT_OPERAND (VFUNCT6, *ip, regno); | |
3107 | continue; | |
3108 | ||
3109 | default: | |
3110 | goto unknown_riscv_ip_operand; | |
3111 | } | |
a63375ac | 3112 | break; /* end RVV */ |
65e4a99a | 3113 | |
e23eba97 | 3114 | case ',': |
437e2ff1 | 3115 | if (*asarg++ == *oparg) |
e23eba97 | 3116 | continue; |
437e2ff1 | 3117 | asarg--; |
e23eba97 NC |
3118 | break; |
3119 | ||
3120 | case '(': | |
3121 | case ')': | |
3122 | case '[': | |
3123 | case ']': | |
437e2ff1 | 3124 | if (*asarg++ == *oparg) |
e23eba97 NC |
3125 | continue; |
3126 | break; | |
3127 | ||
dcd709e0 | 3128 | case '<': /* Shift amount, 0 - 31. */ |
437e2ff1 | 3129 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3130 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3131 | if ((unsigned long) imm_expr->X_add_number > 31) |
a6eeb20a CM |
3132 | as_bad (_("improper shift amount (%"PRIu64")"), |
3133 | imm_expr->X_add_number); | |
e23eba97 NC |
3134 | INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); |
3135 | imm_expr->X_op = O_absent; | |
6eb099ae | 3136 | asarg = expr_parse_end; |
e23eba97 NC |
3137 | continue; |
3138 | ||
dcd709e0 | 3139 | case '>': /* Shift amount, 0 - (XLEN-1). */ |
437e2ff1 | 3140 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3141 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3142 | if ((unsigned long) imm_expr->X_add_number >= xlen) |
a6eeb20a CM |
3143 | as_bad (_("improper shift amount (%"PRIu64")"), |
3144 | imm_expr->X_add_number); | |
e23eba97 NC |
3145 | INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); |
3146 | imm_expr->X_op = O_absent; | |
6eb099ae | 3147 | asarg = expr_parse_end; |
e23eba97 NC |
3148 | continue; |
3149 | ||
dcd709e0 | 3150 | case 'Z': /* CSRRxI immediate. */ |
437e2ff1 | 3151 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3152 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3153 | if ((unsigned long) imm_expr->X_add_number > 31) |
a6eeb20a CM |
3154 | as_bad (_("improper CSRxI immediate (%"PRIu64")"), |
3155 | imm_expr->X_add_number); | |
e23eba97 NC |
3156 | INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); |
3157 | imm_expr->X_op = O_absent; | |
6eb099ae | 3158 | asarg = expr_parse_end; |
e23eba97 NC |
3159 | continue; |
3160 | ||
dcd709e0 | 3161 | case 'E': /* Control register. */ |
5b7c81bd AM |
3162 | insn_with_csr = true; |
3163 | explicit_priv_attr = true; | |
437e2ff1 | 3164 | if (reg_lookup (&asarg, RCLASS_CSR, ®no)) |
e23eba97 NC |
3165 | INSERT_OPERAND (CSR, *ip, regno); |
3166 | else | |
3167 | { | |
437e2ff1 | 3168 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3169 | check_absolute_expr (ip, imm_expr, true); |
e23eba97 | 3170 | if ((unsigned long) imm_expr->X_add_number > 0xfff) |
a6eeb20a CM |
3171 | as_bad (_("improper CSR address (%"PRIu64")"), |
3172 | imm_expr->X_add_number); | |
e23eba97 NC |
3173 | INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); |
3174 | imm_expr->X_op = O_absent; | |
6eb099ae | 3175 | asarg = expr_parse_end; |
e23eba97 NC |
3176 | } |
3177 | continue; | |
3178 | ||
dcd709e0 | 3179 | case 'm': /* Rounding mode. */ |
437e2ff1 NC |
3180 | if (arg_lookup (&asarg, riscv_rm, |
3181 | ARRAY_SIZE (riscv_rm), ®no)) | |
e23eba97 NC |
3182 | { |
3183 | INSERT_OPERAND (RM, *ip, regno); | |
3184 | continue; | |
3185 | } | |
3186 | break; | |
3187 | ||
3188 | case 'P': | |
dcd709e0 | 3189 | case 'Q': /* Fence predecessor/successor. */ |
437e2ff1 NC |
3190 | if (arg_lookup (&asarg, riscv_pred_succ, |
3191 | ARRAY_SIZE (riscv_pred_succ), ®no)) | |
e23eba97 | 3192 | { |
437e2ff1 | 3193 | if (*oparg == 'P') |
e23eba97 NC |
3194 | INSERT_OPERAND (PRED, *ip, regno); |
3195 | else | |
3196 | INSERT_OPERAND (SUCC, *ip, regno); | |
3197 | continue; | |
3198 | } | |
3199 | break; | |
3200 | ||
dcd709e0 NC |
3201 | case 'd': /* Destination register. */ |
3202 | case 's': /* Source register. */ | |
3203 | case 't': /* Target register. */ | |
3204 | case 'r': /* RS3 */ | |
437e2ff1 | 3205 | if (reg_lookup (&asarg, RCLASS_GPR, ®no)) |
e23eba97 | 3206 | { |
437e2ff1 NC |
3207 | char c = *oparg; |
3208 | if (*asarg == ' ') | |
3209 | ++asarg; | |
e23eba97 NC |
3210 | |
3211 | /* Now that we have assembled one operand, we use the args | |
3212 | string to figure out where it goes in the instruction. */ | |
3213 | switch (c) | |
3214 | { | |
3215 | case 's': | |
3216 | INSERT_OPERAND (RS1, *ip, regno); | |
3217 | break; | |
3218 | case 'd': | |
3219 | INSERT_OPERAND (RD, *ip, regno); | |
3220 | break; | |
3221 | case 't': | |
3222 | INSERT_OPERAND (RS2, *ip, regno); | |
3223 | break; | |
0e35537d JW |
3224 | case 'r': |
3225 | INSERT_OPERAND (RS3, *ip, regno); | |
3226 | break; | |
e23eba97 NC |
3227 | } |
3228 | continue; | |
3229 | } | |
3230 | break; | |
3231 | ||
dcd709e0 NC |
3232 | case 'D': /* Floating point RD. */ |
3233 | case 'S': /* Floating point RS1. */ | |
3234 | case 'T': /* Floating point RS2. */ | |
3235 | case 'U': /* Floating point RS1 and RS2. */ | |
3236 | case 'R': /* Floating point RS3. */ | |
de83e514 | 3237 | if (reg_lookup (&asarg, |
3238 | (riscv_subset_supports (&riscv_rps_as, "zfinx") | |
3239 | ? RCLASS_GPR : RCLASS_FPR), ®no)) | |
e23eba97 | 3240 | { |
437e2ff1 NC |
3241 | char c = *oparg; |
3242 | if (*asarg == ' ') | |
3243 | ++asarg; | |
e23eba97 NC |
3244 | switch (c) |
3245 | { | |
3246 | case 'D': | |
3247 | INSERT_OPERAND (RD, *ip, regno); | |
3248 | break; | |
3249 | case 'S': | |
3250 | INSERT_OPERAND (RS1, *ip, regno); | |
3251 | break; | |
3252 | case 'U': | |
3253 | INSERT_OPERAND (RS1, *ip, regno); | |
dcd709e0 | 3254 | /* Fall through. */ |
e23eba97 NC |
3255 | case 'T': |
3256 | INSERT_OPERAND (RS2, *ip, regno); | |
3257 | break; | |
3258 | case 'R': | |
3259 | INSERT_OPERAND (RS3, *ip, regno); | |
3260 | break; | |
3261 | } | |
3262 | continue; | |
3263 | } | |
e23eba97 NC |
3264 | break; |
3265 | ||
3266 | case 'I': | |
437e2ff1 | 3267 | my_getExpression (imm_expr, asarg); |
e23eba97 NC |
3268 | if (imm_expr->X_op != O_big |
3269 | && imm_expr->X_op != O_constant) | |
3270 | break; | |
3271 | normalize_constant_expr (imm_expr); | |
6eb099ae | 3272 | asarg = expr_parse_end; |
e23eba97 NC |
3273 | continue; |
3274 | ||
3275 | case 'A': | |
437e2ff1 | 3276 | my_getExpression (imm_expr, asarg); |
e23eba97 NC |
3277 | normalize_constant_expr (imm_expr); |
3278 | /* The 'A' format specifier must be a symbol. */ | |
3279 | if (imm_expr->X_op != O_symbol) | |
3280 | break; | |
3281 | *imm_reloc = BFD_RELOC_32; | |
6eb099ae | 3282 | asarg = expr_parse_end; |
e23eba97 NC |
3283 | continue; |
3284 | ||
160d1b3d | 3285 | case 'B': |
437e2ff1 | 3286 | my_getExpression (imm_expr, asarg); |
160d1b3d SH |
3287 | normalize_constant_expr (imm_expr); |
3288 | /* The 'B' format specifier must be a symbol or a constant. */ | |
3289 | if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant) | |
3290 | break; | |
3291 | if (imm_expr->X_op == O_symbol) | |
3292 | *imm_reloc = BFD_RELOC_32; | |
6eb099ae | 3293 | asarg = expr_parse_end; |
160d1b3d SH |
3294 | continue; |
3295 | ||
e23eba97 | 3296 | case 'j': /* Sign-extended immediate. */ |
e23eba97 | 3297 | p = percent_op_itype; |
f50fabe4 | 3298 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; |
e23eba97 NC |
3299 | goto alu_op; |
3300 | case 'q': /* Store displacement. */ | |
3301 | p = percent_op_stype; | |
3302 | *imm_reloc = BFD_RELOC_RISCV_LO12_S; | |
3303 | goto load_store; | |
3304 | case 'o': /* Load displacement. */ | |
3305 | p = percent_op_itype; | |
3306 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
3307 | goto load_store; | |
dcd709e0 NC |
3308 | case '1': |
3309 | /* This is used for TLS, where the fourth operand is | |
3310 | %tprel_add, to get a relocation applied to an add | |
3311 | instruction, for relaxation to use. */ | |
e23eba97 | 3312 | p = percent_op_rtype; |
f50fabe4 | 3313 | goto alu_op; |
dcd709e0 | 3314 | case '0': /* AMO displacement, which must be zero. */ |
dc1e8a47 | 3315 | load_store: |
437e2ff1 | 3316 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
e23eba97 | 3317 | continue; |
dc1e8a47 | 3318 | alu_op: |
e23eba97 NC |
3319 | /* If this value won't fit into a 16 bit offset, then go |
3320 | find a macro that will generate the 32 bit offset | |
3321 | code pattern. */ | |
437e2ff1 | 3322 | if (!my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 NC |
3323 | { |
3324 | normalize_constant_expr (imm_expr); | |
3325 | if (imm_expr->X_op != O_constant | |
437e2ff1 NC |
3326 | || (*oparg == '0' && imm_expr->X_add_number != 0) |
3327 | || (*oparg == '1') | |
e23eba97 NC |
3328 | || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 |
3329 | || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) | |
3330 | break; | |
3331 | } | |
6eb099ae | 3332 | asarg = expr_parse_end; |
e23eba97 NC |
3333 | continue; |
3334 | ||
dcd709e0 | 3335 | case 'p': /* PC-relative offset. */ |
dc1e8a47 | 3336 | branch: |
e23eba97 | 3337 | *imm_reloc = BFD_RELOC_12_PCREL; |
437e2ff1 | 3338 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3339 | asarg = expr_parse_end; |
e23eba97 NC |
3340 | continue; |
3341 | ||
dcd709e0 | 3342 | case 'u': /* Upper 20 bits. */ |
e23eba97 | 3343 | p = percent_op_utype; |
437e2ff1 | 3344 | if (!my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 | 3345 | { |
4288405d JW |
3346 | if (imm_expr->X_op != O_constant) |
3347 | break; | |
3348 | ||
e23eba97 NC |
3349 | if (imm_expr->X_add_number < 0 |
3350 | || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) | |
3351 | as_bad (_("lui expression not in range 0..1048575")); | |
3352 | ||
3353 | *imm_reloc = BFD_RELOC_RISCV_HI20; | |
3354 | imm_expr->X_add_number <<= RISCV_IMM_BITS; | |
3355 | } | |
6eb099ae | 3356 | asarg = expr_parse_end; |
e23eba97 NC |
3357 | continue; |
3358 | ||
dcd709e0 | 3359 | case 'a': /* 20-bit PC-relative offset. */ |
dc1e8a47 | 3360 | jump: |
437e2ff1 | 3361 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3362 | asarg = expr_parse_end; |
e23eba97 NC |
3363 | *imm_reloc = BFD_RELOC_RISCV_JMP; |
3364 | continue; | |
3365 | ||
3366 | case 'c': | |
437e2ff1 | 3367 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3368 | asarg = expr_parse_end; |
437e2ff1 | 3369 | if (strcmp (asarg, "@plt") == 0) |
70f35d72 NC |
3370 | asarg += 4; |
3371 | *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; | |
e23eba97 | 3372 | continue; |
1942a048 | 3373 | |
0e35537d | 3374 | case 'O': |
437e2ff1 | 3375 | switch (*++oparg) |
0e35537d JW |
3376 | { |
3377 | case '4': | |
408ab016 | 3378 | if (my_getOpcodeExpression (imm_expr, imm_reloc, asarg) |
0e35537d JW |
3379 | || imm_expr->X_op != O_constant |
3380 | || imm_expr->X_add_number < 0 | |
3381 | || imm_expr->X_add_number >= 128 | |
3382 | || (imm_expr->X_add_number & 0x3) != 3) | |
3383 | { | |
3384 | as_bad (_("bad value for opcode field, " | |
3385 | "value must be 0...127 and " | |
3386 | "lower 2 bits must be 0x3")); | |
3387 | break; | |
3388 | } | |
0e35537d JW |
3389 | INSERT_OPERAND (OP, *ip, imm_expr->X_add_number); |
3390 | imm_expr->X_op = O_absent; | |
6eb099ae | 3391 | asarg = expr_parse_end; |
0e35537d | 3392 | continue; |
1942a048 | 3393 | |
0e35537d | 3394 | case '2': |
408ab016 | 3395 | if (my_getOpcodeExpression (imm_expr, imm_reloc, asarg) |
0e35537d JW |
3396 | || imm_expr->X_op != O_constant |
3397 | || imm_expr->X_add_number < 0 | |
3398 | || imm_expr->X_add_number >= 3) | |
3399 | { | |
3400 | as_bad (_("bad value for opcode field, " | |
3401 | "value must be 0...2")); | |
3402 | break; | |
3403 | } | |
0e35537d JW |
3404 | INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number); |
3405 | imm_expr->X_op = O_absent; | |
6eb099ae | 3406 | asarg = expr_parse_end; |
0e35537d | 3407 | continue; |
1942a048 | 3408 | |
0e35537d | 3409 | default: |
437e2ff1 | 3410 | goto unknown_riscv_ip_operand; |
0e35537d JW |
3411 | } |
3412 | break; | |
3413 | ||
3414 | case 'F': | |
437e2ff1 | 3415 | switch (*++oparg) |
0e35537d JW |
3416 | { |
3417 | case '7': | |
437e2ff1 | 3418 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3419 | || imm_expr->X_op != O_constant |
3420 | || imm_expr->X_add_number < 0 | |
3421 | || imm_expr->X_add_number >= 128) | |
3422 | { | |
3423 | as_bad (_("bad value for funct7 field, " | |
3424 | "value must be 0...127")); | |
3425 | break; | |
3426 | } | |
0e35537d JW |
3427 | INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); |
3428 | imm_expr->X_op = O_absent; | |
6eb099ae | 3429 | asarg = expr_parse_end; |
0e35537d | 3430 | continue; |
1942a048 | 3431 | |
0e35537d | 3432 | case '3': |
437e2ff1 | 3433 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3434 | || imm_expr->X_op != O_constant |
3435 | || imm_expr->X_add_number < 0 | |
3436 | || imm_expr->X_add_number >= 8) | |
3437 | { | |
3438 | as_bad (_("bad value for funct3 field, " | |
3439 | "value must be 0...7")); | |
3440 | break; | |
3441 | } | |
0e35537d JW |
3442 | INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); |
3443 | imm_expr->X_op = O_absent; | |
6eb099ae | 3444 | asarg = expr_parse_end; |
0e35537d | 3445 | continue; |
1942a048 | 3446 | |
0e35537d | 3447 | case '2': |
437e2ff1 | 3448 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3449 | || imm_expr->X_op != O_constant |
3450 | || imm_expr->X_add_number < 0 | |
3451 | || imm_expr->X_add_number >= 4) | |
3452 | { | |
3453 | as_bad (_("bad value for funct2 field, " | |
3454 | "value must be 0...3")); | |
3455 | break; | |
3456 | } | |
0e35537d JW |
3457 | INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number); |
3458 | imm_expr->X_op = O_absent; | |
6eb099ae | 3459 | asarg = expr_parse_end; |
0e35537d JW |
3460 | continue; |
3461 | ||
3462 | default: | |
437e2ff1 | 3463 | goto unknown_riscv_ip_operand; |
0e35537d JW |
3464 | } |
3465 | break; | |
e23eba97 | 3466 | |
3d1cafa0 | 3467 | case 'y': /* bs immediate */ |
3468 | my_getExpression (imm_expr, asarg); | |
3469 | check_absolute_expr (ip, imm_expr, FALSE); | |
3470 | if ((unsigned long)imm_expr->X_add_number > 3) | |
3471 | as_bad(_("Improper bs immediate (%lu)"), | |
3472 | (unsigned long)imm_expr->X_add_number); | |
3473 | INSERT_OPERAND(BS, *ip, imm_expr->X_add_number); | |
3474 | imm_expr->X_op = O_absent; | |
6eb099ae | 3475 | asarg = expr_parse_end; |
3d1cafa0 | 3476 | continue; |
3477 | ||
3478 | case 'Y': /* rnum immediate */ | |
3479 | my_getExpression (imm_expr, asarg); | |
3480 | check_absolute_expr (ip, imm_expr, FALSE); | |
3481 | if ((unsigned long)imm_expr->X_add_number > 10) | |
3482 | as_bad(_("Improper rnum immediate (%lu)"), | |
3483 | (unsigned long)imm_expr->X_add_number); | |
3484 | INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number); | |
3485 | imm_expr->X_op = O_absent; | |
6eb099ae | 3486 | asarg = expr_parse_end; |
3d1cafa0 | 3487 | continue; |
3488 | ||
e925c834 | 3489 | case 'z': |
437e2ff1 | 3490 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e925c834 JW |
3491 | || imm_expr->X_op != O_constant |
3492 | || imm_expr->X_add_number != 0) | |
3493 | break; | |
6eb099ae | 3494 | asarg = expr_parse_end; |
e925c834 JW |
3495 | imm_expr->X_op = O_absent; |
3496 | continue; | |
3497 | ||
6de11ff6 | 3498 | case 'W': /* Various operands for standard z extensions. */ |
54bca63b TO |
3499 | switch (*++oparg) |
3500 | { | |
3501 | case 'i': | |
3502 | switch (*++oparg) | |
3503 | { | |
3504 | case 'f': | |
3505 | /* Prefetch offset for 'Zicbop' extension. | |
3506 | pseudo S-type but lower 5-bits zero. */ | |
3507 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) | |
3508 | continue; | |
3509 | my_getExpression (imm_expr, asarg); | |
3510 | check_absolute_expr (ip, imm_expr, false); | |
3511 | if (((unsigned) (imm_expr->X_add_number) & 0x1fU) | |
3512 | || imm_expr->X_add_number >= RISCV_IMM_REACH / 2 | |
3513 | || imm_expr->X_add_number < -RISCV_IMM_REACH / 2) | |
3514 | as_bad (_ ("improper prefetch offset (%ld)"), | |
3515 | (long) imm_expr->X_add_number); | |
3516 | ip->insn_opcode |= ENCODE_STYPE_IMM ( | |
3517 | (unsigned) (imm_expr->X_add_number) & ~0x1fU); | |
3518 | imm_expr->X_op = O_absent; | |
3519 | asarg = expr_parse_end; | |
3520 | continue; | |
3521 | default: | |
3522 | goto unknown_riscv_ip_operand; | |
3523 | } | |
3524 | break; | |
6de11ff6 | 3525 | |
1f3fc45b CM |
3526 | case 'f': |
3527 | switch (*++oparg) | |
3528 | { | |
3529 | case 'v': | |
3530 | /* FLI.[HSDQ] value field for 'Zfa' extension. */ | |
3531 | if (!arg_lookup (&asarg, riscv_fli_symval, | |
3532 | ARRAY_SIZE (riscv_fli_symval), ®no)) | |
3533 | { | |
3534 | /* 0.0 is not a valid entry in riscv_fli_numval. */ | |
3535 | errno = 0; | |
3536 | float f = strtof (asarg, &asarg); | |
3537 | if (errno != 0 || f == 0.0 | |
3538 | || !flt_lookup (f, riscv_fli_numval, | |
3539 | ARRAY_SIZE(riscv_fli_numval), | |
3540 | ®no)) | |
3541 | { | |
3542 | as_bad (_("bad fli constant operand, " | |
3543 | "supported constants must be in " | |
3544 | "decimal or hexadecimal floating-point " | |
3545 | "literal form")); | |
3546 | break; | |
3547 | } | |
3548 | } | |
3549 | INSERT_OPERAND (RS1, *ip, regno); | |
3550 | continue; | |
3551 | default: | |
3552 | goto unknown_riscv_ip_operand; | |
3553 | } | |
3554 | break; | |
b5c37946 SJ |
3555 | |
3556 | case 'c': | |
3557 | switch (*++oparg) | |
3558 | { | |
3559 | case 'h': /* Immediate field for c.lh/c.lhu/c.sh. */ | |
3560 | /* Handle cases, such as c.sh rs2', (rs1'). */ | |
3561 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) | |
3562 | continue; | |
3563 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) | |
3564 | || imm_expr->X_op != O_constant | |
3565 | || !VALID_ZCB_HALFWORD_UIMM ((valueT) imm_expr->X_add_number)) | |
3566 | break; | |
3567 | ip->insn_opcode |= ENCODE_ZCB_HALFWORD_UIMM (imm_expr->X_add_number); | |
3568 | goto rvc_imm_done; | |
b5c37946 SJ |
3569 | case 'b': /* Immediate field for c.lbu/c.sb. */ |
3570 | /* Handle cases, such as c.lbu rd', (rs1'). */ | |
3571 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) | |
3572 | continue; | |
3573 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) | |
3574 | || imm_expr->X_op != O_constant | |
3575 | || !VALID_ZCB_BYTE_UIMM ((valueT) imm_expr->X_add_number)) | |
3576 | break; | |
3577 | ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number); | |
3578 | goto rvc_imm_done; | |
b5c37946 SJ |
3579 | case 'f': /* Operand for matching immediate 255. */ |
3580 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) | |
3581 | || imm_expr->X_op != O_constant | |
3582 | || imm_expr->X_add_number != 255) | |
3583 | break; | |
3584 | /* This operand is used for matching immediate 255, and | |
3585 | we do not write anything to encoding by this operand. */ | |
3586 | asarg = expr_parse_end; | |
3587 | imm_expr->X_op = O_absent; | |
3588 | continue; | |
b5c37946 SJ |
3589 | default: |
3590 | goto unknown_riscv_ip_operand; | |
3591 | } | |
3592 | break; | |
6de11ff6 | 3593 | |
54bca63b TO |
3594 | default: |
3595 | goto unknown_riscv_ip_operand; | |
3596 | } | |
3597 | break; | |
3b374308 | 3598 | |
6de11ff6 NC |
3599 | case 'X': /* Vendor-specific operands. */ |
3600 | switch (*++oparg) | |
3601 | { | |
3602 | case 't': /* Vendor-specific (T-head) operands. */ | |
8b7419c4 | 3603 | { |
6de11ff6 NC |
3604 | size_t n; |
3605 | size_t s; | |
3606 | bool sign; | |
3607 | switch (*++oparg) | |
3608 | { | |
3609 | case 'l': /* Integer immediate, literal. */ | |
3610 | n = strcspn (++oparg, ","); | |
3611 | if (strncmp (oparg, asarg, n)) | |
3612 | as_bad (_("unexpected literal (%s)"), asarg); | |
3613 | oparg += n - 1; | |
3614 | asarg += n; | |
3615 | continue; | |
3616 | case 's': /* Integer immediate, 'XsN@S' ... N-bit signed immediate at bit S. */ | |
3617 | sign = true; | |
3618 | goto parse_imm; | |
3619 | case 'u': /* Integer immediate, 'XuN@S' ... N-bit unsigned immediate at bit S. */ | |
3620 | sign = false; | |
3621 | goto parse_imm; | |
3622 | parse_imm: | |
3623 | n = strtol (oparg + 1, (char **)&oparg, 10); | |
3624 | if (*oparg != '@') | |
3625 | goto unknown_riscv_ip_operand; | |
3626 | s = strtol (oparg + 1, (char **)&oparg, 10); | |
3627 | oparg--; | |
3628 | ||
3629 | my_getExpression (imm_expr, asarg); | |
3630 | check_absolute_expr (ip, imm_expr, false); | |
3631 | if (!sign) | |
3632 | { | |
3633 | if (!VALIDATE_U_IMM (imm_expr->X_add_number, n)) | |
3634 | as_bad (_("improper immediate value (%"PRIu64")"), | |
3635 | imm_expr->X_add_number); | |
3636 | } | |
3637 | else | |
3638 | { | |
3639 | if (!VALIDATE_S_IMM (imm_expr->X_add_number, n)) | |
3640 | as_bad (_("improper immediate value (%"PRIi64")"), | |
3641 | imm_expr->X_add_number); | |
3642 | } | |
3643 | INSERT_IMM (n, s, *ip, imm_expr->X_add_number); | |
3644 | imm_expr->X_op = O_absent; | |
3645 | asarg = expr_parse_end; | |
3646 | continue; | |
3647 | default: | |
8b7419c4 | 3648 | goto unknown_riscv_ip_operand; |
6de11ff6 | 3649 | } |
8b7419c4 | 3650 | } |
6de11ff6 NC |
3651 | break; |
3652 | ||
3653 | default: | |
3654 | goto unknown_riscv_ip_operand; | |
3655 | } | |
8b7419c4 | 3656 | break; |
54bca63b | 3657 | |
e23eba97 | 3658 | default: |
437e2ff1 NC |
3659 | unknown_riscv_ip_operand: |
3660 | as_fatal (_("internal: unknown argument type `%s'"), | |
3661 | opargStart); | |
e23eba97 NC |
3662 | } |
3663 | break; | |
3664 | } | |
437e2ff1 | 3665 | asarg = asargStart; |
5b7c81bd | 3666 | insn_with_csr = false; |
e23eba97 NC |
3667 | } |
3668 | ||
dc1e8a47 | 3669 | out: |
e23eba97 NC |
3670 | /* Restore the character we might have clobbered above. */ |
3671 | if (save_c) | |
437e2ff1 | 3672 | *(asargStart - 1) = save_c; |
e23eba97 | 3673 | |
7a29ee29 JB |
3674 | probing_insn_operands = false; |
3675 | ||
e23eba97 NC |
3676 | return error; |
3677 | } | |
3678 | ||
a262b82f NC |
3679 | /* Similar to riscv_ip, but assembles an instruction according to the |
3680 | hardcode values of .insn directive. */ | |
3681 | ||
3682 | static const char * | |
3683 | riscv_ip_hardcode (char *str, | |
3684 | struct riscv_cl_insn *ip, | |
3685 | expressionS *imm_expr, | |
3686 | const char *error) | |
3687 | { | |
3688 | struct riscv_opcode *insn; | |
3689 | insn_t values[2] = {0, 0}; | |
3690 | unsigned int num = 0; | |
3691 | ||
3692 | input_line_pointer = str; | |
3693 | do | |
3694 | { | |
3695 | expression (imm_expr); | |
bb996692 | 3696 | switch (imm_expr->X_op) |
a262b82f | 3697 | { |
bb996692 JB |
3698 | case O_constant: |
3699 | values[num++] = (insn_t) imm_expr->X_add_number; | |
3700 | break; | |
3701 | case O_big: | |
634001bb TO |
3702 | /* Extract lower 32-bits of a big number. |
3703 | Assume that generic_bignum_to_int32 work on such number. */ | |
3704 | values[num++] = (insn_t) generic_bignum_to_int32 (); | |
bb996692 JB |
3705 | break; |
3706 | default: | |
a262b82f NC |
3707 | /* The first value isn't constant, so it should be |
3708 | .insn <type> <operands>. We have been parsed it | |
3709 | in the riscv_ip. */ | |
3710 | if (num == 0) | |
3711 | return error; | |
3712 | return _("values must be constant"); | |
3713 | } | |
a262b82f | 3714 | } |
bb996692 | 3715 | while (*input_line_pointer++ == ',' && num < 2 && imm_expr->X_op != O_big); |
a262b82f NC |
3716 | |
3717 | input_line_pointer--; | |
3718 | if (*input_line_pointer != '\0') | |
3719 | return _("unrecognized values"); | |
3720 | ||
cf2ab5ef | 3721 | insn = XCNEW (struct riscv_opcode); |
a262b82f NC |
3722 | insn->match = values[num - 1]; |
3723 | create_insn (ip, insn); | |
3724 | unsigned int bytes = riscv_insn_length (insn->match); | |
bb996692 JB |
3725 | |
3726 | if (num == 2 && values[0] != bytes) | |
3727 | return _("value conflicts with instruction length"); | |
3728 | ||
3729 | if (imm_expr->X_op == O_big) | |
3730 | { | |
634001bb TO |
3731 | unsigned int llen = 0; |
3732 | for (LITTLENUM_TYPE lval = generic_bignum[imm_expr->X_add_number - 1]; | |
3733 | lval != 0; llen++) | |
3734 | lval >>= BITS_PER_CHAR; | |
3735 | unsigned int repr_bytes | |
3736 | = (imm_expr->X_add_number - 1) * CHARS_PER_LITTLENUM + llen; | |
3737 | if (bytes < repr_bytes) | |
bb996692 | 3738 | return _("value conflicts with instruction length"); |
634001bb TO |
3739 | for (num = 0; num < imm_expr->X_add_number - 1; ++num) |
3740 | number_to_chars_littleendian ( | |
3741 | ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, | |
3742 | generic_bignum[num], | |
3743 | CHARS_PER_LITTLENUM); | |
3744 | if (llen != 0) | |
3745 | number_to_chars_littleendian ( | |
3746 | ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, | |
3747 | generic_bignum[num], | |
3748 | llen); | |
3749 | memset(ip->insn_long_opcode + repr_bytes, 0, bytes - repr_bytes); | |
bb996692 JB |
3750 | return NULL; |
3751 | } | |
3752 | ||
3753 | if (bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0) | |
a262b82f NC |
3754 | return _("value conflicts with instruction length"); |
3755 | ||
3756 | return NULL; | |
3757 | } | |
3758 | ||
e23eba97 NC |
3759 | void |
3760 | md_assemble (char *str) | |
3761 | { | |
3762 | struct riscv_cl_insn insn; | |
3763 | expressionS imm_expr; | |
3764 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
3765 | ||
dcd709e0 NC |
3766 | /* The architecture and privileged elf attributes should be set |
3767 | before assembling. */ | |
8f595e9b NC |
3768 | if (!start_assemble) |
3769 | { | |
5b7c81bd | 3770 | start_assemble = true; |
e23eba97 | 3771 | |
dcd709e0 | 3772 | riscv_set_abi_by_arch (); |
8f595e9b NC |
3773 | if (!riscv_set_default_priv_spec (NULL)) |
3774 | return; | |
3775 | } | |
3776 | ||
3190ebcb | 3777 | riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */); |
9b9b1092 | 3778 | |
e4028336 PN |
3779 | const struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr, |
3780 | &imm_reloc, op_hash); | |
2dc8dd17 | 3781 | |
e4028336 | 3782 | if (error.msg) |
e23eba97 | 3783 | { |
e4028336 PN |
3784 | if (error.missing_ext) |
3785 | as_bad ("%s `%s', extension `%s' required", error.msg, | |
3786 | error.statement, error.missing_ext); | |
3787 | else | |
3788 | as_bad ("%s `%s'", error.msg, error.statement); | |
e23eba97 NC |
3789 | return; |
3790 | } | |
3791 | ||
3792 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
3793 | macro (&insn, &imm_expr, &imm_reloc); | |
3794 | else | |
3795 | append_insn (&insn, &imm_expr, imm_reloc); | |
3796 | } | |
3797 | ||
3798 | const char * | |
3799 | md_atof (int type, char *litP, int *sizeP) | |
3800 | { | |
71a75b51 | 3801 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e23eba97 NC |
3802 | } |
3803 | ||
3804 | void | |
3805 | md_number_to_chars (char *buf, valueT val, int n) | |
3806 | { | |
fbc09e7a MC |
3807 | if (target_big_endian) |
3808 | number_to_chars_bigendian (buf, val, n); | |
3809 | else | |
3810 | number_to_chars_littleendian (buf, val, n); | |
e23eba97 NC |
3811 | } |
3812 | ||
3813 | const char *md_shortopts = "O::g::G:"; | |
3814 | ||
3815 | enum options | |
3816 | { | |
2922d21d | 3817 | OPTION_MARCH = OPTION_MD_BASE, |
e23eba97 NC |
3818 | OPTION_PIC, |
3819 | OPTION_NO_PIC, | |
2922d21d | 3820 | OPTION_MABI, |
71060565 JW |
3821 | OPTION_RELAX, |
3822 | OPTION_NO_RELAX, | |
2dc8dd17 JW |
3823 | OPTION_ARCH_ATTR, |
3824 | OPTION_NO_ARCH_ATTR, | |
2ca89224 NC |
3825 | OPTION_CSR_CHECK, |
3826 | OPTION_NO_CSR_CHECK, | |
8f595e9b NC |
3827 | OPTION_MISA_SPEC, |
3828 | OPTION_MPRIV_SPEC, | |
fbc09e7a MC |
3829 | OPTION_BIG_ENDIAN, |
3830 | OPTION_LITTLE_ENDIAN, | |
e23eba97 NC |
3831 | OPTION_END_OF_ENUM |
3832 | }; | |
3833 | ||
3834 | struct option md_longopts[] = | |
3835 | { | |
e23eba97 NC |
3836 | {"march", required_argument, NULL, OPTION_MARCH}, |
3837 | {"fPIC", no_argument, NULL, OPTION_PIC}, | |
3838 | {"fpic", no_argument, NULL, OPTION_PIC}, | |
3839 | {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, | |
2922d21d | 3840 | {"mabi", required_argument, NULL, OPTION_MABI}, |
71060565 JW |
3841 | {"mrelax", no_argument, NULL, OPTION_RELAX}, |
3842 | {"mno-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
2dc8dd17 JW |
3843 | {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR}, |
3844 | {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR}, | |
2ca89224 NC |
3845 | {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK}, |
3846 | {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK}, | |
8f595e9b NC |
3847 | {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC}, |
3848 | {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC}, | |
fbc09e7a MC |
3849 | {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN}, |
3850 | {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
e23eba97 NC |
3851 | |
3852 | {NULL, no_argument, NULL, 0} | |
3853 | }; | |
3854 | size_t md_longopts_size = sizeof (md_longopts); | |
3855 | ||
e23eba97 NC |
3856 | int |
3857 | md_parse_option (int c, const char *arg) | |
3858 | { | |
3859 | switch (c) | |
3860 | { | |
e23eba97 | 3861 | case OPTION_MARCH: |
8f595e9b | 3862 | default_arch_with_ext = arg; |
e23eba97 NC |
3863 | break; |
3864 | ||
3865 | case OPTION_NO_PIC: | |
5b7c81bd | 3866 | riscv_opts.pic = false; |
e23eba97 NC |
3867 | break; |
3868 | ||
3869 | case OPTION_PIC: | |
5b7c81bd | 3870 | riscv_opts.pic = true; |
e23eba97 NC |
3871 | break; |
3872 | ||
2922d21d AW |
3873 | case OPTION_MABI: |
3874 | if (strcmp (arg, "ilp32") == 0) | |
5b7c81bd | 3875 | riscv_set_abi (32, FLOAT_ABI_SOFT, false); |
7f999549 | 3876 | else if (strcmp (arg, "ilp32e") == 0) |
5b7c81bd | 3877 | riscv_set_abi (32, FLOAT_ABI_SOFT, true); |
2922d21d | 3878 | else if (strcmp (arg, "ilp32f") == 0) |
5b7c81bd | 3879 | riscv_set_abi (32, FLOAT_ABI_SINGLE, false); |
2922d21d | 3880 | else if (strcmp (arg, "ilp32d") == 0) |
5b7c81bd | 3881 | riscv_set_abi (32, FLOAT_ABI_DOUBLE, false); |
2922d21d | 3882 | else if (strcmp (arg, "ilp32q") == 0) |
5b7c81bd | 3883 | riscv_set_abi (32, FLOAT_ABI_QUAD, false); |
2922d21d | 3884 | else if (strcmp (arg, "lp64") == 0) |
5b7c81bd | 3885 | riscv_set_abi (64, FLOAT_ABI_SOFT, false); |
2922d21d | 3886 | else if (strcmp (arg, "lp64f") == 0) |
5b7c81bd | 3887 | riscv_set_abi (64, FLOAT_ABI_SINGLE, false); |
2922d21d | 3888 | else if (strcmp (arg, "lp64d") == 0) |
5b7c81bd | 3889 | riscv_set_abi (64, FLOAT_ABI_DOUBLE, false); |
2922d21d | 3890 | else if (strcmp (arg, "lp64q") == 0) |
5b7c81bd | 3891 | riscv_set_abi (64, FLOAT_ABI_QUAD, false); |
2922d21d AW |
3892 | else |
3893 | return 0; | |
5b7c81bd | 3894 | explicit_mabi = true; |
2922d21d AW |
3895 | break; |
3896 | ||
71060565 | 3897 | case OPTION_RELAX: |
5b7c81bd | 3898 | riscv_opts.relax = true; |
71060565 JW |
3899 | break; |
3900 | ||
3901 | case OPTION_NO_RELAX: | |
5b7c81bd | 3902 | riscv_opts.relax = false; |
71060565 JW |
3903 | break; |
3904 | ||
2dc8dd17 | 3905 | case OPTION_ARCH_ATTR: |
5b7c81bd | 3906 | riscv_opts.arch_attr = true; |
2dc8dd17 JW |
3907 | break; |
3908 | ||
3909 | case OPTION_NO_ARCH_ATTR: | |
5b7c81bd | 3910 | riscv_opts.arch_attr = false; |
2dc8dd17 JW |
3911 | break; |
3912 | ||
2ca89224 | 3913 | case OPTION_CSR_CHECK: |
5b7c81bd | 3914 | riscv_opts.csr_check = true; |
2ca89224 NC |
3915 | break; |
3916 | ||
3917 | case OPTION_NO_CSR_CHECK: | |
5b7c81bd | 3918 | riscv_opts.csr_check = false; |
2ca89224 NC |
3919 | break; |
3920 | ||
8f595e9b NC |
3921 | case OPTION_MISA_SPEC: |
3922 | return riscv_set_default_isa_spec (arg); | |
3923 | ||
3924 | case OPTION_MPRIV_SPEC: | |
3925 | return riscv_set_default_priv_spec (arg); | |
3926 | ||
fbc09e7a MC |
3927 | case OPTION_BIG_ENDIAN: |
3928 | target_big_endian = 1; | |
3929 | break; | |
3930 | ||
3931 | case OPTION_LITTLE_ENDIAN: | |
3932 | target_big_endian = 0; | |
3933 | break; | |
3934 | ||
e23eba97 NC |
3935 | default: |
3936 | return 0; | |
3937 | } | |
3938 | ||
3939 | return 1; | |
3940 | } | |
3941 | ||
3942 | void | |
3943 | riscv_after_parse_args (void) | |
3944 | { | |
dcd709e0 NC |
3945 | /* The --with-arch is optional for now, so we still need to set the xlen |
3946 | according to the default_arch, which is set by the --target. */ | |
e23eba97 NC |
3947 | if (xlen == 0) |
3948 | { | |
3949 | if (strcmp (default_arch, "riscv32") == 0) | |
3950 | xlen = 32; | |
3951 | else if (strcmp (default_arch, "riscv64") == 0) | |
3952 | xlen = 64; | |
3953 | else | |
3954 | as_bad ("unknown default architecture `%s'", default_arch); | |
3955 | } | |
8f595e9b | 3956 | |
dcd709e0 | 3957 | /* Set default specs. */ |
8f595e9b NC |
3958 | if (default_isa_spec == ISA_SPEC_CLASS_NONE) |
3959 | riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC); | |
dcd709e0 NC |
3960 | if (default_priv_spec == PRIV_SPEC_CLASS_NONE) |
3961 | riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC); | |
2922d21d | 3962 | |
8f595e9b | 3963 | riscv_set_arch (default_arch_with_ext); |
2922d21d | 3964 | |
0ac2b354 AB |
3965 | /* If the CIE to be produced has not been overridden on the command line, |
3966 | then produce version 3 by default. This allows us to use the full | |
3967 | range of registers in a .cfi_return_column directive. */ | |
3968 | if (flag_dwarf_cie_version == -1) | |
3969 | flag_dwarf_cie_version = 3; | |
e23eba97 NC |
3970 | } |
3971 | ||
7a29ee29 JB |
3972 | bool riscv_parse_name (const char *name, struct expressionS *ep, |
3973 | enum expr_mode mode) | |
3974 | { | |
3975 | unsigned int regno; | |
3976 | symbolS *sym; | |
3977 | ||
3978 | if (!probing_insn_operands) | |
3979 | return false; | |
3980 | ||
3981 | gas_assert (mode == expr_normal); | |
3982 | ||
3983 | regno = reg_lookup_internal (name, RCLASS_GPR); | |
3984 | if (regno == (unsigned int)-1) | |
3985 | return false; | |
3986 | ||
3987 | if (symbol_find (name) != NULL) | |
3988 | return false; | |
3989 | ||
3990 | /* Create a symbol without adding it to the symbol table yet. | |
3991 | Insertion will happen only once we commit to using the insn | |
3992 | we're probing operands for. */ | |
3993 | for (sym = deferred_sym_rootP; sym; sym = symbol_next (sym)) | |
3994 | if (strcmp (name, S_GET_NAME (sym)) == 0) | |
3995 | break; | |
3996 | if (!sym) | |
3997 | { | |
3998 | for (sym = orphan_sym_rootP; sym; sym = symbol_next (sym)) | |
3999 | if (strcmp (name, S_GET_NAME (sym)) == 0) | |
4000 | { | |
4001 | symbol_remove (sym, &orphan_sym_rootP, &orphan_sym_lastP); | |
4002 | break; | |
4003 | } | |
4004 | if (!sym) | |
4005 | sym = symbol_create (name, undefined_section, | |
4006 | &zero_address_frag, 0); | |
4007 | ||
4008 | symbol_append (sym, deferred_sym_lastP, &deferred_sym_rootP, | |
4009 | &deferred_sym_lastP); | |
4010 | } | |
4011 | ||
4012 | ep->X_op = O_symbol; | |
4013 | ep->X_add_symbol = sym; | |
4014 | ep->X_add_number = 0; | |
4015 | ||
4016 | return true; | |
4017 | } | |
4018 | ||
e23eba97 NC |
4019 | long |
4020 | md_pcrel_from (fixS *fixP) | |
4021 | { | |
4022 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
4023 | } | |
4024 | ||
4025 | /* Apply a fixup to the object file. */ | |
4026 | ||
4027 | void | |
4028 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) | |
4029 | { | |
45f76423 | 4030 | unsigned int subtype; |
e23eba97 | 4031 | bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
5b7c81bd | 4032 | bool relaxable = false; |
c1b465c9 | 4033 | offsetT loc; |
a6cbf936 | 4034 | segT sub_segment; |
e23eba97 NC |
4035 | |
4036 | /* Remember value for tc_gen_reloc. */ | |
4037 | fixP->fx_addnumber = *valP; | |
4038 | ||
4039 | switch (fixP->fx_r_type) | |
4040 | { | |
e23eba97 NC |
4041 | case BFD_RELOC_RISCV_HI20: |
4042 | case BFD_RELOC_RISCV_LO12_I: | |
4043 | case BFD_RELOC_RISCV_LO12_S: | |
45f76423 AW |
4044 | bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) |
4045 | | bfd_getl32 (buf), buf); | |
a5ec5e3f | 4046 | if (fixP->fx_addsy == NULL) |
5b7c81bd AM |
4047 | fixP->fx_done = true; |
4048 | relaxable = true; | |
45f76423 AW |
4049 | break; |
4050 | ||
4051 | case BFD_RELOC_RISCV_GOT_HI20: | |
e23eba97 NC |
4052 | case BFD_RELOC_RISCV_ADD8: |
4053 | case BFD_RELOC_RISCV_ADD16: | |
4054 | case BFD_RELOC_RISCV_ADD32: | |
4055 | case BFD_RELOC_RISCV_ADD64: | |
45f76423 | 4056 | case BFD_RELOC_RISCV_SUB6: |
e23eba97 NC |
4057 | case BFD_RELOC_RISCV_SUB8: |
4058 | case BFD_RELOC_RISCV_SUB16: | |
4059 | case BFD_RELOC_RISCV_SUB32: | |
4060 | case BFD_RELOC_RISCV_SUB64: | |
45f76423 | 4061 | case BFD_RELOC_RISCV_RELAX: |
f1cd8b94 KLC |
4062 | /* cvt_frag_to_fill () has called output_leb128 (). */ |
4063 | case BFD_RELOC_RISCV_SET_ULEB128: | |
4064 | case BFD_RELOC_RISCV_SUB_ULEB128: | |
45f76423 AW |
4065 | break; |
4066 | ||
4067 | case BFD_RELOC_RISCV_TPREL_HI20: | |
4068 | case BFD_RELOC_RISCV_TPREL_LO12_I: | |
4069 | case BFD_RELOC_RISCV_TPREL_LO12_S: | |
4070 | case BFD_RELOC_RISCV_TPREL_ADD: | |
5b7c81bd | 4071 | relaxable = true; |
45f76423 AW |
4072 | /* Fall through. */ |
4073 | ||
4074 | case BFD_RELOC_RISCV_TLS_GOT_HI20: | |
4075 | case BFD_RELOC_RISCV_TLS_GD_HI20: | |
4076 | case BFD_RELOC_RISCV_TLS_DTPREL32: | |
4077 | case BFD_RELOC_RISCV_TLS_DTPREL64: | |
e294484e AW |
4078 | if (fixP->fx_addsy != NULL) |
4079 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4080 | else | |
4081 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4082 | _("TLS relocation against a constant")); | |
e23eba97 NC |
4083 | break; |
4084 | ||
e23eba97 | 4085 | case BFD_RELOC_32: |
a6cbf936 KLC |
4086 | /* Use pc-relative relocation for FDE initial location. |
4087 | The symbol address in .eh_frame may be adjusted in | |
4088 | _bfd_elf_discard_section_eh_frame, and the content of | |
4089 | .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. | |
4090 | Therefore, we cannot insert a relocation whose addend symbol is | |
dcd709e0 | 4091 | in .eh_frame. Othrewise, the value may be adjusted twice. */ |
a6cbf936 KLC |
4092 | if (fixP->fx_addsy && fixP->fx_subsy |
4093 | && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) | |
4094 | && strcmp (sub_segment->name, ".eh_frame") == 0 | |
4095 | && S_GET_VALUE (fixP->fx_subsy) | |
4096 | == fixP->fx_frag->fr_address + fixP->fx_where) | |
4097 | { | |
4098 | fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL; | |
4099 | fixP->fx_subsy = NULL; | |
4100 | break; | |
4101 | } | |
4102 | /* Fall through. */ | |
4103 | case BFD_RELOC_64: | |
e23eba97 NC |
4104 | case BFD_RELOC_16: |
4105 | case BFD_RELOC_8: | |
45f76423 | 4106 | case BFD_RELOC_RISCV_CFA: |
e23eba97 NC |
4107 | if (fixP->fx_addsy && fixP->fx_subsy) |
4108 | { | |
4109 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
4110 | fixP->fx_next->fx_addsy = fixP->fx_subsy; | |
4111 | fixP->fx_next->fx_subsy = NULL; | |
4112 | fixP->fx_next->fx_offset = 0; | |
4113 | fixP->fx_subsy = NULL; | |
4114 | ||
4115 | switch (fixP->fx_r_type) | |
4116 | { | |
4117 | case BFD_RELOC_64: | |
4118 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; | |
4119 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; | |
4120 | break; | |
4121 | ||
4122 | case BFD_RELOC_32: | |
4123 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; | |
4124 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
4125 | break; | |
4126 | ||
4127 | case BFD_RELOC_16: | |
4128 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; | |
4129 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
4130 | break; | |
4131 | ||
4132 | case BFD_RELOC_8: | |
4133 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; | |
4134 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
073808ed | 4135 | break; |
e23eba97 | 4136 | |
45f76423 AW |
4137 | case BFD_RELOC_RISCV_CFA: |
4138 | /* Load the byte to get the subtype. */ | |
c1b465c9 KLC |
4139 | subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); |
4140 | loc = fixP->fx_frag->fr_fix - (subtype & 7); | |
45f76423 AW |
4141 | switch (subtype) |
4142 | { | |
4143 | case DW_CFA_advance_loc1: | |
c1b465c9 KLC |
4144 | fixP->fx_where = loc + 1; |
4145 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
4146 | fixP->fx_r_type = BFD_RELOC_RISCV_SET8; |
4147 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
4148 | break; | |
4149 | ||
4150 | case DW_CFA_advance_loc2: | |
4151 | fixP->fx_size = 2; | |
45f76423 | 4152 | fixP->fx_next->fx_size = 2; |
c1b465c9 KLC |
4153 | fixP->fx_where = loc + 1; |
4154 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
4155 | fixP->fx_r_type = BFD_RELOC_RISCV_SET16; |
4156 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
4157 | break; | |
4158 | ||
4159 | case DW_CFA_advance_loc4: | |
4160 | fixP->fx_size = 4; | |
45f76423 | 4161 | fixP->fx_next->fx_size = 4; |
c1b465c9 KLC |
4162 | fixP->fx_where = loc; |
4163 | fixP->fx_next->fx_where = loc; | |
45f76423 AW |
4164 | fixP->fx_r_type = BFD_RELOC_RISCV_SET32; |
4165 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
4166 | break; | |
4167 | ||
4168 | default: | |
4169 | if (subtype < 0x80 && (subtype & 0x40)) | |
4170 | { | |
4171 | /* DW_CFA_advance_loc */ | |
2aece2ba KLC |
4172 | fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; |
4173 | fixP->fx_next->fx_frag = fixP->fx_frag; | |
45f76423 AW |
4174 | fixP->fx_r_type = BFD_RELOC_RISCV_SET6; |
4175 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; | |
4176 | } | |
4177 | else | |
b800637e | 4178 | as_fatal (_("internal: bad CFA value #%d"), subtype); |
45f76423 AW |
4179 | break; |
4180 | } | |
4181 | break; | |
4182 | ||
e23eba97 NC |
4183 | default: |
4184 | /* This case is unreachable. */ | |
4185 | abort (); | |
4186 | } | |
4187 | } | |
4188 | /* Fall through. */ | |
4189 | ||
4190 | case BFD_RELOC_RVA: | |
4191 | /* If we are deleting this reloc entry, we must fill in the | |
4192 | value now. This can happen if we have a .word which is not | |
4193 | resolved when it appears but is later defined. */ | |
4194 | if (fixP->fx_addsy == NULL) | |
4195 | { | |
4196 | gas_assert (fixP->fx_size <= sizeof (valueT)); | |
4197 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); | |
4198 | fixP->fx_done = 1; | |
4199 | } | |
4200 | break; | |
4201 | ||
4202 | case BFD_RELOC_RISCV_JMP: | |
4203 | if (fixP->fx_addsy) | |
4204 | { | |
4205 | /* Fill in a tentative value to improve objdump readability. */ | |
4206 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4207 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4208 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf); |
e23eba97 NC |
4209 | } |
4210 | break; | |
4211 | ||
4212 | case BFD_RELOC_12_PCREL: | |
4213 | if (fixP->fx_addsy) | |
4214 | { | |
4215 | /* Fill in a tentative value to improve objdump readability. */ | |
4216 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4217 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4218 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf); |
e23eba97 NC |
4219 | } |
4220 | break; | |
4221 | ||
4222 | case BFD_RELOC_RISCV_RVC_BRANCH: | |
4223 | if (fixP->fx_addsy) | |
4224 | { | |
4225 | /* Fill in a tentative value to improve objdump readability. */ | |
4226 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4227 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4228 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf); |
e23eba97 NC |
4229 | } |
4230 | break; | |
4231 | ||
4232 | case BFD_RELOC_RISCV_RVC_JUMP: | |
4233 | if (fixP->fx_addsy) | |
4234 | { | |
4235 | /* Fill in a tentative value to improve objdump readability. */ | |
4236 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4237 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4238 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf); |
e23eba97 NC |
4239 | } |
4240 | break; | |
4241 | ||
e23eba97 NC |
4242 | case BFD_RELOC_RISCV_CALL: |
4243 | case BFD_RELOC_RISCV_CALL_PLT: | |
5b7c81bd | 4244 | relaxable = true; |
45f76423 AW |
4245 | break; |
4246 | ||
9d06997a | 4247 | case BFD_RELOC_RISCV_PCREL_HI20: |
45f76423 AW |
4248 | case BFD_RELOC_RISCV_PCREL_LO12_S: |
4249 | case BFD_RELOC_RISCV_PCREL_LO12_I: | |
9d06997a PD |
4250 | relaxable = riscv_opts.relax; |
4251 | break; | |
4252 | ||
e23eba97 NC |
4253 | case BFD_RELOC_RISCV_ALIGN: |
4254 | break; | |
4255 | ||
4256 | default: | |
4257 | /* We ignore generic BFD relocations we don't know about. */ | |
4258 | if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) | |
b800637e | 4259 | as_fatal (_("internal: bad relocation #%d"), fixP->fx_r_type); |
e23eba97 | 4260 | } |
45f76423 | 4261 | |
e294484e | 4262 | if (fixP->fx_subsy != NULL) |
4bf09429 | 4263 | as_bad_subtract (fixP); |
e294484e | 4264 | |
45f76423 AW |
4265 | /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ |
4266 | if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) | |
4267 | { | |
4268 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
4269 | fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; | |
4270 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; | |
b1b11e92 | 4271 | fixP->fx_next->fx_size = 0; |
45f76423 AW |
4272 | } |
4273 | } | |
4274 | ||
4275 | /* Because the value of .cfi_remember_state may changed after relaxation, | |
4276 | we insert a fix to relocate it again in link-time. */ | |
4277 | ||
4278 | void | |
4279 | riscv_pre_output_hook (void) | |
4280 | { | |
4281 | const frchainS *frch; | |
72393fd1 JW |
4282 | segT s; |
4283 | ||
4284 | /* Save the current segment info. */ | |
4285 | segT seg = now_seg; | |
4286 | subsegT subseg = now_subseg; | |
45f76423 AW |
4287 | |
4288 | for (s = stdoutput->sections; s; s = s->next) | |
4289 | for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) | |
4290 | { | |
7cb7b948 | 4291 | fragS *frag; |
45f76423 AW |
4292 | |
4293 | for (frag = frch->frch_root; frag; frag = frag->fr_next) | |
4294 | { | |
4295 | if (frag->fr_type == rs_cfa) | |
4296 | { | |
45f76423 | 4297 | expressionS exp; |
8d1015a8 | 4298 | expressionS *symval; |
45f76423 | 4299 | |
8d1015a8 | 4300 | symval = symbol_get_value_expression (frag->fr_symbol); |
45f76423 | 4301 | exp.X_op = O_subtract; |
8d1015a8 | 4302 | exp.X_add_symbol = symval->X_add_symbol; |
45f76423 | 4303 | exp.X_add_number = 0; |
8d1015a8 | 4304 | exp.X_op_symbol = symval->X_op_symbol; |
45f76423 | 4305 | |
72393fd1 JW |
4306 | /* We must set the segment before creating a frag after all |
4307 | frag chains have been chained together. */ | |
4308 | subseg_set (s, frch->frch_subseg); | |
4309 | ||
c1b465c9 | 4310 | fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, |
45f76423 AW |
4311 | BFD_RELOC_RISCV_CFA); |
4312 | } | |
4313 | } | |
4314 | } | |
72393fd1 JW |
4315 | |
4316 | /* Restore the original segment info. */ | |
4317 | subseg_set (seg, subseg); | |
e23eba97 NC |
4318 | } |
4319 | ||
e23eba97 NC |
4320 | /* Handle the .option pseudo-op. */ |
4321 | ||
4322 | static void | |
4323 | s_riscv_option (int x ATTRIBUTE_UNUSED) | |
4324 | { | |
4325 | char *name = input_line_pointer, ch; | |
4326 | ||
4327 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4328 | ++input_line_pointer; | |
4329 | ch = *input_line_pointer; | |
4330 | *input_line_pointer = '\0'; | |
4331 | ||
4332 | if (strcmp (name, "rvc") == 0) | |
edc77c59 | 4333 | { |
d3ffd7f7 | 4334 | riscv_update_subset (&riscv_rps_as, "+c"); |
40f1a1a4 | 4335 | riscv_reset_subsets_list_arch_str (); |
edc77c59 NC |
4336 | riscv_set_rvc (true); |
4337 | } | |
e23eba97 | 4338 | else if (strcmp (name, "norvc") == 0) |
edc77c59 | 4339 | { |
d3ffd7f7 | 4340 | riscv_update_subset (&riscv_rps_as, "-c"); |
40f1a1a4 | 4341 | riscv_reset_subsets_list_arch_str (); |
edc77c59 NC |
4342 | riscv_set_rvc (false); |
4343 | } | |
e23eba97 | 4344 | else if (strcmp (name, "pic") == 0) |
5b7c81bd | 4345 | riscv_opts.pic = true; |
e23eba97 | 4346 | else if (strcmp (name, "nopic") == 0) |
5b7c81bd | 4347 | riscv_opts.pic = false; |
45f76423 | 4348 | else if (strcmp (name, "relax") == 0) |
5b7c81bd | 4349 | riscv_opts.relax = true; |
45f76423 | 4350 | else if (strcmp (name, "norelax") == 0) |
5b7c81bd | 4351 | riscv_opts.relax = false; |
2ca89224 | 4352 | else if (strcmp (name, "csr-check") == 0) |
5b7c81bd | 4353 | riscv_opts.csr_check = true; |
2ca89224 | 4354 | else if (strcmp (name, "no-csr-check") == 0) |
5b7c81bd | 4355 | riscv_opts.csr_check = false; |
d3ffd7f7 NC |
4356 | else if (strncmp (name, "arch,", 5) == 0) |
4357 | { | |
4358 | name += 5; | |
4359 | if (ISSPACE (*name) && *name != '\0') | |
4360 | name++; | |
4361 | riscv_update_subset (&riscv_rps_as, name); | |
40f1a1a4 | 4362 | riscv_reset_subsets_list_arch_str (); |
e7e599a1 NC |
4363 | |
4364 | riscv_set_rvc (false); | |
b5c37946 SJ |
4365 | if (riscv_subset_supports (&riscv_rps_as, "c") |
4366 | || riscv_subset_supports (&riscv_rps_as, "zca")) | |
e7e599a1 | 4367 | riscv_set_rvc (true); |
acab2a68 TO |
4368 | |
4369 | if (riscv_subset_supports (&riscv_rps_as, "ztso")) | |
4370 | riscv_set_tso (); | |
d3ffd7f7 | 4371 | } |
e23eba97 NC |
4372 | else if (strcmp (name, "push") == 0) |
4373 | { | |
4374 | struct riscv_option_stack *s; | |
4375 | ||
d3ffd7f7 | 4376 | s = XNEW (struct riscv_option_stack); |
e23eba97 NC |
4377 | s->next = riscv_opts_stack; |
4378 | s->options = riscv_opts; | |
f5cb31a8 | 4379 | s->subset_list = riscv_rps_as.subset_list; |
e23eba97 | 4380 | riscv_opts_stack = s; |
f5cb31a8 | 4381 | riscv_rps_as.subset_list = riscv_copy_subset_list (s->subset_list); |
e23eba97 NC |
4382 | } |
4383 | else if (strcmp (name, "pop") == 0) | |
4384 | { | |
4385 | struct riscv_option_stack *s; | |
4386 | ||
4387 | s = riscv_opts_stack; | |
4388 | if (s == NULL) | |
4389 | as_bad (_(".option pop with no .option push")); | |
4390 | else | |
4391 | { | |
f5cb31a8 | 4392 | riscv_subset_list_t *release_subsets = riscv_rps_as.subset_list; |
e23eba97 | 4393 | riscv_opts_stack = s->next; |
d3ffd7f7 | 4394 | riscv_opts = s->options; |
f5cb31a8 | 4395 | riscv_rps_as.subset_list = s->subset_list; |
d3ffd7f7 | 4396 | riscv_release_subset_list (release_subsets); |
e23eba97 NC |
4397 | free (s); |
4398 | } | |
4399 | } | |
4400 | else | |
4401 | { | |
c84b3d7e | 4402 | as_warn (_("unrecognized .option directive: %s"), name); |
e23eba97 NC |
4403 | } |
4404 | *input_line_pointer = ch; | |
4405 | demand_empty_rest_of_line (); | |
4406 | } | |
4407 | ||
4408 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate | |
4409 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
4410 | use in DWARF debug information. */ | |
4411 | ||
4412 | static void | |
4413 | s_dtprel (int bytes) | |
4414 | { | |
4415 | expressionS ex; | |
4416 | char *p; | |
4417 | ||
4418 | expression (&ex); | |
4419 | ||
4420 | if (ex.X_op != O_symbol) | |
4421 | { | |
b800637e | 4422 | as_bad (_("unsupported use of %s"), (bytes == 8 |
e23eba97 NC |
4423 | ? ".dtpreldword" |
4424 | : ".dtprelword")); | |
4425 | ignore_rest_of_line (); | |
4426 | } | |
4427 | ||
4428 | p = frag_more (bytes); | |
4429 | md_number_to_chars (p, 0, bytes); | |
5b7c81bd | 4430 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false, |
e23eba97 NC |
4431 | (bytes == 8 |
4432 | ? BFD_RELOC_RISCV_TLS_DTPREL64 | |
4433 | : BFD_RELOC_RISCV_TLS_DTPREL32)); | |
4434 | ||
4435 | demand_empty_rest_of_line (); | |
4436 | } | |
4437 | ||
4438 | /* Handle the .bss pseudo-op. */ | |
4439 | ||
4440 | static void | |
4441 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
4442 | { | |
4443 | subseg_set (bss_section, 0); | |
4444 | demand_empty_rest_of_line (); | |
4445 | } | |
4446 | ||
e23eba97 | 4447 | static void |
d115ab8e | 4448 | riscv_make_nops (char *buf, bfd_vma bytes) |
e23eba97 | 4449 | { |
d115ab8e | 4450 | bfd_vma i = 0; |
e23eba97 | 4451 | |
e5b737de AW |
4452 | /* RISC-V instructions cannot begin or end on odd addresses, so this case |
4453 | means we are not within a valid instruction sequence. It is thus safe | |
4454 | to use a zero byte, even though that is not a valid instruction. */ | |
4455 | if (bytes % 2 == 1) | |
4456 | buf[i++] = 0; | |
4457 | ||
4458 | /* Use at most one 2-byte NOP. */ | |
4459 | if ((bytes - i) % 4 == 2) | |
e23eba97 | 4460 | { |
fbc09e7a | 4461 | number_to_chars_littleendian (buf + i, RVC_NOP, 2); |
d115ab8e | 4462 | i += 2; |
e23eba97 NC |
4463 | } |
4464 | ||
e5b737de | 4465 | /* Fill the remainder with 4-byte NOPs. */ |
d115ab8e | 4466 | for ( ; i < bytes; i += 4) |
fbc09e7a | 4467 | number_to_chars_littleendian (buf + i, RISCV_NOP, 4); |
d115ab8e | 4468 | } |
e23eba97 | 4469 | |
d115ab8e AW |
4470 | /* Called from md_do_align. Used to create an alignment frag in a |
4471 | code section by emitting a worst-case NOP sequence that the linker | |
4472 | will later relax to the correct number of NOPs. We can't compute | |
4473 | the correct alignment now because of other linker relaxations. */ | |
4474 | ||
5b7c81bd | 4475 | bool |
d115ab8e AW |
4476 | riscv_frag_align_code (int n) |
4477 | { | |
e5b737de | 4478 | bfd_vma bytes = (bfd_vma) 1 << n; |
36877bfb JW |
4479 | bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4; |
4480 | bfd_vma worst_case_bytes = bytes - insn_alignment; | |
4481 | char *nops; | |
ed0816bd | 4482 | expressionS ex; |
d115ab8e | 4483 | |
36877bfb JW |
4484 | /* If we are moving to a smaller alignment than the instruction size, then no |
4485 | alignment is required. */ | |
4486 | if (bytes <= insn_alignment) | |
5b7c81bd | 4487 | return true; |
36877bfb | 4488 | |
d115ab8e AW |
4489 | /* When not relaxing, riscv_handle_align handles code alignment. */ |
4490 | if (!riscv_opts.relax) | |
5b7c81bd | 4491 | return false; |
e23eba97 | 4492 | |
40f1a1a4 NC |
4493 | /* Maybe we should use frag_var to create a new rs_align_code fragment, |
4494 | rather than just use frag_more to handle an alignment here? So that we | |
4495 | don't need to call riscv_mapping_state again later, and then only need | |
4496 | to check frag->fr_type to see if it is frag_align_code. */ | |
e80ae190 JW |
4497 | nops = frag_more (worst_case_bytes); |
4498 | ||
ed0816bd PD |
4499 | ex.X_op = O_constant; |
4500 | ex.X_add_number = worst_case_bytes; | |
d115ab8e | 4501 | |
ed0816bd | 4502 | riscv_make_nops (nops, worst_case_bytes); |
e23eba97 | 4503 | |
ed0816bd | 4504 | fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, |
5b7c81bd | 4505 | &ex, false, BFD_RELOC_RISCV_ALIGN); |
e23eba97 | 4506 | |
3190ebcb | 4507 | riscv_mapping_state (MAP_INSN, worst_case_bytes, true/* fr_align_code */); |
9b9b1092 | 4508 | |
cb2562f5 LX |
4509 | /* We need to start a new frag after the alignment which may be removed by |
4510 | the linker, to prevent the assembler from computing static offsets. | |
4511 | This is necessary to get correct EH info. */ | |
4512 | frag_wane (frag_now); | |
4513 | frag_new (0); | |
4514 | ||
5b7c81bd | 4515 | return true; |
d115ab8e | 4516 | } |
e23eba97 | 4517 | |
d115ab8e AW |
4518 | /* Implement HANDLE_ALIGN. */ |
4519 | ||
4520 | void | |
4521 | riscv_handle_align (fragS *fragP) | |
4522 | { | |
4523 | switch (fragP->fr_type) | |
4524 | { | |
4525 | case rs_align_code: | |
4526 | /* When relaxing, riscv_frag_align_code handles code alignment. */ | |
4527 | if (!riscv_opts.relax) | |
4528 | { | |
e80ae190 JW |
4529 | bfd_signed_vma bytes = (fragP->fr_next->fr_address |
4530 | - fragP->fr_address - fragP->fr_fix); | |
4531 | /* We have 4 byte uncompressed nops. */ | |
4532 | bfd_signed_vma size = 4; | |
4533 | bfd_signed_vma excess = bytes % size; | |
9b9b1092 | 4534 | bfd_boolean odd_padding = (excess % 2 == 1); |
e80ae190 JW |
4535 | char *p = fragP->fr_literal + fragP->fr_fix; |
4536 | ||
4537 | if (bytes <= 0) | |
d115ab8e AW |
4538 | break; |
4539 | ||
e80ae190 JW |
4540 | /* Insert zeros or compressed nops to get 4 byte alignment. */ |
4541 | if (excess) | |
4542 | { | |
9b9b1092 NC |
4543 | if (odd_padding) |
4544 | riscv_add_odd_padding_symbol (fragP); | |
e80ae190 JW |
4545 | riscv_make_nops (p, excess); |
4546 | fragP->fr_fix += excess; | |
4547 | p += excess; | |
4548 | } | |
4549 | ||
9b9b1092 NC |
4550 | /* The frag will be changed to `rs_fill` later. The function |
4551 | `write_contents` will try to fill the remaining spaces | |
4552 | according to the patterns we give. In this case, we give | |
4553 | a 4 byte uncompressed nop as the pattern, and set the size | |
4554 | of the pattern into `fr_var`. The nop will be output to the | |
4555 | file `fr_offset` times. However, `fr_offset` could be zero | |
4556 | if we don't need to pad the boundary finally. */ | |
e80ae190 JW |
4557 | riscv_make_nops (p, size); |
4558 | fragP->fr_var = size; | |
d115ab8e AW |
4559 | } |
4560 | break; | |
4561 | ||
4562 | default: | |
4563 | break; | |
4564 | } | |
e23eba97 NC |
4565 | } |
4566 | ||
9b9b1092 NC |
4567 | /* This usually called from frag_var. */ |
4568 | ||
4569 | void | |
4570 | riscv_init_frag (fragS * fragP, int max_chars) | |
4571 | { | |
4572 | /* Do not add mapping symbol to debug sections. */ | |
4573 | if (bfd_section_flags (now_seg) & SEC_DEBUGGING) | |
4574 | return; | |
4575 | ||
4576 | switch (fragP->fr_type) | |
4577 | { | |
4578 | case rs_fill: | |
4579 | case rs_align: | |
4580 | case rs_align_test: | |
3190ebcb | 4581 | riscv_mapping_state (MAP_DATA, max_chars, false/* fr_align_code */); |
9b9b1092 NC |
4582 | break; |
4583 | case rs_align_code: | |
3190ebcb | 4584 | riscv_mapping_state (MAP_INSN, max_chars, true/* fr_align_code */); |
9b9b1092 NC |
4585 | break; |
4586 | default: | |
4587 | break; | |
4588 | } | |
4589 | } | |
4590 | ||
e23eba97 NC |
4591 | int |
4592 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) | |
4593 | { | |
5b7c81bd | 4594 | return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false)); |
e23eba97 NC |
4595 | } |
4596 | ||
4597 | /* Translate internal representation of relocation info to BFD target | |
4598 | format. */ | |
4599 | ||
4600 | arelent * | |
4601 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
4602 | { | |
4603 | arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); | |
4604 | ||
4605 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
4606 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
4607 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
4608 | reloc->addend = fixp->fx_addnumber; | |
4609 | ||
4610 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
4611 | if (reloc->howto == NULL) | |
4612 | { | |
4613 | if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) | |
4614 | && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) | |
4615 | { | |
4616 | /* We don't have R_RISCV_8/16, but for this special case, | |
4617 | we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ | |
4618 | return reloc; | |
4619 | } | |
4620 | ||
4621 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
4622 | _("cannot represent %s relocation in object file"), | |
4623 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
4624 | return NULL; | |
4625 | } | |
4626 | ||
4627 | return reloc; | |
4628 | } | |
4629 | ||
4630 | int | |
4631 | riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
4632 | { | |
4633 | if (RELAX_BRANCH_P (fragp->fr_subtype)) | |
4634 | { | |
4635 | offsetT old_var = fragp->fr_var; | |
5b7c81bd | 4636 | fragp->fr_var = relaxed_branch_length (fragp, sec, true); |
e23eba97 NC |
4637 | return fragp->fr_var - old_var; |
4638 | } | |
4639 | ||
4640 | return 0; | |
4641 | } | |
4642 | ||
4643 | /* Expand far branches to multi-instruction sequences. */ | |
4644 | ||
4645 | static void | |
4646 | md_convert_frag_branch (fragS *fragp) | |
4647 | { | |
4648 | bfd_byte *buf; | |
4649 | expressionS exp; | |
4650 | fixS *fixp; | |
4651 | insn_t insn; | |
4652 | int rs1, reloc; | |
4653 | ||
4654 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; | |
4655 | ||
4656 | exp.X_op = O_symbol; | |
4657 | exp.X_add_symbol = fragp->fr_symbol; | |
4658 | exp.X_add_number = fragp->fr_offset; | |
4659 | ||
4660 | gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); | |
4661 | ||
4662 | if (RELAX_BRANCH_RVC (fragp->fr_subtype)) | |
4663 | { | |
4664 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
4665 | { | |
4666 | case 8: | |
4667 | case 4: | |
4668 | /* Expand the RVC branch into a RISC-V one. */ | |
4669 | insn = bfd_getl16 (buf); | |
4670 | rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); | |
4671 | if ((insn & MASK_C_J) == MATCH_C_J) | |
4672 | insn = MATCH_JAL; | |
4673 | else if ((insn & MASK_C_JAL) == MATCH_C_JAL) | |
4674 | insn = MATCH_JAL | (X_RA << OP_SH_RD); | |
4675 | else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) | |
4676 | insn = MATCH_BEQ | (rs1 << OP_SH_RS1); | |
4677 | else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) | |
4678 | insn = MATCH_BNE | (rs1 << OP_SH_RS1); | |
4679 | else | |
4680 | abort (); | |
4681 | bfd_putl32 (insn, buf); | |
4682 | break; | |
4683 | ||
4684 | case 6: | |
4685 | /* Invert the branch condition. Branch over the jump. */ | |
4686 | insn = bfd_getl16 (buf); | |
4687 | insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; | |
5a9f5403 | 4688 | insn |= ENCODE_CBTYPE_IMM (6); |
e23eba97 NC |
4689 | bfd_putl16 (insn, buf); |
4690 | buf += 2; | |
4691 | goto jump; | |
4692 | ||
4693 | case 2: | |
4694 | /* Just keep the RVC branch. */ | |
4695 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
4696 | ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; | |
4697 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4698 | 2, &exp, false, reloc); |
e23eba97 NC |
4699 | buf += 2; |
4700 | goto done; | |
4701 | ||
4702 | default: | |
1d65abb5 | 4703 | abort (); |
e23eba97 NC |
4704 | } |
4705 | } | |
4706 | ||
4707 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
4708 | { | |
4709 | case 8: | |
4710 | gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); | |
4711 | ||
4712 | /* Invert the branch condition. Branch over the jump. */ | |
4713 | insn = bfd_getl32 (buf); | |
4714 | insn ^= MATCH_BEQ ^ MATCH_BNE; | |
5a9f5403 | 4715 | insn |= ENCODE_BTYPE_IMM (8); |
fbc09e7a | 4716 | bfd_putl32 (insn, buf); |
e23eba97 NC |
4717 | buf += 4; |
4718 | ||
dc1e8a47 | 4719 | jump: |
e23eba97 NC |
4720 | /* Jump to the target. */ |
4721 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4722 | 4, &exp, false, BFD_RELOC_RISCV_JMP); |
fbc09e7a | 4723 | bfd_putl32 (MATCH_JAL, buf); |
e23eba97 NC |
4724 | buf += 4; |
4725 | break; | |
4726 | ||
4727 | case 4: | |
4728 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
4729 | ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; | |
4730 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4731 | 4, &exp, false, reloc); |
e23eba97 NC |
4732 | buf += 4; |
4733 | break; | |
4734 | ||
4735 | default: | |
4736 | abort (); | |
4737 | } | |
4738 | ||
dc1e8a47 | 4739 | done: |
e23eba97 NC |
4740 | fixp->fx_file = fragp->fr_file; |
4741 | fixp->fx_line = fragp->fr_line; | |
4742 | ||
4743 | gas_assert (buf == (bfd_byte *)fragp->fr_literal | |
4744 | + fragp->fr_fix + fragp->fr_var); | |
4745 | ||
4746 | fragp->fr_fix += fragp->fr_var; | |
4747 | } | |
4748 | ||
4749 | /* Relax a machine dependent frag. This returns the amount by which | |
4750 | the current size of the frag should change. */ | |
4751 | ||
4752 | void | |
4753 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, | |
4754 | fragS *fragp) | |
4755 | { | |
4756 | gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); | |
4757 | md_convert_frag_branch (fragp); | |
4758 | } | |
4759 | ||
4760 | void | |
4761 | md_show_usage (FILE *stream) | |
4762 | { | |
4763 | fprintf (stream, _("\ | |
4764 | RISC-V options:\n\ | |
437e2ff1 | 4765 | -fpic or -fPIC generate position-independent code\n\ |
8f595e9b NC |
4766 | -fno-pic don't generate position-independent code (default)\n\ |
4767 | -march=ISA set the RISC-V architecture\n\ | |
4768 | -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\ | |
86d39e66 | 4769 | -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\ |
8f595e9b NC |
4770 | -mabi=ABI set the RISC-V ABI\n\ |
4771 | -mrelax enable relax (default)\n\ | |
4772 | -mno-relax disable relax\n\ | |
4773 | -march-attr generate RISC-V arch attribute\n\ | |
4774 | -mno-arch-attr don't generate RISC-V arch attribute\n\ | |
437e2ff1 NC |
4775 | -mcsr-check enable the csr ISA and privilege spec version checks\n\ |
4776 | -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\ | |
4777 | -mbig-endian assemble for big-endian\n\ | |
4778 | -mlittle-endian assemble for little-endian\n\ | |
e23eba97 NC |
4779 | ")); |
4780 | } | |
4781 | ||
4782 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
dcd709e0 | 4783 | |
e23eba97 NC |
4784 | void |
4785 | riscv_cfi_frame_initial_instructions (void) | |
4786 | { | |
4787 | cfi_add_CFA_def_cfa_register (X_SP); | |
4788 | } | |
4789 | ||
4790 | int | |
4791 | tc_riscv_regname_to_dw2regnum (char *regname) | |
4792 | { | |
4793 | int reg; | |
4794 | ||
4795 | if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) | |
4796 | return reg; | |
4797 | ||
4798 | if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) | |
4799 | return reg + 32; | |
4800 | ||
7b4f2407 TO |
4801 | if ((reg = reg_lookup_internal (regname, RCLASS_VECR)) >= 0) |
4802 | return reg + 96; | |
4803 | ||
4762fe62 AB |
4804 | /* CSRs are numbered 4096 -> 8191. */ |
4805 | if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0) | |
4806 | return reg + 4096; | |
4807 | ||
e23eba97 NC |
4808 | as_bad (_("unknown register `%s'"), regname); |
4809 | return -1; | |
4810 | } | |
4811 | ||
4812 | void | |
4813 | riscv_elf_final_processing (void) | |
4814 | { | |
6e1605e4 | 4815 | riscv_set_abi_by_arch (); |
40f1a1a4 | 4816 | riscv_release_subset_list (riscv_rps_as.subset_list); |
e23eba97 | 4817 | elf_elfheader (stdoutput)->e_flags |= elf_flags; |
e23eba97 NC |
4818 | } |
4819 | ||
4820 | /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, | |
4821 | since these directives break relaxation when used with symbol deltas. */ | |
4822 | ||
4823 | static void | |
4824 | s_riscv_leb128 (int sign) | |
4825 | { | |
4826 | expressionS exp; | |
4827 | char *save_in = input_line_pointer; | |
4828 | ||
4829 | expression (&exp); | |
f1cd8b94 KLC |
4830 | if (sign && exp.X_op != O_constant) |
4831 | as_bad (_("non-constant .sleb128 is not supported")); | |
4832 | else if (!sign && exp.X_op != O_constant && exp.X_op != O_subtract) | |
4833 | as_bad (_(".uleb128 only supports constant or subtract expressions")); | |
4834 | ||
e23eba97 NC |
4835 | demand_empty_rest_of_line (); |
4836 | ||
4837 | input_line_pointer = save_in; | |
4838 | return s_leb128 (sign); | |
4839 | } | |
4840 | ||
a262b82f NC |
4841 | /* Parse the .insn directive. There are three formats, |
4842 | Format 1: .insn <type> <operand1>, <operand2>, ... | |
4843 | Format 2: .insn <length>, <value> | |
4844 | Format 3: .insn <value>. */ | |
0e35537d JW |
4845 | |
4846 | static void | |
4847 | s_riscv_insn (int x ATTRIBUTE_UNUSED) | |
4848 | { | |
4849 | char *str = input_line_pointer; | |
4850 | struct riscv_cl_insn insn; | |
4851 | expressionS imm_expr; | |
4852 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
4853 | char save_c; | |
4854 | ||
4855 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4856 | ++input_line_pointer; | |
4857 | ||
4858 | save_c = *input_line_pointer; | |
4859 | *input_line_pointer = '\0'; | |
4860 | ||
3190ebcb | 4861 | riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */); |
9b9b1092 | 4862 | |
e4028336 | 4863 | struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr, |
0e35537d | 4864 | &imm_reloc, insn_type_hash); |
e4028336 | 4865 | if (error.msg) |
0e35537d | 4866 | { |
a262b82f | 4867 | char *save_in = input_line_pointer; |
e4028336 | 4868 | error.msg = riscv_ip_hardcode (str, &insn, &imm_expr, error.msg); |
a262b82f | 4869 | input_line_pointer = save_in; |
0e35537d | 4870 | } |
a262b82f | 4871 | |
e4028336 PN |
4872 | if (error.msg) |
4873 | { | |
4874 | if (error.missing_ext) | |
4875 | as_bad ("%s `%s', extension `%s' required", error.msg, error.statement, | |
4876 | error.missing_ext); | |
4877 | else | |
4878 | as_bad ("%s `%s'", error.msg, error.statement); | |
4879 | } | |
634001bb | 4880 | else |
0e35537d JW |
4881 | { |
4882 | gas_assert (insn.insn_mo->pinfo != INSN_MACRO); | |
4883 | append_insn (&insn, &imm_expr, imm_reloc); | |
4884 | } | |
4885 | ||
4886 | *input_line_pointer = save_c; | |
4887 | demand_empty_rest_of_line (); | |
4888 | } | |
4889 | ||
dcd709e0 NC |
4890 | /* Update architecture and privileged elf attributes. If we don't set |
4891 | them, then try to output the default ones. */ | |
2dc8dd17 JW |
4892 | |
4893 | static void | |
8f595e9b | 4894 | riscv_write_out_attrs (void) |
2dc8dd17 | 4895 | { |
8f595e9b | 4896 | const char *arch_str, *priv_str, *p; |
dcd709e0 NC |
4897 | /* versions[0]: major version. |
4898 | versions[1]: minor version. | |
4899 | versions[2]: revision version. */ | |
8f595e9b NC |
4900 | unsigned versions[3] = {0}, number = 0; |
4901 | unsigned int i; | |
2dc8dd17 | 4902 | |
dcd709e0 | 4903 | /* Re-write architecture elf attribute. */ |
40f1a1a4 | 4904 | arch_str = riscv_rps_as.subset_list->arch_str; |
a1d1634d AM |
4905 | if (!bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str)) |
4906 | as_fatal (_("error adding attribute: %s"), | |
4907 | bfd_errmsg (bfd_get_error ())); | |
8f595e9b NC |
4908 | |
4909 | /* For the file without any instruction, we don't set the default_priv_spec | |
dcd709e0 NC |
4910 | according to the privileged elf attributes since the md_assemble isn't |
4911 | called. */ | |
8f595e9b NC |
4912 | if (!start_assemble |
4913 | && !riscv_set_default_priv_spec (NULL)) | |
4914 | return; | |
4915 | ||
dcd709e0 NC |
4916 | /* If we already have set privileged elf attributes, then no need to do |
4917 | anything. Otherwise, don't generate or update them when no CSR and | |
4918 | privileged instructions are used. */ | |
1a79004f | 4919 | if (!explicit_priv_attr) |
3fc6c3dc NC |
4920 | return; |
4921 | ||
3d73d29e | 4922 | RISCV_GET_PRIV_SPEC_NAME (priv_str, default_priv_spec); |
8f595e9b NC |
4923 | p = priv_str; |
4924 | for (i = 0; *p; ++p) | |
4925 | { | |
4926 | if (*p == '.' && i < 3) | |
4927 | { | |
4928 | versions[i++] = number; | |
4929 | number = 0; | |
4930 | } | |
4931 | else if (ISDIGIT (*p)) | |
4932 | number = (number * 10) + (*p - '0'); | |
4933 | else | |
4934 | { | |
b800637e | 4935 | as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str); |
8f595e9b NC |
4936 | return; |
4937 | } | |
4938 | } | |
4939 | versions[i] = number; | |
4940 | ||
dcd709e0 | 4941 | /* Re-write privileged elf attributes. */ |
a1d1634d AM |
4942 | if (!bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, |
4943 | versions[0]) | |
4944 | || !bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, | |
4945 | versions[1]) | |
4946 | || !bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, | |
4947 | versions[2])) | |
4948 | as_fatal (_("error adding attribute: %s"), | |
4949 | bfd_errmsg (bfd_get_error ())); | |
2dc8dd17 JW |
4950 | } |
4951 | ||
dcd709e0 | 4952 | /* Add the default contents for the .riscv.attributes section. */ |
2dc8dd17 JW |
4953 | |
4954 | static void | |
4955 | riscv_set_public_attributes (void) | |
4956 | { | |
8f595e9b NC |
4957 | if (riscv_opts.arch_attr || explicit_attr) |
4958 | riscv_write_out_attrs (); | |
2dc8dd17 JW |
4959 | } |
4960 | ||
f1cd8b94 KLC |
4961 | /* Scan uleb128 subtraction expressions and insert fixups for them. |
4962 | e.g., .uleb128 .L1 - .L0 | |
4963 | Because relaxation may change the value of the subtraction, we | |
4964 | must resolve them at link-time. */ | |
4965 | ||
4966 | static void | |
4967 | riscv_insert_uleb128_fixes (bfd *abfd ATTRIBUTE_UNUSED, | |
4968 | asection *sec, void *xxx ATTRIBUTE_UNUSED) | |
4969 | { | |
4970 | segment_info_type *seginfo = seg_info (sec); | |
4971 | struct frag *fragP; | |
4972 | ||
4973 | subseg_set (sec, 0); | |
4974 | ||
4975 | for (fragP = seginfo->frchainP->frch_root; | |
4976 | fragP; fragP = fragP->fr_next) | |
4977 | { | |
4978 | expressionS *exp, *exp_dup; | |
4979 | ||
4980 | if (fragP->fr_type != rs_leb128 || fragP->fr_symbol == NULL) | |
4981 | continue; | |
4982 | ||
4983 | exp = symbol_get_value_expression (fragP->fr_symbol); | |
4984 | ||
4985 | if (exp->X_op != O_subtract) | |
4986 | continue; | |
4987 | ||
4988 | /* Only unsigned leb128 can be handled. */ | |
4989 | gas_assert (fragP->fr_subtype == 0); | |
4990 | exp_dup = xmemdup (exp, sizeof (*exp), sizeof (*exp)); | |
4991 | exp_dup->X_op = O_symbol; | |
4992 | exp_dup->X_op_symbol = NULL; | |
4993 | ||
4994 | /* Insert relocations to resolve the subtraction at link-time. | |
4995 | Emit the SET relocation first in riscv. */ | |
4996 | exp_dup->X_add_symbol = exp->X_add_symbol; | |
4997 | fix_new_exp (fragP, fragP->fr_fix, 0, | |
4998 | exp_dup, 0, BFD_RELOC_RISCV_SET_ULEB128); | |
4999 | exp_dup->X_add_symbol = exp->X_op_symbol; | |
5000 | fix_new_exp (fragP, fragP->fr_fix, 0, | |
5001 | exp_dup, 0, BFD_RELOC_RISCV_SUB_ULEB128); | |
dc63d568 | 5002 | free ((void *) exp_dup); |
f1cd8b94 KLC |
5003 | } |
5004 | } | |
5005 | ||
2dc8dd17 JW |
5006 | /* Called after all assembly has been done. */ |
5007 | ||
5008 | void | |
ed2917de | 5009 | riscv_md_finish (void) |
2dc8dd17 JW |
5010 | { |
5011 | riscv_set_public_attributes (); | |
f1cd8b94 KLC |
5012 | if (riscv_opts.relax) |
5013 | bfd_map_over_sections (stdoutput, riscv_insert_uleb128_fixes, NULL); | |
2dc8dd17 JW |
5014 | } |
5015 | ||
9b9b1092 NC |
5016 | /* Adjust the symbol table. */ |
5017 | ||
5018 | void | |
5019 | riscv_adjust_symtab (void) | |
5020 | { | |
5021 | bfd_map_over_sections (stdoutput, riscv_check_mapping_symbols, (char *) 0); | |
5022 | elf_adjust_symtab (); | |
5023 | } | |
5024 | ||
2dc8dd17 JW |
5025 | /* Given a symbolic attribute NAME, return the proper integer value. |
5026 | Returns -1 if the attribute is not known. */ | |
5027 | ||
5028 | int | |
5029 | riscv_convert_symbolic_attribute (const char *name) | |
5030 | { | |
5031 | static const struct | |
5032 | { | |
1942a048 NC |
5033 | const char *name; |
5034 | const int tag; | |
2dc8dd17 JW |
5035 | } |
5036 | attribute_table[] = | |
1942a048 NC |
5037 | { |
5038 | /* When you modify this table you should | |
5039 | also modify the list in doc/c-riscv.texi. */ | |
5040 | #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag} | |
5041 | T(arch), | |
5042 | T(priv_spec), | |
5043 | T(priv_spec_minor), | |
5044 | T(priv_spec_revision), | |
5045 | T(unaligned_access), | |
5046 | T(stack_align), | |
2dc8dd17 | 5047 | #undef T |
1942a048 | 5048 | }; |
2dc8dd17 JW |
5049 | |
5050 | if (name == NULL) | |
5051 | return -1; | |
5052 | ||
1942a048 | 5053 | unsigned int i; |
2dc8dd17 JW |
5054 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
5055 | if (strcmp (name, attribute_table[i].name) == 0) | |
5056 | return attribute_table[i].tag; | |
5057 | ||
5058 | return -1; | |
5059 | } | |
5060 | ||
5061 | /* Parse a .attribute directive. */ | |
5062 | ||
5063 | static void | |
5064 | s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) | |
5065 | { | |
5066 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); | |
8f595e9b NC |
5067 | unsigned old_xlen; |
5068 | obj_attribute *attr; | |
2dc8dd17 | 5069 | |
5b7c81bd | 5070 | explicit_attr = true; |
8f595e9b | 5071 | switch (tag) |
2dc8dd17 | 5072 | { |
8f595e9b NC |
5073 | case Tag_RISCV_arch: |
5074 | old_xlen = xlen; | |
2dc8dd17 JW |
5075 | attr = elf_known_obj_attributes_proc (stdoutput); |
5076 | if (!start_assemble) | |
5077 | riscv_set_arch (attr[Tag_RISCV_arch].s); | |
5078 | else | |
b800637e NC |
5079 | as_fatal (_("architecture elf attributes must set before " |
5080 | "any instructions")); | |
2dc8dd17 JW |
5081 | |
5082 | if (old_xlen != xlen) | |
5083 | { | |
5084 | /* We must re-init bfd again if xlen is changed. */ | |
5085 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
5086 | bfd_find_target (riscv_target_format (), stdoutput); | |
5087 | ||
5088 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
b800637e | 5089 | as_warn (_("could not set architecture and machine")); |
2dc8dd17 | 5090 | } |
8f595e9b NC |
5091 | break; |
5092 | ||
5093 | case Tag_RISCV_priv_spec: | |
5094 | case Tag_RISCV_priv_spec_minor: | |
5095 | case Tag_RISCV_priv_spec_revision: | |
5096 | if (start_assemble) | |
b800637e NC |
5097 | as_fatal (_("privileged elf attributes must set before " |
5098 | "any instructions")); | |
8f595e9b NC |
5099 | break; |
5100 | ||
5101 | default: | |
5102 | break; | |
2dc8dd17 JW |
5103 | } |
5104 | } | |
5105 | ||
8155b853 NC |
5106 | /* Mark symbol that it follows a variant CC convention. */ |
5107 | ||
5108 | static void | |
5109 | s_variant_cc (int ignored ATTRIBUTE_UNUSED) | |
5110 | { | |
5111 | char *name; | |
5112 | char c; | |
5113 | symbolS *sym; | |
5114 | asymbol *bfdsym; | |
5115 | elf_symbol_type *elfsym; | |
5116 | ||
5117 | c = get_symbol_name (&name); | |
5118 | if (!*name) | |
5119 | as_bad (_("missing symbol name for .variant_cc directive")); | |
5120 | sym = symbol_find_or_make (name); | |
5121 | restore_line_pointer (c); | |
5122 | demand_empty_rest_of_line (); | |
5123 | ||
5124 | bfdsym = symbol_get_bfdsym (sym); | |
5125 | elfsym = elf_symbol_from (bfdsym); | |
5126 | gas_assert (elfsym); | |
5127 | elfsym->internal_elf_sym.st_other |= STO_RISCV_VARIANT_CC; | |
5128 | } | |
5129 | ||
5130 | /* Same as elf_copy_symbol_attributes, but without copying st_other. | |
5131 | This is needed so RISC-V specific st_other values can be independently | |
5132 | specified for an IFUNC resolver (that is called by the dynamic linker) | |
5133 | and the symbol it resolves (aliased to the resolver). In particular, | |
5134 | if a function symbol has special st_other value set via directives, | |
5135 | then attaching an IFUNC resolver to that symbol should not override | |
5136 | the st_other setting. Requiring the directive on the IFUNC resolver | |
5137 | symbol would be unexpected and problematic in C code, where the two | |
5138 | symbols appear as two independent function declarations. */ | |
5139 | ||
5140 | void | |
5141 | riscv_elf_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
5142 | { | |
5143 | struct elf_obj_sy *srcelf = symbol_get_obj (src); | |
5144 | struct elf_obj_sy *destelf = symbol_get_obj (dest); | |
a3a7f5e1 FS |
5145 | /* If size is unset, copy size from src. Because we don't track whether |
5146 | .size has been used, we can't differentiate .size dest, 0 from the case | |
5147 | where dest's size is unset. */ | |
5148 | if (!destelf->size && S_GET_SIZE (dest) == 0) | |
8155b853 | 5149 | { |
a3a7f5e1 FS |
5150 | if (srcelf->size) |
5151 | { | |
5152 | destelf->size = XNEW (expressionS); | |
5153 | *destelf->size = *srcelf->size; | |
5154 | } | |
5155 | S_SET_SIZE (dest, S_GET_SIZE (src)); | |
8155b853 | 5156 | } |
8155b853 NC |
5157 | } |
5158 | ||
dcd709e0 | 5159 | /* RISC-V pseudo-ops table. */ |
e23eba97 NC |
5160 | static const pseudo_typeS riscv_pseudo_table[] = |
5161 | { | |
e23eba97 NC |
5162 | {"option", s_riscv_option, 0}, |
5163 | {"half", cons, 2}, | |
5164 | {"word", cons, 4}, | |
5165 | {"dword", cons, 8}, | |
5166 | {"dtprelword", s_dtprel, 4}, | |
5167 | {"dtpreldword", s_dtprel, 8}, | |
5168 | {"bss", s_bss, 0}, | |
e23eba97 NC |
5169 | {"uleb128", s_riscv_leb128, 0}, |
5170 | {"sleb128", s_riscv_leb128, 1}, | |
0e35537d | 5171 | {"insn", s_riscv_insn, 0}, |
2dc8dd17 | 5172 | {"attribute", s_riscv_attribute, 0}, |
8155b853 | 5173 | {"variant_cc", s_variant_cc, 0}, |
035784e3 | 5174 | {"float16", float_cons, 'h'}, |
e23eba97 NC |
5175 | |
5176 | { NULL, NULL, 0 }, | |
5177 | }; | |
5178 | ||
5179 | void | |
5180 | riscv_pop_insert (void) | |
5181 | { | |
5182 | extern void pop_insert (const pseudo_typeS *); | |
5183 | ||
5184 | pop_insert (riscv_pseudo_table); | |
5185 | } |