]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - gdb/rl78-tdep.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
GDB copyright headers update after running GDB's copyright.py script.
[thirdparty/binutils-gdb.git] / gdb / rl78-tdep.c
CommitLineData
9058f767
KB		 1/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
2
618f726f 3 Copyright (C) 2011-2016 Free Software Foundation, Inc.
9058f767
KB		 4
5 Contributed by Red Hat, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "prologue-value.h"
25#include "target.h"
26#include "regcache.h"
27#include "opcode/rl78.h"
28#include "dis-asm.h"
29#include "gdbtypes.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "value.h"
34#include "gdbcore.h"
35#include "dwarf2-frame.h"
c47a44f4 36#include "reggroups.h"
9058f767
KB		 37
38#include "elf/rl78.h"
39#include "elf-bfd.h"
40
41/* Register Banks. */
42
43enum
44{
45 RL78_BANK0 = 0,
46 RL78_BANK1 = 1,
47 RL78_BANK2 = 2,
48 RL78_BANK3 = 3,
49 RL78_NUMBANKS = 4,
50 RL78_REGS_PER_BANK = 8
51};
52
53/* Register Numbers. */
54
55enum
56{
57 /* All general purpose registers are 8 bits wide. */
c47a44f4
KB		 58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
66
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
75
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
84
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
93
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
ba89f962 97 RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
c47a44f4
KB		 98
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
104
105 RL78_NUM_REGS,
106
107 /* Pseudo registers. */
ba89f962
KB		 108 RL78_PC_REGNUM = RL78_NUM_REGS,
109 RL78_SP_REGNUM,
c47a44f4
KB		 110
111 RL78_X_REGNUM,
112 RL78_A_REGNUM,
113 RL78_C_REGNUM,
114 RL78_B_REGNUM,
115 RL78_E_REGNUM,
116 RL78_D_REGNUM,
117 RL78_L_REGNUM,
118 RL78_H_REGNUM,
119
120 RL78_AX_REGNUM,
121 RL78_BC_REGNUM,
122 RL78_DE_REGNUM,
123 RL78_HL_REGNUM,
124
125 RL78_BANK0_R0_REGNUM,
9058f767
KB		 126 RL78_BANK0_R1_REGNUM,
127 RL78_BANK0_R2_REGNUM,
128 RL78_BANK0_R3_REGNUM,
129 RL78_BANK0_R4_REGNUM,
130 RL78_BANK0_R5_REGNUM,
131 RL78_BANK0_R6_REGNUM,
132 RL78_BANK0_R7_REGNUM,
133
134 RL78_BANK1_R0_REGNUM,
135 RL78_BANK1_R1_REGNUM,
136 RL78_BANK1_R2_REGNUM,
137 RL78_BANK1_R3_REGNUM,
138 RL78_BANK1_R4_REGNUM,
139 RL78_BANK1_R5_REGNUM,
140 RL78_BANK1_R6_REGNUM,
141 RL78_BANK1_R7_REGNUM,
142
143 RL78_BANK2_R0_REGNUM,
144 RL78_BANK2_R1_REGNUM,
145 RL78_BANK2_R2_REGNUM,
146 RL78_BANK2_R3_REGNUM,
147 RL78_BANK2_R4_REGNUM,
148 RL78_BANK2_R5_REGNUM,
149 RL78_BANK2_R6_REGNUM,
150 RL78_BANK2_R7_REGNUM,
151
152 RL78_BANK3_R0_REGNUM,
153 RL78_BANK3_R1_REGNUM,
154 RL78_BANK3_R2_REGNUM,
155 RL78_BANK3_R3_REGNUM,
156 RL78_BANK3_R4_REGNUM,
157 RL78_BANK3_R5_REGNUM,
158 RL78_BANK3_R6_REGNUM,
159 RL78_BANK3_R7_REGNUM,
160
c47a44f4 161 RL78_BANK0_RP0_REGNUM,
9058f767
KB		 162 RL78_BANK0_RP1_REGNUM,
163 RL78_BANK0_RP2_REGNUM,
164 RL78_BANK0_RP3_REGNUM,
165
166 RL78_BANK1_RP0_REGNUM,
167 RL78_BANK1_RP1_REGNUM,
168 RL78_BANK1_RP2_REGNUM,
169 RL78_BANK1_RP3_REGNUM,
170
171 RL78_BANK2_RP0_REGNUM,
172 RL78_BANK2_RP1_REGNUM,
173 RL78_BANK2_RP2_REGNUM,
174 RL78_BANK2_RP3_REGNUM,
175
176 RL78_BANK3_RP0_REGNUM,
177 RL78_BANK3_RP1_REGNUM,
178 RL78_BANK3_RP2_REGNUM,
179 RL78_BANK3_RP3_REGNUM,
180
6d451942
KB		 181 /* These are the same as the above 16 registers, but have
182 a pointer type for use as base registers in expression
183 evaluation. These are not user visible registers. */
184 RL78_BANK0_RP0_PTR_REGNUM,
185 RL78_BANK0_RP1_PTR_REGNUM,
186 RL78_BANK0_RP2_PTR_REGNUM,
187 RL78_BANK0_RP3_PTR_REGNUM,
188
189 RL78_BANK1_RP0_PTR_REGNUM,
190 RL78_BANK1_RP1_PTR_REGNUM,
191 RL78_BANK1_RP2_PTR_REGNUM,
192 RL78_BANK1_RP3_PTR_REGNUM,
193
194 RL78_BANK2_RP0_PTR_REGNUM,
195 RL78_BANK2_RP1_PTR_REGNUM,
196 RL78_BANK2_RP2_PTR_REGNUM,
197 RL78_BANK2_RP3_PTR_REGNUM,
198
199 RL78_BANK3_RP0_PTR_REGNUM,
200 RL78_BANK3_RP1_PTR_REGNUM,
201 RL78_BANK3_RP2_PTR_REGNUM,
202 RL78_BANK3_RP3_PTR_REGNUM,
203
9058f767
KB		 204 RL78_NUM_TOTAL_REGS,
205 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
206};
207
0bca7f99
KB		 208#define RL78_SP_ADDR 0xffff8
209
9058f767
KB		 210/* Architecture specific data. */
211
212struct gdbarch_tdep
213{
214 /* The ELF header flags specify the multilib used. */
215 int elf_flags;
216
217 struct type *rl78_void,
218 *rl78_uint8,
219 *rl78_int8,
220 *rl78_uint16,
221 *rl78_int16,
222 *rl78_uint32,
223 *rl78_int32,
224 *rl78_data_pointer,
e6280369
KB		 225 *rl78_code_pointer,
226 *rl78_psw_type;
9058f767
KB		 227};
228
229/* This structure holds the results of a prologue analysis. */
230
231struct rl78_prologue
232{
233 /* The offset from the frame base to the stack pointer --- always
234 zero or negative.
235
236 Calling this a "size" is a bit misleading, but given that the
237 stack grows downwards, using offsets for everything keeps one
238 from going completely sign-crazy: you never change anything's
239 sign for an ADD instruction; always change the second operand's
240 sign for a SUB instruction; and everything takes care of
241 itself. */
242 int frame_size;
243
244 /* Non-zero if this function has initialized the frame pointer from
245 the stack pointer, zero otherwise. */
246 int has_frame_ptr;
247
248 /* If has_frame_ptr is non-zero, this is the offset from the frame
249 base to where the frame pointer points. This is always zero or
250 negative. */
251 int frame_ptr_offset;
252
253 /* The address of the first instruction at which the frame has been
254 set up and the arguments are where the debug info says they are
255 --- as best as we can tell. */
256 CORE_ADDR prologue_end;
257
258 /* reg_offset[R] is the offset from the CFA at which register R is
259 saved, or 1 if register R has not been saved. (Real values are
260 always zero or negative.) */
261 int reg_offset[RL78_NUM_TOTAL_REGS];
262};
263
264/* Implement the "register_type" gdbarch method. */
265
266static struct type *
267rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
268{
269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
270
271 if (reg_nr == RL78_PC_REGNUM)
272 return tdep->rl78_code_pointer;
ba89f962
KB		 273 else if (reg_nr == RL78_RAW_PC_REGNUM)
274 return tdep->rl78_uint32;
e6280369
KB		 275 else if (reg_nr == RL78_PSW_REGNUM)
276 return (tdep->rl78_psw_type);
9058f767 277 else if (reg_nr <= RL78_MEM_REGNUM
c47a44f4
KB		 278 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
279 || (RL78_BANK0_R0_REGNUM <= reg_nr
280 && reg_nr <= RL78_BANK3_R7_REGNUM))
9058f767 281 return tdep->rl78_int8;
6d451942
KB		 282 else if (reg_nr == RL78_SP_REGNUM
283 || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
284 && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
9058f767 285 return tdep->rl78_data_pointer;
6d451942
KB		 286 else
287 return tdep->rl78_int16;
9058f767
KB		 288}
289
290/* Implement the "register_name" gdbarch method. */
291
292static const char *
293rl78_register_name (struct gdbarch *gdbarch, int regnr)
294{
295 static const char *const reg_names[] =
296 {
c47a44f4
KB		 297 "", /* bank0_r0 */
298 "", /* bank0_r1 */
299 "", /* bank0_r2 */
300 "", /* bank0_r3 */
301 "", /* bank0_r4 */
302 "", /* bank0_r5 */
303 "", /* bank0_r6 */
304 "", /* bank0_r7 */
305
306 "", /* bank1_r0 */
307 "", /* bank1_r1 */
308 "", /* bank1_r2 */
309 "", /* bank1_r3 */
310 "", /* bank1_r4 */
311 "", /* bank1_r5 */
312 "", /* bank1_r6 */
313 "", /* bank1_r7 */
314
315 "", /* bank2_r0 */
316 "", /* bank2_r1 */
317 "", /* bank2_r2 */
318 "", /* bank2_r3 */
319 "", /* bank2_r4 */
320 "", /* bank2_r5 */
321 "", /* bank2_r6 */
322 "", /* bank2_r7 */
323
324 "", /* bank3_r0 */
325 "", /* bank3_r1 */
326 "", /* bank3_r2 */
327 "", /* bank3_r3 */
328 "", /* bank3_r4 */
329 "", /* bank3_r5 */
330 "", /* bank3_r6 */
331 "", /* bank3_r7 */
332
333 "psw",
334 "es",
335 "cs",
ba89f962 336 "",
c47a44f4
KB		 337
338 "", /* spl */
339 "", /* sph */
340 "pmc",
341 "mem",
342
ba89f962 343 "pc",
c47a44f4
KB		 344 "sp",
345
346 "x",
347 "a",
348 "c",
349 "b",
350 "e",
351 "d",
352 "l",
353 "h",
354
355 "ax",
356 "bc",
357 "de",
358 "hl",
359
9058f767
KB		 360 "bank0_r0",
361 "bank0_r1",
362 "bank0_r2",
363 "bank0_r3",
364 "bank0_r4",
365 "bank0_r5",
366 "bank0_r6",
367 "bank0_r7",
368
369 "bank1_r0",
370 "bank1_r1",
371 "bank1_r2",
372 "bank1_r3",
373 "bank1_r4",
374 "bank1_r5",
375 "bank1_r6",
376 "bank1_r7",
377
378 "bank2_r0",
379 "bank2_r1",
380 "bank2_r2",
381 "bank2_r3",
382 "bank2_r4",
383 "bank2_r5",
384 "bank2_r6",
385 "bank2_r7",
386
387 "bank3_r0",
388 "bank3_r1",
389 "bank3_r2",
390 "bank3_r3",
391 "bank3_r4",
392 "bank3_r5",
393 "bank3_r6",
394 "bank3_r7",
395
9058f767
KB		 396 "bank0_rp0",
397 "bank0_rp1",
398 "bank0_rp2",
399 "bank0_rp3",
400
401 "bank1_rp0",
402 "bank1_rp1",
403 "bank1_rp2",
404 "bank1_rp3",
405
406 "bank2_rp0",
407 "bank2_rp1",
408 "bank2_rp2",
409 "bank2_rp3",
410
411 "bank3_rp0",
412 "bank3_rp1",
413 "bank3_rp2",
6d451942
KB		 414 "bank3_rp3",
415
416 /* The 16 register slots would be named
417 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
418 want these to be user visible registers. */
419 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
c47a44f4 420 };
9058f767 421
c47a44f4
KB		 422 return reg_names[regnr];
423}
9058f767 424
bc3c6b36
KB		 425/* Implement the "register_name" gdbarch method for the g10 variant. */
426
427static const char *
428rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
429{
430 static const char *const reg_names[] =
431 {
432 "", /* bank0_r0 */
433 "", /* bank0_r1 */
434 "", /* bank0_r2 */
435 "", /* bank0_r3 */
436 "", /* bank0_r4 */
437 "", /* bank0_r5 */
438 "", /* bank0_r6 */
439 "", /* bank0_r7 */
440
441 "", /* bank1_r0 */
442 "", /* bank1_r1 */
443 "", /* bank1_r2 */
444 "", /* bank1_r3 */
445 "", /* bank1_r4 */
446 "", /* bank1_r5 */
447 "", /* bank1_r6 */
448 "", /* bank1_r7 */
449
450 "", /* bank2_r0 */
451 "", /* bank2_r1 */
452 "", /* bank2_r2 */
453 "", /* bank2_r3 */
454 "", /* bank2_r4 */
455 "", /* bank2_r5 */
456 "", /* bank2_r6 */
457 "", /* bank2_r7 */
458
459 "", /* bank3_r0 */
460 "", /* bank3_r1 */
461 "", /* bank3_r2 */
462 "", /* bank3_r3 */
463 "", /* bank3_r4 */
464 "", /* bank3_r5 */
465 "", /* bank3_r6 */
466 "", /* bank3_r7 */
467
468 "psw",
469 "es",
470 "cs",
471 "",
472
473 "", /* spl */
474 "", /* sph */
475 "pmc",
476 "mem",
477
478 "pc",
479 "sp",
480
481 "x",
482 "a",
483 "c",
484 "b",
485 "e",
486 "d",
487 "l",
488 "h",
489
490 "ax",
491 "bc",
492 "de",
493 "hl",
494
495 "bank0_r0",
496 "bank0_r1",
497 "bank0_r2",
498 "bank0_r3",
499 "bank0_r4",
500 "bank0_r5",
501 "bank0_r6",
502 "bank0_r7",
503
504 "",
505 "",
506 "",
507 "",
508 "",
509 "",
510 "",
511 "",
512
513 "",
514 "",
515 "",
516 "",
517 "",
518 "",
519 "",
520 "",
521
522 "",
523 "",
524 "",
525 "",
526 "",
527 "",
528 "",
529 "",
530
531 "bank0_rp0",
532 "bank0_rp1",
533 "bank0_rp2",
534 "bank0_rp3",
535
536 "",
537 "",
538 "",
539 "",
540
541 "",
542 "",
543 "",
544 "",
545
546 "",
547 "",
548 "",
6d451942
KB		 549 "",
550
551 /* The 16 register slots would be named
552 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
553 want these to be user visible registers. */
554 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
bc3c6b36
KB		 555 };
556
557 return reg_names[regnr];
558}
559
c47a44f4 560/* Implement the "register_reggroup_p" gdbarch method. */
9058f767 561
c47a44f4
KB		 562static int
563rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
564 struct reggroup *group)
565{
566 if (group == all_reggroup)
567 return 1;
9058f767 568
c47a44f4
KB		 569 /* All other registers are saved and restored. */
570 if (group == save_reggroup || group == restore_reggroup)
571 {
b3ce41ea 572 if ((regnum < RL78_NUM_REGS
ba89f962
KB		 573 && regnum != RL78_SPL_REGNUM
574 && regnum != RL78_SPH_REGNUM
575 && regnum != RL78_RAW_PC_REGNUM)
576 || regnum == RL78_SP_REGNUM
577 || regnum == RL78_PC_REGNUM)
c47a44f4
KB		 578 return 1;
579 else
580 return 0;
581 }
582
583 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
584 || regnum == RL78_ES_REGNUM
585 || regnum == RL78_CS_REGNUM
586 || regnum == RL78_SPL_REGNUM
587 || regnum == RL78_SPH_REGNUM
588 || regnum == RL78_PMC_REGNUM
589 || regnum == RL78_MEM_REGNUM
ba89f962 590 || regnum == RL78_RAW_PC_REGNUM
c47a44f4
KB		 591 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
592 return group == system_reggroup;
593
594 return group == general_reggroup;
9058f767
KB		 595}
596
597/* Strip bits to form an instruction address. (When fetching a
598 32-bit address from the stack, the high eight bits are garbage.
599 This function strips off those unused bits.) */
600
601static CORE_ADDR
602rl78_make_instruction_address (CORE_ADDR addr)
603{
604 return addr & 0xffffff;
605}
606
607/* Set / clear bits necessary to make a data address. */
608
609static CORE_ADDR
610rl78_make_data_address (CORE_ADDR addr)
611{
612 return (addr & 0xffff) | 0xf0000;
613}
614
615/* Implement the "pseudo_register_read" gdbarch method. */
616
617static enum register_status
618rl78_pseudo_register_read (struct gdbarch *gdbarch,
619 struct regcache *regcache,
620 int reg, gdb_byte *buffer)
621{
622 enum register_status status;
623
c47a44f4
KB		 624 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
625 {
626 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
627 + (reg - RL78_BANK0_R0_REGNUM);
628
629 status = regcache_raw_read (regcache, raw_regnum, buffer);
630 }
631 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 632 {
633 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 634 + RL78_RAW_BANK0_R0_REGNUM;
9058f767 635
6d451942
KB		 636 status = regcache_raw_read (regcache, raw_regnum, buffer);
637 if (status == REG_VALID)
638 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
639 }
640 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
641 {
642 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
643 + RL78_RAW_BANK0_R0_REGNUM;
644
9058f767
KB		 645 status = regcache_raw_read (regcache, raw_regnum, buffer);
646 if (status == REG_VALID)
647 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
648 }
649 else if (reg == RL78_SP_REGNUM)
650 {
651 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
652 if (status == REG_VALID)
653 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
654 }
ba89f962
KB		 655 else if (reg == RL78_PC_REGNUM)
656 {
657 gdb_byte rawbuf[4];
658
659 status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
660 memcpy (buffer, rawbuf, 3);
661 }
9058f767
KB		 662 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
663 {
664 ULONGEST psw;
665
666 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
667 if (status == REG_VALID)
668 {
669 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
670 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 671 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 672 + (reg - RL78_X_REGNUM);
673 status = regcache_raw_read (regcache, raw_regnum, buffer);
674 }
675 }
676 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
677 {
678 ULONGEST psw;
679
680 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
681 if (status == REG_VALID)
682 {
683 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
684 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 685 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 686 + 2 * (reg - RL78_AX_REGNUM);
687 status = regcache_raw_read (regcache, raw_regnum, buffer);
688 if (status == REG_VALID)
689 status = regcache_raw_read (regcache, raw_regnum + 1,
690 buffer + 1);
691 }
692 }
693 else
694 gdb_assert_not_reached ("invalid pseudo register number");
695 return status;
696}
697
698/* Implement the "pseudo_register_write" gdbarch method. */
699
700static void
701rl78_pseudo_register_write (struct gdbarch *gdbarch,
702 struct regcache *regcache,
703 int reg, const gdb_byte *buffer)
704{
c47a44f4
KB		 705 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
706 {
707 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
708 + (reg - RL78_BANK0_R0_REGNUM);
709
710 regcache_raw_write (regcache, raw_regnum, buffer);
711 }
712 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 713 {
714 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 715 + RL78_RAW_BANK0_R0_REGNUM;
9058f767 716
6d451942
KB		 717 regcache_raw_write (regcache, raw_regnum, buffer);
718 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
719 }
720 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
721 {
722 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
723 + RL78_RAW_BANK0_R0_REGNUM;
724
9058f767
KB		 725 regcache_raw_write (regcache, raw_regnum, buffer);
726 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
727 }
728 else if (reg == RL78_SP_REGNUM)
729 {
730 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
731 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
732 }
ba89f962
KB		 733 else if (reg == RL78_PC_REGNUM)
734 {
735 gdb_byte rawbuf[4];
736
737 memcpy (rawbuf, buffer, 3);
738 rawbuf[3] = 0;
739 regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
740 }
9058f767
KB		 741 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
742 {
743 ULONGEST psw;
744 int bank;
745 int raw_regnum;
746
747 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
748 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
749 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 750 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 751 + (reg - RL78_X_REGNUM);
752 regcache_raw_write (regcache, raw_regnum, buffer);
753 }
754 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
755 {
756 ULONGEST psw;
757 int bank, raw_regnum;
758
759 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
760 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
761 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 762 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 763 + 2 * (reg - RL78_AX_REGNUM);
764 regcache_raw_write (regcache, raw_regnum, buffer);
765 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
766 }
767 else
768 gdb_assert_not_reached ("invalid pseudo register number");
769}
770
771/* Implement the "breakpoint_from_pc" gdbarch method. */
772
693be288 773static const gdb_byte *
9058f767
KB		 774rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
775 int *lenptr)
776{
777 /* The documented BRK instruction is actually a two byte sequence,
778 {0x61, 0xcc}, but instructions may be as short as one byte.
779 Correspondence with Renesas revealed that the one byte sequence
780 0xff is used when a one byte breakpoint instruction is required. */
781 static gdb_byte breakpoint[] = { 0xff };
782
783 *lenptr = sizeof breakpoint;
784 return breakpoint;
785}
786
787/* Define a "handle" struct for fetching the next opcode. */
788
789struct rl78_get_opcode_byte_handle
790{
791 CORE_ADDR pc;
792};
793
0bca7f99
KB		 794static int
795opc_reg_to_gdb_regnum (int opcreg)
796{
797 switch (opcreg)
798 {
799 case RL78_Reg_X:
800 return RL78_X_REGNUM;
801 case RL78_Reg_A:
802 return RL78_A_REGNUM;
803 case RL78_Reg_C:
804 return RL78_C_REGNUM;
805 case RL78_Reg_B:
806 return RL78_B_REGNUM;
807 case RL78_Reg_E:
808 return RL78_E_REGNUM;
809 case RL78_Reg_D:
810 return RL78_D_REGNUM;
811 case RL78_Reg_L:
812 return RL78_L_REGNUM;
813 case RL78_Reg_H:
814 return RL78_H_REGNUM;
815 case RL78_Reg_AX:
816 return RL78_AX_REGNUM;
817 case RL78_Reg_BC:
818 return RL78_BC_REGNUM;
819 case RL78_Reg_DE:
820 return RL78_DE_REGNUM;
821 case RL78_Reg_HL:
822 return RL78_HL_REGNUM;
823 case RL78_Reg_SP:
824 return RL78_SP_REGNUM;
825 case RL78_Reg_PSW:
826 return RL78_PSW_REGNUM;
827 case RL78_Reg_CS:
828 return RL78_CS_REGNUM;
829 case RL78_Reg_ES:
830 return RL78_ES_REGNUM;
831 case RL78_Reg_PMC:
832 return RL78_PMC_REGNUM;
833 case RL78_Reg_MEM:
834 return RL78_MEM_REGNUM;
835 default:
836 internal_error (__FILE__, __LINE__,
837 _("Undefined mapping for opc reg %d"),
838 opcreg);
839 }
840
841 /* Not reached. */
842 return 0;
843}
844
9058f767
KB		 845/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
846 the memory address of the next byte to fetch. If successful,
847 the address in the handle is updated and the byte fetched is
848 returned as the value of the function. If not successful, -1
849 is returned. */
850
851static int
852rl78_get_opcode_byte (void *handle)
853{
19ba03f4
SM		 854 struct rl78_get_opcode_byte_handle *opcdata
855 = (struct rl78_get_opcode_byte_handle *) handle;
9058f767
KB		 856 int status;
857 gdb_byte byte;
858
859 status = target_read_memory (opcdata->pc, &byte, 1);
860 if (status == 0)
861 {
862 opcdata->pc += 1;
863 return byte;
864 }
865 else
866 return -1;
867}
868
869/* Function for finding saved registers in a 'struct pv_area'; this
870 function is passed to pv_area_scan.
871
872 If VALUE is a saved register, ADDR says it was saved at a constant
873 offset from the frame base, and SIZE indicates that the whole
874 register was saved, record its offset. */
875
876static void
877check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
878 pv_t value)
879{
880 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
881
882 if (value.kind == pvk_register
883 && value.k == 0
884 && pv_is_register (addr, RL78_SP_REGNUM)
f5656ead 885 && size == register_size (target_gdbarch (), value.reg))
9058f767
KB		 886 result->reg_offset[value.reg] = addr.k;
887}
888
889/* Analyze a prologue starting at START_PC, going no further than
890 LIMIT_PC. Fill in RESULT as appropriate. */
891
892static void
893rl78_analyze_prologue (CORE_ADDR start_pc,
894 CORE_ADDR limit_pc, struct rl78_prologue *result)
895{
896 CORE_ADDR pc, next_pc;
897 int rn;
898 pv_t reg[RL78_NUM_TOTAL_REGS];
899 struct pv_area *stack;
900 struct cleanup *back_to;
901 CORE_ADDR after_last_frame_setup_insn = start_pc;
902 int bank = 0;
903
904 memset (result, 0, sizeof (*result));
905
906 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
907 {
908 reg[rn] = pv_register (rn, 0);
909 result->reg_offset[rn] = 1;
910 }
911
f5656ead 912 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
9058f767
KB		 913 back_to = make_cleanup_free_pv_area (stack);
914
915 /* The call instruction has saved the return address on the stack. */
916 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
917 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
918
919 pc = start_pc;
920 while (pc < limit_pc)
921 {
922 int bytes_read;
923 struct rl78_get_opcode_byte_handle opcode_handle;
924 RL78_Opcode_Decoded opc;
925
926 opcode_handle.pc = pc;
927 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
0952813b 928 &opcode_handle, RL78_ISA_DEFAULT);
9058f767
KB		 929 next_pc = pc + bytes_read;
930
931 if (opc.id == RLO_sel)
932 {
933 bank = opc.op[1].addend;
934 }
935 else if (opc.id == RLO_mov
936 && opc.op[0].type == RL78_Operand_PreDec
937 && opc.op[0].reg == RL78_Reg_SP
938 && opc.op[1].type == RL78_Operand_Register)
939 {
940 int rsrc = (bank * RL78_REGS_PER_BANK)
941 + 2 * (opc.op[1].reg - RL78_Reg_AX);
942
943 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
944 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
945 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
946 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
947 after_last_frame_setup_insn = next_pc;
948 }
949 else if (opc.id == RLO_sub
950 && opc.op[0].type == RL78_Operand_Register
951 && opc.op[0].reg == RL78_Reg_SP
952 && opc.op[1].type == RL78_Operand_Immediate)
953 {
954 int addend = opc.op[1].addend;
955
956 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
957 -addend);
958 after_last_frame_setup_insn = next_pc;
959 }
0bca7f99
KB		 960 else if (opc.id == RLO_mov
961 && opc.size == RL78_Word
962 && opc.op[0].type == RL78_Operand_Register
963 && opc.op[1].type == RL78_Operand_Indirect
964 && opc.op[1].addend == RL78_SP_ADDR)
965 {
966 reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
967 = reg[RL78_SP_REGNUM];
968 }
969 else if (opc.id == RLO_sub
970 && opc.size == RL78_Word
971 && opc.op[0].type == RL78_Operand_Register
972 && opc.op[1].type == RL78_Operand_Immediate)
973 {
974 int addend = opc.op[1].addend;
975 int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
976
977 reg[regnum] = pv_add_constant (reg[regnum], -addend);
978 }
979 else if (opc.id == RLO_mov
980 && opc.size == RL78_Word
981 && opc.op[0].type == RL78_Operand_Indirect
982 && opc.op[0].addend == RL78_SP_ADDR
983 && opc.op[1].type == RL78_Operand_Register)
984 {
985 reg[RL78_SP_REGNUM]
986 = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
987 after_last_frame_setup_insn = next_pc;
988 }
9058f767
KB		 989 else
990 {
991 /* Terminate the prologue scan. */
992 break;
993 }
994
995 pc = next_pc;
996 }
997
998 /* Is the frame size (offset, really) a known constant? */
999 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
1000 result->frame_size = reg[RL78_SP_REGNUM].k;
1001
1002 /* Record where all the registers were saved. */
1003 pv_area_scan (stack, check_for_saved, (void *) result);
1004
1005 result->prologue_end = after_last_frame_setup_insn;
1006
1007 do_cleanups (back_to);
1008}
1009
1010/* Implement the "addr_bits_remove" gdbarch method. */
1011
1012static CORE_ADDR
1013rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
1014{
1015 return addr & 0xffffff;
1016}
1017
1018/* Implement the "address_to_pointer" gdbarch method. */
1019
1020static void
1021rl78_address_to_pointer (struct gdbarch *gdbarch,
1022 struct type *type, gdb_byte *buf, CORE_ADDR addr)
1023{
1024 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1025
1026 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
1027 addr & 0xffffff);
1028}
1029
1030/* Implement the "pointer_to_address" gdbarch method. */
1031
1032static CORE_ADDR
1033rl78_pointer_to_address (struct gdbarch *gdbarch,
1034 struct type *type, const gdb_byte *buf)
1035{
1036 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1037 CORE_ADDR addr
1038 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
1039
1040 /* Is it a code address? */
1041 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
1042 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
1043 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
1044 || TYPE_LENGTH (type) == 4)
1045 return rl78_make_instruction_address (addr);
1046 else
1047 return rl78_make_data_address (addr);
1048}
1049
1050/* Implement the "skip_prologue" gdbarch method. */
1051
1052static CORE_ADDR
1053rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1054{
e4569f1e 1055 const char *name;
9058f767
KB		 1056 CORE_ADDR func_addr, func_end;
1057 struct rl78_prologue p;
1058
1059 /* Try to find the extent of the function that contains PC. */
1060 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1061 return pc;
1062
1063 rl78_analyze_prologue (pc, func_end, &p);
1064 return p.prologue_end;
1065}
1066
1067/* Implement the "unwind_pc" gdbarch method. */
1068
1069static CORE_ADDR
1070rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1071{
1072 return rl78_addr_bits_remove
1073 (arch, frame_unwind_register_unsigned (next_frame,
1074 RL78_PC_REGNUM));
1075}
1076
1077/* Implement the "unwind_sp" gdbarch method. */
1078
1079static CORE_ADDR
1080rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1081{
1082 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
1083}
1084
1085/* Given a frame described by THIS_FRAME, decode the prologue of its
1086 associated function if there is not cache entry as specified by
1087 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
1088 return that struct as the value of this function. */
1089
1090static struct rl78_prologue *
1091rl78_analyze_frame_prologue (struct frame_info *this_frame,
1092 void **this_prologue_cache)
1093{
1094 if (!*this_prologue_cache)
1095 {
1096 CORE_ADDR func_start, stop_addr;
1097
1098 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
1099
1100 func_start = get_frame_func (this_frame);
1101 stop_addr = get_frame_pc (this_frame);
1102
1103 /* If we couldn't find any function containing the PC, then
1104 just initialize the prologue cache, but don't do anything. */
1105 if (!func_start)
1106 stop_addr = func_start;
1107
19ba03f4
SM		 1108 rl78_analyze_prologue (func_start, stop_addr,
1109 (struct rl78_prologue *) *this_prologue_cache);
9058f767
KB		 1110 }
1111
19ba03f4 1112 return (struct rl78_prologue *) *this_prologue_cache;
9058f767
KB		 1113}
1114
1115/* Given a frame and a prologue cache, return this frame's base. */
1116
1117static CORE_ADDR
1118rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
1119{
1120 struct rl78_prologue *p
1121 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1122 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
1123
1124 return rl78_make_data_address (sp - p->frame_size);
1125}
1126
1127/* Implement the "frame_this_id" method for unwinding frames. */
1128
1129static void
1130rl78_this_id (struct frame_info *this_frame,
1131 void **this_prologue_cache, struct frame_id *this_id)
1132{
1133 *this_id = frame_id_build (rl78_frame_base (this_frame,
1134 this_prologue_cache),
1135 get_frame_func (this_frame));
1136}
1137
1138/* Implement the "frame_prev_register" method for unwinding frames. */
1139
1140static struct value *
1141rl78_prev_register (struct frame_info *this_frame,
1142 void **this_prologue_cache, int regnum)
1143{
1144 struct rl78_prologue *p
1145 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1146 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
1147
1148 if (regnum == RL78_SP_REGNUM)
1149 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1150
1151 else if (regnum == RL78_SPL_REGNUM)
1152 return frame_unwind_got_constant (this_frame, regnum,
1153 (frame_base & 0xff));
1154
1155 else if (regnum == RL78_SPH_REGNUM)
1156 return frame_unwind_got_constant (this_frame, regnum,
1157 ((frame_base >> 8) & 0xff));
1158
1159 /* If prologue analysis says we saved this register somewhere,
1160 return a description of the stack slot holding it. */
1161 else if (p->reg_offset[regnum] != 1)
1162 {
1163 struct value *rv =
1164 frame_unwind_got_memory (this_frame, regnum,
1165 frame_base + p->reg_offset[regnum]);
1166
1167 if (regnum == RL78_PC_REGNUM)
1168 {
1169 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
1170
1171 return frame_unwind_got_constant (this_frame, regnum, pc);
1172 }
1173 return rv;
1174 }
1175
1176 /* Otherwise, presume we haven't changed the value of this
1177 register, and get it from the next frame. */
1178 else
1179 return frame_unwind_got_register (this_frame, regnum, regnum);
1180}
1181
1182static const struct frame_unwind rl78_unwind =
1183{
1184 NORMAL_FRAME,
1185 default_frame_unwind_stop_reason,
1186 rl78_this_id,
1187 rl78_prev_register,
1188 NULL,
1189 default_frame_sniffer
1190};
1191
1192/* Implement the "dwarf_reg_to_regnum" gdbarch method. */
1193
1194static int
1195rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1196{
1197 if (0 <= reg && reg <= 31)
1198 {
1199 if ((reg & 1) == 0)
6d451942
KB		 1200 /* Map even registers to their 16-bit counterparts which have a
1201 pointer type. This is usually what is required from the DWARF
1202 info. */
1203 return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
9058f767
KB		 1204 else
1205 return reg;
1206 }
1207 else if (reg == 32)
1208 return RL78_SP_REGNUM;
1209 else if (reg == 33)
b3ce41ea
KB		 1210 return -1; /* ap */
1211 else if (reg == 34)
1212 return RL78_PSW_REGNUM;
1213 else if (reg == 35)
1214 return RL78_ES_REGNUM;
1215 else if (reg == 36)
1216 return RL78_CS_REGNUM;
1217 else if (reg == 37)
9058f767
KB		 1218 return RL78_PC_REGNUM;
1219 else
0fde2c53 1220 return -1;
9058f767
KB		 1221}
1222
c47a44f4
KB		 1223/* Implement the `register_sim_regno' gdbarch method. */
1224
1225static int
1226rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1227{
1228 gdb_assert (regnum < RL78_NUM_REGS);
1229
1230 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
1231 just want to override the default here which disallows register
1232 numbers which have no names. */
1233 return regnum;
1234}
1235
9058f767
KB		 1236/* Implement the "return_value" gdbarch method. */
1237
1238static enum return_value_convention
1239rl78_return_value (struct gdbarch *gdbarch,
6a3a010b 1240 struct value *function,
9058f767
KB		 1241 struct type *valtype,
1242 struct regcache *regcache,
1243 gdb_byte *readbuf, const gdb_byte *writebuf)
1244{
1245 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1246 ULONGEST valtype_len = TYPE_LENGTH (valtype);
bc3c6b36 1247 int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10;
9058f767
KB		 1248
1249 if (valtype_len > 8)
1250 return RETURN_VALUE_STRUCT_CONVENTION;
1251
1252 if (readbuf)
1253 {
1254 ULONGEST u;
c47a44f4 1255 int argreg = RL78_RAW_BANK1_R0_REGNUM;
bc3c6b36 1256 CORE_ADDR g10_raddr = 0xffec8;
9058f767
KB		 1257 int offset = 0;
1258
1259 while (valtype_len > 0)
1260 {
bc3c6b36
KB		 1261 if (is_g10)
1262 u = read_memory_integer (g10_raddr, 1,
1263 gdbarch_byte_order (gdbarch));
1264 else
1265 regcache_cooked_read_unsigned (regcache, argreg, &u);
9058f767
KB		 1266 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
1267 valtype_len -= 1;
1268 offset += 1;
1269 argreg++;
bc3c6b36 1270 g10_raddr++;
9058f767
KB		 1271 }
1272 }
1273
1274 if (writebuf)
1275 {
1276 ULONGEST u;
c47a44f4 1277 int argreg = RL78_RAW_BANK1_R0_REGNUM;
bc3c6b36 1278 CORE_ADDR g10_raddr = 0xffec8;
9058f767
KB		 1279 int offset = 0;
1280
1281 while (valtype_len > 0)
1282 {
1283 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
bc3c6b36
KB		 1284 if (is_g10) {
1285 gdb_byte b = u & 0xff;
1286 write_memory (g10_raddr, &b, 1);
1287 }
1288 else
1289 regcache_cooked_write_unsigned (regcache, argreg, u);
9058f767
KB		 1290 valtype_len -= 1;
1291 offset += 1;
1292 argreg++;
bc3c6b36 1293 g10_raddr++;
9058f767
KB		 1294 }
1295 }
1296
1297 return RETURN_VALUE_REGISTER_CONVENTION;
1298}
1299
1300
1301/* Implement the "frame_align" gdbarch method. */
1302
1303static CORE_ADDR
1304rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1305{
1306 return rl78_make_data_address (align_down (sp, 2));
1307}
1308
1309
1310/* Implement the "dummy_id" gdbarch method. */
1311
1312static struct frame_id
1313rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1314{
1315 return
1316 frame_id_build (rl78_make_data_address
1317 (get_frame_register_unsigned
1318 (this_frame, RL78_SP_REGNUM)),
1319 get_frame_pc (this_frame));
1320}
1321
1322
1323/* Implement the "push_dummy_call" gdbarch method. */
1324
1325static CORE_ADDR
1326rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1327 struct regcache *regcache, CORE_ADDR bp_addr,
1328 int nargs, struct value **args, CORE_ADDR sp,
1329 int struct_return, CORE_ADDR struct_addr)
1330{
1331 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1332 gdb_byte buf[4];
1333 int i;
1334
1335 /* Push arguments in reverse order. */
1336 for (i = nargs - 1; i >= 0; i--)
1337 {
1338 struct type *value_type = value_enclosing_type (args[i]);
1339 int len = TYPE_LENGTH (value_type);
1340 int container_len = (len + 1) & ~1;
9058f767
KB		 1341
1342 sp -= container_len;
1343 write_memory (rl78_make_data_address (sp),
1344 value_contents_all (args[i]), len);
1345 }
1346
1347 /* Store struct value address. */
1348 if (struct_return)
1349 {
1350 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1351 sp -= 2;
1352 write_memory (rl78_make_data_address (sp), buf, 2);
1353 }
1354
1355 /* Store return address. */
1356 sp -= 4;
1357 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1358 write_memory (rl78_make_data_address (sp), buf, 4);
1359
1360 /* Finally, update the stack pointer... */
1361 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1362
1363 /* DWARF2/GCC uses the stack address *before* the function call as a
1364 frame's CFA. */
1365 return rl78_make_data_address (sp + 4);
1366}
1367
1368/* Allocate and initialize a gdbarch object. */
1369
1370static struct gdbarch *
1371rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1372{
1373 struct gdbarch *gdbarch;
1374 struct gdbarch_tdep *tdep;
1375 int elf_flags;
1376
1377 /* Extract the elf_flags if available. */
1378 if (info.abfd != NULL
1379 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1380 elf_flags = elf_elfheader (info.abfd)->e_flags;
1381 else
1382 elf_flags = 0;
1383
1384
1385 /* Try to find the architecture in the list of already defined
1386 architectures. */
1387 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1388 arches != NULL;
1389 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1390 {
1391 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1392 continue;
1393
1394 return arches->gdbarch;
1395 }
1396
1397 /* None found, create a new architecture from the information
1398 provided. */
8d749320 1399 tdep = XNEW (struct gdbarch_tdep);
9058f767
KB		 1400 gdbarch = gdbarch_alloc (&info, tdep);
1401 tdep->elf_flags = elf_flags;
1402
1403 /* Initialize types. */
1404 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1405 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1406 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1407 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1408 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1409 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1410 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1411
1412 tdep->rl78_data_pointer
1413 = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
1414 xstrdup ("rl78_data_addr_t"));
1415 TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
1416 TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
1417
1418 tdep->rl78_code_pointer
1419 = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
1420 xstrdup ("rl78_code_addr_t"));
1421 TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
1422 TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
1423
e6280369
KB		 1424 tdep->rl78_psw_type = arch_flags_type (gdbarch, "builtin_type_rl78_psw", 1);
1425 append_flags_type_flag (tdep->rl78_psw_type, 0, "CY");
1426 append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0");
1427 append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1");
1428 append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0");
1429 append_flags_type_flag (tdep->rl78_psw_type, 4, "AC");
1430 append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1");
1431 append_flags_type_flag (tdep->rl78_psw_type, 6, "Z");
1432 append_flags_type_flag (tdep->rl78_psw_type, 7, "IE");
1433
9058f767
KB		 1434 /* Registers. */
1435 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1436 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
bc3c6b36
KB		 1437 if (tdep->elf_flags & E_FLAG_RL78_G10)
1438 set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
1439 else
1440 set_gdbarch_register_name (gdbarch, rl78_register_name);
9058f767
KB		 1441 set_gdbarch_register_type (gdbarch, rl78_register_type);
1442 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1443 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1444 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1445 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1446 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
c47a44f4
KB		 1447 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1448 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
9058f767
KB		 1449
1450 /* Data types. */
1451 set_gdbarch_char_signed (gdbarch, 0);
1452 set_gdbarch_short_bit (gdbarch, 16);
1453 set_gdbarch_int_bit (gdbarch, 16);
1454 set_gdbarch_long_bit (gdbarch, 32);
1455 set_gdbarch_long_long_bit (gdbarch, 64);
1456 set_gdbarch_ptr_bit (gdbarch, 16);
1457 set_gdbarch_addr_bit (gdbarch, 32);
b3ce41ea 1458 set_gdbarch_dwarf2_addr_size (gdbarch, 4);
9058f767
KB		 1459 set_gdbarch_float_bit (gdbarch, 32);
1460 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1461 set_gdbarch_double_bit (gdbarch, 32);
1462 set_gdbarch_long_double_bit (gdbarch, 64);
1463 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1464 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1465 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1466 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1467 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1468
1469 /* Breakpoints. */
1470 set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
1471 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1472
1473 /* Disassembly. */
1474 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1475
1476 /* Frames, prologues, etc. */
1477 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1478 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1479 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1480 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1481 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
b3ce41ea
KB		 1482
1483 dwarf2_append_unwinders (gdbarch);
9058f767
KB		 1484 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1485
1486 /* Dummy frames, return values. */
1487 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1488 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1489 set_gdbarch_return_value (gdbarch, rl78_return_value);
1490
1491 /* Virtual tables. */
1492 set_gdbarch_vbit_in_delta (gdbarch, 1);
1493
1494 return gdbarch;
1495}
1496
693be288
JK		 1497/* -Wmissing-prototypes */
1498extern initialize_file_ftype _initialize_rl78_tdep;
1499
9058f767
KB		 1500/* Register the above initialization routine. */
1501
1502void
1503_initialize_rl78_tdep (void)
1504{
1505 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1506}
A mirror of the official binutils-gdb repository