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bpf: there is no ldinddw nor ldabsdw instructions
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0c45feb1
JM		 12024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
2
3 * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and
4 BPF_INSN_LDABSDW instructions.
5
e775d3a9
NC		 62024-01-15 Nick Clifton <nickc@redhat.com>
7
8 * configure: Regenerate.
9 * po/opcodes.pot: Regenerate.
10
299b91cd
NC		 112024-01-15 Nick Clifton <nickc@redhat.com>
12
13 * 2.42 branch point.
14
862776f2
AA		 152023-11-15 Arsen Arsenović <arsen@aarsen.me>
16
17 * aclocal.m4: Regenerate.
18 * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
19 temporary file to suppress xgettext checking charset names.
20 * configure.ac (SHARED_LIBADD): Use LTLIBINTL rather than
21 LIBINTL.
22 * configure: Regenerate.
23 * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
24 temporary file, to suppress xgettext checking charset names.
25
b90eb3e5
N		 262023-10-05 Neal frager <neal.frager@amd.com>
27
28 * microblaze-opcm.h (struct op_code_struct): Tidy and remove
29 redundant entries.
30 * microblaze-opc.h (MAX_OPCODES): Increase to 300.
31 (op_code_struct): Add address extension instructions.
32
6487710b
N		 332023-10-04 Neal frager <neal.frager@amd.com>
34
b90eb3e5 35 * microblaze-opc.h (struct op_code_struct): Add hiberante
6487710b
N		 36 and suspend entries.
37 * microblaze-opcm.h (enum microblaze_instr): Add microblaze_sleep,
38 hibernate, suspend entries.
39
fd669f71
TT		 402023-08-24 Tom Tromey <tom@tromey.com>
41
42 * cgen.sh: Don't pass "-s" to cgen.
43 * Makefile.in: Rebuild.
44 * Makefile.am (GUILE): Simplify.
45
b5c37946 462023-07-31 Jose E. Marchesi <jose.marchesi@oracle.com>
5b512234 47
b5c37946
SJ		 48 PR 30705
49 * bpf-dis.c (print_insn_bpf): Check that info->section->owner is
50 actually available before using it.
51
522023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
53
54 * bpf-dis.c: Initialize asm_bpf_version to -1.
55 (print_insn_bpf): Set BPF ISA version from the cpu version ELF
56 header flags if no explicit version set in the command line.
57 * disassemble.c (disassemble_init_for_target): Remove unused code.
58
592023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
60
61 * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
62 register.
63
642023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
65
66 * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
67 instructions.
68
692023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
70
71 * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
72 instructions.
73
742023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
75
76 * bpf-opc.c (bpf_opcodes): Add entry for jal.
77
782023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
79
80 * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
81 instructions.
82
832023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
84
85 * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
86 MOVS32{8,16,32}R instructions. and MOVS32I instructions.
87
882023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
89
90 * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
91 * Makefile.in: Regenerate.
386d3059 92
87485f53
NC		 932023-07-03 Nick Clifton <nickc@redhat.com>
94
95 * configure: Regenerate.
96 * po/opcodes.pot: Regenerate.
97
d501d384
NC		 982023-07-03 Nick Clifton <nickc@redhat.com>
99
100 2.41 Branch Point.
101
d595715a
NC		 1022023-05-23 Nick Clifton <nickc@redhat.com>
103
104 * po/sv.po: Updated translation.
105
da9a978a
TT		 1062023-04-21 Tom Tromey <tromey@adacore.com>
107
108 * i386-dis.c (OP_J): Check result of get16.
109
4bbb4dfb
CZ		 1102023-04-12 Claudiu Zissulescu <claziss@synopsys.com>
111
112 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
113 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
114 vsubs2h, and vsubs4h instructions.
115
37522c87
NC		 1162023-04-11 Nick Clifton <nickc@redhat.com>
117
118 PR 30310
119 * nfp-dis.c (init_nfp6000_priv): Check that the output section
120 exists.
121
71f646f2
NC		 1222023-03-15 Nick Clifton <nickc@redhat.com>
123
124 PR 30231
125 * mep-dis.c: Regenerate.
126
77186045
NC		 1272023-03-15 Nick Clifton <nickc@redhat.com>
128
129 PR 30230
130 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
131
31f2faf5
RB		 1322023-02-28 Richard Ball <richard.ball@arm.com>
133
134 * aarch64-opc.c: Add MEC system registers.
135
11982f9f
NC		 1362023-01-03 Nick Clifton <nickc@redhat.com>
137
138 * po/de.po: Updated German translation.
139 * po/ro.po: Updated Romainian translation.
140 * po/uk.po: Updated Ukrainian translation.
141
a72b0718
NC		 1422022-12-31 Nick Clifton <nickc@redhat.com>
143
144 * 2.40 branch created.
145
b2059307
SV		 1462022-11-22 Shahab Vahedi <shahab@synopsys.com>
147
148 * arc-regs.h: Change isa_config address to 0xc1.
149 isa_config exists for ARC700 and ARCV2 and not ARCALL.
150
de1fbe78
YS		 1512022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
152
153 * rx-decode.opc: Switch arguments of the MVTACGU insn.
154 * rx-decode.c: Regenerate.
155
3b8e069a
YS		 1562022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
157
158 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
159 Rm_BANK,Rn is always 1.
160
c07ec968
PB		 1612022-07-21 Peter Bergner <bergner@linux.ibm.com>
162
163 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
164 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
165 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
166 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
167 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
168 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
169 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
170
bbcab336
CZ		 1712022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
172
173 * disassemble.c (disassemble_init_for_target): Set
174 created_styled_output for ARC based targets.
175 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
176 instead of fprintf_ftype throughout.
177 (find_format): Likewise.
178 (print_flags): Likewise.
179 (print_insn_arc): Likewise.
180
0bd09323
NC		 1812022-07-08 Nick Clifton <nickc@redhat.com>
182
183 * 2.39 branch created.
184
a0f3a4c6
MN		 1852022-07-04 Marcus Nilsson <brainbomb@gmail.com>
186
187 * disassemble.c: (disassemble_init_for_target): Set
188 created_styled_output for AVR based targets.
189 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
190 instead of fprintf_ftype throughout.
191 (avr_operand): Pass in and fill disassembler_style when
192 parsing operands.
193
69341966
AK		 1942022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
195
196 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
197 table.
198
e3161106
SM		 1992022-03-16 Simon Marchi <simon.marchi@efficios.com>
200
201 * configure.ac: Handle bfd_amdgcn_arch.
202 * configure: Re-generate.
203
d17e797f
MR		 2042022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
205 Maciej W. Rozycki <macro@orcam.me.uk>
206
207 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
208 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
209 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
210 "bnez" instructions.
211
36d285b9
NC		 2122022-02-17 Nick Clifton <nickc@redhat.com>
213
214 * po/sr.po: Updated Serbian translation.
215
a532eb72
ST		 2162022-02-14 Sergei Trofimovich <siarheit@google.com>
217
218 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
219 * microblaze-opc.h: Follow 'fsqrt' rename.
220
5fe73d46
NC		 2212022-01-24 Nick Clifton <nickc@redhat.com>
222
223 * po/ro.po: Updated Romanian translation.
224 * po/uk.po: Updated Ukranian translation.
225
f908e960
NC		 2262022-01-22 Nick Clifton <nickc@redhat.com>
227
228 * configure: Regenerate.
229 * po/opcodes.pot: Regenerate.
230
a74e1cb3
NC		 2312022-01-22 Nick Clifton <nickc@redhat.com>
232
233 * 2.38 release branch created.
234
6c037fdb
NC		 2352022-01-17 Nick Clifton <nickc@redhat.com>
236
237 * Makefile.in: Regenerate.
238 * po/opcodes.pot: Regenerate.
239
96c7115a
MN		 2402021-12-02 Marcus Nilsson <brainbomb@gmail.com>
241
242 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
243 in insn_type on branching instructions.
244
3a337a86
AB		 2452021-11-25 Andrew Burgess <aburgess@redhat.com>
246 Simon Cook <simon.cook@embecosm.com>
247
248 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
249 (riscv_options): New static global.
250 (disassembler_options_riscv): New function.
251 (print_riscv_disassembler_options): Rewrite to use
252 disassembler_options_riscv.
253
7060c28e
NC		 2542021-11-25 Nick Clifton <nickc@redhat.com>
255
256 PR 28614
257 * aarch64-asm.c: Replace assert(0) with real code.
258 * aarch64-dis.c: Likewise.
259 * aarch64-opc.c: Likewise.
260
79abb939
NC		 2612021-11-25 Nick Clifton <nickc@redhat.com>
262
263 * po/fr.po; Updated French translation.
264
2b677209
MR		 2652021-10-27 Maciej W. Rozycki <macro@embecosm.com>
266
267 * Makefile.am: Remove obsolete comment.
268 * configure.ac: Refer `libbfd.la' to link shared BFD library
269 except for Cygwin.
270 * Makefile.in: Regenerate.
271 * configure: Regenerate.
272
b9004024
NA		 2732021-09-27 Nick Alcock <nick.alcock@oracle.com>
274
275 * configure: Regenerate.
276
4d5d5d46
PB		 2772021-09-25 Peter Bergner <bergner@linux.ibm.com>
278
279 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
280 on POWER5 and later.
281
6a7f5766
AB		 2822021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
283
284 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
285 before an unknown instruction, '%d' is replaced with the
286 instruction length.
287
718aefcf
NC		 2882021-09-02 Nick Clifton <nickc@redhat.com>
289
290 PR 28292
291 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
292 of BFD_RELOC_16.
293
5d9cff51
SV		 2942021-08-17 Shahab Vahedi <shahab@synopsys.com>
295
296 * arc-regs.h (DEF): Fix the register numbers.
297
3ee0cd9e
NC		 2982021-08-10 Nick Clifton <nickc@redhat.com>
299
300 * po/sr.po: Updated Serbian translation.
301
8d56b9fc
CX		 3022021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
303
304 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
305
b180e829
AK		 3062021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
307
308 * s390-opc.txt: Add qpaci.
309
346d80ef
NC		 3102021-07-03 Nick Clifton <nickc@redhat.com>
311
312 * configure: Regenerate.
313 * po/opcodes.pot: Regenerate.
314
51419248
NC		 3152021-07-03 Nick Clifton <nickc@redhat.com>
316
317 * 2.37 release branch created.
318
62194b63
AM		 3192021-07-02 Alan Modra <amodra@gmail.com>
320
321 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
322 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
323 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
324 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
325 (nds32_keyword_gpr): Move declarations to..
326 * nds32-asm.h: ..here, constifying to match definitions.
327
2fe36d31
MF		 3282021-07-01 Mike Frysinger <vapier@gentoo.org>
329
330 * Makefile.am (GUILE): New variable.
331 (CGEN): Use $(GUILE).
332 * Makefile.in: Regenerate.
333
f375d32b
MF		 3342021-07-01 Mike Frysinger <vapier@gentoo.org>
335
336 * mep-asm.c (macros): Mark static & const.
337 (lookup_macro): Change return & m to const.
338 (expand_macro): Change mac to const.
339 (expand_string): Change pmacro to const.
340
9b2beaf7
MF		 3412021-07-01 Mike Frysinger <vapier@gentoo.org>
342
343 * nds32-asm.c (operand_fields): Rename to ...
344 (nds32_operand_fields): ... this.
345 (keyword_gpr): Rename to ...
346 (nds32_keyword_gpr): ... this.
347 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
348 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
349 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
350 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
351 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
352 Mark static.
353 (keywords): Rename to ...
354 (nds32_keywords): ... this.
355 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
356 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
357
ac8ef696
MF		 3582021-07-01 Mike Frysinger <vapier@gentoo.org>
359
360 * z80-dis.c (opc_ed): Make const.
361 (pref_ed): Make p const.
362
52b83874
MF		 3632021-07-01 Mike Frysinger <vapier@gentoo.org>
364
365 * microblaze-dis.c (get_field_special): Make op const.
366 (read_insn_microblaze): Make opr & op const. Rename opcodes to
367 microblaze_opcodes.
368 (print_insn_microblaze): Make op & pop const.
369 (get_insn_microblaze): Make op const. Rename opcodes to
370 microblaze_opcodes.
371 (microblaze_get_target_address): Likewise.
372 * microblaze-opc.h (struct op_code_struct): Make const.
373 Rename opcodes to microblaze_opcodes.
374
6c2ede01
MF		 3752021-07-01 Mike Frysinger <vapier@gentoo.org>
376
377 * aarch64-gen.c (aarch64_opcode_table): Add const.
378 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
379
46b8b3d6
AB		 3802021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
381
382 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
383 available.
384
ded5cb94
AM		 3852021-06-22 Alan Modra <amodra@gmail.com>
386
387 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
388 print separator for pcrel insns.
389
47399e9c
AM		 3902021-06-19 Alan Modra <amodra@gmail.com>
391
392 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
393
d984392e
AM		 3942021-06-19 Alan Modra <amodra@gmail.com>
395
396 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
397 entire buffer.
398
7993124e
AM		 3992021-06-17 Alan Modra <amodra@gmail.com>
400
401 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
402 in table.
403
a38d1396
AM		 4042021-06-03 Alan Modra <amodra@gmail.com>
405
406 PR 1202
407 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
408 Use unsigned int for inst.
409
8f467114
SV		 4102021-06-02 Shahab Vahedi <shahab@synopsys.com>
411
412 * arc-dis.c (arc_option_arg_t): New enumeration.
413 (arc_options): New variable.
414 (disassembler_options_arc): New function.
415 (print_arc_disassembler_options): Reimplement in terms of
416 "disassembler_options_arc".
417
1ff6a3b8
AM		 4182021-05-29 Alan Modra <amodra@gmail.com>
419
420 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
421 Don't special case PPC_OPCODE_RAW.
422 (lookup_prefix): Likewise.
423 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
424 (print_insn_powerpc): ..update caller.
425 * ppc-opc.c (EXT): Define.
426 (powerpc_opcodes): Mark extended mnemonics with EXT.
427 (prefix_opcodes, vle_opcodes): Likewise.
428 (XISEL, XISEL_MASK): Add cr field and simplify.
429 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
430 all isel variants to where the base mnemonic belongs. Sort dstt,
431 dststt and dssall.
432
49149d59
MR		 4332021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
434
435 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
436 COP3 opcode instructions.
437
9573a461
MR		 4382021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
439
440 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
441 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
442 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
443 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
444 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
445 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
446 "cop2", and "cop3" entries.
447
fa495743
MR		 4482021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
449
450 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
451 entries and associated comments.
452
b930964c
MR		 4532021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
454
455 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
456 of "c0".
457
dd844468
MR		 4582021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
459
460 * mips-dis.c (mips_cp1_names_mips): New variable.
461 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
462 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
463 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
464 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
465 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
466 "loongson2f".
467
9204ccd4
MR		 4682021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
469
470 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
471 handling code over to...
472 <OP_REG_CONTROL>: ... this new case.
473 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
474 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
475 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
476 replacing the `G' operand code with `g'. Update "cftc1" and
477 "cftc2" entries replacing the `E' operand code with `y'.
478 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
479 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
480 entries replacing the `G' operand code with `g'.
481
a3fb396f
MR		 4822021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
483
484 * mips-dis.c (mips_cp0_names_r3900): New variable.
485 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
486 for "r3900".
487
cccc84fa
MR		 4882021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
489
490 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
491 and "mtthc2" to using the `G' rather than `g' operand code for
492 the coprocessor control register referred.
493
c9de3168
MR		 4942021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
495
496 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
497 entries with each other.
498
ebcab741
PB		 4992021-05-27 Peter Bergner <bergner@linux.ibm.com>
500
501 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
502
bc30a119
AM		 5032021-05-25 Alan Modra <amodra@gmail.com>
504
505 * cris-desc.c: Regenerate.
506 * cris-desc.h: Regenerate.
507 * cris-opc.h: Regenerate.
508 * po/POTFILES.in: Regenerate.
509
54711280
MF		 5102021-05-24 Mike Frysinger <vapier@gentoo.org>
511
512 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
513 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
514 (CGEN_CPUS): Add cris.
515 (CRIS_DEPS): Define.
516 (stamp-cris): New rule.
517 * cgen.sh: Handle desc action.
518 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
519 * Makefile.in, configure: Regenerate.
520
113bb761
JN		 5212021-05-18 Job Noorman <mtvec@pm.me>
522
523 PR 27814
524 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
525 the elf objects.
526
e683cb41
AC		 5272021-05-17 Alex Coplan <alex.coplan@arm.com>
528
529 * arm-dis.c (mve_opcodes): Fix disassembly of
530 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
531 (is_mve_encoding_conflict): MVE vector loads should not match
532 when P = W = 0.
533 (is_mve_unpredictable): It's not unpredictable to use the same
534 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
535
a680affc
NC		 5362021-05-11 Nick Clifton <nickc@redhat.com>
537
538 PR 27840
539 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
540 the end of the code buffer.
541
0b3e14c9
SH		 5422021-05-06 Stafford Horne <shorne@gmail.com>
543
544 PR 21464
545 * or1k-asm.c: Regenerate.
546
6aee2cb2
MF		 5472021-05-01 Max Filippov <jcmvbkbc@gmail.com>
548
549 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
550 info->insn_info_valid.
551
fe134c65
JB		 5522021-04-26 Jan Beulich <jbeulich@suse.com>
553
554 * i386-opc.tbl (lea): Add Optimize.
555 * opcodes/i386-tbl.h: Re-generate.
556
b3ea7639
MF		 5572020-04-23 Max Filippov <jcmvbkbc@gmail.com>
558
559 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
560 of l32r fetch and display referenced literal value.
561
c1cbb7d8
MF		 5622021-04-23 Max Filippov <jcmvbkbc@gmail.com>
563
564 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
565 to 4 for literal disassembly.
566
02202574
PW		 5672021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
568
569 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
570 for TLBI instruction.
571
cd6608e4
PW		 5722021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
573
574 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
575 DC instruction.
576
fe1640ff
JB		 5772021-04-19 Jan Beulich <jbeulich@suse.com>
578
579 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
580 "qualifier".
581 (convert_mov_to_movewide): Add initializer for "value".
582
100e914d
PW		 5832021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
584
585 * aarch64-opc.c: Add RME system registers.
586
a21b96dd
NC		 5872021-04-16 Lifang Xia <lifang_xia@c-sky.com>
588
589 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
590 "addi d,CV,z" to "c.mv d,CV".
591
43e05cd4
AM		 5922021-04-12 Alan Modra <amodra@gmail.com>
593
594 * configure.ac (--enable-checking): Add support.
595 * config.in: Regenerate.
596 * configure: Regenerate.
597
52efda82
TB		 5982021-04-09 Tejas Belagod <tejas.belagod@arm.com>
599
600 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
601 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
602
c3f72de4
AM		 6032021-04-09 Alan Modra <amodra@gmail.com>
604
605 * ppc-dis.c (struct dis_private): Add "special".
606 (POWERPC_DIALECT): Delete. Replace uses with..
607 (private_data): ..this. New inline function.
608 (disassemble_init_powerpc): Init "special" names.
609 (skip_optional_operands): Add is_pcrel arg, set when detecting R
610 field of prefix instructions.
611 (bsearch_reloc, print_got_plt): New functions.
612 (print_insn_powerpc): For pcrel instructions, print target address
613 and symbol if known, and decode plt and got loads too.
614
ce7d813a
AM		 6152021-04-08 Alan Modra <amodra@gmail.com>
616
617 PR 27684
618 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
619
97bf40d8
AM		 6202021-04-08 Alan Modra <amodra@gmail.com>
621
622 PR 27676
623 * ppc-opc.c (DCBT_EO): Move earlier.
624 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
625 (powerpc_operands): Add THCT and THDS entries.
626 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
627
a2e66773
AM		 6282021-04-06 Alan Modra <amodra@gmail.com>
629
630 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
631 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
632 symbol_at_address_func.
633
ab2af25e
AM		 6342021-04-05 Alan Modra <amodra@gmail.com>
635
636 * configure.ac: Don't check for limits.h, string.h, strings.h or
637 stdlib.h.
638 (AC_ISC_POSIX): Don't invoke.
639 * sysdep.h: Include stdlib.h and string.h unconditionally.
640 * i386-opc.h: Include limits.h unconditionally.
641 * wasm32-dis.c: Likewise.
642 * cgen-opc.c: Don't include alloca-conf.h.
643 * config.in: Regenerate.
644 * configure: Regenerate.
645
e9b095a5
ML		 6462021-04-01 Martin Liska <mliska@suse.cz>
647
648 * arm-dis.c (strneq): Remove strneq and use startswith.
649 * cr16-dis.c (print_insn_cr16): Likewise.
650 * score-dis.c (streq): Likewise.
651 (strneq): Likewise.
652 * score7-dis.c (strneq): Likewise.
653
1cb108e4
AM		 6542021-04-01 Alan Modra <amodra@gmail.com>
655
656 PR 27675
657 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
658
78933a4a
AM		 6592021-03-31 Alan Modra <amodra@gmail.com>
660
661 * sysdep.h (POISON_BFD_BOOLEAN): Define.
662 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
663 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
664 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
665 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
666 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
667 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
668 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
669 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
670 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
671 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
672 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
673 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
674 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
675 and TRUE with true throughout.
676
3dfb1b6d
AM		 6772021-03-31 Alan Modra <amodra@gmail.com>
678
679 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
680 * aarch64-dis.h: Likewise.
681 * aarch64-opc.c: Likewise.
682 * avr-dis.c: Likewise.
683 * csky-dis.c: Likewise.
684 * nds32-asm.c: Likewise.
685 * nds32-dis.c: Likewise.
686 * nfp-dis.c: Likewise.
687 * riscv-dis.c: Likewise.
688 * s12z-dis.c: Likewise.
689 * wasm32-dis.c: Likewise.
690
5e042380
JB		 6912021-03-30 Jan Beulich <jbeulich@suse.com>
692
693 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
694 (i386_seg_prefixes): New.
695 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
696 (i386_seg_prefixes): Declare.
697
34684862
JB		 6982021-03-30 Jan Beulich <jbeulich@suse.com>
699
700 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
701
6288d05f
JB		 7022021-03-30 Jan Beulich <jbeulich@suse.com>
703
704 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
705 * i386-reg.tbl (st): Move down.
706 (st(0)): Delete. Extend comment.
707 * i386-tbl.h: Re-generate.
708
bbe1eca6
JB		 7092021-03-29 Jan Beulich <jbeulich@suse.com>
710
711 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
712 (cmpsd): Move next to cmps.
713 (movsd): Move next to movs.
714 (cmpxchg16b): Move to separate section.
715 (fisttp, fisttpll): Likewise.
716 (monitor, mwait): Likewise.
717 * i386-tbl.h: Re-generate.
718
c8cad9d3
JB		 7192021-03-29 Jan Beulich <jbeulich@suse.com>
720
721 * i386-opc.tbl (psadbw): Add <sse2:comm>.
722 (vpsadbw): Add C.
723 * i386-tbl.h: Re-generate.
724
5cdaf100
JB		 7252021-03-29 Jan Beulich <jbeulich@suse.com>
726
727 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
728 pclmul, gfni): New templates. Use them wherever possible. Move
729 SSE4.1 pextrw into respective section.
730 * i386-tbl.h: Re-generate.
731
73e45eb2
JB		 7322021-03-29 Jan Beulich <jbeulich@suse.com>
733
734 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
735 strtoull(). Bump upper loop bound. Widen masks. Sanity check
736 "length".
737 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
738 Convert all of their uses to representation in opcode.
739
9df6f676
JB		 7402021-03-29 Jan Beulich <jbeulich@suse.com>
741
742 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
743 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
744 value of None. Shrink operands to 3 bits.
745
389d00a5
JB		 7462021-03-29 Jan Beulich <jbeulich@suse.com>
747
748 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 749 "space".
389d00a5
JB		 750 (output_i386_opcode): New local variable "space". Adjust
751 process_i386_opcode_modifier() invocation.
752 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
753 invocation.
754 * i386-tbl.h: Re-generate.
755
63b4cc53
AM		 7562021-03-29 Alan Modra <amodra@gmail.com>
757
758 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
759 (fp_qualifier_p, get_data_pattern): Likewise.
760 (aarch64_get_operand_modifier_from_value): Likewise.
761 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
762 (operand_variant_qualifier_p): Likewise.
763 (qualifier_value_in_range_constraint_p): Likewise.
764 (aarch64_get_qualifier_esize): Likewise.
765 (aarch64_get_qualifier_nelem): Likewise.
766 (aarch64_get_qualifier_standard_value): Likewise.
767 (get_lower_bound, get_upper_bound): Likewise.
768 (aarch64_find_best_match, match_operands_qualifier): Likewise.
769 (aarch64_print_operand): Likewise.
770 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
771 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
772 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
773 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
774 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
775 (print_insn_tic6x): Likewise.
776
3d7d6c1b
AM		 7772021-03-29 Alan Modra <amodra@gmail.com>
778
779 * arc-dis.c (extract_operand_value): Correct NULL cast.
780 * frv-opc.h: Regenerate.
781
c3344b62
JB		 7822021-03-26 Jan Beulich <jbeulich@suse.com>
783
784 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
785 MMX form.
786 * i386-tbl.h: Re-generate.
787
efa30ac3
HAQ		 7882021-03-25 Abid Qadeer <abidh@codesourcery.com>
789
790 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
791 immediate in br.n instruction.
792
596a02ff
JB		 7932021-03-25 Jan Beulich <jbeulich@suse.com>
794
795 * i386-dis.c (XMGatherD, VexGatherD): New.
796 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
797 (print_insn): Check masking for S/G insns.
798 (OP_E_memory): New local variable check_gather. Extend mandatory
799 SIB check. Check register conflicts for (EVEX-encoded) gathers.
800 Extend check for disallowed 16-bit addressing.
801 (OP_VEX): New local variables modrm_reg and sib_index. Convert
802 if()s to switch(). Check register conflicts for (VEX-encoded)
803 gathers. Drop no longer reachable cases.
804 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
805 vgatherdp*.
806
53642852
JB		 8072021-03-25 Jan Beulich <jbeulich@suse.com>
808
809 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
810 zeroing-masking without masking.
811
c0e54661
JB		 8122021-03-25 Jan Beulich <jbeulich@suse.com>
813
814 * i386-opc.tbl (invlpgb): Fix multi-operand form.
815 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
816 single-operand forms as deprecated.
817 * i386-tbl.h: Re-generate.
818
5a403766
AM		 8192021-03-25 Alan Modra <amodra@gmail.com>
820
821 PR 27647
822 * ppc-opc.c (XLOCB_MASK): Delete.
823 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
824 XLBH_MASK.
825 (powerpc_opcodes): Accept a BH field on all extended forms of
826 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
827
9a182d04
JB		 8282021-03-24 Jan Beulich <jbeulich@suse.com>
829
830 * i386-gen.c (output_i386_opcode): Drop processing of
831 opcode_length. Calculate length from base_opcode. Adjust prefix
832 encoding determination.
833 (process_i386_opcodes): Drop output of fake opcode_length.
834 * i386-opc.h (struct insn_template): Drop opcode_length field.
835 * i386-opc.tbl: Drop opcode length field from all templates.
836 * i386-tbl.h: Re-generate.
837
35648716
JB		 8382021-03-24 Jan Beulich <jbeulich@suse.com>
839
840 * i386-gen.c (process_i386_opcode_modifier): Return void. New
841 parameter "prefix". Drop local variable "regular_encoding".
842 Record prefix setting / check for consistency.
843 (output_i386_opcode): Parse opcode_length and base_opcode
844 earlier. Derive prefix encoding. Drop no longer applicable
845 consistency checking. Adjust process_i386_opcode_modifier()
846 invocation.
847 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
848 invocation.
849 * i386-tbl.h: Re-generate.
850
31184569
JB		 8512021-03-24 Jan Beulich <jbeulich@suse.com>
852
853 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
854 check.
855 * i386-opc.h (Prefix_*): Move #define-s.
856 * i386-opc.tbl: Move pseudo prefix enumerator values to
857 extension opcode field. Introduce pseudopfx template.
858 * i386-tbl.h: Re-generate.
859
b933fa4b
JB		 8602021-03-23 Jan Beulich <jbeulich@suse.com>
861
862 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
863 comment.
864 * i386-tbl.h: Re-generate.
865
dac10fb0
JB		 8662021-03-23 Jan Beulich <jbeulich@suse.com>
867
868 * i386-opc.h (struct insn_template): Move cpu_flags field past
869 opcode_modifier one.
870 * i386-tbl.h: Re-generate.
871
441f6aca
JB		 8722021-03-23 Jan Beulich <jbeulich@suse.com>
873
874 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
875 * i386-opc.h (OpcodeSpace): New enumerator.
876 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
877 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
878 SPACE_XOP09, SPACE_XOP0A): ... respectively.
879 (struct i386_opcode_modifier): New field opcodespace. Shrink
880 opcodeprefix field.
881 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
882 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
883 OpcodePrefix uses.
884 * i386-tbl.h: Re-generate.
885
08dedd66
ML		 8862021-03-22 Martin Liska <mliska@suse.cz>
887
888 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
889 * arc-dis.c (parse_option): Likewise.
890 * arm-dis.c (parse_arm_disassembler_options): Likewise.
891 * cris-dis.c (print_with_operands): Likewise.
892 * h8300-dis.c (bfd_h8_disassemble): Likewise.
893 * i386-dis.c (print_insn): Likewise.
894 * ia64-gen.c (fetch_insn_class): Likewise.
895 (parse_resource_users): Likewise.
896 (in_iclass): Likewise.
897 (lookup_specifier): Likewise.
898 (insert_opcode_dependencies): Likewise.
899 * mips-dis.c (parse_mips_ase_option): Likewise.
900 (parse_mips_dis_option): Likewise.
901 * s390-dis.c (disassemble_init_s390): Likewise.
902 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
903
80d49d6a
KLC		 9042021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
905
906 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
907
7fce7ea9
PW		 9082021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
909
910 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
911 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
912
78c84bf9
AM		 9132021-03-12 Alan Modra <amodra@gmail.com>
914
915 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
916
fd1fd061
JB		 9172021-03-11 Jan Beulich <jbeulich@suse.com>
918
919 * i386-dis.c (OP_XMM): Re-order checks.
920
ac7a2311
JB		 9212021-03-11 Jan Beulich <jbeulich@suse.com>
922
923 * i386-dis.c (putop): Drop need_vex check when also checking
924 vex.evex.
925 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
926 checking vex.b.
927
da944c8a
JB		 9282021-03-11 Jan Beulich <jbeulich@suse.com>
929
930 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
931 checks. Move case label past broadcast check.
932
b763d508
JB		 9332021-03-10 Jan Beulich <jbeulich@suse.com>
934
935 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
936 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
937 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
938 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
939 EVEX_W_0F38C7_M_0_L_2): Delete.
940 (REG_EVEX_0F38C7_M_0_L_2): New.
941 (intel_operand_size): Handle VEX and EVEX the same for
942 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
943 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
944 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
945 vex_vsib_q_w_d_mode uses.
946 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
947 0F38A1, and 0F38A3 entries.
948 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
949 entry.
950 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
951 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
952 0F38A3 entries.
953
32e31ad7
JB		 9542021-03-10 Jan Beulich <jbeulich@suse.com>
955
956 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
957 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
958 MOD_VEX_0FXOP_09_12): Rename to ...
959 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
960 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
961 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
962 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
963 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
964 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
965 (reg_table): Adjust comments.
966 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
967 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
968 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
969 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
970 (vex_len_table): Adjust opcode 0A_12 entry.
971 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
972 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
973 (rm_table): Move hreset entry.
974
85ba7507
JB		 9752021-03-10 Jan Beulich <jbeulich@suse.com>
976
977 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
978 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
979 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
980 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
981 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
982 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
983 (get_valid_dis386): Also handle 512-bit vector length when
984 vectoring into vex_len_table[].
985 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
986 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
987 entries.
988 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
989 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
990 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
991 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
992 entries.
993
066f82b9
JB		 9942021-03-10 Jan Beulich <jbeulich@suse.com>
995
996 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
997 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
998 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
999 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
1000 entries.
1001 * i386-dis-evex-len.h (evex_len_table): Likewise.
1002 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
1003
fc681dd6
JB		 10042021-03-10 Jan Beulich <jbeulich@suse.com>
1005
1006 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
1007 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
1008 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
1009 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
1010 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
1011 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
1012 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
1013 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
1014 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1015 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1016 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1017 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
1018 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
1019 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
1020 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
1021 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
1022 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
1023 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
1024 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
1025 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1026 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
1027 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
1028 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1029 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
1030 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1031 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
1032 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
1033 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
1034 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
1035 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
1036 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
1037 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
1038 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
1039 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
1040 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
1041 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
1042 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
1043 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
1044 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
1045 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
1046 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
1047 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
1048 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
1049 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
1050 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
1051 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
1052 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
1053 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
1054 EVEX_W_0F3A43_L_n): New.
1055 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
1056 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
1057 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
1058 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
1059 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
1060 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
1061 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
1062 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
1063 0F385B, 0F38C6, and 0F38C7 entries.
1064 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
1065 0F38C6 and 0F38C7.
1066 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
1067 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
1068 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
1069 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
1070
13954a31
JB		 10712021-03-10 Jan Beulich <jbeulich@suse.com>
1072
1073 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
1074 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
1075 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
1076 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
1077 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
1078 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
1079 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
1080 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
1081 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1082 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1083 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1084 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1085 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1086 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1087 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1088 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1089 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1090 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1091 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1092 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1093 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1094 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1095 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1096 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1097 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1098 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1099 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1100 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1101 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1102 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1103 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1104 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1105 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1106 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1107 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1108 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1109 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1110 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1111 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1112 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1113 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1114 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1115 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1116 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1117 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1118 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1119 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1120 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1121 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1122 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1123 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1124 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1125 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1126 VEX_W_0F99_P_2_LEN_0): Delete.
1127 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1128 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1129 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1130 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1131 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1132 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1133 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1134 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1135 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1136 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1137 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1138 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1139 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1140 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1141 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1142 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1143 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1144 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1145 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1146 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1147 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1148 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1149 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1150 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1151 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1152 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1153 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1154 (prefix_table): No longer link to vex_len_table[] for opcodes
1155 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1156 0F92, 0F93, 0F98, and 0F99.
1157 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1158 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1159 0F98, and 0F99.
1160 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1161 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1162 0F98, and 0F99.
1163 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1164 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1165 0F98, and 0F99.
1166 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1167 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1168 0F98, and 0F99.
1169
14d10c6c
JB		 11702021-03-10 Jan Beulich <jbeulich@suse.com>
1171
1172 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1173 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1174 REG_VEX_0F73_M_0 respectively.
1175 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1176 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1177 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1178 MOD_VEX_0F73_REG_7): Delete.
1179 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1180 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1181 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1182 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1183 PREFIX_VEX_0F3AF0_L_0 respectively.
1184 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1185 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1186 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1187 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1188 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1189 VEX_LEN_0F38F7): New.
1190 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1191 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1192 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1193 0F38F3.
1194 (prefix_table): No longer link to vex_len_table[] for opcodes
1195 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1196 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1197 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1198 0F38F6, 0F38F7, and 0F3AF0.
1199 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1200 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1201 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1202 0F73.
1203
00ec1875
JB		 12042021-03-10 Jan Beulich <jbeulich@suse.com>
1205
1206 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1207 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1208 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1209 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1210 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1211 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1212 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1213 73.
1214 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1215 0F72, and 0F73.
1216 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1217 0F73.
1218
31941983
JB		 12192021-03-10 Jan Beulich <jbeulich@suse.com>
1220
1221 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1222 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1223 (reg_table): Don't link to mod_table[] where not needed. Add
1224 PREFIX_IGNORED to nop entries.
1225 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1226 (mod_table): Add nop entries next to prefetch ones. Drop
1227 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1228 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1229 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1230 PREFIX_OPCODE from endbr* entries.
1231 (get_valid_dis386): Also consider entry's name when zapping
1232 vindex.
1233 (print_insn): Handle PREFIX_IGNORED.
1234
742732c7
JB		 12352021-03-09 Jan Beulich <jbeulich@suse.com>
1236
1237 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1238 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1239 element.
1240 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1241 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1242 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1243 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1244 (struct i386_opcode_modifier): Delete notrackprefixok,
1245 islockable, hleprefixok, and repprefixok fields. Add prefixok
1246 field.
1247 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1248 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1249 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1250 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1251 Replace HLEPrefixOk.
1252 * opcodes/i386-tbl.h: Re-generate.
1253
e93a3b27
JB		 12542021-03-09 Jan Beulich <jbeulich@suse.com>
1255
1256 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1257 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1258 64-bit form.
1259 * opcodes/i386-tbl.h: Re-generate.
1260
75363b6d
JB		 12612021-03-03 Jan Beulich <jbeulich@suse.com>
1262
1263 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1264 for {} instead of {0}. Don't look for '0'.
1265 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1266 size specifiers.
1267
5a9f5403
NC		 12682021-02-19 Nelson Chu <nelson.chu@sifive.com>
1269
1270 PR 27158
1271 * riscv-dis.c (print_insn_args): Updated encoding macros.
1272 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1273 (match_c_addi16sp): Updated encoding macros.
1274 (match_c_lui): Likewise.
1275 (match_c_lui_with_hint): Likewise.
1276 (match_c_addi4spn): Likewise.
1277 (match_c_slli): Likewise.
1278 (match_slli_as_c_slli): Likewise.
1279 (match_c_slli64): Likewise.
1280 (match_srxi_as_c_srxi): Likewise.
1281 (riscv_insn_types): Added .insn css/cl/cs.
1282
3d73d29e
NC		 12832021-02-18 Nelson Chu <nelson.chu@sifive.com>
1284
1285 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1286 (default_priv_spec): Updated type to riscv_spec_class.
1287 (parse_riscv_dis_option): Updated.
1288 * riscv-opc.c: Moved stuff and make the file tidy.
1289
b9b204b3
AM		 12902021-02-17 Alan Modra <amodra@gmail.com>
1291
1292 * wasm32-dis.c: Include limits.h.
1293 (CHAR_BIT): Provide backup define.
1294 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1295 Correct signed overflow checking.
1296
394ae71f
JB		 12972021-02-16 Jan Beulich <jbeulich@suse.com>
1298
1299 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1300 * i386-tbl.h: Re-generate.
1301
b818b220
JB		 13022021-02-16 Jan Beulich <jbeulich@suse.com>
1303
1304 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1305 Oword.
1306 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1307
ba2b480f
AK		 13082021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1309
1310 * s390-mkopc.c (main): Accept arch14 as cpu string.
1311 * s390-opc.txt: Add new arch14 instructions.
1312
95148614
NA		 13132021-02-04 Nick Alcock <nick.alcock@oracle.com>
1314
1315 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1316 favour of LIBINTL.
1317 * configure: Regenerated.
1318
bfd428bc
MF		 13192021-02-08 Mike Frysinger <vapier@gentoo.org>
1320
1321 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1322 * tic54x-opc.c (regs): Rename to ...
1323 (tic54x_regs): ... this.
1324 (mmregs): Rename to ...
1325 (tic54x_mmregs): ... this.
1326 (condition_codes): Rename to ...
1327 (tic54x_condition_codes): ... this.
1328 (cc2_codes): Rename to ...
1329 (tic54x_cc2_codes): ... this.
1330 (cc3_codes): Rename to ...
1331 (tic54x_cc3_codes): ... this.
1332 (status_bits): Rename to ...
1333 (tic54x_status_bits): ... this.
1334 (misc_symbols): Rename to ...
1335 (tic54x_misc_symbols): ... this.
1336
24075dcc
NC		 13372021-02-04 Nelson Chu <nelson.chu@sifive.com>
1338
1339 * riscv-opc.c (MASK_RVB_IMM): Removed.
1340 (riscv_opcodes): Removed zb* instructions.
1341 (riscv_ext_version_table): Removed versions for zb*.
1342
c3ffb8f3
AM		 13432021-01-26 Alan Modra <amodra@gmail.com>
1344
1345 * i386-gen.c (parse_template): Ensure entire template_instance
1346 is initialised.
1347
1942a048
NC		 13482021-01-15 Nelson Chu <nelson.chu@sifive.com>
1349
1350 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1351 (riscv_fpr_names_abi): Likewise.
1352 (riscv_opcodes): Likewise.
1353 (riscv_insn_types): Likewise.
1354
b800637e
NC		 13552021-01-15 Nelson Chu <nelson.chu@sifive.com>
1356
1357 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1358
dcd709e0
NC		 13592021-01-15 Nelson Chu <nelson.chu@sifive.com>
1360
1361 * riscv-dis.c: Comments tidy and improvement.
1362 * riscv-opc.c: Likewise.
1363
5347ed60
AM		 13642021-01-13 Alan Modra <amodra@gmail.com>
1365
1366 * Makefile.in: Regenerate.
1367
d546b610
L		 13682021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1369
1370 PR binutils/26792
1371 * configure.ac: Use GNU_MAKE_JOBSERVER.
1372 * aclocal.m4: Regenerated.
1373 * configure: Likewise.
1374
6d104cac
NC		 13752021-01-12 Nick Clifton <nickc@redhat.com>
1376
1377 * po/sr.po: Updated Serbian translation.
1378
83b33c6c
L		 13792021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1380
1381 PR ld/27173
1382 * configure: Regenerated.
1383
82c70b08
KT		 13842021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1385
1386 * aarch64-asm-2.c: Regenerate.
1387 * aarch64-dis-2.c: Likewise.
1388 * aarch64-opc-2.c: Likewise.
1389 * aarch64-opc.c (aarch64_print_operand):
1390 Delete handling of AARCH64_OPND_CSRE_CSR.
1391 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1392 (CSRE): Likewise.
1393 (_CSRE_INSN): Likewise.
1394 (aarch64_opcode_table): Delete csr.
1395
a8aa72b9
NC		 13962021-01-11 Nick Clifton <nickc@redhat.com>
1397
1398 * po/de.po: Updated German translation.
1399 * po/fr.po: Updated French translation.
1400 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1401 * po/sv.po: Updated Swedish translation.
1402 * po/uk.po: Updated Ukranian translation.
1403
a4966cd9
L		 14042021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1405
1406 * configure: Regenerated.
1407
573fe3fb
NC		 14082021-01-09 Nick Clifton <nickc@redhat.com>
1409
1410 * configure: Regenerate.
1411 * po/opcodes.pot: Regenerate.
1412
055bc77a
NC		 14132021-01-09 Nick Clifton <nickc@redhat.com>
1414
1415 * 2.36 release branch crated.
1416
aae7fcb8
PB		 14172021-01-08 Peter Bergner <bergner@linux.ibm.com>
1418
1419 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1420 (DW, (XRC_MASK): Define.
1421 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1422
64307045
AM		 14232021-01-09 Alan Modra <amodra@gmail.com>
1424
1425 * configure: Regenerate.
1426
ed205222
NC		 14272021-01-08 Nick Clifton <nickc@redhat.com>
1428
1429 * po/sv.po: Updated Swedish translation.
1430
fb932b57
NC		 14312021-01-08 Nick Clifton <nickc@redhat.com>
1432
e84c8716
NC		 1433 PR 27129
1434 * aarch64-dis.c (determine_disassembling_preference): Move call to
1435 aarch64_match_operands_constraint outside of the assertion.
1436 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1437 Replace with a return of FALSE.
1438
fb932b57
NC		 1439 PR 27139
1440 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1441 core system register.
1442
f4782128
ST		 14432021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1444
1445 * configure: Regenerate.
1446
1b0927db
NC		 14472021-01-07 Nick Clifton <nickc@redhat.com>
1448
1449 * po/fr.po: Updated French translation.
1450
3b288c8e
FN		 14512021-01-07 Fredrik Noring <noring@nocrew.org>
1452
1453 * m68k-opc.c (chkl): Change minimum architecture requirement to
1454 m68020.
1455
aa881ecd
PT		 14562021-01-07 Philipp Tomsich <prt@gnu.org>
1457
1458 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1459
2652cfad
CXW		 14602021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1461 Jim Wilson <jimw@sifive.com>
1462 Andrew Waterman <andrew@sifive.com>
1463 Maxim Blinov <maxim.blinov@embecosm.com>
1464 Kito Cheng <kito.cheng@sifive.com>
1465 Nelson Chu <nelson.chu@sifive.com>
1466
1467 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1468 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1469
250d07de
AM		 14702021-01-01 Alan Modra <amodra@gmail.com>
1471
1472 Update year range in copyright notice of all files.
1473
c2795844 1474For older changes see ChangeLog-2020
3499769a 1475\f
fd67aa11 1476Copyright (C) 2021-2024 Free Software Foundation, Inc.
3499769a
AM		 1477
1478Copying and distribution of this file, with or without modification,
1479are permitted in any medium without royalty provided the copyright
1480notice and this notice are preserved.
1481
1482Local Variables:
1483mode: change-log
1484left-margin: 8
1485fill-column: 74
1486version-control: never
1487End:
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