]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4d5d5d46
PB		 12021-09-25 Peter Bergner <bergner@linux.ibm.com>
2
3 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
4 on POWER5 and later.
5
6a7f5766
AB		 62021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
7
8 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
9 before an unknown instruction, '%d' is replaced with the
10 instruction length.
11
718aefcf
NC		 122021-09-02 Nick Clifton <nickc@redhat.com>
13
14 PR 28292
15 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
16 of BFD_RELOC_16.
17
5d9cff51
SV		 182021-08-17 Shahab Vahedi <shahab@synopsys.com>
19
20 * arc-regs.h (DEF): Fix the register numbers.
21
3ee0cd9e
NC		 222021-08-10 Nick Clifton <nickc@redhat.com>
23
24 * po/sr.po: Updated Serbian translation.
25
8d56b9fc
CX		 262021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
27
28 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
29
b180e829
AK		 302021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
31
32 * s390-opc.txt: Add qpaci.
33
346d80ef
NC		 342021-07-03 Nick Clifton <nickc@redhat.com>
35
36 * configure: Regenerate.
37 * po/opcodes.pot: Regenerate.
38
51419248
NC		 392021-07-03 Nick Clifton <nickc@redhat.com>
40
41 * 2.37 release branch created.
42
62194b63
AM		 432021-07-02 Alan Modra <amodra@gmail.com>
44
45 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
46 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
47 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
48 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
49 (nds32_keyword_gpr): Move declarations to..
50 * nds32-asm.h: ..here, constifying to match definitions.
51
2fe36d31
MF		 522021-07-01 Mike Frysinger <vapier@gentoo.org>
53
54 * Makefile.am (GUILE): New variable.
55 (CGEN): Use $(GUILE).
56 * Makefile.in: Regenerate.
57
f375d32b
MF		 582021-07-01 Mike Frysinger <vapier@gentoo.org>
59
60 * mep-asm.c (macros): Mark static & const.
61 (lookup_macro): Change return & m to const.
62 (expand_macro): Change mac to const.
63 (expand_string): Change pmacro to const.
64
9b2beaf7
MF		 652021-07-01 Mike Frysinger <vapier@gentoo.org>
66
67 * nds32-asm.c (operand_fields): Rename to ...
68 (nds32_operand_fields): ... this.
69 (keyword_gpr): Rename to ...
70 (nds32_keyword_gpr): ... this.
71 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
72 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
73 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
74 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
75 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
76 Mark static.
77 (keywords): Rename to ...
78 (nds32_keywords): ... this.
79 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
80 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
81
ac8ef696
MF		 822021-07-01 Mike Frysinger <vapier@gentoo.org>
83
84 * z80-dis.c (opc_ed): Make const.
85 (pref_ed): Make p const.
86
52b83874
MF		 872021-07-01 Mike Frysinger <vapier@gentoo.org>
88
89 * microblaze-dis.c (get_field_special): Make op const.
90 (read_insn_microblaze): Make opr & op const. Rename opcodes to
91 microblaze_opcodes.
92 (print_insn_microblaze): Make op & pop const.
93 (get_insn_microblaze): Make op const. Rename opcodes to
94 microblaze_opcodes.
95 (microblaze_get_target_address): Likewise.
96 * microblaze-opc.h (struct op_code_struct): Make const.
97 Rename opcodes to microblaze_opcodes.
98
6c2ede01
MF		 992021-07-01 Mike Frysinger <vapier@gentoo.org>
100
101 * aarch64-gen.c (aarch64_opcode_table): Add const.
102 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
103
46b8b3d6
AB		 1042021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
105
106 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
107 available.
108
ded5cb94
AM		 1092021-06-22 Alan Modra <amodra@gmail.com>
110
111 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
112 print separator for pcrel insns.
113
47399e9c
AM		 1142021-06-19 Alan Modra <amodra@gmail.com>
115
116 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
117
d984392e
AM		 1182021-06-19 Alan Modra <amodra@gmail.com>
119
120 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
121 entire buffer.
122
7993124e
AM		 1232021-06-17 Alan Modra <amodra@gmail.com>
124
125 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
126 in table.
127
a38d1396
AM		 1282021-06-03 Alan Modra <amodra@gmail.com>
129
130 PR 1202
131 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
132 Use unsigned int for inst.
133
8f467114
SV		 1342021-06-02 Shahab Vahedi <shahab@synopsys.com>
135
136 * arc-dis.c (arc_option_arg_t): New enumeration.
137 (arc_options): New variable.
138 (disassembler_options_arc): New function.
139 (print_arc_disassembler_options): Reimplement in terms of
140 "disassembler_options_arc".
141
1ff6a3b8
AM		 1422021-05-29 Alan Modra <amodra@gmail.com>
143
144 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
145 Don't special case PPC_OPCODE_RAW.
146 (lookup_prefix): Likewise.
147 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
148 (print_insn_powerpc): ..update caller.
149 * ppc-opc.c (EXT): Define.
150 (powerpc_opcodes): Mark extended mnemonics with EXT.
151 (prefix_opcodes, vle_opcodes): Likewise.
152 (XISEL, XISEL_MASK): Add cr field and simplify.
153 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
154 all isel variants to where the base mnemonic belongs. Sort dstt,
155 dststt and dssall.
156
49149d59
MR		 1572021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
158
159 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
160 COP3 opcode instructions.
161
9573a461
MR		 1622021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
163
164 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
165 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
166 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
167 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
168 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
169 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
170 "cop2", and "cop3" entries.
171
fa495743
MR		 1722021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
173
174 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
175 entries and associated comments.
176
b930964c
MR		 1772021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
178
179 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
180 of "c0".
181
dd844468
MR		 1822021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
183
184 * mips-dis.c (mips_cp1_names_mips): New variable.
185 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
186 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
187 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
188 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
189 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
190 "loongson2f".
191
9204ccd4
MR		 1922021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
193
194 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
195 handling code over to...
196 <OP_REG_CONTROL>: ... this new case.
197 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
198 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
199 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
200 replacing the `G' operand code with `g'. Update "cftc1" and
201 "cftc2" entries replacing the `E' operand code with `y'.
202 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
203 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
204 entries replacing the `G' operand code with `g'.
205
a3fb396f
MR		 2062021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
207
208 * mips-dis.c (mips_cp0_names_r3900): New variable.
209 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
210 for "r3900".
211
cccc84fa
MR		 2122021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
213
214 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
215 and "mtthc2" to using the `G' rather than `g' operand code for
216 the coprocessor control register referred.
217
c9de3168
MR		 2182021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
219
220 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
221 entries with each other.
222
ebcab741
PB		 2232021-05-27 Peter Bergner <bergner@linux.ibm.com>
224
225 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
226
bc30a119
AM		 2272021-05-25 Alan Modra <amodra@gmail.com>
228
229 * cris-desc.c: Regenerate.
230 * cris-desc.h: Regenerate.
231 * cris-opc.h: Regenerate.
232 * po/POTFILES.in: Regenerate.
233
54711280
MF		 2342021-05-24 Mike Frysinger <vapier@gentoo.org>
235
236 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
237 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
238 (CGEN_CPUS): Add cris.
239 (CRIS_DEPS): Define.
240 (stamp-cris): New rule.
241 * cgen.sh: Handle desc action.
242 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
243 * Makefile.in, configure: Regenerate.
244
113bb761
JN		 2452021-05-18 Job Noorman <mtvec@pm.me>
246
247 PR 27814
248 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
249 the elf objects.
250
e683cb41
AC		 2512021-05-17 Alex Coplan <alex.coplan@arm.com>
252
253 * arm-dis.c (mve_opcodes): Fix disassembly of
254 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
255 (is_mve_encoding_conflict): MVE vector loads should not match
256 when P = W = 0.
257 (is_mve_unpredictable): It's not unpredictable to use the same
258 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
259
a680affc
NC		 2602021-05-11 Nick Clifton <nickc@redhat.com>
261
262 PR 27840
263 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
264 the end of the code buffer.
265
0b3e14c9
SH		 2662021-05-06 Stafford Horne <shorne@gmail.com>
267
268 PR 21464
269 * or1k-asm.c: Regenerate.
270
6aee2cb2
MF		 2712021-05-01 Max Filippov <jcmvbkbc@gmail.com>
272
273 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
274 info->insn_info_valid.
275
fe134c65
JB		 2762021-04-26 Jan Beulich <jbeulich@suse.com>
277
278 * i386-opc.tbl (lea): Add Optimize.
279 * opcodes/i386-tbl.h: Re-generate.
280
b3ea7639
MF		 2812020-04-23 Max Filippov <jcmvbkbc@gmail.com>
282
283 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
284 of l32r fetch and display referenced literal value.
285
c1cbb7d8
MF		 2862021-04-23 Max Filippov <jcmvbkbc@gmail.com>
287
288 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
289 to 4 for literal disassembly.
290
02202574
PW		 2912021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
292
293 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
294 for TLBI instruction.
295
cd6608e4
PW		 2962021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
297
298 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
299 DC instruction.
300
fe1640ff
JB		 3012021-04-19 Jan Beulich <jbeulich@suse.com>
302
303 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
304 "qualifier".
305 (convert_mov_to_movewide): Add initializer for "value".
306
100e914d
PW		 3072021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
308
309 * aarch64-opc.c: Add RME system registers.
310
a21b96dd
NC		 3112021-04-16 Lifang Xia <lifang_xia@c-sky.com>
312
313 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
314 "addi d,CV,z" to "c.mv d,CV".
315
43e05cd4
AM		 3162021-04-12 Alan Modra <amodra@gmail.com>
317
318 * configure.ac (--enable-checking): Add support.
319 * config.in: Regenerate.
320 * configure: Regenerate.
321
52efda82
TB		 3222021-04-09 Tejas Belagod <tejas.belagod@arm.com>
323
324 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
325 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
326
c3f72de4
AM		 3272021-04-09 Alan Modra <amodra@gmail.com>
328
329 * ppc-dis.c (struct dis_private): Add "special".
330 (POWERPC_DIALECT): Delete. Replace uses with..
331 (private_data): ..this. New inline function.
332 (disassemble_init_powerpc): Init "special" names.
333 (skip_optional_operands): Add is_pcrel arg, set when detecting R
334 field of prefix instructions.
335 (bsearch_reloc, print_got_plt): New functions.
336 (print_insn_powerpc): For pcrel instructions, print target address
337 and symbol if known, and decode plt and got loads too.
338
ce7d813a
AM		 3392021-04-08 Alan Modra <amodra@gmail.com>
340
341 PR 27684
342 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
343
97bf40d8
AM		 3442021-04-08 Alan Modra <amodra@gmail.com>
345
346 PR 27676
347 * ppc-opc.c (DCBT_EO): Move earlier.
348 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
349 (powerpc_operands): Add THCT and THDS entries.
350 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
351
a2e66773
AM		 3522021-04-06 Alan Modra <amodra@gmail.com>
353
354 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
355 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
356 symbol_at_address_func.
357
ab2af25e
AM		 3582021-04-05 Alan Modra <amodra@gmail.com>
359
360 * configure.ac: Don't check for limits.h, string.h, strings.h or
361 stdlib.h.
362 (AC_ISC_POSIX): Don't invoke.
363 * sysdep.h: Include stdlib.h and string.h unconditionally.
364 * i386-opc.h: Include limits.h unconditionally.
365 * wasm32-dis.c: Likewise.
366 * cgen-opc.c: Don't include alloca-conf.h.
367 * config.in: Regenerate.
368 * configure: Regenerate.
369
e9b095a5
ML		 3702021-04-01 Martin Liska <mliska@suse.cz>
371
372 * arm-dis.c (strneq): Remove strneq and use startswith.
373 * cr16-dis.c (print_insn_cr16): Likewise.
374 * score-dis.c (streq): Likewise.
375 (strneq): Likewise.
376 * score7-dis.c (strneq): Likewise.
377
1cb108e4
AM		 3782021-04-01 Alan Modra <amodra@gmail.com>
379
380 PR 27675
381 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
382
78933a4a
AM		 3832021-03-31 Alan Modra <amodra@gmail.com>
384
385 * sysdep.h (POISON_BFD_BOOLEAN): Define.
386 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
387 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
388 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
389 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
390 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
391 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
392 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
393 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
394 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
395 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
396 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
397 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
398 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
399 and TRUE with true throughout.
400
3dfb1b6d
AM		 4012021-03-31 Alan Modra <amodra@gmail.com>
402
403 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
404 * aarch64-dis.h: Likewise.
405 * aarch64-opc.c: Likewise.
406 * avr-dis.c: Likewise.
407 * csky-dis.c: Likewise.
408 * nds32-asm.c: Likewise.
409 * nds32-dis.c: Likewise.
410 * nfp-dis.c: Likewise.
411 * riscv-dis.c: Likewise.
412 * s12z-dis.c: Likewise.
413 * wasm32-dis.c: Likewise.
414
5e042380
JB		 4152021-03-30 Jan Beulich <jbeulich@suse.com>
416
417 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
418 (i386_seg_prefixes): New.
419 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
420 (i386_seg_prefixes): Declare.
421
34684862
JB		 4222021-03-30 Jan Beulich <jbeulich@suse.com>
423
424 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
425
6288d05f
JB		 4262021-03-30 Jan Beulich <jbeulich@suse.com>
427
428 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
429 * i386-reg.tbl (st): Move down.
430 (st(0)): Delete. Extend comment.
431 * i386-tbl.h: Re-generate.
432
bbe1eca6
JB		 4332021-03-29 Jan Beulich <jbeulich@suse.com>
434
435 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
436 (cmpsd): Move next to cmps.
437 (movsd): Move next to movs.
438 (cmpxchg16b): Move to separate section.
439 (fisttp, fisttpll): Likewise.
440 (monitor, mwait): Likewise.
441 * i386-tbl.h: Re-generate.
442
c8cad9d3
JB		 4432021-03-29 Jan Beulich <jbeulich@suse.com>
444
445 * i386-opc.tbl (psadbw): Add <sse2:comm>.
446 (vpsadbw): Add C.
447 * i386-tbl.h: Re-generate.
448
5cdaf100
JB		 4492021-03-29 Jan Beulich <jbeulich@suse.com>
450
451 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
452 pclmul, gfni): New templates. Use them wherever possible. Move
453 SSE4.1 pextrw into respective section.
454 * i386-tbl.h: Re-generate.
455
73e45eb2
JB		 4562021-03-29 Jan Beulich <jbeulich@suse.com>
457
458 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
459 strtoull(). Bump upper loop bound. Widen masks. Sanity check
460 "length".
461 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
462 Convert all of their uses to representation in opcode.
463
9df6f676
JB		 4642021-03-29 Jan Beulich <jbeulich@suse.com>
465
466 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
467 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
468 value of None. Shrink operands to 3 bits.
469
389d00a5
JB		 4702021-03-29 Jan Beulich <jbeulich@suse.com>
471
472 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 473 "space".
389d00a5
JB		 474 (output_i386_opcode): New local variable "space". Adjust
475 process_i386_opcode_modifier() invocation.
476 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
477 invocation.
478 * i386-tbl.h: Re-generate.
479
63b4cc53
AM		 4802021-03-29 Alan Modra <amodra@gmail.com>
481
482 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
483 (fp_qualifier_p, get_data_pattern): Likewise.
484 (aarch64_get_operand_modifier_from_value): Likewise.
485 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
486 (operand_variant_qualifier_p): Likewise.
487 (qualifier_value_in_range_constraint_p): Likewise.
488 (aarch64_get_qualifier_esize): Likewise.
489 (aarch64_get_qualifier_nelem): Likewise.
490 (aarch64_get_qualifier_standard_value): Likewise.
491 (get_lower_bound, get_upper_bound): Likewise.
492 (aarch64_find_best_match, match_operands_qualifier): Likewise.
493 (aarch64_print_operand): Likewise.
494 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
495 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
496 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
497 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
498 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
499 (print_insn_tic6x): Likewise.
500
3d7d6c1b
AM		 5012021-03-29 Alan Modra <amodra@gmail.com>
502
503 * arc-dis.c (extract_operand_value): Correct NULL cast.
504 * frv-opc.h: Regenerate.
505
c3344b62
JB		 5062021-03-26 Jan Beulich <jbeulich@suse.com>
507
508 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
509 MMX form.
510 * i386-tbl.h: Re-generate.
511
efa30ac3
HAQ		 5122021-03-25 Abid Qadeer <abidh@codesourcery.com>
513
514 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
515 immediate in br.n instruction.
516
596a02ff
JB		 5172021-03-25 Jan Beulich <jbeulich@suse.com>
518
519 * i386-dis.c (XMGatherD, VexGatherD): New.
520 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
521 (print_insn): Check masking for S/G insns.
522 (OP_E_memory): New local variable check_gather. Extend mandatory
523 SIB check. Check register conflicts for (EVEX-encoded) gathers.
524 Extend check for disallowed 16-bit addressing.
525 (OP_VEX): New local variables modrm_reg and sib_index. Convert
526 if()s to switch(). Check register conflicts for (VEX-encoded)
527 gathers. Drop no longer reachable cases.
528 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
529 vgatherdp*.
530
53642852
JB		 5312021-03-25 Jan Beulich <jbeulich@suse.com>
532
533 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
534 zeroing-masking without masking.
535
c0e54661
JB		 5362021-03-25 Jan Beulich <jbeulich@suse.com>
537
538 * i386-opc.tbl (invlpgb): Fix multi-operand form.
539 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
540 single-operand forms as deprecated.
541 * i386-tbl.h: Re-generate.
542
5a403766
AM		 5432021-03-25 Alan Modra <amodra@gmail.com>
544
545 PR 27647
546 * ppc-opc.c (XLOCB_MASK): Delete.
547 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
548 XLBH_MASK.
549 (powerpc_opcodes): Accept a BH field on all extended forms of
550 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
551
9a182d04
JB		 5522021-03-24 Jan Beulich <jbeulich@suse.com>
553
554 * i386-gen.c (output_i386_opcode): Drop processing of
555 opcode_length. Calculate length from base_opcode. Adjust prefix
556 encoding determination.
557 (process_i386_opcodes): Drop output of fake opcode_length.
558 * i386-opc.h (struct insn_template): Drop opcode_length field.
559 * i386-opc.tbl: Drop opcode length field from all templates.
560 * i386-tbl.h: Re-generate.
561
35648716
JB		 5622021-03-24 Jan Beulich <jbeulich@suse.com>
563
564 * i386-gen.c (process_i386_opcode_modifier): Return void. New
565 parameter "prefix". Drop local variable "regular_encoding".
566 Record prefix setting / check for consistency.
567 (output_i386_opcode): Parse opcode_length and base_opcode
568 earlier. Derive prefix encoding. Drop no longer applicable
569 consistency checking. Adjust process_i386_opcode_modifier()
570 invocation.
571 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
572 invocation.
573 * i386-tbl.h: Re-generate.
574
31184569
JB		 5752021-03-24 Jan Beulich <jbeulich@suse.com>
576
577 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
578 check.
579 * i386-opc.h (Prefix_*): Move #define-s.
580 * i386-opc.tbl: Move pseudo prefix enumerator values to
581 extension opcode field. Introduce pseudopfx template.
582 * i386-tbl.h: Re-generate.
583
b933fa4b
JB		 5842021-03-23 Jan Beulich <jbeulich@suse.com>
585
586 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
587 comment.
588 * i386-tbl.h: Re-generate.
589
dac10fb0
JB		 5902021-03-23 Jan Beulich <jbeulich@suse.com>
591
592 * i386-opc.h (struct insn_template): Move cpu_flags field past
593 opcode_modifier one.
594 * i386-tbl.h: Re-generate.
595
441f6aca
JB		 5962021-03-23 Jan Beulich <jbeulich@suse.com>
597
598 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
599 * i386-opc.h (OpcodeSpace): New enumerator.
600 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
601 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
602 SPACE_XOP09, SPACE_XOP0A): ... respectively.
603 (struct i386_opcode_modifier): New field opcodespace. Shrink
604 opcodeprefix field.
605 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
606 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
607 OpcodePrefix uses.
608 * i386-tbl.h: Re-generate.
609
08dedd66
ML		 6102021-03-22 Martin Liska <mliska@suse.cz>
611
612 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
613 * arc-dis.c (parse_option): Likewise.
614 * arm-dis.c (parse_arm_disassembler_options): Likewise.
615 * cris-dis.c (print_with_operands): Likewise.
616 * h8300-dis.c (bfd_h8_disassemble): Likewise.
617 * i386-dis.c (print_insn): Likewise.
618 * ia64-gen.c (fetch_insn_class): Likewise.
619 (parse_resource_users): Likewise.
620 (in_iclass): Likewise.
621 (lookup_specifier): Likewise.
622 (insert_opcode_dependencies): Likewise.
623 * mips-dis.c (parse_mips_ase_option): Likewise.
624 (parse_mips_dis_option): Likewise.
625 * s390-dis.c (disassemble_init_s390): Likewise.
626 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
627
80d49d6a
KLC		 6282021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
629
630 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
631
7fce7ea9
PW		 6322021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
633
634 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
635 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
636
78c84bf9
AM		 6372021-03-12 Alan Modra <amodra@gmail.com>
638
639 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
640
fd1fd061
JB		 6412021-03-11 Jan Beulich <jbeulich@suse.com>
642
643 * i386-dis.c (OP_XMM): Re-order checks.
644
ac7a2311
JB		 6452021-03-11 Jan Beulich <jbeulich@suse.com>
646
647 * i386-dis.c (putop): Drop need_vex check when also checking
648 vex.evex.
649 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
650 checking vex.b.
651
da944c8a
JB		 6522021-03-11 Jan Beulich <jbeulich@suse.com>
653
654 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
655 checks. Move case label past broadcast check.
656
b763d508
JB		 6572021-03-10 Jan Beulich <jbeulich@suse.com>
658
659 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
660 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
661 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
662 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
663 EVEX_W_0F38C7_M_0_L_2): Delete.
664 (REG_EVEX_0F38C7_M_0_L_2): New.
665 (intel_operand_size): Handle VEX and EVEX the same for
666 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
667 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
668 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
669 vex_vsib_q_w_d_mode uses.
670 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
671 0F38A1, and 0F38A3 entries.
672 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
673 entry.
674 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
675 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
676 0F38A3 entries.
677
32e31ad7
JB		 6782021-03-10 Jan Beulich <jbeulich@suse.com>
679
680 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
681 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
682 MOD_VEX_0FXOP_09_12): Rename to ...
683 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
684 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
685 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
686 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
687 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
688 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
689 (reg_table): Adjust comments.
690 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
691 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
692 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
693 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
694 (vex_len_table): Adjust opcode 0A_12 entry.
695 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
696 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
697 (rm_table): Move hreset entry.
698
85ba7507
JB		 6992021-03-10 Jan Beulich <jbeulich@suse.com>
700
701 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
702 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
703 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
704 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
705 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
706 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
707 (get_valid_dis386): Also handle 512-bit vector length when
708 vectoring into vex_len_table[].
709 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
710 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
711 entries.
712 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
713 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
714 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
715 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
716 entries.
717
066f82b9
JB		 7182021-03-10 Jan Beulich <jbeulich@suse.com>
719
720 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
721 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
722 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
723 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
724 entries.
725 * i386-dis-evex-len.h (evex_len_table): Likewise.
726 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
727
fc681dd6
JB		 7282021-03-10 Jan Beulich <jbeulich@suse.com>
729
730 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
731 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
732 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
733 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
734 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
735 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
736 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
737 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
738 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
739 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
740 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
741 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
742 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
743 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
744 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
745 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
746 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
747 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
748 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
749 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
750 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
751 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
752 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
753 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
754 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
755 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
756 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
757 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
758 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
759 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
760 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
761 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
762 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
763 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
764 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
765 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
766 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
767 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
768 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
769 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
770 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
771 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
772 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
773 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
774 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
775 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
776 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
777 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
778 EVEX_W_0F3A43_L_n): New.
779 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
780 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
781 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
782 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
783 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
784 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
785 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
786 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
787 0F385B, 0F38C6, and 0F38C7 entries.
788 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
789 0F38C6 and 0F38C7.
790 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
791 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
792 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
793 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
794
13954a31
JB		 7952021-03-10 Jan Beulich <jbeulich@suse.com>
796
797 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
798 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
799 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
800 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
801 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
802 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
803 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
804 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
805 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
806 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
807 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
808 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
809 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
810 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
811 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
812 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
813 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
814 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
815 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
816 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
817 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
818 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
819 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
820 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
821 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
822 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
823 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
824 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
825 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
826 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
827 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
828 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
829 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
830 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
831 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
832 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
833 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
834 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
835 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
836 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
837 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
838 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
839 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
840 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
841 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
842 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
843 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
844 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
845 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
846 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
847 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
848 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
849 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
850 VEX_W_0F99_P_2_LEN_0): Delete.
851 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
852 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
853 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
854 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
855 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
856 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
857 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
858 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
859 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
860 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
861 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
862 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
863 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
864 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
865 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
866 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
867 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
868 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
869 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
870 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
871 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
872 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
873 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
874 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
875 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
876 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
877 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
878 (prefix_table): No longer link to vex_len_table[] for opcodes
879 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
880 0F92, 0F93, 0F98, and 0F99.
881 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
882 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
883 0F98, and 0F99.
884 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
885 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
886 0F98, and 0F99.
887 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
888 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
889 0F98, and 0F99.
890 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
891 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
892 0F98, and 0F99.
893
14d10c6c
JB		 8942021-03-10 Jan Beulich <jbeulich@suse.com>
895
896 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
897 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
898 REG_VEX_0F73_M_0 respectively.
899 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
900 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
901 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
902 MOD_VEX_0F73_REG_7): Delete.
903 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
904 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
905 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
906 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
907 PREFIX_VEX_0F3AF0_L_0 respectively.
908 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
909 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
910 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
911 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
912 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
913 VEX_LEN_0F38F7): New.
914 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
915 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
916 0F72, and 0F73. No longer link to vex_len_table[] for opcode
917 0F38F3.
918 (prefix_table): No longer link to vex_len_table[] for opcodes
919 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
920 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
921 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
922 0F38F6, 0F38F7, and 0F3AF0.
923 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
924 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
925 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
926 0F73.
927
00ec1875
JB		 9282021-03-10 Jan Beulich <jbeulich@suse.com>
929
930 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
931 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
932 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
933 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
934 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
935 (MOD_0F71, MOD_0F72, MOD_0F73): New.
936 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
937 73.
938 (reg_table): No longer link to mod_table[] for opcodes 0F71,
939 0F72, and 0F73.
940 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
941 0F73.
942
31941983
JB		 9432021-03-10 Jan Beulich <jbeulich@suse.com>
944
945 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
946 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
947 (reg_table): Don't link to mod_table[] where not needed. Add
948 PREFIX_IGNORED to nop entries.
949 (prefix_table): Replace PREFIX_OPCODE in nop entries.
950 (mod_table): Add nop entries next to prefetch ones. Drop
951 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
952 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
953 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
954 PREFIX_OPCODE from endbr* entries.
955 (get_valid_dis386): Also consider entry's name when zapping
956 vindex.
957 (print_insn): Handle PREFIX_IGNORED.
958
742732c7
JB		 9592021-03-09 Jan Beulich <jbeulich@suse.com>
960
961 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
962 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
963 element.
964 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
965 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
966 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
967 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
968 (struct i386_opcode_modifier): Delete notrackprefixok,
969 islockable, hleprefixok, and repprefixok fields. Add prefixok
970 field.
971 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
972 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
973 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
974 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
975 Replace HLEPrefixOk.
976 * opcodes/i386-tbl.h: Re-generate.
977
e93a3b27
JB		 9782021-03-09 Jan Beulich <jbeulich@suse.com>
979
980 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
981 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
982 64-bit form.
983 * opcodes/i386-tbl.h: Re-generate.
984
75363b6d
JB		 9852021-03-03 Jan Beulich <jbeulich@suse.com>
986
987 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
988 for {} instead of {0}. Don't look for '0'.
989 * i386-opc.tbl: Drop operand count field. Drop redundant operand
990 size specifiers.
991
5a9f5403
NC		 9922021-02-19 Nelson Chu <nelson.chu@sifive.com>
993
994 PR 27158
995 * riscv-dis.c (print_insn_args): Updated encoding macros.
996 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
997 (match_c_addi16sp): Updated encoding macros.
998 (match_c_lui): Likewise.
999 (match_c_lui_with_hint): Likewise.
1000 (match_c_addi4spn): Likewise.
1001 (match_c_slli): Likewise.
1002 (match_slli_as_c_slli): Likewise.
1003 (match_c_slli64): Likewise.
1004 (match_srxi_as_c_srxi): Likewise.
1005 (riscv_insn_types): Added .insn css/cl/cs.
1006
3d73d29e
NC		 10072021-02-18 Nelson Chu <nelson.chu@sifive.com>
1008
1009 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1010 (default_priv_spec): Updated type to riscv_spec_class.
1011 (parse_riscv_dis_option): Updated.
1012 * riscv-opc.c: Moved stuff and make the file tidy.
1013
b9b204b3
AM		 10142021-02-17 Alan Modra <amodra@gmail.com>
1015
1016 * wasm32-dis.c: Include limits.h.
1017 (CHAR_BIT): Provide backup define.
1018 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1019 Correct signed overflow checking.
1020
394ae71f
JB		 10212021-02-16 Jan Beulich <jbeulich@suse.com>
1022
1023 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1024 * i386-tbl.h: Re-generate.
1025
b818b220
JB		 10262021-02-16 Jan Beulich <jbeulich@suse.com>
1027
1028 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1029 Oword.
1030 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1031
ba2b480f
AK		 10322021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1033
1034 * s390-mkopc.c (main): Accept arch14 as cpu string.
1035 * s390-opc.txt: Add new arch14 instructions.
1036
95148614
NA		 10372021-02-04 Nick Alcock <nick.alcock@oracle.com>
1038
1039 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1040 favour of LIBINTL.
1041 * configure: Regenerated.
1042
bfd428bc
MF		 10432021-02-08 Mike Frysinger <vapier@gentoo.org>
1044
1045 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1046 * tic54x-opc.c (regs): Rename to ...
1047 (tic54x_regs): ... this.
1048 (mmregs): Rename to ...
1049 (tic54x_mmregs): ... this.
1050 (condition_codes): Rename to ...
1051 (tic54x_condition_codes): ... this.
1052 (cc2_codes): Rename to ...
1053 (tic54x_cc2_codes): ... this.
1054 (cc3_codes): Rename to ...
1055 (tic54x_cc3_codes): ... this.
1056 (status_bits): Rename to ...
1057 (tic54x_status_bits): ... this.
1058 (misc_symbols): Rename to ...
1059 (tic54x_misc_symbols): ... this.
1060
24075dcc
NC		 10612021-02-04 Nelson Chu <nelson.chu@sifive.com>
1062
1063 * riscv-opc.c (MASK_RVB_IMM): Removed.
1064 (riscv_opcodes): Removed zb* instructions.
1065 (riscv_ext_version_table): Removed versions for zb*.
1066
c3ffb8f3
AM		 10672021-01-26 Alan Modra <amodra@gmail.com>
1068
1069 * i386-gen.c (parse_template): Ensure entire template_instance
1070 is initialised.
1071
1942a048
NC		 10722021-01-15 Nelson Chu <nelson.chu@sifive.com>
1073
1074 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1075 (riscv_fpr_names_abi): Likewise.
1076 (riscv_opcodes): Likewise.
1077 (riscv_insn_types): Likewise.
1078
b800637e
NC		 10792021-01-15 Nelson Chu <nelson.chu@sifive.com>
1080
1081 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1082
dcd709e0
NC		 10832021-01-15 Nelson Chu <nelson.chu@sifive.com>
1084
1085 * riscv-dis.c: Comments tidy and improvement.
1086 * riscv-opc.c: Likewise.
1087
5347ed60
AM		 10882021-01-13 Alan Modra <amodra@gmail.com>
1089
1090 * Makefile.in: Regenerate.
1091
d546b610
L		 10922021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1093
1094 PR binutils/26792
1095 * configure.ac: Use GNU_MAKE_JOBSERVER.
1096 * aclocal.m4: Regenerated.
1097 * configure: Likewise.
1098
6d104cac
NC		 10992021-01-12 Nick Clifton <nickc@redhat.com>
1100
1101 * po/sr.po: Updated Serbian translation.
1102
83b33c6c
L		 11032021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1104
1105 PR ld/27173
1106 * configure: Regenerated.
1107
82c70b08
KT		 11082021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1109
1110 * aarch64-asm-2.c: Regenerate.
1111 * aarch64-dis-2.c: Likewise.
1112 * aarch64-opc-2.c: Likewise.
1113 * aarch64-opc.c (aarch64_print_operand):
1114 Delete handling of AARCH64_OPND_CSRE_CSR.
1115 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1116 (CSRE): Likewise.
1117 (_CSRE_INSN): Likewise.
1118 (aarch64_opcode_table): Delete csr.
1119
a8aa72b9
NC		 11202021-01-11 Nick Clifton <nickc@redhat.com>
1121
1122 * po/de.po: Updated German translation.
1123 * po/fr.po: Updated French translation.
1124 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1125 * po/sv.po: Updated Swedish translation.
1126 * po/uk.po: Updated Ukranian translation.
1127
a4966cd9
L		 11282021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1129
1130 * configure: Regenerated.
1131
573fe3fb
NC		 11322021-01-09 Nick Clifton <nickc@redhat.com>
1133
1134 * configure: Regenerate.
1135 * po/opcodes.pot: Regenerate.
1136
055bc77a
NC		 11372021-01-09 Nick Clifton <nickc@redhat.com>
1138
1139 * 2.36 release branch crated.
1140
aae7fcb8
PB		 11412021-01-08 Peter Bergner <bergner@linux.ibm.com>
1142
1143 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1144 (DW, (XRC_MASK): Define.
1145 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1146
64307045
AM		 11472021-01-09 Alan Modra <amodra@gmail.com>
1148
1149 * configure: Regenerate.
1150
ed205222
NC		 11512021-01-08 Nick Clifton <nickc@redhat.com>
1152
1153 * po/sv.po: Updated Swedish translation.
1154
fb932b57
NC		 11552021-01-08 Nick Clifton <nickc@redhat.com>
1156
e84c8716
NC		 1157 PR 27129
1158 * aarch64-dis.c (determine_disassembling_preference): Move call to
1159 aarch64_match_operands_constraint outside of the assertion.
1160 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1161 Replace with a return of FALSE.
1162
fb932b57
NC		 1163 PR 27139
1164 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1165 core system register.
1166
f4782128
ST		 11672021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1168
1169 * configure: Regenerate.
1170
1b0927db
NC		 11712021-01-07 Nick Clifton <nickc@redhat.com>
1172
1173 * po/fr.po: Updated French translation.
1174
3b288c8e
FN		 11752021-01-07 Fredrik Noring <noring@nocrew.org>
1176
1177 * m68k-opc.c (chkl): Change minimum architecture requirement to
1178 m68020.
1179
aa881ecd
PT		 11802021-01-07 Philipp Tomsich <prt@gnu.org>
1181
1182 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1183
2652cfad
CXW		 11842021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1185 Jim Wilson <jimw@sifive.com>
1186 Andrew Waterman <andrew@sifive.com>
1187 Maxim Blinov <maxim.blinov@embecosm.com>
1188 Kito Cheng <kito.cheng@sifive.com>
1189 Nelson Chu <nelson.chu@sifive.com>
1190
1191 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1192 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1193
250d07de
AM		 11942021-01-01 Alan Modra <amodra@gmail.com>
1195
1196 Update year range in copyright notice of all files.
1197
c2795844 1198For older changes see ChangeLog-2020
3499769a 1199\f
c2795844 1200Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1201
1202Copying and distribution of this file, with or without modification,
1203are permitted in any medium without royalty provided the copyright
1204notice and this notice are preserved.
1205
1206Local Variables:
1207mode: change-log
1208left-margin: 8
1209fill-column: 74
1210version-control: never
1211End:
A mirror of the official binutils-gdb repository