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bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5cbe5492
JM		 12023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
2
3 * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
4 instructions.
5
3ccfc0b4
JM		 62023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
7
8 * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
9 instructions.
10
c2ca88d7
JM		 112023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
12
13 * bpf-opc.c (bpf_opcodes): Add entry for jal.
14
c24fd954
JM		 152023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
16
17 * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
18 instructions.
19
2f3dbc5f
JM		 202023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
21
22 * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
23 MOVS32{8,16,32}R instructions. and MOVS32I instructions.
24
386d3059
JM		 252023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
26
27 * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
28 * Makefile.in: Regenerate.
29
87485f53
NC		 302023-07-03 Nick Clifton <nickc@redhat.com>
31
32 * configure: Regenerate.
33 * po/opcodes.pot: Regenerate.
34
d501d384
NC		 352023-07-03 Nick Clifton <nickc@redhat.com>
36
37 2.41 Branch Point.
38
d595715a
NC		 392023-05-23 Nick Clifton <nickc@redhat.com>
40
41 * po/sv.po: Updated translation.
42
da9a978a
TT		 432023-04-21 Tom Tromey <tromey@adacore.com>
44
45 * i386-dis.c (OP_J): Check result of get16.
46
4bbb4dfb
CZ		 472023-04-12 Claudiu Zissulescu <claziss@synopsys.com>
48
49 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
50 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
51 vsubs2h, and vsubs4h instructions.
52
37522c87
NC		 532023-04-11 Nick Clifton <nickc@redhat.com>
54
55 PR 30310
56 * nfp-dis.c (init_nfp6000_priv): Check that the output section
57 exists.
58
71f646f2
NC		 592023-03-15 Nick Clifton <nickc@redhat.com>
60
61 PR 30231
62 * mep-dis.c: Regenerate.
63
77186045
NC		 642023-03-15 Nick Clifton <nickc@redhat.com>
65
66 PR 30230
67 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
68
31f2faf5
RB		 692023-02-28 Richard Ball <richard.ball@arm.com>
70
71 * aarch64-opc.c: Add MEC system registers.
72
11982f9f
NC		 732023-01-03 Nick Clifton <nickc@redhat.com>
74
75 * po/de.po: Updated German translation.
76 * po/ro.po: Updated Romainian translation.
77 * po/uk.po: Updated Ukrainian translation.
78
a72b0718
NC		 792022-12-31 Nick Clifton <nickc@redhat.com>
80
81 * 2.40 branch created.
82
b2059307
SV		 832022-11-22 Shahab Vahedi <shahab@synopsys.com>
84
85 * arc-regs.h: Change isa_config address to 0xc1.
86 isa_config exists for ARC700 and ARCV2 and not ARCALL.
87
de1fbe78
YS		 882022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
89
90 * rx-decode.opc: Switch arguments of the MVTACGU insn.
91 * rx-decode.c: Regenerate.
92
3b8e069a
YS		 932022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
94
95 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
96 Rm_BANK,Rn is always 1.
97
c07ec968
PB		 982022-07-21 Peter Bergner <bergner@linux.ibm.com>
99
100 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
101 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
102 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
103 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
104 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
105 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
106 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
107
bbcab336
CZ		 1082022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
109
110 * disassemble.c (disassemble_init_for_target): Set
111 created_styled_output for ARC based targets.
112 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
113 instead of fprintf_ftype throughout.
114 (find_format): Likewise.
115 (print_flags): Likewise.
116 (print_insn_arc): Likewise.
117
0bd09323
NC		 1182022-07-08 Nick Clifton <nickc@redhat.com>
119
120 * 2.39 branch created.
121
a0f3a4c6
MN		 1222022-07-04 Marcus Nilsson <brainbomb@gmail.com>
123
124 * disassemble.c: (disassemble_init_for_target): Set
125 created_styled_output for AVR based targets.
126 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
127 instead of fprintf_ftype throughout.
128 (avr_operand): Pass in and fill disassembler_style when
129 parsing operands.
130
69341966
AK		 1312022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
132
133 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
134 table.
135
e3161106
SM		 1362022-03-16 Simon Marchi <simon.marchi@efficios.com>
137
138 * configure.ac: Handle bfd_amdgcn_arch.
139 * configure: Re-generate.
140
d17e797f
MR		 1412022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
142 Maciej W. Rozycki <macro@orcam.me.uk>
143
144 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
145 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
146 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
147 "bnez" instructions.
148
36d285b9
NC		 1492022-02-17 Nick Clifton <nickc@redhat.com>
150
151 * po/sr.po: Updated Serbian translation.
152
a532eb72
ST		 1532022-02-14 Sergei Trofimovich <siarheit@google.com>
154
155 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
156 * microblaze-opc.h: Follow 'fsqrt' rename.
157
5fe73d46
NC		 1582022-01-24 Nick Clifton <nickc@redhat.com>
159
160 * po/ro.po: Updated Romanian translation.
161 * po/uk.po: Updated Ukranian translation.
162
f908e960
NC		 1632022-01-22 Nick Clifton <nickc@redhat.com>
164
165 * configure: Regenerate.
166 * po/opcodes.pot: Regenerate.
167
a74e1cb3
NC		 1682022-01-22 Nick Clifton <nickc@redhat.com>
169
170 * 2.38 release branch created.
171
6c037fdb
NC		 1722022-01-17 Nick Clifton <nickc@redhat.com>
173
174 * Makefile.in: Regenerate.
175 * po/opcodes.pot: Regenerate.
176
96c7115a
MN		 1772021-12-02 Marcus Nilsson <brainbomb@gmail.com>
178
179 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
180 in insn_type on branching instructions.
181
3a337a86
AB		 1822021-11-25 Andrew Burgess <aburgess@redhat.com>
183 Simon Cook <simon.cook@embecosm.com>
184
185 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
186 (riscv_options): New static global.
187 (disassembler_options_riscv): New function.
188 (print_riscv_disassembler_options): Rewrite to use
189 disassembler_options_riscv.
190
7060c28e
NC		 1912021-11-25 Nick Clifton <nickc@redhat.com>
192
193 PR 28614
194 * aarch64-asm.c: Replace assert(0) with real code.
195 * aarch64-dis.c: Likewise.
196 * aarch64-opc.c: Likewise.
197
79abb939
NC		 1982021-11-25 Nick Clifton <nickc@redhat.com>
199
200 * po/fr.po; Updated French translation.
201
2b677209
MR		 2022021-10-27 Maciej W. Rozycki <macro@embecosm.com>
203
204 * Makefile.am: Remove obsolete comment.
205 * configure.ac: Refer `libbfd.la' to link shared BFD library
206 except for Cygwin.
207 * Makefile.in: Regenerate.
208 * configure: Regenerate.
209
b9004024
NA		 2102021-09-27 Nick Alcock <nick.alcock@oracle.com>
211
212 * configure: Regenerate.
213
4d5d5d46
PB		 2142021-09-25 Peter Bergner <bergner@linux.ibm.com>
215
216 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
217 on POWER5 and later.
218
6a7f5766
AB		 2192021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
220
221 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
222 before an unknown instruction, '%d' is replaced with the
223 instruction length.
224
718aefcf
NC		 2252021-09-02 Nick Clifton <nickc@redhat.com>
226
227 PR 28292
228 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
229 of BFD_RELOC_16.
230
5d9cff51
SV		 2312021-08-17 Shahab Vahedi <shahab@synopsys.com>
232
233 * arc-regs.h (DEF): Fix the register numbers.
234
3ee0cd9e
NC		 2352021-08-10 Nick Clifton <nickc@redhat.com>
236
237 * po/sr.po: Updated Serbian translation.
238
8d56b9fc
CX		 2392021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
240
241 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
242
b180e829
AK		 2432021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
244
245 * s390-opc.txt: Add qpaci.
246
346d80ef
NC		 2472021-07-03 Nick Clifton <nickc@redhat.com>
248
249 * configure: Regenerate.
250 * po/opcodes.pot: Regenerate.
251
51419248
NC		 2522021-07-03 Nick Clifton <nickc@redhat.com>
253
254 * 2.37 release branch created.
255
62194b63
AM		 2562021-07-02 Alan Modra <amodra@gmail.com>
257
258 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
259 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
260 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
261 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
262 (nds32_keyword_gpr): Move declarations to..
263 * nds32-asm.h: ..here, constifying to match definitions.
264
2fe36d31
MF		 2652021-07-01 Mike Frysinger <vapier@gentoo.org>
266
267 * Makefile.am (GUILE): New variable.
268 (CGEN): Use $(GUILE).
269 * Makefile.in: Regenerate.
270
f375d32b
MF		 2712021-07-01 Mike Frysinger <vapier@gentoo.org>
272
273 * mep-asm.c (macros): Mark static & const.
274 (lookup_macro): Change return & m to const.
275 (expand_macro): Change mac to const.
276 (expand_string): Change pmacro to const.
277
9b2beaf7
MF		 2782021-07-01 Mike Frysinger <vapier@gentoo.org>
279
280 * nds32-asm.c (operand_fields): Rename to ...
281 (nds32_operand_fields): ... this.
282 (keyword_gpr): Rename to ...
283 (nds32_keyword_gpr): ... this.
284 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
285 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
286 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
287 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
288 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
289 Mark static.
290 (keywords): Rename to ...
291 (nds32_keywords): ... this.
292 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
293 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
294
ac8ef696
MF		 2952021-07-01 Mike Frysinger <vapier@gentoo.org>
296
297 * z80-dis.c (opc_ed): Make const.
298 (pref_ed): Make p const.
299
52b83874
MF		 3002021-07-01 Mike Frysinger <vapier@gentoo.org>
301
302 * microblaze-dis.c (get_field_special): Make op const.
303 (read_insn_microblaze): Make opr & op const. Rename opcodes to
304 microblaze_opcodes.
305 (print_insn_microblaze): Make op & pop const.
306 (get_insn_microblaze): Make op const. Rename opcodes to
307 microblaze_opcodes.
308 (microblaze_get_target_address): Likewise.
309 * microblaze-opc.h (struct op_code_struct): Make const.
310 Rename opcodes to microblaze_opcodes.
311
6c2ede01
MF		 3122021-07-01 Mike Frysinger <vapier@gentoo.org>
313
314 * aarch64-gen.c (aarch64_opcode_table): Add const.
315 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
316
46b8b3d6
AB		 3172021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
318
319 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
320 available.
321
ded5cb94
AM		 3222021-06-22 Alan Modra <amodra@gmail.com>
323
324 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
325 print separator for pcrel insns.
326
47399e9c
AM		 3272021-06-19 Alan Modra <amodra@gmail.com>
328
329 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
330
d984392e
AM		 3312021-06-19 Alan Modra <amodra@gmail.com>
332
333 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
334 entire buffer.
335
7993124e
AM		 3362021-06-17 Alan Modra <amodra@gmail.com>
337
338 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
339 in table.
340
a38d1396
AM		 3412021-06-03 Alan Modra <amodra@gmail.com>
342
343 PR 1202
344 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
345 Use unsigned int for inst.
346
8f467114
SV		 3472021-06-02 Shahab Vahedi <shahab@synopsys.com>
348
349 * arc-dis.c (arc_option_arg_t): New enumeration.
350 (arc_options): New variable.
351 (disassembler_options_arc): New function.
352 (print_arc_disassembler_options): Reimplement in terms of
353 "disassembler_options_arc".
354
1ff6a3b8
AM		 3552021-05-29 Alan Modra <amodra@gmail.com>
356
357 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
358 Don't special case PPC_OPCODE_RAW.
359 (lookup_prefix): Likewise.
360 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
361 (print_insn_powerpc): ..update caller.
362 * ppc-opc.c (EXT): Define.
363 (powerpc_opcodes): Mark extended mnemonics with EXT.
364 (prefix_opcodes, vle_opcodes): Likewise.
365 (XISEL, XISEL_MASK): Add cr field and simplify.
366 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
367 all isel variants to where the base mnemonic belongs. Sort dstt,
368 dststt and dssall.
369
49149d59
MR		 3702021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
371
372 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
373 COP3 opcode instructions.
374
9573a461
MR		 3752021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
376
377 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
378 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
379 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
380 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
381 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
382 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
383 "cop2", and "cop3" entries.
384
fa495743
MR		 3852021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
386
387 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
388 entries and associated comments.
389
b930964c
MR		 3902021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
391
392 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
393 of "c0".
394
dd844468
MR		 3952021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
396
397 * mips-dis.c (mips_cp1_names_mips): New variable.
398 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
399 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
400 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
401 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
402 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
403 "loongson2f".
404
9204ccd4
MR		 4052021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
406
407 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
408 handling code over to...
409 <OP_REG_CONTROL>: ... this new case.
410 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
411 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
412 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
413 replacing the `G' operand code with `g'. Update "cftc1" and
414 "cftc2" entries replacing the `E' operand code with `y'.
415 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
416 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
417 entries replacing the `G' operand code with `g'.
418
a3fb396f
MR		 4192021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
420
421 * mips-dis.c (mips_cp0_names_r3900): New variable.
422 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
423 for "r3900".
424
cccc84fa
MR		 4252021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
426
427 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
428 and "mtthc2" to using the `G' rather than `g' operand code for
429 the coprocessor control register referred.
430
c9de3168
MR		 4312021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
432
433 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
434 entries with each other.
435
ebcab741
PB		 4362021-05-27 Peter Bergner <bergner@linux.ibm.com>
437
438 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
439
bc30a119
AM		 4402021-05-25 Alan Modra <amodra@gmail.com>
441
442 * cris-desc.c: Regenerate.
443 * cris-desc.h: Regenerate.
444 * cris-opc.h: Regenerate.
445 * po/POTFILES.in: Regenerate.
446
54711280
MF		 4472021-05-24 Mike Frysinger <vapier@gentoo.org>
448
449 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
450 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
451 (CGEN_CPUS): Add cris.
452 (CRIS_DEPS): Define.
453 (stamp-cris): New rule.
454 * cgen.sh: Handle desc action.
455 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
456 * Makefile.in, configure: Regenerate.
457
113bb761
JN		 4582021-05-18 Job Noorman <mtvec@pm.me>
459
460 PR 27814
461 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
462 the elf objects.
463
e683cb41
AC		 4642021-05-17 Alex Coplan <alex.coplan@arm.com>
465
466 * arm-dis.c (mve_opcodes): Fix disassembly of
467 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
468 (is_mve_encoding_conflict): MVE vector loads should not match
469 when P = W = 0.
470 (is_mve_unpredictable): It's not unpredictable to use the same
471 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
472
a680affc
NC		 4732021-05-11 Nick Clifton <nickc@redhat.com>
474
475 PR 27840
476 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
477 the end of the code buffer.
478
0b3e14c9
SH		 4792021-05-06 Stafford Horne <shorne@gmail.com>
480
481 PR 21464
482 * or1k-asm.c: Regenerate.
483
6aee2cb2
MF		 4842021-05-01 Max Filippov <jcmvbkbc@gmail.com>
485
486 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
487 info->insn_info_valid.
488
fe134c65
JB		 4892021-04-26 Jan Beulich <jbeulich@suse.com>
490
491 * i386-opc.tbl (lea): Add Optimize.
492 * opcodes/i386-tbl.h: Re-generate.
493
b3ea7639
MF		 4942020-04-23 Max Filippov <jcmvbkbc@gmail.com>
495
496 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
497 of l32r fetch and display referenced literal value.
498
c1cbb7d8
MF		 4992021-04-23 Max Filippov <jcmvbkbc@gmail.com>
500
501 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
502 to 4 for literal disassembly.
503
02202574
PW		 5042021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
505
506 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
507 for TLBI instruction.
508
cd6608e4
PW		 5092021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
510
511 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
512 DC instruction.
513
fe1640ff
JB		 5142021-04-19 Jan Beulich <jbeulich@suse.com>
515
516 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
517 "qualifier".
518 (convert_mov_to_movewide): Add initializer for "value".
519
100e914d
PW		 5202021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
521
522 * aarch64-opc.c: Add RME system registers.
523
a21b96dd
NC		 5242021-04-16 Lifang Xia <lifang_xia@c-sky.com>
525
526 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
527 "addi d,CV,z" to "c.mv d,CV".
528
43e05cd4
AM		 5292021-04-12 Alan Modra <amodra@gmail.com>
530
531 * configure.ac (--enable-checking): Add support.
532 * config.in: Regenerate.
533 * configure: Regenerate.
534
52efda82
TB		 5352021-04-09 Tejas Belagod <tejas.belagod@arm.com>
536
537 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
538 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
539
c3f72de4
AM		 5402021-04-09 Alan Modra <amodra@gmail.com>
541
542 * ppc-dis.c (struct dis_private): Add "special".
543 (POWERPC_DIALECT): Delete. Replace uses with..
544 (private_data): ..this. New inline function.
545 (disassemble_init_powerpc): Init "special" names.
546 (skip_optional_operands): Add is_pcrel arg, set when detecting R
547 field of prefix instructions.
548 (bsearch_reloc, print_got_plt): New functions.
549 (print_insn_powerpc): For pcrel instructions, print target address
550 and symbol if known, and decode plt and got loads too.
551
ce7d813a
AM		 5522021-04-08 Alan Modra <amodra@gmail.com>
553
554 PR 27684
555 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
556
97bf40d8
AM		 5572021-04-08 Alan Modra <amodra@gmail.com>
558
559 PR 27676
560 * ppc-opc.c (DCBT_EO): Move earlier.
561 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
562 (powerpc_operands): Add THCT and THDS entries.
563 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
564
a2e66773
AM		 5652021-04-06 Alan Modra <amodra@gmail.com>
566
567 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
568 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
569 symbol_at_address_func.
570
ab2af25e
AM		 5712021-04-05 Alan Modra <amodra@gmail.com>
572
573 * configure.ac: Don't check for limits.h, string.h, strings.h or
574 stdlib.h.
575 (AC_ISC_POSIX): Don't invoke.
576 * sysdep.h: Include stdlib.h and string.h unconditionally.
577 * i386-opc.h: Include limits.h unconditionally.
578 * wasm32-dis.c: Likewise.
579 * cgen-opc.c: Don't include alloca-conf.h.
580 * config.in: Regenerate.
581 * configure: Regenerate.
582
e9b095a5
ML		 5832021-04-01 Martin Liska <mliska@suse.cz>
584
585 * arm-dis.c (strneq): Remove strneq and use startswith.
586 * cr16-dis.c (print_insn_cr16): Likewise.
587 * score-dis.c (streq): Likewise.
588 (strneq): Likewise.
589 * score7-dis.c (strneq): Likewise.
590
1cb108e4
AM		 5912021-04-01 Alan Modra <amodra@gmail.com>
592
593 PR 27675
594 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
595
78933a4a
AM		 5962021-03-31 Alan Modra <amodra@gmail.com>
597
598 * sysdep.h (POISON_BFD_BOOLEAN): Define.
599 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
600 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
601 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
602 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
603 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
604 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
605 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
606 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
607 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
608 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
609 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
610 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
611 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
612 and TRUE with true throughout.
613
3dfb1b6d
AM		 6142021-03-31 Alan Modra <amodra@gmail.com>
615
616 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
617 * aarch64-dis.h: Likewise.
618 * aarch64-opc.c: Likewise.
619 * avr-dis.c: Likewise.
620 * csky-dis.c: Likewise.
621 * nds32-asm.c: Likewise.
622 * nds32-dis.c: Likewise.
623 * nfp-dis.c: Likewise.
624 * riscv-dis.c: Likewise.
625 * s12z-dis.c: Likewise.
626 * wasm32-dis.c: Likewise.
627
5e042380
JB		 6282021-03-30 Jan Beulich <jbeulich@suse.com>
629
630 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
631 (i386_seg_prefixes): New.
632 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
633 (i386_seg_prefixes): Declare.
634
34684862
JB		 6352021-03-30 Jan Beulich <jbeulich@suse.com>
636
637 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
638
6288d05f
JB		 6392021-03-30 Jan Beulich <jbeulich@suse.com>
640
641 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
642 * i386-reg.tbl (st): Move down.
643 (st(0)): Delete. Extend comment.
644 * i386-tbl.h: Re-generate.
645
bbe1eca6
JB		 6462021-03-29 Jan Beulich <jbeulich@suse.com>
647
648 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
649 (cmpsd): Move next to cmps.
650 (movsd): Move next to movs.
651 (cmpxchg16b): Move to separate section.
652 (fisttp, fisttpll): Likewise.
653 (monitor, mwait): Likewise.
654 * i386-tbl.h: Re-generate.
655
c8cad9d3
JB		 6562021-03-29 Jan Beulich <jbeulich@suse.com>
657
658 * i386-opc.tbl (psadbw): Add <sse2:comm>.
659 (vpsadbw): Add C.
660 * i386-tbl.h: Re-generate.
661
5cdaf100
JB		 6622021-03-29 Jan Beulich <jbeulich@suse.com>
663
664 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
665 pclmul, gfni): New templates. Use them wherever possible. Move
666 SSE4.1 pextrw into respective section.
667 * i386-tbl.h: Re-generate.
668
73e45eb2
JB		 6692021-03-29 Jan Beulich <jbeulich@suse.com>
670
671 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
672 strtoull(). Bump upper loop bound. Widen masks. Sanity check
673 "length".
674 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
675 Convert all of their uses to representation in opcode.
676
9df6f676
JB		 6772021-03-29 Jan Beulich <jbeulich@suse.com>
678
679 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
680 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
681 value of None. Shrink operands to 3 bits.
682
389d00a5
JB		 6832021-03-29 Jan Beulich <jbeulich@suse.com>
684
685 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 686 "space".
389d00a5
JB		 687 (output_i386_opcode): New local variable "space". Adjust
688 process_i386_opcode_modifier() invocation.
689 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
690 invocation.
691 * i386-tbl.h: Re-generate.
692
63b4cc53
AM		 6932021-03-29 Alan Modra <amodra@gmail.com>
694
695 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
696 (fp_qualifier_p, get_data_pattern): Likewise.
697 (aarch64_get_operand_modifier_from_value): Likewise.
698 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
699 (operand_variant_qualifier_p): Likewise.
700 (qualifier_value_in_range_constraint_p): Likewise.
701 (aarch64_get_qualifier_esize): Likewise.
702 (aarch64_get_qualifier_nelem): Likewise.
703 (aarch64_get_qualifier_standard_value): Likewise.
704 (get_lower_bound, get_upper_bound): Likewise.
705 (aarch64_find_best_match, match_operands_qualifier): Likewise.
706 (aarch64_print_operand): Likewise.
707 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
708 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
709 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
710 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
711 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
712 (print_insn_tic6x): Likewise.
713
3d7d6c1b
AM		 7142021-03-29 Alan Modra <amodra@gmail.com>
715
716 * arc-dis.c (extract_operand_value): Correct NULL cast.
717 * frv-opc.h: Regenerate.
718
c3344b62
JB		 7192021-03-26 Jan Beulich <jbeulich@suse.com>
720
721 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
722 MMX form.
723 * i386-tbl.h: Re-generate.
724
efa30ac3
HAQ		 7252021-03-25 Abid Qadeer <abidh@codesourcery.com>
726
727 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
728 immediate in br.n instruction.
729
596a02ff
JB		 7302021-03-25 Jan Beulich <jbeulich@suse.com>
731
732 * i386-dis.c (XMGatherD, VexGatherD): New.
733 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
734 (print_insn): Check masking for S/G insns.
735 (OP_E_memory): New local variable check_gather. Extend mandatory
736 SIB check. Check register conflicts for (EVEX-encoded) gathers.
737 Extend check for disallowed 16-bit addressing.
738 (OP_VEX): New local variables modrm_reg and sib_index. Convert
739 if()s to switch(). Check register conflicts for (VEX-encoded)
740 gathers. Drop no longer reachable cases.
741 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
742 vgatherdp*.
743
53642852
JB		 7442021-03-25 Jan Beulich <jbeulich@suse.com>
745
746 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
747 zeroing-masking without masking.
748
c0e54661
JB		 7492021-03-25 Jan Beulich <jbeulich@suse.com>
750
751 * i386-opc.tbl (invlpgb): Fix multi-operand form.
752 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
753 single-operand forms as deprecated.
754 * i386-tbl.h: Re-generate.
755
5a403766
AM		 7562021-03-25 Alan Modra <amodra@gmail.com>
757
758 PR 27647
759 * ppc-opc.c (XLOCB_MASK): Delete.
760 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
761 XLBH_MASK.
762 (powerpc_opcodes): Accept a BH field on all extended forms of
763 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
764
9a182d04
JB		 7652021-03-24 Jan Beulich <jbeulich@suse.com>
766
767 * i386-gen.c (output_i386_opcode): Drop processing of
768 opcode_length. Calculate length from base_opcode. Adjust prefix
769 encoding determination.
770 (process_i386_opcodes): Drop output of fake opcode_length.
771 * i386-opc.h (struct insn_template): Drop opcode_length field.
772 * i386-opc.tbl: Drop opcode length field from all templates.
773 * i386-tbl.h: Re-generate.
774
35648716
JB		 7752021-03-24 Jan Beulich <jbeulich@suse.com>
776
777 * i386-gen.c (process_i386_opcode_modifier): Return void. New
778 parameter "prefix". Drop local variable "regular_encoding".
779 Record prefix setting / check for consistency.
780 (output_i386_opcode): Parse opcode_length and base_opcode
781 earlier. Derive prefix encoding. Drop no longer applicable
782 consistency checking. Adjust process_i386_opcode_modifier()
783 invocation.
784 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
785 invocation.
786 * i386-tbl.h: Re-generate.
787
31184569
JB		 7882021-03-24 Jan Beulich <jbeulich@suse.com>
789
790 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
791 check.
792 * i386-opc.h (Prefix_*): Move #define-s.
793 * i386-opc.tbl: Move pseudo prefix enumerator values to
794 extension opcode field. Introduce pseudopfx template.
795 * i386-tbl.h: Re-generate.
796
b933fa4b
JB		 7972021-03-23 Jan Beulich <jbeulich@suse.com>
798
799 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
800 comment.
801 * i386-tbl.h: Re-generate.
802
dac10fb0
JB		 8032021-03-23 Jan Beulich <jbeulich@suse.com>
804
805 * i386-opc.h (struct insn_template): Move cpu_flags field past
806 opcode_modifier one.
807 * i386-tbl.h: Re-generate.
808
441f6aca
JB		 8092021-03-23 Jan Beulich <jbeulich@suse.com>
810
811 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
812 * i386-opc.h (OpcodeSpace): New enumerator.
813 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
814 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
815 SPACE_XOP09, SPACE_XOP0A): ... respectively.
816 (struct i386_opcode_modifier): New field opcodespace. Shrink
817 opcodeprefix field.
818 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
819 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
820 OpcodePrefix uses.
821 * i386-tbl.h: Re-generate.
822
08dedd66
ML		 8232021-03-22 Martin Liska <mliska@suse.cz>
824
825 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
826 * arc-dis.c (parse_option): Likewise.
827 * arm-dis.c (parse_arm_disassembler_options): Likewise.
828 * cris-dis.c (print_with_operands): Likewise.
829 * h8300-dis.c (bfd_h8_disassemble): Likewise.
830 * i386-dis.c (print_insn): Likewise.
831 * ia64-gen.c (fetch_insn_class): Likewise.
832 (parse_resource_users): Likewise.
833 (in_iclass): Likewise.
834 (lookup_specifier): Likewise.
835 (insert_opcode_dependencies): Likewise.
836 * mips-dis.c (parse_mips_ase_option): Likewise.
837 (parse_mips_dis_option): Likewise.
838 * s390-dis.c (disassemble_init_s390): Likewise.
839 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
840
80d49d6a
KLC		 8412021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
842
843 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
844
7fce7ea9
PW		 8452021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
846
847 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
848 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
849
78c84bf9
AM		 8502021-03-12 Alan Modra <amodra@gmail.com>
851
852 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
853
fd1fd061
JB		 8542021-03-11 Jan Beulich <jbeulich@suse.com>
855
856 * i386-dis.c (OP_XMM): Re-order checks.
857
ac7a2311
JB		 8582021-03-11 Jan Beulich <jbeulich@suse.com>
859
860 * i386-dis.c (putop): Drop need_vex check when also checking
861 vex.evex.
862 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
863 checking vex.b.
864
da944c8a
JB		 8652021-03-11 Jan Beulich <jbeulich@suse.com>
866
867 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
868 checks. Move case label past broadcast check.
869
b763d508
JB		 8702021-03-10 Jan Beulich <jbeulich@suse.com>
871
872 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
873 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
874 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
875 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
876 EVEX_W_0F38C7_M_0_L_2): Delete.
877 (REG_EVEX_0F38C7_M_0_L_2): New.
878 (intel_operand_size): Handle VEX and EVEX the same for
879 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
880 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
881 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
882 vex_vsib_q_w_d_mode uses.
883 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
884 0F38A1, and 0F38A3 entries.
885 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
886 entry.
887 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
888 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
889 0F38A3 entries.
890
32e31ad7
JB		 8912021-03-10 Jan Beulich <jbeulich@suse.com>
892
893 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
894 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
895 MOD_VEX_0FXOP_09_12): Rename to ...
896 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
897 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
898 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
899 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
900 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
901 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
902 (reg_table): Adjust comments.
903 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
904 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
905 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
906 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
907 (vex_len_table): Adjust opcode 0A_12 entry.
908 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
909 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
910 (rm_table): Move hreset entry.
911
85ba7507
JB		 9122021-03-10 Jan Beulich <jbeulich@suse.com>
913
914 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
915 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
916 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
917 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
918 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
919 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
920 (get_valid_dis386): Also handle 512-bit vector length when
921 vectoring into vex_len_table[].
922 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
923 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
924 entries.
925 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
926 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
927 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
928 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
929 entries.
930
066f82b9
JB		 9312021-03-10 Jan Beulich <jbeulich@suse.com>
932
933 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
934 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
935 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
936 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
937 entries.
938 * i386-dis-evex-len.h (evex_len_table): Likewise.
939 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
940
fc681dd6
JB		 9412021-03-10 Jan Beulich <jbeulich@suse.com>
942
943 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
944 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
945 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
946 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
947 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
948 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
949 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
950 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
951 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
952 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
953 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
954 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
955 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
956 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
957 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
958 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
959 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
960 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
961 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
962 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
963 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
964 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
965 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
966 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
967 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
968 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
969 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
970 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
971 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
972 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
973 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
974 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
975 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
976 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
977 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
978 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
979 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
980 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
981 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
982 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
983 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
984 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
985 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
986 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
987 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
988 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
989 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
990 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
991 EVEX_W_0F3A43_L_n): New.
992 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
993 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
994 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
995 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
996 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
997 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
998 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
999 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
1000 0F385B, 0F38C6, and 0F38C7 entries.
1001 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
1002 0F38C6 and 0F38C7.
1003 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
1004 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
1005 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
1006 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
1007
13954a31
JB		 10082021-03-10 Jan Beulich <jbeulich@suse.com>
1009
1010 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
1011 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
1012 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
1013 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
1014 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
1015 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
1016 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
1017 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
1018 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1019 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1020 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1021 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1022 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1023 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1024 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1025 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1026 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1027 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1028 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1029 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1030 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1031 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1032 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1033 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1034 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1035 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1036 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1037 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1038 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1039 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1040 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1041 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1042 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1043 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1044 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1045 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1046 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1047 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1048 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1049 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1050 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1051 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1052 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1053 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1054 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1055 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1056 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1057 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1058 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1059 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1060 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1061 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1062 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1063 VEX_W_0F99_P_2_LEN_0): Delete.
1064 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1065 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1066 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1067 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1068 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1069 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1070 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1071 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1072 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1073 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1074 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1075 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1076 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1077 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1078 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1079 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1080 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1081 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1082 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1083 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1084 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1085 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1086 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1087 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1088 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1089 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1090 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1091 (prefix_table): No longer link to vex_len_table[] for opcodes
1092 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1093 0F92, 0F93, 0F98, and 0F99.
1094 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1095 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1096 0F98, and 0F99.
1097 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1098 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1099 0F98, and 0F99.
1100 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1101 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1102 0F98, and 0F99.
1103 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1104 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1105 0F98, and 0F99.
1106
14d10c6c
JB		 11072021-03-10 Jan Beulich <jbeulich@suse.com>
1108
1109 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1110 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1111 REG_VEX_0F73_M_0 respectively.
1112 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1113 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1114 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1115 MOD_VEX_0F73_REG_7): Delete.
1116 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1117 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1118 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1119 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1120 PREFIX_VEX_0F3AF0_L_0 respectively.
1121 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1122 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1123 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1124 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1125 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1126 VEX_LEN_0F38F7): New.
1127 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1128 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1129 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1130 0F38F3.
1131 (prefix_table): No longer link to vex_len_table[] for opcodes
1132 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1133 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1134 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1135 0F38F6, 0F38F7, and 0F3AF0.
1136 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1137 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1138 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1139 0F73.
1140
00ec1875
JB		 11412021-03-10 Jan Beulich <jbeulich@suse.com>
1142
1143 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1144 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1145 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1146 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1147 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1148 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1149 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1150 73.
1151 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1152 0F72, and 0F73.
1153 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1154 0F73.
1155
31941983
JB		 11562021-03-10 Jan Beulich <jbeulich@suse.com>
1157
1158 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1159 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1160 (reg_table): Don't link to mod_table[] where not needed. Add
1161 PREFIX_IGNORED to nop entries.
1162 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1163 (mod_table): Add nop entries next to prefetch ones. Drop
1164 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1165 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1166 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1167 PREFIX_OPCODE from endbr* entries.
1168 (get_valid_dis386): Also consider entry's name when zapping
1169 vindex.
1170 (print_insn): Handle PREFIX_IGNORED.
1171
742732c7
JB		 11722021-03-09 Jan Beulich <jbeulich@suse.com>
1173
1174 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1175 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1176 element.
1177 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1178 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1179 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1180 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1181 (struct i386_opcode_modifier): Delete notrackprefixok,
1182 islockable, hleprefixok, and repprefixok fields. Add prefixok
1183 field.
1184 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1185 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1186 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1187 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1188 Replace HLEPrefixOk.
1189 * opcodes/i386-tbl.h: Re-generate.
1190
e93a3b27
JB		 11912021-03-09 Jan Beulich <jbeulich@suse.com>
1192
1193 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1194 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1195 64-bit form.
1196 * opcodes/i386-tbl.h: Re-generate.
1197
75363b6d
JB		 11982021-03-03 Jan Beulich <jbeulich@suse.com>
1199
1200 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1201 for {} instead of {0}. Don't look for '0'.
1202 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1203 size specifiers.
1204
5a9f5403
NC		 12052021-02-19 Nelson Chu <nelson.chu@sifive.com>
1206
1207 PR 27158
1208 * riscv-dis.c (print_insn_args): Updated encoding macros.
1209 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1210 (match_c_addi16sp): Updated encoding macros.
1211 (match_c_lui): Likewise.
1212 (match_c_lui_with_hint): Likewise.
1213 (match_c_addi4spn): Likewise.
1214 (match_c_slli): Likewise.
1215 (match_slli_as_c_slli): Likewise.
1216 (match_c_slli64): Likewise.
1217 (match_srxi_as_c_srxi): Likewise.
1218 (riscv_insn_types): Added .insn css/cl/cs.
1219
3d73d29e
NC		 12202021-02-18 Nelson Chu <nelson.chu@sifive.com>
1221
1222 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1223 (default_priv_spec): Updated type to riscv_spec_class.
1224 (parse_riscv_dis_option): Updated.
1225 * riscv-opc.c: Moved stuff and make the file tidy.
1226
b9b204b3
AM		 12272021-02-17 Alan Modra <amodra@gmail.com>
1228
1229 * wasm32-dis.c: Include limits.h.
1230 (CHAR_BIT): Provide backup define.
1231 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1232 Correct signed overflow checking.
1233
394ae71f
JB		 12342021-02-16 Jan Beulich <jbeulich@suse.com>
1235
1236 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1237 * i386-tbl.h: Re-generate.
1238
b818b220
JB		 12392021-02-16 Jan Beulich <jbeulich@suse.com>
1240
1241 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1242 Oword.
1243 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1244
ba2b480f
AK		 12452021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1246
1247 * s390-mkopc.c (main): Accept arch14 as cpu string.
1248 * s390-opc.txt: Add new arch14 instructions.
1249
95148614
NA		 12502021-02-04 Nick Alcock <nick.alcock@oracle.com>
1251
1252 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1253 favour of LIBINTL.
1254 * configure: Regenerated.
1255
bfd428bc
MF		 12562021-02-08 Mike Frysinger <vapier@gentoo.org>
1257
1258 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1259 * tic54x-opc.c (regs): Rename to ...
1260 (tic54x_regs): ... this.
1261 (mmregs): Rename to ...
1262 (tic54x_mmregs): ... this.
1263 (condition_codes): Rename to ...
1264 (tic54x_condition_codes): ... this.
1265 (cc2_codes): Rename to ...
1266 (tic54x_cc2_codes): ... this.
1267 (cc3_codes): Rename to ...
1268 (tic54x_cc3_codes): ... this.
1269 (status_bits): Rename to ...
1270 (tic54x_status_bits): ... this.
1271 (misc_symbols): Rename to ...
1272 (tic54x_misc_symbols): ... this.
1273
24075dcc
NC		 12742021-02-04 Nelson Chu <nelson.chu@sifive.com>
1275
1276 * riscv-opc.c (MASK_RVB_IMM): Removed.
1277 (riscv_opcodes): Removed zb* instructions.
1278 (riscv_ext_version_table): Removed versions for zb*.
1279
c3ffb8f3
AM		 12802021-01-26 Alan Modra <amodra@gmail.com>
1281
1282 * i386-gen.c (parse_template): Ensure entire template_instance
1283 is initialised.
1284
1942a048
NC		 12852021-01-15 Nelson Chu <nelson.chu@sifive.com>
1286
1287 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1288 (riscv_fpr_names_abi): Likewise.
1289 (riscv_opcodes): Likewise.
1290 (riscv_insn_types): Likewise.
1291
b800637e
NC		 12922021-01-15 Nelson Chu <nelson.chu@sifive.com>
1293
1294 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1295
dcd709e0
NC		 12962021-01-15 Nelson Chu <nelson.chu@sifive.com>
1297
1298 * riscv-dis.c: Comments tidy and improvement.
1299 * riscv-opc.c: Likewise.
1300
5347ed60
AM		 13012021-01-13 Alan Modra <amodra@gmail.com>
1302
1303 * Makefile.in: Regenerate.
1304
d546b610
L		 13052021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1306
1307 PR binutils/26792
1308 * configure.ac: Use GNU_MAKE_JOBSERVER.
1309 * aclocal.m4: Regenerated.
1310 * configure: Likewise.
1311
6d104cac
NC		 13122021-01-12 Nick Clifton <nickc@redhat.com>
1313
1314 * po/sr.po: Updated Serbian translation.
1315
83b33c6c
L		 13162021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1317
1318 PR ld/27173
1319 * configure: Regenerated.
1320
82c70b08
KT		 13212021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1322
1323 * aarch64-asm-2.c: Regenerate.
1324 * aarch64-dis-2.c: Likewise.
1325 * aarch64-opc-2.c: Likewise.
1326 * aarch64-opc.c (aarch64_print_operand):
1327 Delete handling of AARCH64_OPND_CSRE_CSR.
1328 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1329 (CSRE): Likewise.
1330 (_CSRE_INSN): Likewise.
1331 (aarch64_opcode_table): Delete csr.
1332
a8aa72b9
NC		 13332021-01-11 Nick Clifton <nickc@redhat.com>
1334
1335 * po/de.po: Updated German translation.
1336 * po/fr.po: Updated French translation.
1337 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1338 * po/sv.po: Updated Swedish translation.
1339 * po/uk.po: Updated Ukranian translation.
1340
a4966cd9
L		 13412021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1342
1343 * configure: Regenerated.
1344
573fe3fb
NC		 13452021-01-09 Nick Clifton <nickc@redhat.com>
1346
1347 * configure: Regenerate.
1348 * po/opcodes.pot: Regenerate.
1349
055bc77a
NC		 13502021-01-09 Nick Clifton <nickc@redhat.com>
1351
1352 * 2.36 release branch crated.
1353
aae7fcb8
PB		 13542021-01-08 Peter Bergner <bergner@linux.ibm.com>
1355
1356 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1357 (DW, (XRC_MASK): Define.
1358 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1359
64307045
AM		 13602021-01-09 Alan Modra <amodra@gmail.com>
1361
1362 * configure: Regenerate.
1363
ed205222
NC		 13642021-01-08 Nick Clifton <nickc@redhat.com>
1365
1366 * po/sv.po: Updated Swedish translation.
1367
fb932b57
NC		 13682021-01-08 Nick Clifton <nickc@redhat.com>
1369
e84c8716
NC		 1370 PR 27129
1371 * aarch64-dis.c (determine_disassembling_preference): Move call to
1372 aarch64_match_operands_constraint outside of the assertion.
1373 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1374 Replace with a return of FALSE.
1375
fb932b57
NC		 1376 PR 27139
1377 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1378 core system register.
1379
f4782128
ST		 13802021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1381
1382 * configure: Regenerate.
1383
1b0927db
NC		 13842021-01-07 Nick Clifton <nickc@redhat.com>
1385
1386 * po/fr.po: Updated French translation.
1387
3b288c8e
FN		 13882021-01-07 Fredrik Noring <noring@nocrew.org>
1389
1390 * m68k-opc.c (chkl): Change minimum architecture requirement to
1391 m68020.
1392
aa881ecd
PT		 13932021-01-07 Philipp Tomsich <prt@gnu.org>
1394
1395 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1396
2652cfad
CXW		 13972021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1398 Jim Wilson <jimw@sifive.com>
1399 Andrew Waterman <andrew@sifive.com>
1400 Maxim Blinov <maxim.blinov@embecosm.com>
1401 Kito Cheng <kito.cheng@sifive.com>
1402 Nelson Chu <nelson.chu@sifive.com>
1403
1404 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1405 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1406
250d07de
AM		 14072021-01-01 Alan Modra <amodra@gmail.com>
1408
1409 Update year range in copyright notice of all files.
1410
c2795844 1411For older changes see ChangeLog-2020
3499769a 1412\f
d87bef3a 1413Copyright (C) 2021-2023 Free Software Foundation, Inc.
3499769a
AM		 1414
1415Copying and distribution of this file, with or without modification,
1416are permitted in any medium without royalty provided the copyright
1417notice and this notice are preserved.
1418
1419Local Variables:
1420mode: change-log
1421left-margin: 8
1422fill-column: 74
1423version-control: never
1424End:
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