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1 | /* cpustate.h -- Prototypes for AArch64 simulator functions. |
2 | ||
618f726f | 3 | Copyright (C) 2015-2016 Free Software Foundation, Inc. |
2e8cf49e NC |
4 | |
5 | Contributed by Red Hat. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | ||
24 | #include "sim-main.h" | |
25 | #include "cpustate.h" | |
26 | #include "simulator.h" | |
27 | ||
28 | /* Some operands are allowed to access the stack pointer (reg 31). | |
29 | For others a read from r31 always returns 0, and a write to r31 is ignored. */ | |
30 | #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg)) | |
31 | ||
32 | void | |
33 | aarch64_set_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint64_t val) | |
34 | { | |
35 | if (reg == R31 && ! r31_is_sp) | |
36 | { | |
37 | TRACE_REGISTER (cpu, " GR[31] NOT CHANGED!"); | |
38 | return; | |
39 | } | |
40 | ||
41 | if (val != cpu->gr[reg].u64) | |
42 | TRACE_REGISTER (cpu, | |
43 | " GR[%2d] changes from %16" PRIx64 " to %16" PRIx64, | |
44 | reg, cpu->gr[reg].u64, val); | |
45 | ||
46 | cpu->gr[reg].u64 = val; | |
47 | } | |
48 | ||
49 | void | |
50 | aarch64_set_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp, int64_t val) | |
51 | { | |
52 | if (reg == R31 && ! r31_is_sp) | |
53 | { | |
54 | TRACE_REGISTER (cpu, " GR[31] NOT CHANGED!"); | |
55 | return; | |
56 | } | |
57 | ||
58 | if (val != cpu->gr[reg].s64) | |
59 | TRACE_REGISTER (cpu, | |
60 | " GR[%2d] changes from %16" PRIx64 " to %16" PRIx64, | |
61 | reg, cpu->gr[reg].s64, val); | |
62 | ||
63 | cpu->gr[reg].s64 = val; | |
64 | } | |
65 | ||
66 | uint64_t | |
67 | aarch64_get_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
68 | { | |
69 | return cpu->gr[reg_num(reg)].u64; | |
70 | } | |
71 | ||
72 | int64_t | |
73 | aarch64_get_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
74 | { | |
75 | return cpu->gr[reg_num(reg)].s64; | |
76 | } | |
77 | ||
78 | uint32_t | |
79 | aarch64_get_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
80 | { | |
81 | return cpu->gr[reg_num(reg)].u32; | |
82 | } | |
83 | ||
84 | int32_t | |
85 | aarch64_get_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
86 | { | |
87 | return cpu->gr[reg_num(reg)].s32; | |
88 | } | |
89 | ||
90 | uint32_t | |
91 | aarch64_get_reg_u16 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
92 | { | |
93 | return cpu->gr[reg_num(reg)].u16; | |
94 | } | |
95 | ||
96 | int32_t | |
97 | aarch64_get_reg_s16 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
98 | { | |
99 | return cpu->gr[reg_num(reg)].s16; | |
100 | } | |
101 | ||
102 | uint32_t | |
103 | aarch64_get_reg_u8 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
104 | { | |
105 | return cpu->gr[reg_num(reg)].u8; | |
106 | } | |
107 | ||
108 | int32_t | |
109 | aarch64_get_reg_s8 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
110 | { | |
111 | return cpu->gr[reg_num(reg)].s8; | |
112 | } | |
113 | ||
114 | uint64_t | |
115 | aarch64_get_PC (sim_cpu *cpu) | |
116 | { | |
117 | return cpu->pc; | |
118 | } | |
119 | ||
120 | uint64_t | |
121 | aarch64_get_next_PC (sim_cpu *cpu) | |
122 | { | |
123 | return cpu->nextpc; | |
124 | } | |
125 | ||
126 | void | |
127 | aarch64_set_next_PC (sim_cpu *cpu, uint64_t next) | |
128 | { | |
129 | if (next != cpu->nextpc + 4) | |
130 | TRACE_REGISTER (cpu, | |
131 | " NextPC changes from %16" PRIx64 " to %16" PRIx64, | |
132 | cpu->nextpc, next); | |
133 | ||
134 | cpu->nextpc = next; | |
135 | } | |
136 | ||
137 | void | |
138 | aarch64_set_next_PC_by_offset (sim_cpu *cpu, int64_t offset) | |
139 | { | |
140 | if (cpu->pc + offset != cpu->nextpc + 4) | |
141 | TRACE_REGISTER (cpu, | |
142 | " NextPC changes from %16" PRIx64 " to %16" PRIx64, | |
143 | cpu->nextpc, cpu->pc + offset); | |
144 | ||
145 | cpu->nextpc = cpu->pc + offset; | |
146 | } | |
147 | ||
148 | /* Install nextpc as current pc. */ | |
149 | void | |
150 | aarch64_update_PC (sim_cpu *cpu) | |
151 | { | |
152 | cpu->pc = cpu->nextpc; | |
153 | /* Rezero the register we hand out when asked for ZR just in case it | |
154 | was used as the destination for a write by the previous | |
155 | instruction. */ | |
156 | cpu->gr[32].u64 = 0UL; | |
157 | } | |
158 | ||
159 | /* This instruction can be used to save the next PC to LR | |
160 | just before installing a branch PC. */ | |
161 | void | |
162 | aarch64_save_LR (sim_cpu *cpu) | |
163 | { | |
164 | if (cpu->gr[LR].u64 != cpu->nextpc) | |
165 | TRACE_REGISTER (cpu, | |
166 | " LR changes from %16" PRIx64 " to %16" PRIx64, | |
167 | cpu->gr[LR].u64, cpu->nextpc); | |
168 | ||
169 | cpu->gr[LR].u64 = cpu->nextpc; | |
170 | } | |
171 | ||
172 | static const char * | |
173 | decode_cpsr (FlagMask flags) | |
174 | { | |
175 | switch (flags & CPSR_ALL_FLAGS) | |
176 | { | |
177 | default: | |
178 | case 0: return "----"; | |
179 | case 1: return "---V"; | |
180 | case 2: return "--C-"; | |
181 | case 3: return "--CV"; | |
182 | case 4: return "-Z--"; | |
183 | case 5: return "-Z-V"; | |
184 | case 6: return "-ZC-"; | |
185 | case 7: return "-ZCV"; | |
186 | case 8: return "N---"; | |
187 | case 9: return "N--V"; | |
188 | case 10: return "N-C-"; | |
189 | case 11: return "N-CV"; | |
190 | case 12: return "NZ--"; | |
191 | case 13: return "NZ-V"; | |
192 | case 14: return "NZC-"; | |
193 | case 15: return "NZCV"; | |
194 | } | |
195 | } | |
196 | ||
197 | /* Retrieve the CPSR register as an int. */ | |
198 | uint32_t | |
199 | aarch64_get_CPSR (sim_cpu *cpu) | |
200 | { | |
201 | return cpu->CPSR; | |
202 | } | |
203 | ||
204 | /* Set the CPSR register as an int. */ | |
205 | void | |
206 | aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags) | |
207 | { | |
208 | if (TRACE_REGISTER_P (cpu)) | |
209 | { | |
210 | if (cpu->CPSR != new_flags) | |
211 | TRACE_REGISTER (cpu, | |
212 | " CPSR changes from %s to %s", | |
213 | decode_cpsr (cpu->CPSR), decode_cpsr (new_flags)); | |
214 | else | |
215 | TRACE_REGISTER (cpu, | |
216 | " CPSR stays at %s", decode_cpsr (cpu->CPSR)); | |
217 | } | |
218 | ||
219 | cpu->CPSR = new_flags & CPSR_ALL_FLAGS; | |
220 | } | |
221 | ||
222 | /* Read a specific subset of the CPSR as a bit pattern. */ | |
223 | uint32_t | |
224 | aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask) | |
225 | { | |
226 | return cpu->CPSR & mask; | |
227 | } | |
228 | ||
229 | /* Assign a specific subset of the CPSR as a bit pattern. */ | |
230 | void | |
231 | aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value) | |
232 | { | |
233 | uint32_t old_flags = cpu->CPSR; | |
234 | ||
235 | mask &= CPSR_ALL_FLAGS; | |
236 | cpu->CPSR &= ~ mask; | |
237 | cpu->CPSR |= (value & mask); | |
238 | ||
239 | if (old_flags != cpu->CPSR) | |
240 | TRACE_REGISTER (cpu, | |
241 | " CPSR changes from %s to %s", | |
242 | decode_cpsr (old_flags), decode_cpsr (cpu->CPSR)); | |
243 | } | |
244 | ||
245 | /* Test the value of a single CPSR returned as non-zero or zero. */ | |
246 | uint32_t | |
247 | aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
248 | { | |
249 | return cpu->CPSR & bit; | |
250 | } | |
251 | ||
252 | /* Set a single flag in the CPSR. */ | |
253 | void | |
254 | aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
255 | { | |
256 | uint32_t old_flags = cpu->CPSR; | |
257 | ||
258 | cpu->CPSR |= (bit & CPSR_ALL_FLAGS); | |
259 | ||
260 | if (old_flags != cpu->CPSR) | |
261 | TRACE_REGISTER (cpu, | |
262 | " CPSR changes from %s to %s", | |
263 | decode_cpsr (old_flags), decode_cpsr (cpu->CPSR)); | |
264 | } | |
265 | ||
266 | /* Clear a single flag in the CPSR. */ | |
267 | void | |
268 | aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
269 | { | |
270 | uint32_t old_flags = cpu->CPSR; | |
271 | ||
272 | cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS); | |
273 | ||
274 | if (old_flags != cpu->CPSR) | |
275 | TRACE_REGISTER (cpu, | |
276 | " CPSR changes from %s to %s", | |
277 | decode_cpsr (old_flags), decode_cpsr (cpu->CPSR)); | |
278 | } | |
279 | ||
280 | float | |
281 | aarch64_get_FP_float (sim_cpu *cpu, VReg reg) | |
282 | { | |
283 | return cpu->fr[reg].s; | |
284 | } | |
285 | ||
286 | double | |
287 | aarch64_get_FP_double (sim_cpu *cpu, VReg reg) | |
288 | { | |
289 | return cpu->fr[reg].d; | |
290 | } | |
291 | ||
292 | void | |
293 | aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a) | |
294 | { | |
295 | a->v[0] = cpu->fr[reg].v[0]; | |
296 | a->v[1] = cpu->fr[reg].v[1]; | |
297 | } | |
298 | ||
299 | void | |
300 | aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val) | |
301 | { | |
302 | if (val != cpu->fr[reg].s) | |
303 | TRACE_REGISTER (cpu, | |
304 | " FR[%d] changes from %f to %f", | |
305 | reg, cpu->fr[reg].s, val); | |
306 | ||
307 | cpu->fr[reg].s = val; | |
308 | } | |
309 | ||
310 | void | |
311 | aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val) | |
312 | { | |
313 | if (val != cpu->fr[reg].d) | |
314 | TRACE_REGISTER (cpu, | |
315 | " FR[%d] changes from %f to %f", | |
316 | reg, cpu->fr[reg].d, val); | |
317 | ||
318 | cpu->fr[reg].d = val; | |
319 | } | |
320 | ||
321 | void | |
322 | aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a) | |
323 | { | |
324 | if (cpu->fr[reg].v[0] != a.v[0] | |
325 | || cpu->fr[reg].v[1] != a.v[1]) | |
326 | TRACE_REGISTER (cpu, | |
327 | " FR[%d] changes from [%0lx %0lx] to [%lx %lx] ", | |
328 | reg, | |
329 | cpu->fr[reg].v[0], cpu->fr[reg].v[1], | |
330 | a.v[0], a.v[1]); | |
331 | ||
332 | cpu->fr[reg].v[0] = a.v[0]; | |
333 | cpu->fr[reg].v[1] = a.v[1]; | |
334 | } | |
335 | ||
336 | uint64_t | |
337 | aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element) | |
338 | { | |
339 | return cpu->fr[reg].v[element]; | |
340 | } | |
341 | ||
342 | uint32_t | |
343 | aarch64_get_vec_u32 (sim_cpu *cpu, VReg regno, unsigned element) | |
344 | { | |
345 | return cpu->fr[regno].w[element]; | |
346 | } | |
347 | ||
348 | uint16_t | |
349 | aarch64_get_vec_u16 (sim_cpu *cpu, VReg regno, unsigned element) | |
350 | { | |
351 | return cpu->fr[regno].h[element]; | |
352 | } | |
353 | ||
354 | uint8_t | |
355 | aarch64_get_vec_u8 (sim_cpu *cpu, VReg regno, unsigned element) | |
356 | { | |
357 | return cpu->fr[regno].b[element]; | |
358 | } | |
359 | ||
360 | void | |
361 | aarch64_set_vec_u64 (sim_cpu * cpu, | |
362 | VReg regno, | |
363 | unsigned element, | |
364 | uint64_t value) | |
365 | { | |
366 | if (value != cpu->fr[regno].v[element]) | |
367 | TRACE_REGISTER (cpu, | |
368 | " VR[%2d].<long>[%d] changes from %16" PRIx64 | |
369 | " to %16" PRIx64, | |
370 | regno, element, cpu->fr[regno].v[element], value); | |
371 | ||
372 | cpu->fr[regno].v[element] = value; | |
373 | } | |
374 | ||
375 | void | |
376 | aarch64_set_vec_u32 (sim_cpu * cpu, | |
377 | VReg regno, | |
378 | unsigned element, | |
379 | uint32_t value) | |
380 | { | |
381 | if (value != cpu->fr[regno].w[element]) | |
382 | TRACE_REGISTER (cpu, | |
383 | " VR[%2d].<word>[%d] changes from %8x to %8x", | |
384 | regno, element, cpu->fr[regno].w[element], value); | |
385 | ||
386 | cpu->fr[regno].w[element] = value; | |
387 | } | |
388 | ||
389 | void | |
390 | aarch64_set_vec_u16 (sim_cpu * cpu, | |
391 | VReg regno, | |
392 | unsigned element, | |
393 | uint16_t value) | |
394 | { | |
395 | if (value != cpu->fr[regno].h[element]) | |
396 | TRACE_REGISTER (cpu, | |
397 | " VR[%2d].<half>[%d] changes from %4x to %4x", | |
398 | regno, element, cpu->fr[regno].h[element], value); | |
399 | ||
400 | cpu->fr[regno].h[element] = value; | |
401 | } | |
402 | ||
403 | void | |
404 | aarch64_set_vec_u8 (sim_cpu *cpu, VReg regno, unsigned element, uint8_t value) | |
405 | { | |
406 | if (value != cpu->fr[regno].b[element]) | |
407 | TRACE_REGISTER (cpu, | |
408 | " VR[%2d].<byte>[%d] changes from %x to %x", | |
409 | regno, element, cpu->fr[regno].b[element], value); | |
410 | ||
411 | cpu->fr[regno].b[element] = value; | |
412 | } | |
413 | ||
414 | void | |
415 | aarch64_set_FPSR (sim_cpu *cpu, uint32_t value) | |
416 | { | |
417 | if (cpu->FPSR != value) | |
418 | TRACE_REGISTER (cpu, | |
419 | " FPSR changes from %x to %x", cpu->FPSR, value); | |
420 | ||
421 | cpu->FPSR = value & FPSR_ALL_FPSRS; | |
422 | } | |
423 | ||
424 | uint32_t | |
425 | aarch64_get_FPSR (sim_cpu *cpu) | |
426 | { | |
427 | return cpu->FPSR; | |
428 | } | |
429 | ||
430 | void | |
431 | aarch64_set_FPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value) | |
432 | { | |
433 | uint32_t old_FPSR = cpu->FPSR; | |
434 | ||
435 | mask &= FPSR_ALL_FPSRS; | |
436 | cpu->FPSR &= ~mask; | |
437 | cpu->FPSR |= (value & mask); | |
438 | ||
439 | if (cpu->FPSR != old_FPSR) | |
440 | TRACE_REGISTER (cpu, | |
441 | " FPSR changes from %x to %x", old_FPSR, cpu->FPSR); | |
442 | } | |
443 | ||
444 | uint32_t | |
445 | aarch64_get_FPSR_bits (sim_cpu *cpu, uint32_t mask) | |
446 | { | |
447 | mask &= FPSR_ALL_FPSRS; | |
448 | return cpu->FPSR & mask; | |
449 | } | |
450 | ||
451 | int | |
452 | aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag) | |
453 | { | |
454 | return cpu->FPSR & flag; | |
455 | } | |
456 | ||
457 | float | |
458 | aarch64_get_vec_float (sim_cpu *cpu, VReg v, unsigned e) | |
459 | { | |
460 | return cpu->fr[v].S[e]; | |
461 | } | |
462 | ||
463 | double | |
464 | aarch64_get_vec_double (sim_cpu *cpu, VReg v, unsigned e) | |
465 | { | |
466 | return cpu->fr[v].D[e]; | |
467 | } | |
468 | ||
469 | void | |
470 | aarch64_set_vec_float (sim_cpu *cpu, VReg v, unsigned e, float f) | |
471 | { | |
472 | if (f != cpu->fr[v].S[e]) | |
473 | TRACE_REGISTER (cpu, | |
474 | " VR[%2d].<float>[%d] changes from %f to %f", | |
475 | v, e, cpu->fr[v].S[e], f); | |
476 | ||
477 | cpu->fr[v].S[e] = f; | |
478 | } | |
479 | ||
480 | void | |
481 | aarch64_set_vec_double (sim_cpu *cpu, VReg v, unsigned e, double d) | |
482 | { | |
483 | if (d != cpu->fr[v].D[e]) | |
484 | TRACE_REGISTER (cpu, | |
485 | " VR[%2d].<double>[%d] changes from %f to %f", | |
486 | v, e, cpu->fr[v].D[e], d); | |
487 | ||
488 | cpu->fr[v].D[e] = d; | |
489 | } | |
490 | ||
491 | int64_t | |
492 | aarch64_get_vec_s64 (sim_cpu *cpu, VReg regno, unsigned element) | |
493 | { | |
494 | return cpu->fr[regno].V[element]; | |
495 | } | |
496 | ||
497 | int32_t | |
498 | aarch64_get_vec_s32 (sim_cpu *cpu, VReg regno, unsigned element) | |
499 | { | |
500 | return cpu->fr[regno].W[element]; | |
501 | } | |
502 | ||
503 | int16_t | |
504 | aarch64_get_vec_s16 (sim_cpu *cpu, VReg regno, unsigned element) | |
505 | { | |
506 | return cpu->fr[regno].H[element]; | |
507 | } | |
508 | ||
509 | int8_t | |
510 | aarch64_get_vec_s8 (sim_cpu *cpu, VReg regno, unsigned element) | |
511 | { | |
512 | return cpu->fr[regno].B[element]; | |
513 | } | |
514 | ||
515 | void | |
516 | aarch64_set_vec_s64 (sim_cpu *cpu, VReg regno, unsigned element, int64_t value) | |
517 | { | |
518 | if (value != cpu->fr[regno].V[element]) | |
519 | TRACE_REGISTER (cpu, | |
520 | " VR[%2d].<long>[%d] changes from %16" PRIx64 " to %16" PRIx64, | |
521 | regno, element, cpu->fr[regno].V[element], value); | |
522 | ||
523 | cpu->fr[regno].V[element] = value; | |
524 | } | |
525 | ||
526 | void | |
527 | aarch64_set_vec_s32 (sim_cpu *cpu, VReg regno, unsigned element, int32_t value) | |
528 | { | |
529 | if (value != cpu->fr[regno].W[element]) | |
530 | TRACE_REGISTER (cpu, | |
531 | " VR[%2d].<word>[%d] changes from %8x to %8x", | |
532 | regno, element, cpu->fr[regno].W[element], value); | |
533 | ||
534 | cpu->fr[regno].W[element] = value; | |
535 | } | |
536 | ||
537 | void | |
538 | aarch64_set_vec_s16 (sim_cpu *cpu, VReg regno, unsigned element, int16_t value) | |
539 | { | |
540 | if (value != cpu->fr[regno].H[element]) | |
541 | TRACE_REGISTER (cpu, | |
542 | " VR[%2d].<half>[%d] changes from %4x to %4x", | |
543 | regno, element, cpu->fr[regno].H[element], value); | |
544 | ||
545 | cpu->fr[regno].H[element] = value; | |
546 | } | |
547 | ||
548 | void | |
549 | aarch64_set_vec_s8 (sim_cpu *cpu, VReg regno, unsigned element, int8_t value) | |
550 | { | |
551 | if (value != cpu->fr[regno].B[element]) | |
552 | TRACE_REGISTER (cpu, | |
553 | " VR[%2d].<byte>[%d] changes from %x to %x", | |
554 | regno, element, cpu->fr[regno].B[element], value); | |
555 | ||
556 | cpu->fr[regno].B[element] = value; | |
557 | } |