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2e8cf49e NC |
1 | /* cpustate.h -- Prototypes for AArch64 simulator functions. |
2 | ||
1d506c26 | 3 | Copyright (C) 2015-2024 Free Software Foundation, Inc. |
2e8cf49e NC |
4 | |
5 | Contributed by Red Hat. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
6df01ab8 MF |
22 | /* This must come before any other includes. */ |
23 | #include "defs.h" | |
24 | ||
2e8cf49e | 25 | #include <stdio.h> |
c0386d4d | 26 | #include <math.h> |
2e8cf49e NC |
27 | |
28 | #include "sim-main.h" | |
1fef66b0 | 29 | #include "sim-signal.h" |
2e8cf49e NC |
30 | #include "cpustate.h" |
31 | #include "simulator.h" | |
cd5b6074 | 32 | #include "libiberty.h" |
2e8cf49e | 33 | |
e24a921d MF |
34 | #include "aarch64-sim.h" |
35 | ||
2e8cf49e NC |
36 | /* Some operands are allowed to access the stack pointer (reg 31). |
37 | For others a read from r31 always returns 0, and a write to r31 is ignored. */ | |
38 | #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg)) | |
39 | ||
40 | void | |
41 | aarch64_set_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint64_t val) | |
42 | { | |
6a08ae19 MF |
43 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
44 | ||
2e8cf49e NC |
45 | if (reg == R31 && ! r31_is_sp) |
46 | { | |
e101a78b | 47 | TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!"); |
2e8cf49e NC |
48 | return; |
49 | } | |
50 | ||
6a08ae19 | 51 | if (val != aarch64_cpu->gr[reg].u64) |
2e8cf49e | 52 | TRACE_REGISTER (cpu, |
e101a78b | 53 | "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64, |
6a08ae19 | 54 | reg, aarch64_cpu->gr[reg].u64, val); |
2e8cf49e | 55 | |
6a08ae19 | 56 | aarch64_cpu->gr[reg].u64 = val; |
2e8cf49e NC |
57 | } |
58 | ||
59 | void | |
60 | aarch64_set_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp, int64_t val) | |
61 | { | |
6a08ae19 MF |
62 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
63 | ||
2e8cf49e NC |
64 | if (reg == R31 && ! r31_is_sp) |
65 | { | |
e101a78b | 66 | TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!"); |
2e8cf49e NC |
67 | return; |
68 | } | |
69 | ||
6a08ae19 | 70 | if (val != aarch64_cpu->gr[reg].s64) |
2e8cf49e | 71 | TRACE_REGISTER (cpu, |
e101a78b | 72 | "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64, |
6a08ae19 | 73 | reg, aarch64_cpu->gr[reg].s64, val); |
2e8cf49e | 74 | |
6a08ae19 | 75 | aarch64_cpu->gr[reg].s64 = val; |
2e8cf49e NC |
76 | } |
77 | ||
78 | uint64_t | |
79 | aarch64_get_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
80 | { | |
6a08ae19 | 81 | return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u64; |
2e8cf49e NC |
82 | } |
83 | ||
84 | int64_t | |
85 | aarch64_get_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
86 | { | |
6a08ae19 | 87 | return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s64; |
2e8cf49e NC |
88 | } |
89 | ||
90 | uint32_t | |
91 | aarch64_get_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
92 | { | |
6a08ae19 | 93 | return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u32; |
2e8cf49e NC |
94 | } |
95 | ||
96 | int32_t | |
97 | aarch64_get_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
98 | { | |
6a08ae19 | 99 | return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s32; |
2e8cf49e NC |
100 | } |
101 | ||
7517e550 NC |
102 | void |
103 | aarch64_set_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp, int32_t val) | |
104 | { | |
6a08ae19 MF |
105 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
106 | ||
7517e550 NC |
107 | if (reg == R31 && ! r31_is_sp) |
108 | { | |
109 | TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!"); | |
110 | return; | |
111 | } | |
112 | ||
6a08ae19 | 113 | if (val != aarch64_cpu->gr[reg].s32) |
7517e550 | 114 | TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x", |
6a08ae19 | 115 | reg, aarch64_cpu->gr[reg].s32, val); |
7517e550 NC |
116 | |
117 | /* The ARM ARM states that (C1.2.4): | |
118 | When the data size is 32 bits, the lower 32 bits of the | |
119 | register are used and the upper 32 bits are ignored on | |
120 | a read and cleared to zero on a write. | |
121 | We simulate this by first clearing the whole 64-bits and | |
122 | then writing to the 32-bit value in the GRegister union. */ | |
6a08ae19 MF |
123 | aarch64_cpu->gr[reg].s64 = 0; |
124 | aarch64_cpu->gr[reg].s32 = val; | |
7517e550 NC |
125 | } |
126 | ||
127 | void | |
128 | aarch64_set_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint32_t val) | |
129 | { | |
6a08ae19 MF |
130 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
131 | ||
7517e550 NC |
132 | if (reg == R31 && ! r31_is_sp) |
133 | { | |
134 | TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!"); | |
135 | return; | |
136 | } | |
137 | ||
6a08ae19 | 138 | if (val != aarch64_cpu->gr[reg].u32) |
7517e550 | 139 | TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x", |
6a08ae19 | 140 | reg, aarch64_cpu->gr[reg].u32, val); |
7517e550 | 141 | |
6a08ae19 MF |
142 | aarch64_cpu->gr[reg].u64 = 0; |
143 | aarch64_cpu->gr[reg].u32 = val; | |
7517e550 NC |
144 | } |
145 | ||
2e8cf49e NC |
146 | uint32_t |
147 | aarch64_get_reg_u16 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
148 | { | |
6a08ae19 | 149 | return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u16; |
2e8cf49e NC |
150 | } |
151 | ||
152 | int32_t | |
153 | aarch64_get_reg_s16 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
154 | { | |
6a08ae19 | 155 | return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s16; |
2e8cf49e NC |
156 | } |
157 | ||
158 | uint32_t | |
159 | aarch64_get_reg_u8 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
160 | { | |
6a08ae19 | 161 | return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].u8; |
2e8cf49e NC |
162 | } |
163 | ||
164 | int32_t | |
165 | aarch64_get_reg_s8 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
166 | { | |
6a08ae19 | 167 | return AARCH64_SIM_CPU (cpu)->gr[reg_num(reg)].s8; |
2e8cf49e NC |
168 | } |
169 | ||
170 | uint64_t | |
171 | aarch64_get_PC (sim_cpu *cpu) | |
172 | { | |
6a08ae19 | 173 | return AARCH64_SIM_CPU (cpu)->pc; |
2e8cf49e NC |
174 | } |
175 | ||
176 | uint64_t | |
177 | aarch64_get_next_PC (sim_cpu *cpu) | |
178 | { | |
6a08ae19 | 179 | return AARCH64_SIM_CPU (cpu)->nextpc; |
2e8cf49e NC |
180 | } |
181 | ||
182 | void | |
183 | aarch64_set_next_PC (sim_cpu *cpu, uint64_t next) | |
184 | { | |
6a08ae19 MF |
185 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
186 | ||
187 | if (next != aarch64_cpu->nextpc + 4) | |
2e8cf49e | 188 | TRACE_REGISTER (cpu, |
e101a78b | 189 | "NextPC changes from %16" PRIx64 " to %16" PRIx64, |
6a08ae19 | 190 | aarch64_cpu->nextpc, next); |
2e8cf49e | 191 | |
6a08ae19 | 192 | aarch64_cpu->nextpc = next; |
2e8cf49e NC |
193 | } |
194 | ||
195 | void | |
196 | aarch64_set_next_PC_by_offset (sim_cpu *cpu, int64_t offset) | |
197 | { | |
6a08ae19 MF |
198 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
199 | ||
200 | if (aarch64_cpu->pc + offset != aarch64_cpu->nextpc + 4) | |
2e8cf49e | 201 | TRACE_REGISTER (cpu, |
e101a78b | 202 | "NextPC changes from %16" PRIx64 " to %16" PRIx64, |
6a08ae19 | 203 | aarch64_cpu->nextpc, aarch64_cpu->pc + offset); |
2e8cf49e | 204 | |
6a08ae19 | 205 | aarch64_cpu->nextpc = aarch64_cpu->pc + offset; |
2e8cf49e NC |
206 | } |
207 | ||
208 | /* Install nextpc as current pc. */ | |
209 | void | |
210 | aarch64_update_PC (sim_cpu *cpu) | |
211 | { | |
6a08ae19 MF |
212 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
213 | ||
214 | aarch64_cpu->pc = aarch64_cpu->nextpc; | |
2e8cf49e NC |
215 | /* Rezero the register we hand out when asked for ZR just in case it |
216 | was used as the destination for a write by the previous | |
217 | instruction. */ | |
6a08ae19 | 218 | aarch64_cpu->gr[32].u64 = 0UL; |
2e8cf49e NC |
219 | } |
220 | ||
221 | /* This instruction can be used to save the next PC to LR | |
222 | just before installing a branch PC. */ | |
223 | void | |
224 | aarch64_save_LR (sim_cpu *cpu) | |
225 | { | |
6a08ae19 MF |
226 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
227 | ||
228 | if (aarch64_cpu->gr[LR].u64 != aarch64_cpu->nextpc) | |
2e8cf49e | 229 | TRACE_REGISTER (cpu, |
e101a78b | 230 | "LR changes from %16" PRIx64 " to %16" PRIx64, |
6a08ae19 | 231 | aarch64_cpu->gr[LR].u64, aarch64_cpu->nextpc); |
2e8cf49e | 232 | |
6a08ae19 | 233 | aarch64_cpu->gr[LR].u64 = aarch64_cpu->nextpc; |
2e8cf49e NC |
234 | } |
235 | ||
236 | static const char * | |
237 | decode_cpsr (FlagMask flags) | |
238 | { | |
239 | switch (flags & CPSR_ALL_FLAGS) | |
240 | { | |
241 | default: | |
242 | case 0: return "----"; | |
243 | case 1: return "---V"; | |
244 | case 2: return "--C-"; | |
245 | case 3: return "--CV"; | |
246 | case 4: return "-Z--"; | |
247 | case 5: return "-Z-V"; | |
248 | case 6: return "-ZC-"; | |
249 | case 7: return "-ZCV"; | |
250 | case 8: return "N---"; | |
251 | case 9: return "N--V"; | |
252 | case 10: return "N-C-"; | |
253 | case 11: return "N-CV"; | |
254 | case 12: return "NZ--"; | |
255 | case 13: return "NZ-V"; | |
256 | case 14: return "NZC-"; | |
257 | case 15: return "NZCV"; | |
258 | } | |
259 | } | |
260 | ||
261 | /* Retrieve the CPSR register as an int. */ | |
262 | uint32_t | |
263 | aarch64_get_CPSR (sim_cpu *cpu) | |
264 | { | |
6a08ae19 | 265 | return AARCH64_SIM_CPU (cpu)->CPSR; |
2e8cf49e NC |
266 | } |
267 | ||
268 | /* Set the CPSR register as an int. */ | |
269 | void | |
270 | aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags) | |
271 | { | |
6a08ae19 MF |
272 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
273 | ||
2e8cf49e NC |
274 | if (TRACE_REGISTER_P (cpu)) |
275 | { | |
6a08ae19 | 276 | if (aarch64_cpu->CPSR != new_flags) |
2e8cf49e | 277 | TRACE_REGISTER (cpu, |
e101a78b | 278 | "CPSR changes from %s to %s", |
6a08ae19 | 279 | decode_cpsr (aarch64_cpu->CPSR), decode_cpsr (new_flags)); |
2e8cf49e NC |
280 | else |
281 | TRACE_REGISTER (cpu, | |
6a08ae19 | 282 | "CPSR stays at %s", decode_cpsr (aarch64_cpu->CPSR)); |
2e8cf49e NC |
283 | } |
284 | ||
6a08ae19 | 285 | aarch64_cpu->CPSR = new_flags & CPSR_ALL_FLAGS; |
2e8cf49e NC |
286 | } |
287 | ||
288 | /* Read a specific subset of the CPSR as a bit pattern. */ | |
289 | uint32_t | |
290 | aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask) | |
291 | { | |
6a08ae19 | 292 | return AARCH64_SIM_CPU (cpu)->CPSR & mask; |
2e8cf49e NC |
293 | } |
294 | ||
295 | /* Assign a specific subset of the CPSR as a bit pattern. */ | |
296 | void | |
297 | aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value) | |
298 | { | |
6a08ae19 MF |
299 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
300 | uint32_t old_flags = aarch64_cpu->CPSR; | |
2e8cf49e NC |
301 | |
302 | mask &= CPSR_ALL_FLAGS; | |
6a08ae19 MF |
303 | aarch64_cpu->CPSR &= ~ mask; |
304 | aarch64_cpu->CPSR |= (value & mask); | |
2e8cf49e | 305 | |
6a08ae19 | 306 | if (old_flags != aarch64_cpu->CPSR) |
2e8cf49e | 307 | TRACE_REGISTER (cpu, |
e101a78b | 308 | "CPSR changes from %s to %s", |
6a08ae19 | 309 | decode_cpsr (old_flags), decode_cpsr (aarch64_cpu->CPSR)); |
2e8cf49e NC |
310 | } |
311 | ||
312 | /* Test the value of a single CPSR returned as non-zero or zero. */ | |
313 | uint32_t | |
314 | aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
315 | { | |
6a08ae19 | 316 | return AARCH64_SIM_CPU (cpu)->CPSR & bit; |
2e8cf49e NC |
317 | } |
318 | ||
319 | /* Set a single flag in the CPSR. */ | |
320 | void | |
321 | aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
322 | { | |
6a08ae19 MF |
323 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
324 | uint32_t old_flags = aarch64_cpu->CPSR; | |
2e8cf49e | 325 | |
6a08ae19 | 326 | aarch64_cpu->CPSR |= (bit & CPSR_ALL_FLAGS); |
2e8cf49e | 327 | |
6a08ae19 | 328 | if (old_flags != aarch64_cpu->CPSR) |
2e8cf49e | 329 | TRACE_REGISTER (cpu, |
e101a78b | 330 | "CPSR changes from %s to %s", |
6a08ae19 | 331 | decode_cpsr (old_flags), decode_cpsr (aarch64_cpu->CPSR)); |
2e8cf49e NC |
332 | } |
333 | ||
334 | /* Clear a single flag in the CPSR. */ | |
335 | void | |
336 | aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
337 | { | |
6a08ae19 MF |
338 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
339 | uint32_t old_flags = aarch64_cpu->CPSR; | |
2e8cf49e | 340 | |
6a08ae19 | 341 | aarch64_cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS); |
2e8cf49e | 342 | |
6a08ae19 | 343 | if (old_flags != aarch64_cpu->CPSR) |
2e8cf49e | 344 | TRACE_REGISTER (cpu, |
e101a78b | 345 | "CPSR changes from %s to %s", |
6a08ae19 | 346 | decode_cpsr (old_flags), decode_cpsr (aarch64_cpu->CPSR)); |
2e8cf49e NC |
347 | } |
348 | ||
5ab6d79e NC |
349 | float |
350 | aarch64_get_FP_half (sim_cpu *cpu, VReg reg) | |
351 | { | |
6a08ae19 | 352 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
5ab6d79e NC |
353 | union |
354 | { | |
355 | uint16_t h[2]; | |
356 | float f; | |
357 | } u; | |
358 | ||
7517e550 | 359 | u.h[0] = 0; |
6a08ae19 | 360 | u.h[1] = aarch64_cpu->fr[reg].h[0]; |
5ab6d79e NC |
361 | return u.f; |
362 | } | |
363 | ||
364 | ||
2e8cf49e NC |
365 | float |
366 | aarch64_get_FP_float (sim_cpu *cpu, VReg reg) | |
367 | { | |
6a08ae19 | 368 | return AARCH64_SIM_CPU (cpu)->fr[reg].s; |
2e8cf49e NC |
369 | } |
370 | ||
371 | double | |
372 | aarch64_get_FP_double (sim_cpu *cpu, VReg reg) | |
373 | { | |
6a08ae19 | 374 | return AARCH64_SIM_CPU (cpu)->fr[reg].d; |
2e8cf49e NC |
375 | } |
376 | ||
377 | void | |
378 | aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a) | |
379 | { | |
6a08ae19 MF |
380 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
381 | ||
382 | a->v[0] = aarch64_cpu->fr[reg].v[0]; | |
383 | a->v[1] = aarch64_cpu->fr[reg].v[1]; | |
2e8cf49e NC |
384 | } |
385 | ||
5ab6d79e NC |
386 | void |
387 | aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val) | |
388 | { | |
6a08ae19 | 389 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
5ab6d79e NC |
390 | union |
391 | { | |
392 | uint16_t h[2]; | |
393 | float f; | |
394 | } u; | |
395 | ||
396 | u.f = val; | |
6a08ae19 MF |
397 | aarch64_cpu->fr[reg].h[0] = u.h[1]; |
398 | aarch64_cpu->fr[reg].h[1] = 0; | |
5ab6d79e NC |
399 | } |
400 | ||
401 | ||
2e8cf49e NC |
402 | void |
403 | aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val) | |
404 | { | |
6a08ae19 MF |
405 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
406 | ||
407 | if (val != aarch64_cpu->fr[reg].s | |
c0386d4d | 408 | /* Handle +/- zero. */ |
6a08ae19 | 409 | || signbit (val) != signbit (aarch64_cpu->fr[reg].s)) |
e101a78b NC |
410 | { |
411 | FRegister v; | |
412 | ||
413 | v.s = val; | |
414 | TRACE_REGISTER (cpu, | |
f1ca3215 | 415 | "FR[%d].s changes from %f to %f [hex: %0" PRIx64 "]", |
6a08ae19 | 416 | reg, aarch64_cpu->fr[reg].s, val, v.v[0]); |
e101a78b | 417 | } |
2e8cf49e | 418 | |
6a08ae19 | 419 | aarch64_cpu->fr[reg].s = val; |
2e8cf49e NC |
420 | } |
421 | ||
422 | void | |
423 | aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val) | |
424 | { | |
6a08ae19 MF |
425 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
426 | ||
427 | if (val != aarch64_cpu->fr[reg].d | |
c0386d4d | 428 | /* Handle +/- zero. */ |
6a08ae19 | 429 | || signbit (val) != signbit (aarch64_cpu->fr[reg].d)) |
e101a78b NC |
430 | { |
431 | FRegister v; | |
2e8cf49e | 432 | |
e101a78b NC |
433 | v.d = val; |
434 | TRACE_REGISTER (cpu, | |
f1ca3215 | 435 | "FR[%d].d changes from %f to %f [hex: %0" PRIx64 "]", |
6a08ae19 | 436 | reg, aarch64_cpu->fr[reg].d, val, v.v[0]); |
e101a78b | 437 | } |
6a08ae19 | 438 | aarch64_cpu->fr[reg].d = val; |
2e8cf49e NC |
439 | } |
440 | ||
441 | void | |
442 | aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a) | |
443 | { | |
6a08ae19 MF |
444 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
445 | ||
446 | if (aarch64_cpu->fr[reg].v[0] != a.v[0] | |
447 | || aarch64_cpu->fr[reg].v[1] != a.v[1]) | |
2e8cf49e | 448 | TRACE_REGISTER (cpu, |
f1ca3215 MF |
449 | "FR[%d].q changes from [%0" PRIx64 " %0" PRIx64 "] to [%0" |
450 | PRIx64 " %0" PRIx64 "] ", | |
2e8cf49e | 451 | reg, |
6a08ae19 | 452 | aarch64_cpu->fr[reg].v[0], aarch64_cpu->fr[reg].v[1], |
2e8cf49e NC |
453 | a.v[0], a.v[1]); |
454 | ||
6a08ae19 MF |
455 | aarch64_cpu->fr[reg].v[0] = a.v[0]; |
456 | aarch64_cpu->fr[reg].v[1] = a.v[1]; | |
2e8cf49e NC |
457 | } |
458 | ||
6a08ae19 MF |
459 | #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \ |
460 | do \ | |
461 | { \ | |
462 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); \ | |
463 | \ | |
464 | if (ELEMENT >= ARRAY_SIZE (aarch64_cpu->fr[0].FIELD)) \ | |
e101a78b | 465 | { \ |
6a08ae19 | 466 | TRACE_REGISTER (cpu, \ |
e101a78b NC |
467 | "Internal SIM error: invalid element number: %d ",\ |
468 | ELEMENT); \ | |
469 | sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \ | |
470 | sim_stopped, SIM_SIGBUS); \ | |
471 | } \ | |
6a08ae19 | 472 | return aarch64_cpu->fr[REG].FIELD [ELEMENT]; \ |
e101a78b NC |
473 | } \ |
474 | while (0) | |
475 | ||
2e8cf49e NC |
476 | uint64_t |
477 | aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element) | |
478 | { | |
e101a78b | 479 | GET_VEC_ELEMENT (reg, element, v); |
2e8cf49e NC |
480 | } |
481 | ||
482 | uint32_t | |
e101a78b | 483 | aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element) |
2e8cf49e | 484 | { |
e101a78b | 485 | GET_VEC_ELEMENT (reg, element, w); |
2e8cf49e NC |
486 | } |
487 | ||
488 | uint16_t | |
e101a78b | 489 | aarch64_get_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element) |
2e8cf49e | 490 | { |
e101a78b | 491 | GET_VEC_ELEMENT (reg, element, h); |
2e8cf49e NC |
492 | } |
493 | ||
494 | uint8_t | |
e101a78b | 495 | aarch64_get_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element) |
2e8cf49e | 496 | { |
e101a78b | 497 | GET_VEC_ELEMENT (reg, element, b); |
2e8cf49e NC |
498 | } |
499 | ||
e101a78b NC |
500 | int64_t |
501 | aarch64_get_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 502 | { |
e101a78b | 503 | GET_VEC_ELEMENT (reg, element, V); |
2e8cf49e NC |
504 | } |
505 | ||
e101a78b NC |
506 | int32_t |
507 | aarch64_get_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 508 | { |
e101a78b | 509 | GET_VEC_ELEMENT (reg, element, W); |
2e8cf49e NC |
510 | } |
511 | ||
e101a78b NC |
512 | int16_t |
513 | aarch64_get_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 514 | { |
e101a78b | 515 | GET_VEC_ELEMENT (reg, element, H); |
2e8cf49e NC |
516 | } |
517 | ||
e101a78b NC |
518 | int8_t |
519 | aarch64_get_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 520 | { |
e101a78b | 521 | GET_VEC_ELEMENT (reg, element, B); |
2e8cf49e NC |
522 | } |
523 | ||
e101a78b NC |
524 | float |
525 | aarch64_get_vec_float (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 526 | { |
e101a78b | 527 | GET_VEC_ELEMENT (reg, element, S); |
2e8cf49e NC |
528 | } |
529 | ||
e101a78b NC |
530 | double |
531 | aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element) | |
532 | { | |
533 | GET_VEC_ELEMENT (reg, element, D); | |
534 | } | |
535 | ||
536 | ||
7517e550 NC |
537 | #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \ |
538 | do \ | |
539 | { \ | |
6a08ae19 MF |
540 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); \ |
541 | \ | |
542 | if (ELEMENT >= ARRAY_SIZE (aarch64_cpu->fr[0].FIELD)) \ | |
e101a78b | 543 | { \ |
7517e550 | 544 | TRACE_REGISTER (cpu, \ |
e101a78b NC |
545 | "Internal SIM error: invalid element number: %d ",\ |
546 | ELEMENT); \ | |
547 | sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \ | |
548 | sim_stopped, SIM_SIGBUS); \ | |
549 | } \ | |
6a08ae19 | 550 | if (VAL != aarch64_cpu->fr[REG].FIELD [ELEMENT]) \ |
e101a78b NC |
551 | TRACE_REGISTER (cpu, \ |
552 | "VR[%2d]." #FIELD " [%d] changes from " PRINTER \ | |
553 | " to " PRINTER , REG, \ | |
6a08ae19 | 554 | ELEMENT, aarch64_cpu->fr[REG].FIELD [ELEMENT], VAL); \ |
7517e550 | 555 | \ |
6a08ae19 | 556 | aarch64_cpu->fr[REG].FIELD [ELEMENT] = VAL; \ |
7517e550 | 557 | } \ |
e101a78b | 558 | while (0) |
2e8cf49e NC |
559 | |
560 | void | |
ef0d8ffc | 561 | aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val) |
2e8cf49e | 562 | { |
f1ca3215 | 563 | SET_VEC_ELEMENT (reg, element, val, v, "%16" PRIx64); |
2e8cf49e NC |
564 | } |
565 | ||
e101a78b | 566 | void |
ef0d8ffc | 567 | aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val) |
2e8cf49e | 568 | { |
e101a78b | 569 | SET_VEC_ELEMENT (reg, element, val, w, "%8x"); |
2e8cf49e NC |
570 | } |
571 | ||
e101a78b | 572 | void |
ef0d8ffc | 573 | aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val) |
2e8cf49e | 574 | { |
e101a78b | 575 | SET_VEC_ELEMENT (reg, element, val, h, "%4x"); |
2e8cf49e NC |
576 | } |
577 | ||
e101a78b | 578 | void |
ef0d8ffc | 579 | aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val) |
2e8cf49e | 580 | { |
e101a78b | 581 | SET_VEC_ELEMENT (reg, element, val, b, "%x"); |
2e8cf49e NC |
582 | } |
583 | ||
584 | void | |
e101a78b | 585 | aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val) |
2e8cf49e | 586 | { |
f1ca3215 | 587 | SET_VEC_ELEMENT (reg, element, val, V, "%16" PRIx64); |
2e8cf49e NC |
588 | } |
589 | ||
590 | void | |
e101a78b | 591 | aarch64_set_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element, int32_t val) |
2e8cf49e | 592 | { |
e101a78b | 593 | SET_VEC_ELEMENT (reg, element, val, W, "%8x"); |
2e8cf49e NC |
594 | } |
595 | ||
e101a78b NC |
596 | void |
597 | aarch64_set_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element, int16_t val) | |
2e8cf49e | 598 | { |
e101a78b | 599 | SET_VEC_ELEMENT (reg, element, val, H, "%4x"); |
2e8cf49e NC |
600 | } |
601 | ||
e101a78b NC |
602 | void |
603 | aarch64_set_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element, int8_t val) | |
2e8cf49e | 604 | { |
e101a78b | 605 | SET_VEC_ELEMENT (reg, element, val, B, "%x"); |
2e8cf49e NC |
606 | } |
607 | ||
e101a78b NC |
608 | void |
609 | aarch64_set_vec_float (sim_cpu *cpu, VReg reg, unsigned element, float val) | |
2e8cf49e | 610 | { |
e101a78b | 611 | SET_VEC_ELEMENT (reg, element, val, S, "%f"); |
2e8cf49e NC |
612 | } |
613 | ||
e101a78b NC |
614 | void |
615 | aarch64_set_vec_double (sim_cpu *cpu, VReg reg, unsigned element, double val) | |
2e8cf49e | 616 | { |
e101a78b | 617 | SET_VEC_ELEMENT (reg, element, val, D, "%f"); |
2e8cf49e NC |
618 | } |
619 | ||
620 | void | |
e101a78b | 621 | aarch64_set_FPSR (sim_cpu *cpu, uint32_t value) |
2e8cf49e | 622 | { |
6a08ae19 MF |
623 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
624 | ||
625 | if (aarch64_cpu->FPSR != value) | |
2e8cf49e | 626 | TRACE_REGISTER (cpu, |
6a08ae19 | 627 | "FPSR changes from %x to %x", aarch64_cpu->FPSR, value); |
2e8cf49e | 628 | |
6a08ae19 | 629 | aarch64_cpu->FPSR = value & FPSR_ALL_FPSRS; |
2e8cf49e NC |
630 | } |
631 | ||
e101a78b NC |
632 | uint32_t |
633 | aarch64_get_FPSR (sim_cpu *cpu) | |
2e8cf49e | 634 | { |
6a08ae19 | 635 | return AARCH64_SIM_CPU (cpu)->FPSR; |
2e8cf49e NC |
636 | } |
637 | ||
638 | void | |
e101a78b | 639 | aarch64_set_FPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value) |
2e8cf49e | 640 | { |
6a08ae19 MF |
641 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
642 | uint32_t old_FPSR = aarch64_cpu->FPSR; | |
e101a78b NC |
643 | |
644 | mask &= FPSR_ALL_FPSRS; | |
6a08ae19 MF |
645 | aarch64_cpu->FPSR &= ~mask; |
646 | aarch64_cpu->FPSR |= (value & mask); | |
2e8cf49e | 647 | |
6a08ae19 | 648 | if (aarch64_cpu->FPSR != old_FPSR) |
e101a78b | 649 | TRACE_REGISTER (cpu, |
6a08ae19 | 650 | "FPSR changes from %x to %x", old_FPSR, aarch64_cpu->FPSR); |
2e8cf49e NC |
651 | } |
652 | ||
e101a78b NC |
653 | uint32_t |
654 | aarch64_get_FPSR_bits (sim_cpu *cpu, uint32_t mask) | |
2e8cf49e | 655 | { |
e101a78b | 656 | mask &= FPSR_ALL_FPSRS; |
6a08ae19 | 657 | return AARCH64_SIM_CPU (cpu)->FPSR & mask; |
e101a78b | 658 | } |
2e8cf49e | 659 | |
e101a78b NC |
660 | int |
661 | aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag) | |
662 | { | |
6a08ae19 | 663 | return AARCH64_SIM_CPU (cpu)->FPSR & flag; |
2e8cf49e | 664 | } |
5ab6d79e NC |
665 | |
666 | uint64_t | |
ef0d8ffc | 667 | aarch64_get_thread_id (sim_cpu *cpu) |
5ab6d79e | 668 | { |
6a08ae19 | 669 | return AARCH64_SIM_CPU (cpu)->tpidr; |
5ab6d79e NC |
670 | } |
671 | ||
672 | uint32_t | |
ef0d8ffc | 673 | aarch64_get_FPCR (sim_cpu *cpu) |
5ab6d79e | 674 | { |
6a08ae19 | 675 | return AARCH64_SIM_CPU (cpu)->FPCR; |
5ab6d79e NC |
676 | } |
677 | ||
678 | void | |
ef0d8ffc | 679 | aarch64_set_FPCR (sim_cpu *cpu, uint32_t val) |
5ab6d79e | 680 | { |
6a08ae19 MF |
681 | struct aarch64_sim_cpu *aarch64_cpu = AARCH64_SIM_CPU (cpu); |
682 | ||
683 | if (aarch64_cpu->FPCR != val) | |
5ab6d79e | 684 | TRACE_REGISTER (cpu, |
6a08ae19 MF |
685 | "FPCR changes from %x to %x", aarch64_cpu->FPCR, val); |
686 | aarch64_cpu->FPCR = val; | |
5ab6d79e | 687 | } |