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df1756f4 1/* Simulator for Atmel's AVR core.
3666a048 2 Copyright (C) 2009-2021 Free Software Foundation, Inc.
df1756f4
TG		 3 Written by Tristan Gingold, AdaCore.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
6df01ab8
MF		 20/* This must come before any other includes. */
21#include "defs.h"
df1756f4 22
df1756f4 23#include <string.h>
68ed2854 24
df1756f4 25#include "bfd.h"
df1756f4 26#include "libiberty.h"
df68e12b 27#include "sim/sim.h"
9943d318
MF		 28
29#include "sim-main.h"
30#include "sim-base.h"
31#include "sim-options.h"
1fef66b0 32#include "sim-signal.h"
df1756f4
TG		 33
34/* As AVR is a 8/16 bits processor, define handy types. */
35typedef unsigned short int word;
36typedef signed short int sword;
37typedef unsigned char byte;
38typedef signed char sbyte;
39
df1756f4
TG		 40/* Max size of I space (which is always flash on avr). */
41#define MAX_AVR_FLASH (128 * 1024)
42#define PC_MASK (MAX_AVR_FLASH - 1)
43
44/* Mac size of D space. */
45#define MAX_AVR_SRAM (64 * 1024)
46#define SRAM_MASK (MAX_AVR_SRAM - 1)
47
48/* D space offset in ELF file. */
49#define SRAM_VADDR 0x800000
50
51/* Simulator specific ports. */
52#define STDIO_PORT 0x52
53#define EXIT_PORT 0x4F
54#define ABORT_PORT 0x49
55
56/* GDB defined register numbers. */
57#define AVR_SREG_REGNUM 32
58#define AVR_SP_REGNUM 33
59#define AVR_PC_REGNUM 34
60
61/* Memory mapped registers. */
62#define SREG 0x5F
63#define REG_SP 0x5D
64#define EIND 0x5C
65#define RAMPZ 0x5B
66
67#define REGX 0x1a
68#define REGY 0x1c
69#define REGZ 0x1e
70#define REGZ_LO 0x1e
71#define REGZ_HI 0x1f
72
73/* Sreg (status) bits. */
74#define SREG_I 0x80
75#define SREG_T 0x40
76#define SREG_H 0x20
77#define SREG_S 0x10
78#define SREG_V 0x08
79#define SREG_N 0x04
80#define SREG_Z 0x02
81#define SREG_C 0x01
82
83/* In order to speed up emulation we use a simple approach:
84 a code is associated with each instruction. The pre-decoding occurs
85 usually once when the instruction is first seen.
86 This works well because I&D spaces are separated.
87
88 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
89*/
90enum avr_opcode
91 {
92 /* Opcode not yet decoded. */
93 OP_unknown,
94 OP_bad,
95
96 OP_nop,
97
98 OP_rjmp,
99 OP_rcall,
100 OP_ret,
101 OP_reti,
102
103 OP_break,
104
105 OP_brbs,
106 OP_brbc,
107
108 OP_bset,
109 OP_bclr,
110
111 OP_bld,
112 OP_bst,
113
114 OP_sbrc,
115 OP_sbrs,
116
117 OP_eor,
118 OP_and,
119 OP_andi,
120 OP_or,
121 OP_ori,
122 OP_com,
123 OP_swap,
124 OP_neg,
125
126 OP_out,
127 OP_in,
128 OP_cbi,
129 OP_sbi,
130
131 OP_sbic,
132 OP_sbis,
133
134 OP_ldi,
135 OP_cpse,
136 OP_cp,
137 OP_cpi,
138 OP_cpc,
139 OP_sub,
140 OP_sbc,
141 OP_sbiw,
142 OP_adiw,
143 OP_add,
144 OP_adc,
145 OP_subi,
146 OP_sbci,
147 OP_inc,
148 OP_dec,
149 OP_lsr,
150 OP_ror,
151 OP_asr,
152
153 OP_mul,
154 OP_muls,
155 OP_mulsu,
156 OP_fmul,
157 OP_fmuls,
158 OP_fmulsu,
159
160 OP_mov,
161 OP_movw,
162
163 OP_push,
164 OP_pop,
165
166 OP_st_X,
167 OP_st_dec_X,
168 OP_st_X_inc,
169 OP_st_Y_inc,
170 OP_st_dec_Y,
171 OP_st_Z_inc,
172 OP_st_dec_Z,
173 OP_std_Y,
174 OP_std_Z,
175 OP_ldd_Y,
176 OP_ldd_Z,
177 OP_ld_Z_inc,
178 OP_ld_dec_Z,
179 OP_ld_Y_inc,
180 OP_ld_dec_Y,
181 OP_ld_X,
182 OP_ld_X_inc,
183 OP_ld_dec_X,
184
185 OP_lpm,
186 OP_lpm_Z,
187 OP_lpm_inc_Z,
188 OP_elpm,
189 OP_elpm_Z,
190 OP_elpm_inc_Z,
191
192 OP_ijmp,
193 OP_icall,
194
195 OP_eijmp,
196 OP_eicall,
197
198 /* 2 words opcodes. */
199#define OP_2words OP_jmp
200 OP_jmp,
201 OP_call,
202 OP_sts,
203 OP_lds
204 };
205
206struct avr_insn_cell
207{
208 /* The insn (16 bits). */
209 word op;
210
211 /* Pre-decoding code. */
212 enum avr_opcode code : 8;
213 /* One byte of additional information. */
214 byte r;
215};
216
217/* I&D memories. */
9943d318 218/* TODO: Should be moved to SIM_CPU. */
df1756f4
TG		 219static struct avr_insn_cell flash[MAX_AVR_FLASH];
220static byte sram[MAX_AVR_SRAM];
221
df1756f4
TG		 222/* Sign extend a value. */
223static int sign_ext (word val, int nb_bits)
224{
225 if (val & (1 << (nb_bits - 1)))
1d19cae7 226 return val | -(1 << nb_bits);
df1756f4
TG		 227 return val;
228}
229
230/* Insn field extractors. */
231
232/* Extract xxxx_xxxRx_xxxx_RRRR. */
233static inline byte get_r (word op)
234{
235 return (op & 0xf) | ((op >> 5) & 0x10);
236}
237
238/* Extract xxxx_xxxxx_xxxx_RRRR. */
239static inline byte get_r16 (word op)
240{
241 return 16 + (op & 0xf);
242}
243
244/* Extract xxxx_xxxxx_xxxx_xRRR. */
245static inline byte get_r16_23 (word op)
246{
247 return 16 + (op & 0x7);
248}
249
250/* Extract xxxx_xxxD_DDDD_xxxx. */
251static inline byte get_d (word op)
252{
253 return (op >> 4) & 0x1f;
254}
255
256/* Extract xxxx_xxxx_DDDD_xxxx. */
257static inline byte get_d16 (word op)
258{
259 return 16 + ((op >> 4) & 0x0f);
260}
261
262/* Extract xxxx_xxxx_xDDD_xxxx. */
263static inline byte get_d16_23 (word op)
264{
265 return 16 + ((op >> 4) & 0x07);
266}
267
268/* Extract xxxx_xAAx_xxxx_AAAA. */
269static inline byte get_A (word op)
270{
271 return (op & 0x0f) | ((op & 0x600) >> 5);
272}
273
274/* Extract xxxx_xxxx_AAAA_Axxx. */
275static inline byte get_biA (word op)
276{
277 return (op >> 3) & 0x1f;
278}
279
280/* Extract xxxx_KKKK_xxxx_KKKK. */
281static inline byte get_K (word op)
282{
283 return (op & 0xf) | ((op & 0xf00) >> 4);
284}
285
286/* Extract xxxx_xxKK_KKKK_Kxxx. */
287static inline int get_k (word op)
288{
289 return sign_ext ((op & 0x3f8) >> 3, 7);
290}
291
292/* Extract xxxx_xxxx_xxDD_xxxx. */
293static inline byte get_d24 (word op)
294{
295 return 24 + ((op >> 3) & 6);
296}
297
298/* Extract xxxx_xxxx_KKxx_KKKK. */
299static inline byte get_k6 (word op)
300{
301 return (op & 0xf) | ((op >> 2) & 0x30);
302}
303
304/* Extract xxQx_QQxx_xxxx_xQQQ. */
305static inline byte get_q (word op)
306{
307 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20);
308}
309
310/* Extract xxxx_xxxx_xxxx_xBBB. */
311static inline byte get_b (word op)
312{
313 return (op & 7);
314}
315
316/* AVR is little endian. */
317static inline word
318read_word (unsigned int addr)
319{
320 return sram[addr] | (sram[addr + 1] << 8);
321}
322
323static inline void
324write_word (unsigned int addr, word w)
325{
326 sram[addr] = w;
327 sram[addr + 1] = w >> 8;
328}
329
330static inline word
331read_word_post_inc (unsigned int addr)
332{
333 word v = read_word (addr);
334 write_word (addr, v + 1);
335 return v;
336}
337
338static inline word
339read_word_pre_dec (unsigned int addr)
340{
341 word v = read_word (addr) - 1;
342 write_word (addr, v);
343 return v;
344}
345
346static void
347update_flags_logic (byte res)
348{
349 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
350 if (res == 0)
351 sram[SREG] |= SREG_Z;
352 if (res & 0x80)
353 sram[SREG] |= SREG_N | SREG_S;
354}
355
356static void
357update_flags_add (byte r, byte a, byte b)
358{
359 byte carry;
360
361 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
362 if (r & 0x80)
363 sram[SREG] |= SREG_N;
364 carry = (a & b) | (a & ~r) | (b & ~r);
365 if (carry & 0x08)
366 sram[SREG] |= SREG_H;
367 if (carry & 0x80)
368 sram[SREG] |= SREG_C;
369 if (((a & b & ~r) | (~a & ~b & r)) & 0x80)
370 sram[SREG] |= SREG_V;
371 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
372 sram[SREG] |= SREG_S;
373 if (r == 0)
374 sram[SREG] |= SREG_Z;
375}
376
377static void update_flags_sub (byte r, byte a, byte b)
378{
379 byte carry;
380
381 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
382 if (r & 0x80)
383 sram[SREG] |= SREG_N;
384 carry = (~a & b) | (b & r) | (r & ~a);
385 if (carry & 0x08)
386 sram[SREG] |= SREG_H;
387 if (carry & 0x80)
388 sram[SREG] |= SREG_C;
389 if (((a & ~b & ~r) | (~a & b & r)) & 0x80)
390 sram[SREG] |= SREG_V;
391 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
392 sram[SREG] |= SREG_S;
393 /* Note: Z is not set. */
394}
395
396static enum avr_opcode
397decode (unsigned int pc)
398{
399 word op1 = flash[pc].op;
400
401 switch ((op1 >> 12) & 0x0f)
402 {
403 case 0x0:
404 switch ((op1 >> 10) & 0x3)
405 {
406 case 0x0:
407 switch ((op1 >> 8) & 0x3)
408 {
409 case 0x0:
410 if (op1 == 0)
411 return OP_nop;
412 break;
413 case 0x1:
414 return OP_movw;
415 case 0x2:
416 return OP_muls;
417 case 0x3:
418 if (op1 & 0x80)
419 {
420 if (op1 & 0x08)
421 return OP_fmulsu;
422 else
423 return OP_fmuls;
424 }
425 else
426 {
427 if (op1 & 0x08)
428 return OP_fmul;
429 else
430 return OP_mulsu;
431 }
432 }
433 break;
434 case 0x1:
435 return OP_cpc;
436 case 0x2:
437 flash[pc].r = SREG_C;
438 return OP_sbc;
439 case 0x3:
440 flash[pc].r = 0;
441 return OP_add;
442 }
443 break;
444 case 0x1:
445 switch ((op1 >> 10) & 0x3)
446 {
447 case 0x0:
448 return OP_cpse;
449 case 0x1:
450 return OP_cp;
451 case 0x2:
452 flash[pc].r = 0;
453 return OP_sub;
454 case 0x3:
455 flash[pc].r = SREG_C;
456 return OP_adc;
457 }
458 break;
459 case 0x2:
460 switch ((op1 >> 10) & 0x3)
461 {
462 case 0x0:
463 return OP_and;
464 case 0x1:
465 return OP_eor;
466 case 0x2:
467 return OP_or;
468 case 0x3:
469 return OP_mov;
470 }
471 break;
472 case 0x3:
473 return OP_cpi;
474 case 0x4:
475 return OP_sbci;
476 case 0x5:
477 return OP_subi;
478 case 0x6:
479 return OP_ori;
480 case 0x7:
481 return OP_andi;
482 case 0x8:
483 case 0xa:
484 if (op1 & 0x0200)
485 {
486 if (op1 & 0x0008)
487 {
488 flash[pc].r = get_q (op1);
489 return OP_std_Y;
490 }
491 else
492 {
493 flash[pc].r = get_q (op1);
494 return OP_std_Z;
495 }
496 }
497 else
498 {
499 if (op1 & 0x0008)
500 {
501 flash[pc].r = get_q (op1);
502 return OP_ldd_Y;
503 }
504 else
505 {
506 flash[pc].r = get_q (op1);
507 return OP_ldd_Z;
508 }
509 }
510 break;
511 case 0x9: /* 9xxx */
512 switch ((op1 >> 8) & 0xf)
513 {
514 case 0x0:
515 case 0x1:
516 switch ((op1 >> 0) & 0xf)
517 {
518 case 0x0:
519 return OP_lds;
520 case 0x1:
521 return OP_ld_Z_inc;
522 case 0x2:
523 return OP_ld_dec_Z;
524 case 0x4:
525 return OP_lpm_Z;
526 case 0x5:
527 return OP_lpm_inc_Z;
528 case 0x6:
529 return OP_elpm_Z;
530 case 0x7:
531 return OP_elpm_inc_Z;
532 case 0x9:
533 return OP_ld_Y_inc;
534 case 0xa:
535 return OP_ld_dec_Y;
536 case 0xc:
537 return OP_ld_X;
538 case 0xd:
539 return OP_ld_X_inc;
540 case 0xe:
541 return OP_ld_dec_X;
542 case 0xf:
543 return OP_pop;
544 }
545 break;
546 case 0x2:
547 case 0x3:
548 switch ((op1 >> 0) & 0xf)
549 {
550 case 0x0:
551 return OP_sts;
552 case 0x1:
553 return OP_st_Z_inc;
554 case 0x2:
555 return OP_st_dec_Z;
556 case 0x9:
557 return OP_st_Y_inc;
558 case 0xa:
559 return OP_st_dec_Y;
560 case 0xc:
561 return OP_st_X;
562 case 0xd:
563 return OP_st_X_inc;
564 case 0xe:
565 return OP_st_dec_X;
566 case 0xf:
567 return OP_push;
568 }
569 break;
570 case 0x4:
571 case 0x5:
572 switch (op1 & 0xf)
573 {
574 case 0x0:
575 return OP_com;
576 case 0x1:
577 return OP_neg;
578 case 0x2:
579 return OP_swap;
580 case 0x3:
581 return OP_inc;
582 case 0x5:
583 flash[pc].r = 0x80;
584 return OP_asr;
585 case 0x6:
586 flash[pc].r = 0;
587 return OP_lsr;
588 case 0x7:
589 return OP_ror;
590 case 0x8: /* 9[45]x8 */
591 switch ((op1 >> 4) & 0x1f)
592 {
593 case 0x00:
594 case 0x01:
595 case 0x02:
596 case 0x03:
597 case 0x04:
598 case 0x05:
599 case 0x06:
600 case 0x07:
601 return OP_bset;
602 case 0x08:
603 case 0x09:
604 case 0x0a:
605 case 0x0b:
606 case 0x0c:
607 case 0x0d:
608 case 0x0e:
609 case 0x0f:
610 return OP_bclr;
611 case 0x10:
612 return OP_ret;
613 case 0x11:
614 return OP_reti;
615 case 0x19:
616 return OP_break;
617 case 0x1c:
618 return OP_lpm;
619 case 0x1d:
620 return OP_elpm;
621 default:
622 break;
623 }
624 break;
625 case 0x9: /* 9[45]x9 */
626 switch ((op1 >> 4) & 0x1f)
627 {
628 case 0x00:
629 return OP_ijmp;
630 case 0x01:
631 return OP_eijmp;
632 case 0x10:
633 return OP_icall;
634 case 0x11:
635 return OP_eicall;
636 default:
637 break;
638 }
639 break;
640 case 0xa:
641 return OP_dec;
642 case 0xc:
643 case 0xd:
644 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
645 return OP_jmp;
646 case 0xe:
647 case 0xf:
648 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
649 return OP_call;
650 }
651 break;
652 case 0x6:
653 return OP_adiw;
654 case 0x7:
655 return OP_sbiw;
656 case 0x8:
657 return OP_cbi;
658 case 0x9:
659 return OP_sbic;
660 case 0xa:
661 return OP_sbi;
662 case 0xb:
663 return OP_sbis;
664 case 0xc:
665 case 0xd:
666 case 0xe:
667 case 0xf:
668 return OP_mul;
669 }
670 break;
671 case 0xb:
672 flash[pc].r = get_A (op1);
673 if (((op1 >> 11) & 1) == 0)
674 return OP_in;
675 else
676 return OP_out;
677 case 0xc:
678 return OP_rjmp;
679 case 0xd:
680 return OP_rcall;
681 case 0xe:
682 return OP_ldi;
683 case 0xf:
684 switch ((op1 >> 9) & 7)
685 {
686 case 0:
687 case 1:
688 flash[pc].r = 1 << (op1 & 7);
689 return OP_brbs;
690 case 2:
691 case 3:
692 flash[pc].r = 1 << (op1 & 7);
693 return OP_brbc;
694 case 4:
695 if ((op1 & 8) == 0)
696 {
697 flash[pc].r = 1 << (op1 & 7);
698 return OP_bld;
699 }
700 break;
701 case 5:
702 if ((op1 & 8) == 0)
703 {
704 flash[pc].r = 1 << (op1 & 7);
705 return OP_bst;
706 }
707 break;
708 case 6:
709 if ((op1 & 8) == 0)
710 {
711 flash[pc].r = 1 << (op1 & 7);
712 return OP_sbrc;
713 }
714 break;
715 case 7:
716 if ((op1 & 8) == 0)
717 {
718 flash[pc].r = 1 << (op1 & 7);
719 return OP_sbrs;
720 }
721 break;
722 }
723 }
df1756f4 724
9943d318 725 return OP_bad;
df1756f4
TG		 726}
727
728static void
82d442c6 729do_call (SIM_CPU *cpu, unsigned int npc)
df1756f4 730{
937af0fd 731 const struct avr_sim_state *state = AVR_SIM_STATE (CPU_STATE (cpu));
df1756f4
TG		 732 unsigned int sp = read_word (REG_SP);
733
734 /* Big endian! */
82d442c6
MF		 735 sram[sp--] = cpu->pc;
736 sram[sp--] = cpu->pc >> 8;
937af0fd 737 if (state->avr_pc22)
df1756f4 738 {
82d442c6
MF		 739 sram[sp--] = cpu->pc >> 16;
740 cpu->cycles++;
df1756f4
TG		 741 }
742 write_word (REG_SP, sp);
82d442c6
MF		 743 cpu->pc = npc & PC_MASK;
744 cpu->cycles += 3;
df1756f4
TG		 745}
746
747static int
748get_insn_length (unsigned int p)
749{
750 if (flash[p].code == OP_unknown)
751 flash[p].code = decode(p);
752 if (flash[p].code >= OP_2words)
753 return 2;
754 else
755 return 1;
756}
757
758static unsigned int
759get_z (void)
760{
761 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO];
762}
763
764static unsigned char
765get_lpm (unsigned int addr)
766{
767 word w;
768
769 w = flash[(addr >> 1) & PC_MASK].op;
770 if (addr & 1)
771 w >>= 8;
772 return w;
773}
774
775static void
82d442c6 776gen_mul (SIM_CPU *cpu, unsigned int res)
df1756f4
TG		 777{
778 write_word (0, res);
779 sram[SREG] &= ~(SREG_Z | SREG_C);
780 if (res == 0)
781 sram[SREG] |= SREG_Z;
782 if (res & 0x8000)
783 sram[SREG] |= SREG_C;
82d442c6 784 cpu->cycles++;
df1756f4
TG		 785}
786
9943d318
MF		 787static void
788step_once (SIM_CPU *cpu)
df1756f4
TG		 789{
790 unsigned int ipc;
791
9943d318
MF		 792 int code;
793 word op;
794 byte res;
795 byte r, d, vd;
df1756f4 796
9943d318 797 again:
82d442c6
MF		 798 code = flash[cpu->pc].code;
799 op = flash[cpu->pc].op;
df1756f4 800
9943d318
MF		 801#if 0
802 if (tracing && code != OP_unknown)
df1756f4
TG		 803 {
804 if (verbose > 0) {
805 int flags;
806 int i;
9943d318 807
df1756f4
TG		 808 sim_cb_eprintf (callback, "R00-07:");
809 for (i = 0; i < 8; i++)
810 sim_cb_eprintf (callback, " %02x", sram[i]);
811 sim_cb_eprintf (callback, " -");
812 for (i = 8; i < 16; i++)
813 sim_cb_eprintf (callback, " %02x", sram[i]);
814 sim_cb_eprintf (callback, " SP: %02x %02x",
815 sram[REG_SP + 1], sram[REG_SP]);
816 sim_cb_eprintf (callback, "\n");
817 sim_cb_eprintf (callback, "R16-31:");
818 for (i = 16; i < 24; i++)
819 sim_cb_eprintf (callback, " %02x", sram[i]);
820 sim_cb_eprintf (callback, " -");
821 for (i = 24; i < 32; i++)
822 sim_cb_eprintf (callback, " %02x", sram[i]);
823 sim_cb_eprintf (callback, " ");
824 flags = sram[SREG];
825 for (i = 0; i < 8; i++)
826 sim_cb_eprintf (callback, "%c",
827 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-');
828 sim_cb_eprintf (callback, "\n");
829 }
830
9943d318 831 if (!tracing)
82d442c6 832 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * cpu->pc, flash[cpu->pc].op);
df1756f4
TG		 833 else
834 {
835 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
82d442c6
MF		 836 2 * cpu->pc, flash[cpu->pc].op, code, flash[cpu->pc].r);
837 disassemble_insn (CPU_STATE (cpu), cpu->pc);
df1756f4
TG		 838 sim_cb_eprintf (callback, "\n");
839 }
840 }
9943d318 841#endif
df1756f4 842
82d442c6
MF		 843 ipc = cpu->pc;
844 cpu->pc = (cpu->pc + 1) & PC_MASK;
845 cpu->cycles++;
df1756f4 846
9943d318
MF		 847 switch (code)
848 {
849 case OP_unknown:
850 flash[ipc].code = decode(ipc);
82d442c6
MF		 851 cpu->pc = ipc;
852 cpu->cycles--;
9943d318
MF		 853 goto again;
854
855 case OP_nop:
856 break;
857
858 case OP_jmp:
859 /* 2 words instruction, but we don't care about the pc. */
82d442c6
MF		 860 cpu->pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK;
861 cpu->cycles += 2;
9943d318
MF		 862 break;
863
864 case OP_eijmp:
82d442c6
MF		 865 cpu->pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK;
866 cpu->cycles += 2;
9943d318
MF		 867 break;
868
869 case OP_ijmp:
82d442c6
MF		 870 cpu->pc = read_word (REGZ) & PC_MASK;
871 cpu->cycles += 1;
9943d318
MF		 872 break;
873
874 case OP_call:
875 /* 2 words instruction. */
82d442c6
MF		 876 cpu->pc++;
877 do_call (cpu, (flash[ipc].r << 16) | flash[ipc + 1].op);
9943d318
MF		 878 break;
879
880 case OP_eicall:
82d442c6 881 do_call (cpu, (sram[EIND] << 16) | read_word (REGZ));
9943d318
MF		 882 break;
883
884 case OP_icall:
82d442c6 885 do_call (cpu, read_word (REGZ));
9943d318
MF		 886 break;
887
888 case OP_rcall:
82d442c6 889 do_call (cpu, cpu->pc + sign_ext (op & 0xfff, 12));
9943d318
MF		 890 break;
891
892 case OP_reti:
893 sram[SREG] |= SREG_I;
894 /* Fall through */
895 case OP_ret:
df1756f4 896 {
937af0fd 897 const struct avr_sim_state *state = AVR_SIM_STATE (CPU_STATE (cpu));
9943d318 898 unsigned int sp = read_word (REG_SP);
937af0fd 899 if (state->avr_pc22)
9943d318 900 {
82d442c6
MF		 901 cpu->pc = sram[++sp] << 16;
902 cpu->cycles++;
9943d318 903 }
df1756f4 904 else
82d442c6
MF		 905 cpu->pc = 0;
906 cpu->pc |= sram[++sp] << 8;
907 cpu->pc |= sram[++sp];
9943d318
MF		 908 write_word (REG_SP, sp);
909 }
82d442c6 910 cpu->cycles += 3;
9943d318
MF		 911 break;
912
913 case OP_break:
914 /* Stop on this address. */
59f48f5a 915 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, ipc, sim_stopped, SIM_SIGTRAP);
9943d318
MF		 916 break;
917
918 case OP_bld:
919 d = get_d (op);
920 r = flash[ipc].r;
921 if (sram[SREG] & SREG_T)
922 sram[d] |= r;
923 else
924 sram[d] &= ~r;
925 break;
926
927 case OP_bst:
928 if (sram[get_d (op)] & flash[ipc].r)
929 sram[SREG] |= SREG_T;
930 else
931 sram[SREG] &= ~SREG_T;
932 break;
933
934 case OP_sbrc:
935 case OP_sbrs:
936 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0))
df1756f4 937 {
82d442c6
MF		 938 int l = get_insn_length (cpu->pc);
939 cpu->pc += l;
940 cpu->cycles += l;
df1756f4 941 }
9943d318 942 break;
df1756f4 943
9943d318
MF		 944 case OP_push:
945 {
946 unsigned int sp = read_word (REG_SP);
947 sram[sp--] = sram[get_d (op)];
948 write_word (REG_SP, sp);
949 }
82d442c6 950 cpu->cycles++;
9943d318 951 break;
df1756f4 952
9943d318
MF		 953 case OP_pop:
954 {
955 unsigned int sp = read_word (REG_SP);
956 sram[get_d (op)] = sram[++sp];
957 write_word (REG_SP, sp);
958 }
82d442c6 959 cpu->cycles++;
9943d318
MF		 960 break;
961
962 case OP_bclr:
963 sram[SREG] &= ~(1 << ((op >> 4) & 0x7));
964 break;
965
966 case OP_bset:
967 sram[SREG] |= 1 << ((op >> 4) & 0x7);
968 break;
969
970 case OP_rjmp:
82d442c6
MF		 971 cpu->pc = (cpu->pc + sign_ext (op & 0xfff, 12)) & PC_MASK;
972 cpu->cycles++;
9943d318
MF		 973 break;
974
975 case OP_eor:
976 d = get_d (op);
977 res = sram[d] ^ sram[get_r (op)];
978 sram[d] = res;
979 update_flags_logic (res);
980 break;
981
982 case OP_and:
983 d = get_d (op);
984 res = sram[d] & sram[get_r (op)];
985 sram[d] = res;
986 update_flags_logic (res);
987 break;
988
989 case OP_andi:
990 d = get_d16 (op);
991 res = sram[d] & get_K (op);
992 sram[d] = res;
993 update_flags_logic (res);
994 break;
995
996 case OP_or:
997 d = get_d (op);
998 res = sram[d] | sram[get_r (op)];
999 sram[d] = res;
1000 update_flags_logic (res);
1001 break;
1002
1003 case OP_ori:
1004 d = get_d16 (op);
1005 res = sram[d] | get_K (op);
1006 sram[d] = res;
1007 update_flags_logic (res);
1008 break;
1009
1010 case OP_com:
1011 d = get_d (op);
1012 res = ~sram[d];
1013 sram[d] = res;
1014 update_flags_logic (res);
1015 sram[SREG] |= SREG_C;
1016 break;
1017
1018 case OP_swap:
1019 d = get_d (op);
1020 vd = sram[d];
1021 sram[d] = (vd >> 4) | (vd << 4);
1022 break;
1023
1024 case OP_neg:
1025 d = get_d (op);
1026 vd = sram[d];
1027 res = -vd;
1028 sram[d] = res;
1029 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1030 if (res == 0)
1031 sram[SREG] |= SREG_Z;
1032 else
df1756f4 1033 sram[SREG] |= SREG_C;
9943d318
MF		 1034 if (res == 0x80)
1035 sram[SREG] |= SREG_V | SREG_N;
1036 else if (res & 0x80)
1037 sram[SREG] |= SREG_N | SREG_S;
1038 if ((res | vd) & 0x08)
1039 sram[SREG] |= SREG_H;
1040 break;
1041
1042 case OP_inc:
1043 d = get_d (op);
1044 res = sram[d] + 1;
1045 sram[d] = res;
1046 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1047 if (res == 0x80)
1048 sram[SREG] |= SREG_V | SREG_N;
1049 else if (res & 0x80)
1050 sram[SREG] |= SREG_N | SREG_S;
1051 else if (res == 0)
1052 sram[SREG] |= SREG_Z;
1053 break;
1054
1055 case OP_dec:
1056 d = get_d (op);
1057 res = sram[d] - 1;
1058 sram[d] = res;
1059 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1060 if (res == 0x7f)
1061 sram[SREG] |= SREG_V | SREG_S;
1062 else if (res & 0x80)
1063 sram[SREG] |= SREG_N | SREG_S;
1064 else if (res == 0)
1065 sram[SREG] |= SREG_Z;
1066 break;
1067
1068 case OP_lsr:
1069 case OP_asr:
1070 d = get_d (op);
1071 vd = sram[d];
1072 res = (vd >> 1) | (vd & flash[ipc].r);
1073 sram[d] = res;
1074 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1075 if (vd & 1)
1076 sram[SREG] |= SREG_C | SREG_S;
1077 if (res & 0x80)
1078 sram[SREG] |= SREG_N;
1079 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1080 sram[SREG] |= SREG_V;
1081 if (res == 0)
1082 sram[SREG] |= SREG_Z;
1083 break;
1084
1085 case OP_ror:
1086 d = get_d (op);
1087 vd = sram[d];
1088 res = vd >> 1 | (sram[SREG] << 7);
1089 sram[d] = res;
1090 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1091 if (vd & 1)
1092 sram[SREG] |= SREG_C | SREG_S;
1093 if (res & 0x80)
1094 sram[SREG] |= SREG_N;
1095 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1096 sram[SREG] |= SREG_V;
1097 if (res == 0)
1098 sram[SREG] |= SREG_Z;
1099 break;
1100
1101 case OP_mul:
82d442c6 1102 gen_mul (cpu, (word)sram[get_r (op)] * (word)sram[get_d (op)]);
9943d318
MF		 1103 break;
1104
1105 case OP_muls:
82d442c6
MF		 1106 gen_mul (cpu, (sword)(sbyte)sram[get_r16 (op)]
1107 * (sword)(sbyte)sram[get_d16 (op)]);
9943d318
MF		 1108 break;
1109
1110 case OP_mulsu:
82d442c6
MF		 1111 gen_mul (cpu, (sword)(word)sram[get_r16_23 (op)]
1112 * (sword)(sbyte)sram[get_d16_23 (op)]);
9943d318
MF		 1113 break;
1114
1115 case OP_fmul:
82d442c6
MF		 1116 gen_mul (cpu, ((word)sram[get_r16_23 (op)]
1117 * (word)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1118 break;
1119
1120 case OP_fmuls:
82d442c6
MF		 1121 gen_mul (cpu, ((sword)(sbyte)sram[get_r16_23 (op)]
1122 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1123 break;
1124
1125 case OP_fmulsu:
82d442c6
MF		 1126 gen_mul (cpu, ((sword)(word)sram[get_r16_23 (op)]
1127 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1128 break;
1129
1130 case OP_adc:
1131 case OP_add:
1132 r = sram[get_r (op)];
1133 d = get_d (op);
1134 vd = sram[d];
1135 res = r + vd + (sram[SREG] & flash[ipc].r);
1136 sram[d] = res;
1137 update_flags_add (res, vd, r);
1138 break;
1139
1140 case OP_sub:
1141 d = get_d (op);
1142 vd = sram[d];
1143 r = sram[get_r (op)];
1144 res = vd - r;
1145 sram[d] = res;
1146 update_flags_sub (res, vd, r);
1147 if (res == 0)
1148 sram[SREG] |= SREG_Z;
1149 break;
1150
1151 case OP_sbc:
1152 {
1153 byte old = sram[SREG];
df1756f4
TG		 1154 d = get_d (op);
1155 vd = sram[d];
1156 r = sram[get_r (op)];
9943d318 1157 res = vd - r - (old & SREG_C);
df1756f4
TG		 1158 sram[d] = res;
1159 update_flags_sub (res, vd, r);
9943d318 1160 if (res == 0 && (old & SREG_Z))
df1756f4 1161 sram[SREG] |= SREG_Z;
9943d318
MF		 1162 }
1163 break;
1164
1165 case OP_subi:
1166 d = get_d16 (op);
1167 vd = sram[d];
1168 r = get_K (op);
1169 res = vd - r;
1170 sram[d] = res;
1171 update_flags_sub (res, vd, r);
1172 if (res == 0)
1173 sram[SREG] |= SREG_Z;
1174 break;
1175
1176 case OP_sbci:
1177 {
1178 byte old = sram[SREG];
df1756f4 1179
df1756f4
TG		 1180 d = get_d16 (op);
1181 vd = sram[d];
1182 r = get_K (op);
9943d318 1183 res = vd - r - (old & SREG_C);
df1756f4
TG		 1184 sram[d] = res;
1185 update_flags_sub (res, vd, r);
9943d318 1186 if (res == 0 && (old & SREG_Z))
df1756f4 1187 sram[SREG] |= SREG_Z;
9943d318
MF		 1188 }
1189 break;
1190
1191 case OP_mov:
1192 sram[get_d (op)] = sram[get_r (op)];
1193 break;
1194
1195 case OP_movw:
1196 d = (op & 0xf0) >> 3;
1197 r = (op & 0x0f) << 1;
1198 sram[d] = sram[r];
1199 sram[d + 1] = sram[r + 1];
1200 break;
1201
1202 case OP_out:
1203 d = get_A (op) + 0x20;
1204 res = sram[get_d (op)];
1205 sram[d] = res;
1206 if (d == STDIO_PORT)
1207 putchar (res);
1208 else if (d == EXIT_PORT)
82d442c6 1209 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 0);
9943d318 1210 else if (d == ABORT_PORT)
82d442c6 1211 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 1);
9943d318
MF		 1212 break;
1213
1214 case OP_in:
1215 d = get_A (op) + 0x20;
1216 sram[get_d (op)] = sram[d];
1217 break;
1218
1219 case OP_cbi:
1220 d = get_biA (op) + 0x20;
1221 sram[d] &= ~(1 << get_b(op));
1222 break;
1223
1224 case OP_sbi:
1225 d = get_biA (op) + 0x20;
1226 sram[d] |= 1 << get_b(op);
1227 break;
1228
1229 case OP_sbic:
1230 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op)))
df1756f4 1231 {
82d442c6
MF		 1232 int l = get_insn_length (cpu->pc);
1233 cpu->pc += l;
1234 cpu->cycles += l;
df1756f4 1235 }
9943d318 1236 break;
df1756f4 1237
9943d318
MF		 1238 case OP_sbis:
1239 if (sram[get_biA (op) + 0x20] & 1 << get_b(op))
1240 {
82d442c6
MF		 1241 int l = get_insn_length (cpu->pc);
1242 cpu->pc += l;
1243 cpu->cycles += l;
9943d318
MF		 1244 }
1245 break;
1246
1247 case OP_ldi:
1248 res = get_K (op);
1249 d = get_d16 (op);
1250 sram[d] = res;
1251 break;
1252
1253 case OP_lds:
82d442c6
MF		 1254 sram[get_d (op)] = sram[flash[cpu->pc].op];
1255 cpu->pc++;
1256 cpu->cycles++;
9943d318
MF		 1257 break;
1258
1259 case OP_sts:
82d442c6
MF		 1260 sram[flash[cpu->pc].op] = sram[get_d (op)];
1261 cpu->pc++;
1262 cpu->cycles++;
9943d318
MF		 1263 break;
1264
1265 case OP_cpse:
1266 if (sram[get_r (op)] == sram[get_d (op)])
1267 {
82d442c6
MF		 1268 int l = get_insn_length (cpu->pc);
1269 cpu->pc += l;
1270 cpu->cycles += l;
9943d318
MF		 1271 }
1272 break;
1273
1274 case OP_cp:
1275 r = sram[get_r (op)];
1276 d = sram[get_d (op)];
1277 res = d - r;
1278 update_flags_sub (res, d, r);
1279 if (res == 0)
1280 sram[SREG] |= SREG_Z;
1281 break;
1282
1283 case OP_cpi:
1284 r = get_K (op);
1285 d = sram[get_d16 (op)];
1286 res = d - r;
1287 update_flags_sub (res, d, r);
1288 if (res == 0)
1289 sram[SREG] |= SREG_Z;
1290 break;
1291
1292 case OP_cpc:
1293 {
1294 byte old = sram[SREG];
df1756f4 1295 d = sram[get_d (op)];
9943d318
MF		 1296 r = sram[get_r (op)];
1297 res = d - r - (old & SREG_C);
df1756f4 1298 update_flags_sub (res, d, r);
9943d318 1299 if (res == 0 && (old & SREG_Z))
df1756f4 1300 sram[SREG] |= SREG_Z;
9943d318
MF		 1301 }
1302 break;
df1756f4 1303
9943d318
MF		 1304 case OP_brbc:
1305 if (!(sram[SREG] & flash[ipc].r))
1306 {
82d442c6
MF		 1307 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK;
1308 cpu->cycles++;
9943d318
MF		 1309 }
1310 break;
df1756f4 1311
9943d318
MF		 1312 case OP_brbs:
1313 if (sram[SREG] & flash[ipc].r)
df1756f4 1314 {
82d442c6
MF		 1315 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK;
1316 cpu->cycles++;
df1756f4 1317 }
9943d318
MF		 1318 break;
1319
1320 case OP_lpm:
1321 sram[0] = get_lpm (read_word (REGZ));
82d442c6 1322 cpu->cycles += 2;
9943d318
MF		 1323 break;
1324
1325 case OP_lpm_Z:
1326 sram[get_d (op)] = get_lpm (read_word (REGZ));
82d442c6 1327 cpu->cycles += 2;
9943d318
MF		 1328 break;
1329
1330 case OP_lpm_inc_Z:
1331 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ));
82d442c6 1332 cpu->cycles += 2;
9943d318
MF		 1333 break;
1334
1335 case OP_elpm:
1336 sram[0] = get_lpm (get_z ());
82d442c6 1337 cpu->cycles += 2;
9943d318
MF		 1338 break;
1339
1340 case OP_elpm_Z:
1341 sram[get_d (op)] = get_lpm (get_z ());
82d442c6 1342 cpu->cycles += 2;
9943d318
MF		 1343 break;
1344
1345 case OP_elpm_inc_Z:
1346 {
1347 unsigned int z = get_z ();
df1756f4 1348
9943d318
MF		 1349 sram[get_d (op)] = get_lpm (z);
1350 z++;
1351 sram[REGZ_LO] = z;
1352 sram[REGZ_HI] = z >> 8;
1353 sram[RAMPZ] = z >> 16;
1354 }
82d442c6 1355 cpu->cycles += 2;
9943d318
MF		 1356 break;
1357
1358 case OP_ld_Z_inc:
1359 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK];
82d442c6 1360 cpu->cycles++;
9943d318
MF		 1361 break;
1362
1363 case OP_ld_dec_Z:
1364 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK];
82d442c6 1365 cpu->cycles++;
9943d318
MF		 1366 break;
1367
1368 case OP_ld_X_inc:
1369 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK];
82d442c6 1370 cpu->cycles++;
9943d318
MF		 1371 break;
1372
1373 case OP_ld_dec_X:
1374 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK];
82d442c6 1375 cpu->cycles++;
9943d318
MF		 1376 break;
1377
1378 case OP_ld_Y_inc:
1379 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK];
82d442c6 1380 cpu->cycles++;
9943d318
MF		 1381 break;
1382
1383 case OP_ld_dec_Y:
1384 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK];
82d442c6 1385 cpu->cycles++;
9943d318
MF		 1386 break;
1387
1388 case OP_st_X:
1389 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1390 cpu->cycles++;
9943d318
MF		 1391 break;
1392
1393 case OP_st_X_inc:
1394 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1395 cpu->cycles++;
9943d318
MF		 1396 break;
1397
1398 case OP_st_dec_X:
1399 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1400 cpu->cycles++;
9943d318
MF		 1401 break;
1402
1403 case OP_st_Z_inc:
1404 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1405 cpu->cycles++;
9943d318
MF		 1406 break;
1407
1408 case OP_st_dec_Z:
1409 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1410 cpu->cycles++;
9943d318
MF		 1411 break;
1412
1413 case OP_st_Y_inc:
1414 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1415 cpu->cycles++;
9943d318
MF		 1416 break;
1417
1418 case OP_st_dec_Y:
1419 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1420 cpu->cycles++;
9943d318
MF		 1421 break;
1422
1423 case OP_std_Y:
1424 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)];
82d442c6 1425 cpu->cycles++;
9943d318
MF		 1426 break;
1427
1428 case OP_std_Z:
1429 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)];
82d442c6 1430 cpu->cycles++;
9943d318
MF		 1431 break;
1432
1433 case OP_ldd_Z:
1434 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r];
82d442c6 1435 cpu->cycles++;
9943d318
MF		 1436 break;
1437
1438 case OP_ldd_Y:
1439 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r];
82d442c6 1440 cpu->cycles++;
9943d318
MF		 1441 break;
1442
1443 case OP_ld_X:
1444 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK];
82d442c6 1445 cpu->cycles++;
9943d318
MF		 1446 break;
1447
1448 case OP_sbiw:
1449 {
1450 word wk = get_k6 (op);
1451 word wres;
1452 word wr;
df1756f4 1453
9943d318
MF		 1454 d = get_d24 (op);
1455 wr = read_word (d);
1456 wres = wr - wk;
df1756f4 1457
9943d318
MF		 1458 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1459 if (wres == 0)
1460 sram[SREG] |= SREG_Z;
1461 if (wres & 0x8000)
1462 sram[SREG] |= SREG_N;
1463 if (wres & ~wr & 0x8000)
1464 sram[SREG] |= SREG_C;
1465 if (~wres & wr & 0x8000)
1466 sram[SREG] |= SREG_V;
1467 if (((~wres & wr) ^ wres) & 0x8000)
1468 sram[SREG] |= SREG_S;
1469 write_word (d, wres);
1470 }
82d442c6 1471 cpu->cycles++;
9943d318 1472 break;
df1756f4 1473
9943d318
MF		 1474 case OP_adiw:
1475 {
1476 word wk = get_k6 (op);
1477 word wres;
1478 word wr;
1479
1480 d = get_d24 (op);
1481 wr = read_word (d);
1482 wres = wr + wk;
1483
1484 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1485 if (wres == 0)
1486 sram[SREG] |= SREG_Z;
1487 if (wres & 0x8000)
1488 sram[SREG] |= SREG_N;
1489 if (~wres & wr & 0x8000)
1490 sram[SREG] |= SREG_C;
1491 if (wres & ~wr & 0x8000)
1492 sram[SREG] |= SREG_V;
1493 if (((wres & ~wr) ^ wres) & 0x8000)
1494 sram[SREG] |= SREG_S;
1495 write_word (d, wres);
df1756f4 1496 }
82d442c6 1497 cpu->cycles++;
9943d318 1498 break;
df1756f4 1499
9943d318 1500 case OP_bad:
82d442c6 1501 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
df1756f4 1502
9943d318 1503 default:
82d442c6 1504 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
9943d318
MF		 1505 }
1506}
1507
1508void
1509sim_engine_run (SIM_DESC sd,
1510 int next_cpu_nr, /* ignore */
1511 int nr_cpus, /* ignore */
1512 int siggnal) /* ignore */
df1756f4 1513{
9943d318
MF		 1514 SIM_CPU *cpu;
1515
1516 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1517
1518 cpu = STATE_CPU (sd, 0);
df1756f4 1519
9943d318
MF		 1520 while (1)
1521 {
1522 step_once (cpu);
1523 if (sim_events_tick (sd))
1524 sim_events_process (sd);
1525 }
df1756f4
TG		 1526}
1527
1528int
5558e7e6 1529sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
df1756f4
TG		 1530{
1531 int osize = size;
1532
1533 if (addr >= 0 && addr < SRAM_VADDR)
1534 {
8f0ac700 1535 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1536 {
8f0ac700
TG		 1537 word val = flash[addr >> 1].op;
1538
1539 if (addr & 1)
1540 val = (val & 0xff) | (buffer[0] << 8);
1541 else
1542 val = (val & 0xff00) | buffer[0];
1543
1544 flash[addr >> 1].op = val;
1545 flash[addr >> 1].code = OP_unknown;
df1756f4 1546 addr++;
8f0ac700
TG		 1547 buffer++;
1548 size--;
df1756f4
TG		 1549 }
1550 return osize - size;
1551 }
1552 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1553 {
1554 addr -= SRAM_VADDR;
1555 if (addr + size > MAX_AVR_SRAM)
1556 size = MAX_AVR_SRAM - addr;
1557 memcpy (sram + addr, buffer, size);
1558 return size;
1559 }
1560 else
1561 return 0;
1562}
1563
1564int
1565sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1566{
1567 int osize = size;
1568
1569 if (addr >= 0 && addr < SRAM_VADDR)
1570 {
8f0ac700 1571 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1572 {
8f0ac700
TG		 1573 word val = flash[addr >> 1].op;
1574
1575 if (addr & 1)
1576 val >>= 8;
1577
1578 *buffer++ = val;
df1756f4 1579 addr++;
8f0ac700 1580 size--;
df1756f4
TG		 1581 }
1582 return osize - size;
1583 }
1584 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1585 {
1586 addr -= SRAM_VADDR;
1587 if (addr + size > MAX_AVR_SRAM)
1588 size = MAX_AVR_SRAM - addr;
1589 memcpy (buffer, sram + addr, size);
1590 return size;
1591 }
1592 else
1593 {
1594 /* Avoid errors. */
1595 memset (buffer, 0, size);
1596 return size;
1597 }
1598}
1599
807eaf04
MF		 1600static int
1601avr_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
df1756f4
TG		 1602{
1603 if (rn < 32 && length == 1)
1604 {
1605 sram[rn] = *memory;
1606 return 1;
1607 }
1608 if (rn == AVR_SREG_REGNUM && length == 1)
1609 {
1610 sram[SREG] = *memory;
1611 return 1;
1612 }
1613 if (rn == AVR_SP_REGNUM && length == 2)
1614 {
1615 sram[REG_SP] = memory[0];
1616 sram[REG_SP + 1] = memory[1];
1617 return 2;
1618 }
1619 if (rn == AVR_PC_REGNUM && length == 4)
1620 {
82d442c6
MF		 1621 cpu->pc = (memory[0] >> 1) | (memory[1] << 7)
1622 | (memory[2] << 15) | (memory[3] << 23);
1623 cpu->pc &= PC_MASK;
df1756f4
TG		 1624 return 4;
1625 }
1626 return 0;
1627}
1628
807eaf04
MF		 1629static int
1630avr_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
df1756f4
TG		 1631{
1632 if (rn < 32 && length == 1)
1633 {
1634 *memory = sram[rn];
1635 return 1;
1636 }
1637 if (rn == AVR_SREG_REGNUM && length == 1)
1638 {
1639 *memory = sram[SREG];
1640 return 1;
1641 }
1642 if (rn == AVR_SP_REGNUM && length == 2)
1643 {
1644 memory[0] = sram[REG_SP];
1645 memory[1] = sram[REG_SP + 1];
1646 return 2;
1647 }
1648 if (rn == AVR_PC_REGNUM && length == 4)
1649 {
82d442c6
MF		 1650 memory[0] = cpu->pc << 1;
1651 memory[1] = cpu->pc >> 7;
1652 memory[2] = cpu->pc >> 15;
1653 memory[3] = cpu->pc >> 23;
df1756f4
TG		 1654 return 4;
1655 }
1656 return 0;
1657}
1658
4c0cab1e
MF		 1659static sim_cia
1660avr_pc_get (sim_cpu *cpu)
1661{
82d442c6 1662 return cpu->pc;
4c0cab1e
MF		 1663}
1664
1665static void
82d442c6 1666avr_pc_set (sim_cpu *cpu, sim_cia pc)
4c0cab1e 1667{
82d442c6 1668 cpu->pc = pc;
4c0cab1e
MF		 1669}
1670
9943d318
MF		 1671static void
1672free_state (SIM_DESC sd)
df1756f4 1673{
9943d318
MF		 1674 if (STATE_MODULES (sd) != NULL)
1675 sim_module_uninstall (sd);
1676 sim_cpu_free_all (sd);
1677 sim_state_free (sd);
df1756f4
TG		 1678}
1679
1680SIM_DESC
2e3d4f4d
MF		 1681sim_open (SIM_OPEN_KIND kind, host_callback *cb,
1682 struct bfd *abfd, char * const *argv)
df1756f4 1683{
4c0cab1e 1684 int i;
937af0fd 1685 SIM_DESC sd = sim_state_alloc_extra (kind, cb, sizeof (struct avr_sim_state));
9943d318 1686 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
df1756f4 1687
ba307cdd
MF		 1688 /* Set default options before parsing user options. */
1689 current_alignment = STRICT_ALIGNMENT;
f9a4d543 1690 current_target_byte_order = BFD_ENDIAN_LITTLE;
ba307cdd 1691
9943d318 1692 /* The cpu data is kept in a separately allocated chunk of memory. */
d5a71b11 1693 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
9943d318
MF		 1694 {
1695 free_state (sd);
1696 return 0;
1697 }
df1756f4 1698
9943d318
MF		 1699 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1700 {
1701 free_state (sd);
1702 return 0;
1703 }
df1756f4 1704
77cf2ef5 1705 /* The parser will print an error message for us, so we silently return. */
9943d318
MF		 1706 if (sim_parse_args (sd, argv) != SIM_RC_OK)
1707 {
1708 free_state (sd);
1709 return 0;
1710 }
33bcfade 1711
9943d318
MF		 1712 /* Check for/establish the a reference program image. */
1713 if (sim_analyze_program (sd,
1714 (STATE_PROG_ARGV (sd) != NULL
1715 ? *STATE_PROG_ARGV (sd)
1716 : NULL), abfd) != SIM_RC_OK)
1717 {
1718 free_state (sd);
1719 return 0;
1720 }
df1756f4 1721
9943d318
MF		 1722 /* Configure/verify the target byte order and other runtime
1723 configuration options. */
1724 if (sim_config (sd) != SIM_RC_OK)
1725 {
1726 sim_module_uninstall (sd);
1727 return 0;
1728 }
df1756f4 1729
9943d318
MF		 1730 if (sim_post_argv_init (sd) != SIM_RC_OK)
1731 {
1732 /* Uninstall the modules to avoid memory leaks,
1733 file descriptor leaks, etc. */
1734 sim_module_uninstall (sd);
1735 return 0;
1736 }
df1756f4 1737
4c0cab1e
MF		 1738 /* CPU specific initialization. */
1739 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
1740 {
1741 SIM_CPU *cpu = STATE_CPU (sd, i);
1742
807eaf04
MF		 1743 CPU_REG_FETCH (cpu) = avr_reg_fetch;
1744 CPU_REG_STORE (cpu) = avr_reg_store;
4c0cab1e
MF		 1745 CPU_PC_FETCH (cpu) = avr_pc_get;
1746 CPU_PC_STORE (cpu) = avr_pc_set;
1747 }
1748
9943d318
MF		 1749 /* Clear all the memory. */
1750 memset (sram, 0, sizeof (sram));
1751 memset (flash, 0, sizeof (flash));
df1756f4 1752
9943d318 1753 return sd;
df1756f4
TG		 1754}
1755
9943d318 1756SIM_RC
2e3d4f4d
MF		 1757sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
1758 char * const *argv, char * const *env)
df1756f4 1759{
937af0fd 1760 struct avr_sim_state *state = AVR_SIM_STATE (sd);
82d442c6
MF		 1761 SIM_CPU *cpu = STATE_CPU (sd, 0);
1762 SIM_ADDR addr;
1763
9943d318
MF		 1764 /* Set the PC. */
1765 if (abfd != NULL)
82d442c6 1766 addr = bfd_get_start_address (abfd);
9943d318 1767 else
82d442c6
MF		 1768 addr = 0;
1769 sim_pc_set (cpu, addr);
af9f7da7 1770
9943d318 1771 if (abfd != NULL)
937af0fd 1772 state->avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6);
9943d318
MF		 1773
1774 return SIM_RC_OK;
af9f7da7 1775}
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