]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/ft32/interp.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[thirdparty/binutils-gdb.git] / sim / ft32 / interp.c
CommitLineData
f46e4eb7
JB		 1/* Simulator for the FT32 processor
2
3666a048 3 Copyright (C) 2008-2021 Free Software Foundation, Inc.
f46e4eb7
JB		 4 Contributed by FTDI <support@ftdichip.com>
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "config.h"
22#include <fcntl.h>
23#include <signal.h>
24#include <stdlib.h>
25#include <stdint.h>
26
27#include "bfd.h"
df68e12b 28#include "sim/callback.h"
f46e4eb7 29#include "libiberty.h"
df68e12b 30#include "sim/sim.h"
f46e4eb7
JB		 31
32#include "sim-main.h"
33#include "sim-options.h"
34
35#include "opcode/ft32.h"
36
37/*
38 * FT32 is a Harvard architecture: RAM and code occupy
39 * different address spaces.
40 *
41 * sim and gdb model FT32 memory by adding 0x800000 to RAM
42 * addresses. This means that sim/gdb can treat all addresses
43 * similarly.
44 *
45 * The address space looks like:
46 *
47 * 00000 start of code memory
48 * 3ffff end of code memory
49 * 800000 start of RAM
50 * 80ffff end of RAM
51 */
52
53#define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */
54
55static unsigned long
56ft32_extract_unsigned_integer (unsigned char *addr, int len)
57{
58 unsigned long retval;
59 unsigned char *p;
60 unsigned char *startaddr = (unsigned char *) addr;
61 unsigned char *endaddr = startaddr + len;
62
63 /* Start at the most significant end of the integer, and work towards
64 the least significant. */
65 retval = 0;
66
67 for (p = endaddr; p > startaddr;)
68 retval = (retval << 8) | * -- p;
69
70 return retval;
71}
72
73static void
74ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
75{
76 unsigned char *p;
77 unsigned char *startaddr = (unsigned char *)addr;
78 unsigned char *endaddr = startaddr + len;
79
80 for (p = startaddr; p < endaddr; p++)
81 {
82 *p = val & 0xff;
83 val >>= 8;
84 }
85}
86
87/*
88 * Align EA according to its size DW.
89 * The FT32 ignores the low bit of a 16-bit addresss,
90 * and the low two bits of a 32-bit address.
91 */
92static uint32_t ft32_align (uint32_t dw, uint32_t ea)
93{
94 switch (dw)
95 {
96 case 1:
97 ea &= ~1;
98 break;
99 case 2:
100 ea &= ~3;
101 break;
102 default:
103 break;
104 }
105 return ea;
106}
107
108/* Read an item from memory address EA, sized DW. */
109static uint32_t
110ft32_read_item (SIM_DESC sd, int dw, uint32_t ea)
111{
112 sim_cpu *cpu = STATE_CPU (sd, 0);
034685f9 113 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 114 uint8_t byte[4];
115 uint32_t r;
116
117 ea = ft32_align (dw, ea);
118
119 switch (dw) {
120 case 0:
121 return sim_core_read_aligned_1 (cpu, cia, read_map, ea);
122 case 1:
123 return sim_core_read_aligned_2 (cpu, cia, read_map, ea);
124 case 2:
125 return sim_core_read_aligned_4 (cpu, cia, read_map, ea);
126 default:
127 abort ();
128 }
129}
130
131/* Write item V to memory address EA, sized DW. */
132static void
133ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v)
134{
135 sim_cpu *cpu = STATE_CPU (sd, 0);
034685f9 136 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 137 uint8_t byte[4];
138
139 ea = ft32_align (dw, ea);
140
141 switch (dw) {
142 case 0:
143 sim_core_write_aligned_1 (cpu, cia, write_map, ea, v);
144 break;
145 case 1:
146 sim_core_write_aligned_2 (cpu, cia, write_map, ea, v);
147 break;
148 case 2:
149 sim_core_write_aligned_4 (cpu, cia, write_map, ea, v);
150 break;
151 default:
152 abort ();
153 }
154}
155
156#define ILLEGAL() \
157 sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL)
158
159static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea)
160{
161 sim_cpu *cpu = STATE_CPU (sd, 0);
162 uint32_t insnpc = cpu->state.pc;
163 uint32_t r;
164 uint8_t byte[4];
165
166 ea &= 0x1ffff;
167 if (ea & ~0xffff)
168 {
169 /* Simulate some IO devices */
170 switch (ea)
171 {
bcd68f9e
JB		 172 case 0x10000:
173 return getchar ();
f46e4eb7
JB		 174 case 0x1fff4:
175 /* Read the simulator cycle timer. */
176 return cpu->state.cycles / 100;
177 default:
178 sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n",
179 ea, insnpc);
180 ILLEGAL ();
181 }
182 }
183 return ft32_read_item (sd, dw, RAM_BIAS + ea);
184}
185
186static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d)
187{
188 sim_cpu *cpu = STATE_CPU (sd, 0);
189 ea &= 0x1ffff;
190 if (ea & 0x10000)
191 {
192 /* Simulate some IO devices */
193 switch (ea)
194 {
195 case 0x10000:
196 /* Console output */
197 putchar (d & 0xff);
198 break;
199 case 0x1fc80:
200 /* Unlock the PM write port */
201 cpu->state.pm_unlock = (d == 0x1337f7d1);
202 break;
203 case 0x1fc84:
204 /* Set the PM write address register */
205 cpu->state.pm_addr = d;
206 break;
207 case 0x1fc88:
71c34ca7
JB		 208 if (cpu->state.pm_unlock)
209 {
210 /* Write to PM. */
211 ft32_write_item (sd, dw, cpu->state.pm_addr, d);
212 cpu->state.pm_addr += 4;
213 }
f46e4eb7
JB		 214 break;
215 case 0x1fffc:
216 /* Normal exit. */
217 sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.regs[0]);
218 break;
219 case 0x1fff8:
220 sim_io_printf (sd, "Debug write %08x\n", d);
221 break;
222 default:
223 sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea);
224 }
225 }
226 else
227 ft32_write_item (sd, dw, RAM_BIAS + ea, d);
228}
229
230#define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea))
231#define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d))
232
233/* LSBS (n) is a mask of the least significant N bits. */
234#define LSBS(n) ((1U << (n)) - 1)
235
236static void ft32_push (SIM_DESC sd, uint32_t v)
237{
238 sim_cpu *cpu = STATE_CPU (sd, 0);
239 cpu->state.regs[FT32_HARD_SP] -= 4;
240 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
241 cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v);
242}
243
244static uint32_t ft32_pop (SIM_DESC sd)
245{
246 sim_cpu *cpu = STATE_CPU (sd, 0);
247 uint32_t r = cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]);
248 cpu->state.regs[FT32_HARD_SP] += 4;
249 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
250 return r;
251}
252
253/* Extract the low SIZ bits of N as an unsigned number. */
254static int nunsigned (int siz, int n)
255{
256 return n & LSBS (siz);
257}
258
259/* Extract the low SIZ bits of N as a signed number. */
260static int nsigned (int siz, int n)
261{
262 int shift = (sizeof (int) * 8) - siz;
263 return (n << shift) >> shift;
264}
265
266/* Signed division N / D, matching hw behavior for (MIN_INT, -1). */
267static uint32_t ft32sdiv (uint32_t n, uint32_t d)
268{
269 if (n == 0x80000000UL && d == 0xffffffffUL)
270 return 0x80000000UL;
271 else
272 return (uint32_t)((int)n / (int)d);
273}
274
275/* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */
276static uint32_t ft32smod (uint32_t n, uint32_t d)
277{
278 if (n == 0x80000000UL && d == 0xffffffffUL)
279 return 0;
280 else
281 return (uint32_t)((int)n % (int)d);
282}
283
284/* Circular rotate right N by B bits. */
285static uint32_t ror (uint32_t n, uint32_t b)
286{
287 b &= 31;
288 return (n >> b) | (n << (32 - b));
289}
290
291/* Implement the BINS machine instruction.
292 See FT32 Programmer's Reference for details. */
293static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos)
294{
295 uint32_t bitmask = LSBS (len) << pos;
296 return (d & ~bitmask) | ((f << pos) & bitmask);
297}
298
299/* Implement the FLIP machine instruction.
300 See FT32 Programmer's Reference for details. */
301static uint32_t flip (uint32_t x, uint32_t b)
302{
303 if (b & 1)
304 x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1;
305 if (b & 2)
306 x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2;
307 if (b & 4)
308 x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4;
309 if (b & 8)
310 x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8;
311 if (b & 16)
312 x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16;
313 return x;
314}
315
316static void
317step_once (SIM_DESC sd)
318{
319 sim_cpu *cpu = STATE_CPU (sd, 0);
034685f9 320 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 321 uint32_t inst;
322 uint32_t dw;
323 uint32_t cb;
324 uint32_t r_d;
325 uint32_t cr;
326 uint32_t cv;
327 uint32_t bt;
328 uint32_t r_1;
329 uint32_t rimm;
330 uint32_t r_2;
331 uint32_t k20;
332 uint32_t pa;
333 uint32_t aa;
334 uint32_t k16;
3b4b0a62 335 uint32_t k15;
f46e4eb7
JB		 336 uint32_t al;
337 uint32_t r_1v;
338 uint32_t rimmv;
339 uint32_t bit_pos;
340 uint32_t bit_len;
341 uint32_t upper;
342 uint32_t insnpc;
dcc31d28
JB		 343 unsigned int sc[2];
344 int isize;
f46e4eb7 345
f46e4eb7
JB		 346 inst = ft32_read_item (sd, 2, cpu->state.pc);
347 cpu->state.cycles += 1;
348
dcc31d28
JB		 349 if ((STATE_ARCHITECTURE (sd)->mach == bfd_mach_ft32b)
350 && ft32_decode_shortcode (cpu->state.pc, inst, sc))
351 {
352 if ((cpu->state.pc & 3) == 0)
353 inst = sc[0];
354 else
355 inst = sc[1];
356 isize = 2;
357 }
358 else
359 isize = 4;
360
f46e4eb7
JB		 361 /* Handle "call 8" (which is FT32's "break" equivalent) here. */
362 if (inst == 0x00340002)
363 {
364 sim_engine_halt (sd, cpu, NULL,
365 cpu->state.pc,
366 sim_stopped, SIM_SIGTRAP);
367 goto escape;
368 }
369
370 dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ);
371 cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ);
372 r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ);
373 cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ);
374 cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ);
375 bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ);
376 r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ);
377 rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ);
378 r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ);
379 k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ));
380 pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ);
381 aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ);
382 k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ);
3b4b0a62
JB		 383 k15 = (inst >> FT32_FLD_K15_BIT) & LSBS (FT32_FLD_K15_SIZ);
384 if (k15 & 0x80)
385 k15 ^= 0x7f00;
386 if (k15 & 0x4000)
387 k15 -= 0x8000;
f46e4eb7
JB		 388 al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ);
389
390 r_1v = cpu->state.regs[r_1];
391 rimmv = (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0x1f];
392
393 bit_pos = rimmv & 31;
394 bit_len = 0xf & (rimmv >> 5);
395 if (bit_len == 0)
396 bit_len = 16;
397
398 upper = (inst >> 27);
399
400 insnpc = cpu->state.pc;
dcc31d28 401 cpu->state.pc += isize;
f46e4eb7
JB		 402 switch (upper)
403 {
404 case FT32_PAT_TOC:
405 case FT32_PAT_TOCI:
406 {
407 int take = (cr == 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) == cv);
408 if (take)
409 {
410 cpu->state.cycles += 1;
411 if (bt)
412 ft32_push (sd, cpu->state.pc); /* this is a call. */
413 if (upper == FT32_PAT_TOC)
414 cpu->state.pc = pa << 2;
415 else
416 cpu->state.pc = cpu->state.regs[r_2];
417 if (cpu->state.pc == 0x8)
418 goto escape;
419 }
420 }
421 break;
422
423 case FT32_PAT_ALUOP:
424 case FT32_PAT_CMPOP:
425 {
426 uint32_t result;
427 switch (al)
428 {
429 case 0x0: result = r_1v + rimmv; break;
430 case 0x1: result = ror (r_1v, rimmv); break;
431 case 0x2: result = r_1v - rimmv; break;
432 case 0x3: result = (r_1v << 10) | (1023 & rimmv); break;
433 case 0x4: result = r_1v & rimmv; break;
434 case 0x5: result = r_1v | rimmv; break;
435 case 0x6: result = r_1v ^ rimmv; break;
436 case 0x7: result = ~(r_1v ^ rimmv); break;
437 case 0x8: result = r_1v << rimmv; break;
438 case 0x9: result = r_1v >> rimmv; break;
439 case 0xa: result = (int32_t)r_1v >> rimmv; break;
440 case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break;
441 case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break;
442 case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break;
443 case 0xe: result = flip (r_1v, rimmv); break;
444 default:
445 sim_io_eprintf (sd, "Unhandled alu %#x\n", al);
446 ILLEGAL ();
447 }
448 if (upper == FT32_PAT_ALUOP)
449 cpu->state.regs[r_d] = result;
450 else
451 {
452 uint32_t dwmask = 0;
453 int dwsiz = 0;
454 int zero;
455 int sign;
456 int ahi;
457 int bhi;
458 int overflow;
459 int carry;
460 int bit;
461 uint64_t ra;
462 uint64_t rb;
463 int above;
464 int greater;
465 int greatereq;
466
467 switch (dw)
468 {
469 case 0: dwsiz = 7; dwmask = 0xffU; break;
470 case 1: dwsiz = 15; dwmask = 0xffffU; break;
471 case 2: dwsiz = 31; dwmask = 0xffffffffU; break;
472 }
473
474 zero = (0 == (result & dwmask));
475 sign = 1 & (result >> dwsiz);
476 ahi = 1 & (r_1v >> dwsiz);
477 bhi = 1 & (rimmv >> dwsiz);
478 overflow = (sign != ahi) & (ahi == !bhi);
479 bit = (dwsiz + 1);
480 ra = r_1v & dwmask;
481 rb = rimmv & dwmask;
482 switch (al)
483 {
484 case 0x0: carry = 1 & ((ra + rb) >> bit); break;
485 case 0x2: carry = 1 & ((ra - rb) >> bit); break;
486 default: carry = 0; break;
487 }
488 above = (!carry & !zero);
489 greater = (sign == overflow) & !zero;
490 greatereq = (sign == overflow);
491
492 cpu->state.regs[r_d] = (
493 (above << 6) |
494 (greater << 5) |
495 (greatereq << 4) |
496 (sign << 3) |
497 (overflow << 2) |
498 (carry << 1) |
499 (zero << 0));
500 }
501 }
502 break;
503
504 case FT32_PAT_LDK:
505 cpu->state.regs[r_d] = k20;
506 break;
507
508 case FT32_PAT_LPM:
509 cpu->state.regs[r_d] = ft32_read_item (sd, dw, pa << 2);
510 cpu->state.cycles += 1;
511 break;
512
513 case FT32_PAT_LPMI:
3b4b0a62 514 cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k15);
f46e4eb7
JB		 515 cpu->state.cycles += 1;
516 break;
517
518 case FT32_PAT_STA:
519 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
520 break;
521
522 case FT32_PAT_STI:
3b4b0a62 523 cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k15, cpu->state.regs[r_1]);
f46e4eb7
JB		 524 break;
525
526 case FT32_PAT_LDA:
527 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, aa);
528 cpu->state.cycles += 1;
529 break;
530
531 case FT32_PAT_LDI:
3b4b0a62 532 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15);
f46e4eb7
JB		 533 cpu->state.cycles += 1;
534 break;
535
536 case FT32_PAT_EXA:
537 {
538 uint32_t tmp;
539 tmp = cpu_mem_read (sd, dw, aa);
540 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
541 cpu->state.regs[r_d] = tmp;
542 cpu->state.cycles += 1;
543 }
544 break;
545
546 case FT32_PAT_EXI:
547 {
548 uint32_t tmp;
3b4b0a62
JB		 549 tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15);
550 cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k15, cpu->state.regs[r_d]);
f46e4eb7
JB		 551 cpu->state.regs[r_d] = tmp;
552 cpu->state.cycles += 1;
553 }
554 break;
555
556 case FT32_PAT_PUSH:
557 ft32_push (sd, r_1v);
558 break;
559
560 case FT32_PAT_LINK:
561 ft32_push (sd, cpu->state.regs[r_d]);
562 cpu->state.regs[r_d] = cpu->state.regs[FT32_HARD_SP];
563 cpu->state.regs[FT32_HARD_SP] -= k16;
564 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
565 break;
566
567 case FT32_PAT_UNLINK:
568 cpu->state.regs[FT32_HARD_SP] = cpu->state.regs[r_d];
569 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
570 cpu->state.regs[r_d] = ft32_pop (sd);
571 break;
572
573 case FT32_PAT_POP:
574 cpu->state.cycles += 1;
575 cpu->state.regs[r_d] = ft32_pop (sd);
576 break;
577
578 case FT32_PAT_RETURN:
579 cpu->state.pc = ft32_pop (sd);
580 break;
581
582 case FT32_PAT_FFUOP:
583 switch (al)
584 {
585 case 0x0:
586 cpu->state.regs[r_d] = r_1v / rimmv;
587 break;
588 case 0x1:
589 cpu->state.regs[r_d] = r_1v % rimmv;
590 break;
591 case 0x2:
592 cpu->state.regs[r_d] = ft32sdiv (r_1v, rimmv);
593 break;
594 case 0x3:
595 cpu->state.regs[r_d] = ft32smod (r_1v, rimmv);
596 break;
597
598 case 0x4:
599 {
600 /* strcmp instruction. */
601 uint32_t a = r_1v;
602 uint32_t b = rimmv;
603 uint32_t i = 0;
604 while ((GET_BYTE (a + i) != 0) &&
605 (GET_BYTE (a + i) == GET_BYTE (b + i)))
606 i++;
607 cpu->state.regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i);
608 }
609 break;
610
611 case 0x5:
612 {
613 /* memcpy instruction. */
614 uint32_t src = r_1v;
615 uint32_t dst = cpu->state.regs[r_d];
616 uint32_t i;
395b0d8a 617 for (i = 0; i < (rimmv & 0x7fff); i++)
f46e4eb7
JB		 618 PUT_BYTE (dst + i, GET_BYTE (src + i));
619 }
620 break;
621 case 0x6:
622 {
623 /* strlen instruction. */
624 uint32_t src = r_1v;
625 uint32_t i;
626 for (i = 0; GET_BYTE (src + i) != 0; i++)
627 ;
628 cpu->state.regs[r_d] = i;
629 }
630 break;
631 case 0x7:
632 {
633 /* memset instruction. */
634 uint32_t dst = cpu->state.regs[r_d];
635 uint32_t i;
395b0d8a 636 for (i = 0; i < (rimmv & 0x7fff); i++)
f46e4eb7
JB		 637 PUT_BYTE (dst + i, r_1v);
638 }
639 break;
640 case 0x8:
641 cpu->state.regs[r_d] = r_1v * rimmv;
642 break;
643 case 0x9:
644 cpu->state.regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32;
645 break;
646 case 0xa:
647 {
648 /* stpcpy instruction. */
649 uint32_t src = r_1v;
650 uint32_t dst = cpu->state.regs[r_d];
651 uint32_t i;
652 for (i = 0; GET_BYTE (src + i) != 0; i++)
653 PUT_BYTE (dst + i, GET_BYTE (src + i));
654 PUT_BYTE (dst + i, 0);
655 cpu->state.regs[r_d] = dst + i;
656 }
657 break;
658 case 0xe:
659 {
660 /* streamout instruction. */
661 uint32_t i;
662 uint32_t src = cpu->state.regs[r_1];
663 for (i = 0; i < rimmv; i += (1 << dw))
664 {
665 cpu_mem_write (sd,
666 dw,
667 cpu->state.regs[r_d],
668 cpu_mem_read (sd, dw, src));
669 src += (1 << dw);
670 }
671 }
672 break;
673 default:
674 sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc);
675 ILLEGAL ();
676 }
677 break;
678
679 default:
680 sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc);
681 ILLEGAL ();
682 }
683 cpu->state.num_i++;
684
685escape:
686 ;
687}
688
689void
690sim_engine_run (SIM_DESC sd,
691 int next_cpu_nr, /* ignore */
692 int nr_cpus, /* ignore */
693 int siggnal) /* ignore */
694{
695 sim_cpu *cpu;
696
697 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
698
699 cpu = STATE_CPU (sd, 0);
700
701 while (1)
702 {
703 step_once (sd);
704 if (sim_events_tick (sd))
705 sim_events_process (sd);
706 }
707}
708
f46e4eb7
JB		 709static uint32_t *
710ft32_lookup_register (SIM_CPU *cpu, int nr)
711{
712 /* Handle the register number translation here.
713 * Sim registers are 0-31.
714 * Other tools (gcc, gdb) use:
715 * 0 - fp
716 * 1 - sp
717 * 2 - r0
718 * 31 - cc
719 */
720
721 if ((nr < 0) || (nr > 32))
722 {
723 sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr);
724 abort ();
725 }
726
727 switch (nr)
728 {
729 case FT32_FP_REGNUM:
730 return &cpu->state.regs[FT32_HARD_FP];
731 case FT32_SP_REGNUM:
732 return &cpu->state.regs[FT32_HARD_SP];
733 case FT32_CC_REGNUM:
734 return &cpu->state.regs[FT32_HARD_CC];
735 case FT32_PC_REGNUM:
736 return &cpu->state.pc;
737 default:
738 return &cpu->state.regs[nr - 2];
739 }
740}
741
742static int
743ft32_reg_store (SIM_CPU *cpu,
744 int rn,
745 unsigned char *memory,
746 int length)
747{
748 if (0 <= rn && rn <= 32)
749 {
750 if (length == 4)
751 *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4);
752
753 return 4;
754 }
755 else
756 return 0;
757}
758
759static int
760ft32_reg_fetch (SIM_CPU *cpu,
761 int rn,
762 unsigned char *memory,
763 int length)
764{
765 if (0 <= rn && rn <= 32)
766 {
767 if (length == 4)
768 ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn));
769
770 return 4;
771 }
772 else
773 return 0;
774}
775
776static sim_cia
777ft32_pc_get (SIM_CPU *cpu)
778{
65f90968 779 return cpu->state.pc;
f46e4eb7
JB		 780}
781
782static void
783ft32_pc_set (SIM_CPU *cpu, sim_cia newpc)
784{
785 cpu->state.pc = newpc;
786}
787
788/* Cover function of sim_state_free to free the cpu buffers as well. */
789
790static void
791free_state (SIM_DESC sd)
792{
793 if (STATE_MODULES (sd) != NULL)
794 sim_module_uninstall (sd);
795 sim_cpu_free_all (sd);
796 sim_state_free (sd);
797}
798
799SIM_DESC
800sim_open (SIM_OPEN_KIND kind,
801 host_callback *cb,
802 struct bfd *abfd,
2e3d4f4d 803 char * const *argv)
f46e4eb7
JB		 804{
805 char c;
806 size_t i;
807 SIM_DESC sd = sim_state_alloc (kind, cb);
808
809 /* The cpu data is kept in a separately allocated chunk of memory. */
d5a71b11 810 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
f46e4eb7
JB		 811 {
812 free_state (sd);
813 return 0;
814 }
815
816 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
817 {
818 free_state (sd);
819 return 0;
820 }
821
77cf2ef5 822 /* The parser will print an error message for us, so we silently return. */
f46e4eb7
JB		 823 if (sim_parse_args (sd, argv) != SIM_RC_OK)
824 {
825 free_state (sd);
826 return 0;
827 }
828
829 /* Allocate external memory if none specified by user.
830 Use address 4 here in case the user wanted address 0 unmapped. */
831 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
832 {
833 sim_do_command (sd, "memory region 0x00000000,0x40000");
834 sim_do_command (sd, "memory region 0x800000,0x10000");
835 }
836
837 /* Check for/establish the reference program image. */
838 if (sim_analyze_program (sd,
839 (STATE_PROG_ARGV (sd) != NULL
840 ? *STATE_PROG_ARGV (sd)
841 : NULL), abfd) != SIM_RC_OK)
842 {
843 free_state (sd);
844 return 0;
845 }
846
847 /* Configure/verify the target byte order and other runtime
848 configuration options. */
849 if (sim_config (sd) != SIM_RC_OK)
850 {
851 free_state (sd);
852 return 0;
853 }
854
855 if (sim_post_argv_init (sd) != SIM_RC_OK)
856 {
857 free_state (sd);
858 return 0;
859 }
860
861 /* CPU specific initialization. */
862 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
863 {
864 SIM_CPU *cpu = STATE_CPU (sd, i);
865
866 CPU_REG_FETCH (cpu) = ft32_reg_fetch;
867 CPU_REG_STORE (cpu) = ft32_reg_store;
868 CPU_PC_FETCH (cpu) = ft32_pc_get;
869 CPU_PC_STORE (cpu) = ft32_pc_set;
870 }
871
872 return sd;
873}
874
f46e4eb7
JB		 875SIM_RC
876sim_create_inferior (SIM_DESC sd,
877 struct bfd *abfd,
2e3d4f4d
MF		 878 char * const *argv,
879 char * const *env)
f46e4eb7
JB		 880{
881 uint32_t addr;
882 sim_cpu *cpu = STATE_CPU (sd, 0);
883
884 /* Set the PC. */
885 if (abfd != NULL)
886 addr = bfd_get_start_address (abfd);
887 else
888 addr = 0;
889
0e967299
MF		 890 /* Standalone mode (i.e. `run`) will take care of the argv for us in
891 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
892 with `gdb`), we need to handle it because the user can change the
893 argv on the fly via gdb's 'run'. */
894 if (STATE_PROG_ARGV (sd) != argv)
f46e4eb7
JB		 895 {
896 freeargv (STATE_PROG_ARGV (sd));
897 STATE_PROG_ARGV (sd) = dupargv (argv);
898 }
899 cpu->state.regs[FT32_HARD_SP] = addr;
900 cpu->state.num_i = 0;
901 cpu->state.cycles = 0;
902 cpu->state.next_tick_cycle = 100000;
903
904 return SIM_RC_OK;
905}
A mirror of the official binutils-gdb repository