]>
Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
18 | */ | |
19 | ||
20 | #include "config.h" | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <signal.h> | |
24 | #ifdef HAVE_TIME_H | |
25 | #include <time.h> | |
26 | #endif | |
27 | #ifdef HAVE_STDLIB_H | |
28 | #include <stdlib.h> | |
29 | #endif | |
30 | #ifdef HAVE_SYS_PARAM_H | |
31 | #include <sys/param.h> | |
32 | #endif | |
c906108c SS |
33 | #include "ansidecl.h" |
34 | #include "bfd.h" | |
35 | #include "callback.h" | |
36 | #include "remote-sim.h" | |
37 | ||
38 | #ifndef SIGTRAP | |
39 | # define SIGTRAP 5 | |
40 | #endif | |
41 | ||
42 | int debug; | |
43 | ||
44 | host_callback *sim_callback; | |
45 | ||
46 | static SIM_OPEN_KIND sim_kind; | |
47 | static char *myname; | |
48 | ||
49 | /* FIXME: Needs to live in header file. | |
50 | This header should also include the things in remote-sim.h. | |
51 | One could move this to remote-sim.h but this function isn't needed | |
52 | by gdb. */ | |
53 | void sim_set_simcache_size PARAMS ((int)); | |
54 | ||
55 | #define X(op, size) op*4+size | |
56 | ||
57 | #define SP (h8300hmode ? SL:SW) | |
58 | #define SB 0 | |
59 | #define SW 1 | |
60 | #define SL 2 | |
61 | #define OP_REG 1 | |
62 | #define OP_DEC 2 | |
63 | #define OP_DISP 3 | |
64 | #define OP_INC 4 | |
65 | #define OP_PCREL 5 | |
66 | #define OP_MEM 6 | |
67 | #define OP_CCR 7 | |
68 | #define OP_IMM 8 | |
69 | #define OP_ABS 10 | |
70 | #define h8_opcodes ops | |
71 | #define DEFINE_TABLE | |
72 | #include "opcode/h8300.h" | |
73 | ||
74 | #include "inst.h" | |
75 | ||
0ef9643e | 76 | /* The rate at which to call the host's poll_quit callback. */ |
7a292a7a SS |
77 | |
78 | #define POLL_QUIT_INTERVAL 0x80000 | |
79 | ||
c906108c SS |
80 | #define LOW_BYTE(x) ((x) & 0xff) |
81 | #define HIGH_BYTE(x) (((x)>>8) & 0xff) | |
82 | #define P(X,Y) ((X<<8) | Y) | |
83 | ||
84 | #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; | |
85 | ||
86 | #define GETSR() \ | |
87 | c = (cpu.ccr >> 0) & 1;\ | |
88 | v = (cpu.ccr >> 1) & 1;\ | |
89 | nz = !((cpu.ccr >> 2) & 1);\ | |
90 | n = (cpu.ccr >> 3) & 1; | |
91 | ||
92 | #ifdef __CHAR_IS_SIGNED__ | |
93 | #define SEXTCHAR(x) ((char)(x)) | |
94 | #endif | |
95 | ||
96 | #ifndef SEXTCHAR | |
97 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff) | |
98 | #endif | |
99 | ||
100 | #define UEXTCHAR(x) ((x) & 0xff) | |
101 | #define UEXTSHORT(x) ((x) & 0xffff) | |
102 | #define SEXTSHORT(x) ((short)(x)) | |
103 | ||
104 | static cpu_state_type cpu; | |
105 | ||
106 | int h8300hmode = 0; | |
107 | int h8300smode = 0; | |
108 | ||
109 | static int memory_size; | |
110 | ||
c906108c SS |
111 | static int |
112 | get_now () | |
113 | { | |
114 | #ifndef WIN32 | |
115 | return time (0); | |
116 | #endif | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static int | |
121 | now_persec () | |
122 | { | |
123 | return 1; | |
124 | } | |
125 | ||
c906108c SS |
126 | static int |
127 | bitfrom (x) | |
128 | { | |
129 | switch (x & SIZE) | |
130 | { | |
131 | case L_8: | |
132 | return SB; | |
133 | case L_16: | |
134 | return SW; | |
135 | case L_32: | |
136 | return SL; | |
137 | case L_P: | |
138 | return h8300hmode ? SL : SW; | |
139 | } | |
140 | } | |
141 | ||
0ef9643e | 142 | static unsigned int |
c906108c SS |
143 | lvalue (x, rn) |
144 | { | |
145 | switch (x / 4) | |
146 | { | |
147 | case OP_DISP: | |
148 | if (rn == 8) | |
149 | { | |
150 | return X (OP_IMM, SP); | |
151 | } | |
152 | return X (OP_REG, SP); | |
153 | ||
154 | case OP_MEM: | |
c906108c | 155 | return X (OP_MEM, SP); |
0ef9643e | 156 | |
c906108c SS |
157 | default: |
158 | abort (); | |
159 | } | |
160 | } | |
161 | ||
162 | static unsigned int | |
163 | decode (addr, data, dst) | |
164 | int addr; | |
165 | unsigned char *data; | |
166 | decoded_inst *dst; | |
167 | ||
168 | { | |
169 | int rs = 0; | |
170 | int rd = 0; | |
171 | int rdisp = 0; | |
172 | int abs = 0; | |
c906108c | 173 | int bit = 0; |
0ef9643e | 174 | int plen = 0; |
6d028502 | 175 | struct h8_opcode *q; |
c906108c | 176 | int size = 0; |
0ef9643e | 177 | |
c906108c SS |
178 | dst->dst.type = -1; |
179 | dst->src.type = -1; | |
0ef9643e JL |
180 | |
181 | /* Find the exact opcode/arg combo. */ | |
6d028502 | 182 | for (q = h8_opcodes; q->name; q++) |
c906108c | 183 | { |
6d028502 | 184 | op_type *nib = q->data.nib; |
c906108c SS |
185 | unsigned int len = 0; |
186 | ||
c906108c SS |
187 | while (1) |
188 | { | |
189 | op_type looking_for = *nib; | |
190 | int thisnib = data[len >> 1]; | |
191 | ||
192 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
193 | ||
194 | if (looking_for < 16 && looking_for >= 0) | |
195 | { | |
196 | if (looking_for != thisnib) | |
197 | goto fail; | |
198 | } | |
199 | else | |
200 | { | |
201 | if ((int) looking_for & (int) B31) | |
202 | { | |
203 | if (!(((int) thisnib & 0x8) != 0)) | |
204 | goto fail; | |
0ef9643e JL |
205 | |
206 | looking_for = (op_type) ((int) looking_for & ~(int) B31); | |
c906108c SS |
207 | thisnib &= 0x7; |
208 | } | |
0ef9643e | 209 | |
c906108c SS |
210 | if ((int) looking_for & (int) B30) |
211 | { | |
212 | if (!(((int) thisnib & 0x8) == 0)) | |
213 | goto fail; | |
0ef9643e | 214 | |
c906108c SS |
215 | looking_for = (op_type) ((int) looking_for & ~(int) B30); |
216 | } | |
0ef9643e | 217 | |
c906108c SS |
218 | if (looking_for & DBIT) |
219 | { | |
0a17cd59 AC |
220 | /* Exclude adds/subs by looking at bit 0 and 2, and |
221 | make sure the operand size, either w or l, | |
222 | matches by looking at bit 1. */ | |
223 | if ((looking_for & 7) != (thisnib & 7)) | |
c906108c | 224 | goto fail; |
0ef9643e | 225 | |
c906108c SS |
226 | abs = (thisnib & 0x8) ? 2 : 1; |
227 | } | |
228 | else if (looking_for & (REG | IND | INC | DEC)) | |
229 | { | |
230 | if (looking_for & REG) | |
231 | { | |
0ef9643e | 232 | /* Can work out size from the register. */ |
c906108c SS |
233 | size = bitfrom (looking_for); |
234 | } | |
235 | if (looking_for & SRC) | |
0ef9643e | 236 | rs = thisnib; |
c906108c | 237 | else |
0ef9643e | 238 | rd = thisnib; |
c906108c SS |
239 | } |
240 | else if (looking_for & L_16) | |
241 | { | |
242 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
243 | plen = 16; | |
244 | if (looking_for & (PCREL | DISP)) | |
245 | { | |
246 | abs = (short) (abs); | |
247 | } | |
248 | } | |
249 | else if (looking_for & ABSJMP) | |
250 | { | |
0ef9643e | 251 | abs = (data[1] << 16) | (data[2] << 8) | (data[3]); |
c906108c SS |
252 | } |
253 | else if (looking_for & MEMIND) | |
254 | { | |
255 | abs = data[1]; | |
256 | } | |
257 | else if (looking_for & L_32) | |
258 | { | |
259 | int i = len >> 1; | |
0ef9643e | 260 | |
c906108c SS |
261 | abs = (data[i] << 24) |
262 | | (data[i + 1] << 16) | |
263 | | (data[i + 2] << 8) | |
264 | | (data[i + 3]); | |
265 | ||
266 | plen = 32; | |
267 | } | |
268 | else if (looking_for & L_24) | |
269 | { | |
270 | int i = len >> 1; | |
0ef9643e | 271 | |
c906108c SS |
272 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
273 | plen = 24; | |
274 | } | |
275 | else if (looking_for & IGNORE) | |
276 | { | |
0ef9643e | 277 | ; |
c906108c SS |
278 | } |
279 | else if (looking_for & DISPREG) | |
280 | { | |
281 | rdisp = thisnib & 0x7; | |
282 | } | |
283 | else if (looking_for & KBIT) | |
284 | { | |
285 | switch (thisnib) | |
286 | { | |
287 | case 9: | |
288 | abs = 4; | |
289 | break; | |
290 | case 8: | |
291 | abs = 2; | |
292 | break; | |
293 | case 0: | |
294 | abs = 1; | |
295 | break; | |
0a17cd59 AC |
296 | default: |
297 | goto fail; | |
c906108c SS |
298 | } |
299 | } | |
300 | else if (looking_for & L_8) | |
301 | { | |
302 | plen = 8; | |
303 | ||
304 | if (looking_for & PCREL) | |
305 | { | |
306 | abs = SEXTCHAR (data[len >> 1]); | |
307 | } | |
308 | else if (looking_for & ABS8MEM) | |
309 | { | |
310 | plen = 8; | |
311 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
0ef9643e | 312 | abs |= data[len >> 1] & 0xff; |
c906108c | 313 | } |
0ef9643e | 314 | else |
c906108c SS |
315 | { |
316 | abs = data[len >> 1] & 0xff; | |
317 | } | |
318 | } | |
319 | else if (looking_for & L_3) | |
320 | { | |
321 | plen = 3; | |
322 | ||
323 | bit = thisnib; | |
324 | } | |
325 | else if (looking_for == E) | |
326 | { | |
327 | dst->op = q; | |
328 | ||
0ef9643e | 329 | /* Fill in the args. */ |
c906108c SS |
330 | { |
331 | op_type *args = q->args.nib; | |
332 | int hadone = 0; | |
333 | ||
334 | while (*args != E) | |
335 | { | |
336 | int x = *args; | |
337 | int rn = (x & DST) ? rd : rs; | |
338 | ea_type *p; | |
339 | ||
340 | if (x & DST) | |
0ef9643e | 341 | p = &(dst->dst); |
c906108c | 342 | else |
0ef9643e | 343 | p = &(dst->src); |
c906108c | 344 | |
0ef9643e | 345 | if (x & L_3) |
c906108c SS |
346 | { |
347 | p->type = X (OP_IMM, size); | |
348 | p->literal = bit; | |
349 | } | |
350 | else if (x & (IMM | KBIT | DBIT)) | |
351 | { | |
352 | p->type = X (OP_IMM, size); | |
353 | p->literal = abs; | |
354 | } | |
355 | else if (x & REG) | |
356 | { | |
6d028502 KH |
357 | /* Reset the size. |
358 | Some ops (like mul) have two sizes. */ | |
c906108c SS |
359 | |
360 | size = bitfrom (x); | |
361 | p->type = X (OP_REG, size); | |
362 | p->reg = rn; | |
363 | } | |
364 | else if (x & INC) | |
365 | { | |
366 | p->type = X (OP_INC, size); | |
367 | p->reg = rn & 0x7; | |
368 | } | |
369 | else if (x & DEC) | |
370 | { | |
371 | p->type = X (OP_DEC, size); | |
372 | p->reg = rn & 0x7; | |
373 | } | |
374 | else if (x & IND) | |
375 | { | |
376 | p->type = X (OP_DISP, size); | |
377 | p->reg = rn & 0x7; | |
378 | p->literal = 0; | |
379 | } | |
380 | else if (x & (ABS | ABSJMP | ABS8MEM)) | |
381 | { | |
382 | p->type = X (OP_DISP, size); | |
383 | p->literal = abs; | |
384 | p->reg = 8; | |
385 | } | |
386 | else if (x & MEMIND) | |
387 | { | |
388 | p->type = X (OP_MEM, size); | |
389 | p->literal = abs; | |
390 | } | |
391 | else if (x & PCREL) | |
392 | { | |
393 | p->type = X (OP_PCREL, size); | |
394 | p->literal = abs + addr + 2; | |
395 | if (x & L_16) | |
396 | p->literal += 2; | |
397 | } | |
398 | else if (x & ABSJMP) | |
399 | { | |
400 | p->type = X (OP_IMM, SP); | |
401 | p->literal = abs; | |
402 | } | |
403 | else if (x & DISP) | |
404 | { | |
405 | p->type = X (OP_DISP, size); | |
406 | p->literal = abs; | |
407 | p->reg = rdisp & 0x7; | |
408 | } | |
409 | else if (x & CCR) | |
410 | { | |
411 | p->type = OP_CCR; | |
412 | } | |
413 | else | |
414 | printf ("Hmmmm %x", x); | |
415 | ||
416 | args++; | |
417 | } | |
418 | } | |
419 | ||
0ef9643e JL |
420 | /* But a jmp or a jsr gets automagically lvalued, |
421 | since we branch to their address not their | |
422 | contents. */ | |
c906108c SS |
423 | if (q->how == O (O_JSR, SB) |
424 | || q->how == O (O_JMP, SB)) | |
425 | { | |
426 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
427 | } | |
428 | ||
429 | if (dst->dst.type == -1) | |
430 | dst->dst = dst->src; | |
431 | ||
432 | dst->opcode = q->how; | |
433 | dst->cycles = q->time; | |
434 | ||
0ef9643e | 435 | /* And a jsr to 0xc4 is turned into a magic trap. */ |
c906108c SS |
436 | |
437 | if (dst->opcode == O (O_JSR, SB)) | |
438 | { | |
439 | if (dst->src.literal == 0xc4) | |
440 | { | |
441 | dst->opcode = O (O_SYSCALL, SB); | |
442 | } | |
443 | } | |
444 | ||
445 | dst->next_pc = addr + len / 2; | |
446 | return; | |
447 | } | |
448 | else | |
98ecb0a7 | 449 | printf ("Don't understand %x \n", looking_for); |
c906108c SS |
450 | } |
451 | ||
452 | len++; | |
453 | nib++; | |
454 | } | |
455 | ||
456 | fail: | |
6d028502 | 457 | ; |
c906108c SS |
458 | } |
459 | ||
0ef9643e | 460 | /* Fell off the end. */ |
c906108c SS |
461 | dst->opcode = O (O_ILL, SB); |
462 | } | |
463 | ||
c906108c SS |
464 | static void |
465 | compile (pc) | |
466 | { | |
467 | int idx; | |
468 | ||
469 | /* find the next cache entry to use */ | |
470 | ||
471 | idx = cpu.cache_top + 1; | |
472 | cpu.compiles++; | |
473 | if (idx >= cpu.csize) | |
474 | { | |
475 | idx = 1; | |
476 | } | |
477 | cpu.cache_top = idx; | |
478 | ||
479 | /* Throw away its old meaning */ | |
480 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; | |
481 | ||
482 | /* set to new address */ | |
483 | cpu.cache[idx].oldpc = pc; | |
484 | ||
485 | /* fill in instruction info */ | |
486 | decode (pc, cpu.memory + pc, cpu.cache + idx); | |
487 | ||
488 | /* point to new cache entry */ | |
489 | cpu.cache_idx[pc] = idx; | |
490 | } | |
491 | ||
492 | ||
493 | static unsigned char *breg[18]; | |
494 | static unsigned short *wreg[18]; | |
495 | static unsigned int *lreg[18]; | |
496 | ||
497 | #define GET_B_REG(x) *(breg[x]) | |
498 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
499 | #define GET_W_REG(x) *(wreg[x]) | |
500 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
501 | ||
502 | #define GET_L_REG(x) *(lreg[x]) | |
503 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
504 | ||
505 | #define GET_MEMORY_L(x) \ | |
506 | (x < memory_size \ | |
507 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
508 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
509 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
510 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
511 | ||
512 | #define GET_MEMORY_W(x) \ | |
513 | (x < memory_size \ | |
514 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
515 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
516 | ||
517 | ||
518 | #define GET_MEMORY_B(x) \ | |
519 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
520 | ||
521 | #define SET_MEMORY_L(x,y) \ | |
522 | { register unsigned char *_p; register int __y = y; \ | |
523 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
524 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
525 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
526 | ||
527 | #define SET_MEMORY_W(x,y) \ | |
528 | { register unsigned char *_p; register int __y = y; \ | |
529 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
530 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
531 | ||
532 | #define SET_MEMORY_B(x,y) \ | |
533 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
534 | ||
535 | int | |
536 | fetch (arg, n) | |
537 | ea_type *arg; | |
538 | { | |
539 | int rn = arg->reg; | |
540 | int abs = arg->literal; | |
541 | int r; | |
542 | int t; | |
543 | ||
544 | switch (arg->type) | |
545 | { | |
546 | case X (OP_REG, SB): | |
547 | return GET_B_REG (rn); | |
548 | case X (OP_REG, SW): | |
549 | return GET_W_REG (rn); | |
550 | case X (OP_REG, SL): | |
551 | return GET_L_REG (rn); | |
552 | case X (OP_IMM, SB): | |
553 | case X (OP_IMM, SW): | |
554 | case X (OP_IMM, SL): | |
555 | return abs; | |
556 | case X (OP_DEC, SB): | |
557 | abort (); | |
558 | ||
559 | case X (OP_INC, SB): | |
560 | t = GET_L_REG (rn); | |
561 | t &= cpu.mask; | |
562 | r = GET_MEMORY_B (t); | |
563 | t++; | |
564 | t = t & cpu.mask; | |
565 | SET_L_REG (rn, t); | |
566 | return r; | |
567 | break; | |
568 | case X (OP_INC, SW): | |
569 | t = GET_L_REG (rn); | |
570 | t &= cpu.mask; | |
571 | r = GET_MEMORY_W (t); | |
572 | t += 2; | |
573 | t = t & cpu.mask; | |
574 | SET_L_REG (rn, t); | |
575 | return r; | |
576 | case X (OP_INC, SL): | |
577 | t = GET_L_REG (rn); | |
578 | t &= cpu.mask; | |
579 | r = GET_MEMORY_L (t); | |
580 | ||
581 | t += 4; | |
582 | t = t & cpu.mask; | |
583 | SET_L_REG (rn, t); | |
584 | return r; | |
585 | ||
586 | case X (OP_DISP, SB): | |
587 | t = GET_L_REG (rn) + abs; | |
588 | t &= cpu.mask; | |
589 | return GET_MEMORY_B (t); | |
590 | ||
591 | case X (OP_DISP, SW): | |
592 | t = GET_L_REG (rn) + abs; | |
593 | t &= cpu.mask; | |
594 | return GET_MEMORY_W (t); | |
595 | ||
596 | case X (OP_DISP, SL): | |
597 | t = GET_L_REG (rn) + abs; | |
598 | t &= cpu.mask; | |
599 | return GET_MEMORY_L (t); | |
600 | ||
601 | case X (OP_MEM, SL): | |
602 | t = GET_MEMORY_L (abs); | |
603 | t &= cpu.mask; | |
604 | return t; | |
605 | ||
606 | case X (OP_MEM, SW): | |
607 | t = GET_MEMORY_W (abs); | |
608 | t &= cpu.mask; | |
609 | return t; | |
610 | ||
611 | default: | |
612 | abort (); | |
613 | ||
614 | } | |
615 | } | |
616 | ||
617 | ||
618 | static | |
619 | void | |
620 | store (arg, n) | |
621 | ea_type *arg; | |
622 | int n; | |
623 | { | |
624 | int rn = arg->reg; | |
625 | int abs = arg->literal; | |
626 | int t; | |
627 | ||
628 | switch (arg->type) | |
629 | { | |
630 | case X (OP_REG, SB): | |
631 | SET_B_REG (rn, n); | |
632 | break; | |
633 | case X (OP_REG, SW): | |
634 | SET_W_REG (rn, n); | |
635 | break; | |
636 | case X (OP_REG, SL): | |
637 | SET_L_REG (rn, n); | |
638 | break; | |
639 | ||
640 | case X (OP_DEC, SB): | |
641 | t = GET_L_REG (rn) - 1; | |
642 | t &= cpu.mask; | |
643 | SET_L_REG (rn, t); | |
644 | SET_MEMORY_B (t, n); | |
645 | ||
646 | break; | |
647 | case X (OP_DEC, SW): | |
648 | t = (GET_L_REG (rn) - 2) & cpu.mask; | |
649 | SET_L_REG (rn, t); | |
650 | SET_MEMORY_W (t, n); | |
651 | break; | |
652 | ||
653 | case X (OP_DEC, SL): | |
654 | t = (GET_L_REG (rn) - 4) & cpu.mask; | |
655 | SET_L_REG (rn, t); | |
656 | SET_MEMORY_L (t, n); | |
657 | break; | |
658 | ||
659 | case X (OP_DISP, SB): | |
660 | t = GET_L_REG (rn) + abs; | |
661 | t &= cpu.mask; | |
662 | SET_MEMORY_B (t, n); | |
663 | break; | |
664 | ||
665 | case X (OP_DISP, SW): | |
666 | t = GET_L_REG (rn) + abs; | |
667 | t &= cpu.mask; | |
668 | SET_MEMORY_W (t, n); | |
669 | break; | |
670 | ||
671 | case X (OP_DISP, SL): | |
672 | t = GET_L_REG (rn) + abs; | |
673 | t &= cpu.mask; | |
674 | SET_MEMORY_L (t, n); | |
675 | break; | |
676 | default: | |
677 | abort (); | |
678 | } | |
679 | } | |
680 | ||
681 | ||
682 | static union | |
683 | { | |
684 | short int i; | |
685 | struct | |
686 | { | |
687 | char low; | |
688 | char high; | |
689 | } | |
690 | u; | |
691 | } | |
692 | ||
693 | littleendian; | |
694 | ||
695 | static | |
696 | void | |
697 | init_pointers () | |
698 | { | |
699 | static int init; | |
700 | ||
701 | if (!init) | |
702 | { | |
703 | int i; | |
704 | ||
705 | init = 1; | |
706 | littleendian.i = 1; | |
707 | ||
708 | if (h8300hmode) | |
709 | memory_size = H8300H_MSIZE; | |
710 | else | |
711 | memory_size = H8300_MSIZE; | |
712 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
713 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
714 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
715 | ||
716 | /* `msize' must be a power of two */ | |
717 | if ((memory_size & (memory_size - 1)) != 0) | |
718 | abort (); | |
719 | cpu.mask = memory_size - 1; | |
720 | ||
721 | for (i = 0; i < 9; i++) | |
722 | { | |
723 | cpu.regs[i] = 0; | |
724 | } | |
725 | ||
726 | for (i = 0; i < 8; i++) | |
727 | { | |
728 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
729 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
730 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
731 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
732 | cpu.regs[i] = 0x00112233; | |
733 | while (p < e) | |
734 | { | |
735 | if (*p == 0x22) | |
736 | { | |
737 | breg[i] = p; | |
738 | } | |
739 | if (*p == 0x33) | |
740 | { | |
741 | breg[i + 8] = p; | |
742 | } | |
743 | p++; | |
744 | } | |
745 | while (q < u) | |
746 | { | |
747 | if (*q == 0x2233) | |
748 | { | |
749 | wreg[i] = q; | |
750 | } | |
751 | if (*q == 0x0011) | |
752 | { | |
753 | wreg[i + 8] = q; | |
754 | } | |
755 | q++; | |
756 | } | |
757 | cpu.regs[i] = 0; | |
758 | lreg[i] = &cpu.regs[i]; | |
759 | } | |
760 | ||
761 | lreg[8] = &cpu.regs[8]; | |
762 | ||
763 | /* initialize the seg registers */ | |
764 | if (!cpu.cache) | |
765 | sim_set_simcache_size (CSIZE); | |
766 | } | |
767 | } | |
768 | ||
769 | static void | |
770 | control_c (sig, code, scp, addr) | |
771 | int sig; | |
772 | int code; | |
773 | char *scp; | |
774 | char *addr; | |
775 | { | |
776 | cpu.state = SIM_STATE_STOPPED; | |
777 | cpu.exception = SIGINT; | |
778 | } | |
779 | ||
780 | #define C (c != 0) | |
781 | #define Z (nz == 0) | |
782 | #define V (v != 0) | |
783 | #define N (n != 0) | |
784 | ||
785 | static int | |
786 | mop (code, bsize, sign) | |
787 | decoded_inst *code; | |
788 | int bsize; | |
789 | int sign; | |
790 | { | |
791 | int multiplier; | |
792 | int multiplicand; | |
793 | int result; | |
794 | int n, nz; | |
795 | ||
796 | if (sign) | |
797 | { | |
798 | multiplicand = | |
799 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
800 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
801 | multiplier = | |
802 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
803 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
804 | } | |
805 | else | |
806 | { | |
807 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
808 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
809 | multiplier = | |
810 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
811 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
812 | ||
813 | } | |
814 | result = multiplier * multiplicand; | |
815 | ||
816 | if (sign) | |
817 | { | |
818 | n = result & (bsize ? 0x8000 : 0x80000000); | |
819 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
820 | } | |
821 | if (bsize) | |
822 | { | |
823 | SET_W_REG (code->dst.reg, result); | |
824 | } | |
825 | else | |
826 | { | |
827 | SET_L_REG (code->dst.reg, result); | |
828 | } | |
829 | /* return ((n==1) << 1) | (nz==1); */ | |
830 | ||
831 | } | |
832 | ||
833 | #define ONOT(name, how) \ | |
834 | case O(name, SB): \ | |
835 | { \ | |
836 | int t; \ | |
837 | int hm = 0x80; \ | |
838 | rd = GET_B_REG (code->src.reg); \ | |
839 | how; \ | |
840 | goto shift8; \ | |
841 | } \ | |
842 | case O(name, SW): \ | |
843 | { \ | |
844 | int t; \ | |
845 | int hm = 0x8000; \ | |
846 | rd = GET_W_REG (code->src.reg); \ | |
847 | how; \ | |
848 | goto shift16; \ | |
849 | } \ | |
850 | case O(name, SL): \ | |
851 | { \ | |
852 | int t; \ | |
853 | int hm = 0x80000000; \ | |
854 | rd = GET_L_REG (code->src.reg); \ | |
855 | how; \ | |
856 | goto shift32; \ | |
857 | } | |
858 | ||
859 | #define OSHIFTS(name, how1, how2) \ | |
860 | case O(name, SB): \ | |
861 | { \ | |
862 | int t; \ | |
863 | int hm = 0x80; \ | |
864 | rd = GET_B_REG (code->src.reg); \ | |
865 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
866 | { \ | |
867 | how1; \ | |
868 | } \ | |
869 | else \ | |
870 | { \ | |
871 | how2; \ | |
872 | } \ | |
873 | goto shift8; \ | |
874 | } \ | |
875 | case O(name, SW): \ | |
876 | { \ | |
877 | int t; \ | |
878 | int hm = 0x8000; \ | |
879 | rd = GET_W_REG (code->src.reg); \ | |
880 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
881 | { \ | |
882 | how1; \ | |
883 | } \ | |
884 | else \ | |
885 | { \ | |
886 | how2; \ | |
887 | } \ | |
888 | goto shift16; \ | |
889 | } \ | |
890 | case O(name, SL): \ | |
891 | { \ | |
892 | int t; \ | |
893 | int hm = 0x80000000; \ | |
894 | rd = GET_L_REG (code->src.reg); \ | |
895 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
896 | { \ | |
897 | how1; \ | |
898 | } \ | |
899 | else \ | |
900 | { \ | |
901 | how2; \ | |
902 | } \ | |
903 | goto shift32; \ | |
904 | } | |
905 | ||
906 | #define OBITOP(name,f, s, op) \ | |
907 | case O(name, SB): \ | |
908 | { \ | |
909 | int m; \ | |
910 | int b; \ | |
911 | if (f) ea = fetch (&code->dst); \ | |
912 | m=1<< fetch(&code->src); \ | |
913 | op; \ | |
914 | if(s) store (&code->dst,ea); goto next; \ | |
915 | } | |
916 | ||
917 | int | |
918 | sim_stop (sd) | |
919 | SIM_DESC sd; | |
920 | { | |
921 | cpu.state = SIM_STATE_STOPPED; | |
922 | cpu.exception = SIGINT; | |
923 | return 1; | |
924 | } | |
925 | ||
926 | void | |
927 | sim_resume (sd, step, siggnal) | |
928 | SIM_DESC sd; | |
929 | { | |
930 | static int init1; | |
931 | int cycles = 0; | |
932 | int insts = 0; | |
933 | int tick_start = get_now (); | |
934 | void (*prev) (); | |
935 | int poll_count = 0; | |
936 | int res; | |
937 | int tmp; | |
938 | int rd; | |
939 | int ea; | |
940 | int bit; | |
941 | int pc; | |
942 | int c, nz, v, n; | |
943 | int oldmask; | |
944 | init_pointers (); | |
945 | ||
946 | prev = signal (SIGINT, control_c); | |
947 | ||
948 | if (step) | |
949 | { | |
950 | cpu.state = SIM_STATE_STOPPED; | |
951 | cpu.exception = SIGTRAP; | |
952 | } | |
953 | else | |
954 | { | |
955 | cpu.state = SIM_STATE_RUNNING; | |
956 | cpu.exception = 0; | |
957 | } | |
958 | ||
959 | pc = cpu.pc; | |
960 | ||
961 | /* The PC should never be odd. */ | |
962 | if (pc & 0x1) | |
963 | abort (); | |
964 | ||
965 | GETSR (); | |
966 | oldmask = cpu.mask; | |
967 | if (!h8300hmode) | |
968 | cpu.mask = 0xffff; | |
969 | do | |
970 | { | |
971 | int cidx; | |
972 | decoded_inst *code; | |
973 | ||
974 | top: | |
975 | cidx = cpu.cache_idx[pc]; | |
976 | code = cpu.cache + cidx; | |
977 | ||
978 | ||
979 | #define ALUOP(STORE, NAME, HOW) \ | |
980 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
981 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
982 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
983 | ||
984 | ||
985 | #define LOGOP(NAME, HOW) \ | |
986 | case O(NAME,SB): HOW; goto log8;\ | |
987 | case O(NAME, SW): HOW; goto log16;\ | |
988 | case O(NAME,SL): HOW; goto log32; | |
989 | ||
990 | ||
991 | ||
992 | #if ADEBUG | |
993 | if (debug) | |
994 | { | |
995 | printf ("%x %d %s\n", pc, code->opcode, | |
996 | code->op ? code->op->name : "**"); | |
997 | } | |
998 | cpu.stats[code->opcode]++; | |
999 | ||
1000 | #endif | |
1001 | ||
1002 | cycles += code->cycles; | |
1003 | insts++; | |
1004 | switch (code->opcode) | |
1005 | { | |
1006 | case 0: | |
1007 | /* | |
1008 | * This opcode is a fake for when we get to an | |
1009 | * instruction which hasnt been compiled | |
1010 | */ | |
1011 | compile (pc); | |
1012 | goto top; | |
1013 | break; | |
1014 | ||
1015 | ||
1016 | case O (O_SUBX, SB): | |
1017 | rd = fetch (&code->dst); | |
1018 | ea = fetch (&code->src); | |
1019 | ea = -(ea + C); | |
1020 | res = rd + ea; | |
1021 | goto alu8; | |
1022 | ||
1023 | case O (O_ADDX, SB): | |
1024 | rd = fetch (&code->dst); | |
1025 | ea = fetch (&code->src); | |
1026 | ea = C + ea; | |
1027 | res = rd + ea; | |
1028 | goto alu8; | |
1029 | ||
1030 | #define EA ea = fetch(&code->src); | |
1031 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
1032 | ||
1033 | ALUOP (1, O_SUB, RD_EA; | |
1034 | ea = -ea; | |
1035 | res = rd + ea); | |
1036 | ALUOP (1, O_NEG, EA; | |
1037 | ea = -ea; | |
1038 | rd = 0; | |
1039 | res = rd + ea); | |
1040 | ||
1041 | case O (O_ADD, SB): | |
1042 | rd = GET_B_REG (code->dst.reg); | |
1043 | ea = fetch (&code->src); | |
1044 | res = rd + ea; | |
1045 | goto alu8; | |
1046 | case O (O_ADD, SW): | |
1047 | rd = GET_W_REG (code->dst.reg); | |
1048 | ea = fetch (&code->src); | |
1049 | res = rd + ea; | |
1050 | goto alu16; | |
1051 | case O (O_ADD, SL): | |
1052 | rd = GET_L_REG (code->dst.reg); | |
1053 | ea = fetch (&code->src); | |
1054 | res = rd + ea; | |
1055 | goto alu32; | |
1056 | ||
1057 | ||
1058 | LOGOP (O_AND, RD_EA; | |
1059 | res = rd & ea); | |
1060 | ||
1061 | LOGOP (O_OR, RD_EA; | |
1062 | res = rd | ea); | |
1063 | ||
1064 | LOGOP (O_XOR, RD_EA; | |
1065 | res = rd ^ ea); | |
1066 | ||
1067 | ||
1068 | case O (O_MOV_TO_MEM, SB): | |
1069 | res = GET_B_REG (code->src.reg); | |
1070 | goto log8; | |
1071 | case O (O_MOV_TO_MEM, SW): | |
1072 | res = GET_W_REG (code->src.reg); | |
1073 | goto log16; | |
1074 | case O (O_MOV_TO_MEM, SL): | |
1075 | res = GET_L_REG (code->src.reg); | |
1076 | goto log32; | |
1077 | ||
1078 | ||
1079 | case O (O_MOV_TO_REG, SB): | |
1080 | res = fetch (&code->src); | |
1081 | SET_B_REG (code->dst.reg, res); | |
1082 | goto just_flags_log8; | |
1083 | case O (O_MOV_TO_REG, SW): | |
1084 | res = fetch (&code->src); | |
1085 | SET_W_REG (code->dst.reg, res); | |
1086 | goto just_flags_log16; | |
1087 | case O (O_MOV_TO_REG, SL): | |
1088 | res = fetch (&code->src); | |
1089 | SET_L_REG (code->dst.reg, res); | |
1090 | goto just_flags_log32; | |
1091 | ||
1092 | ||
1093 | case O (O_ADDS, SL): | |
1094 | SET_L_REG (code->dst.reg, | |
1095 | GET_L_REG (code->dst.reg) | |
1096 | + code->src.literal); | |
1097 | ||
1098 | goto next; | |
1099 | ||
1100 | case O (O_SUBS, SL): | |
1101 | SET_L_REG (code->dst.reg, | |
1102 | GET_L_REG (code->dst.reg) | |
1103 | - code->src.literal); | |
1104 | goto next; | |
1105 | ||
1106 | case O (O_CMP, SB): | |
1107 | rd = fetch (&code->dst); | |
1108 | ea = fetch (&code->src); | |
1109 | ea = -ea; | |
1110 | res = rd + ea; | |
1111 | goto just_flags_alu8; | |
1112 | ||
1113 | case O (O_CMP, SW): | |
1114 | rd = fetch (&code->dst); | |
1115 | ea = fetch (&code->src); | |
1116 | ea = -ea; | |
1117 | res = rd + ea; | |
1118 | goto just_flags_alu16; | |
1119 | ||
1120 | case O (O_CMP, SL): | |
1121 | rd = fetch (&code->dst); | |
1122 | ea = fetch (&code->src); | |
1123 | ea = -ea; | |
1124 | res = rd + ea; | |
1125 | goto just_flags_alu32; | |
1126 | ||
1127 | ||
1128 | case O (O_DEC, SB): | |
1129 | rd = GET_B_REG (code->src.reg); | |
1130 | ea = -1; | |
1131 | res = rd + ea; | |
1132 | SET_B_REG (code->src.reg, res); | |
1133 | goto just_flags_inc8; | |
1134 | ||
1135 | case O (O_DEC, SW): | |
1136 | rd = GET_W_REG (code->dst.reg); | |
1137 | ea = -code->src.literal; | |
1138 | res = rd + ea; | |
1139 | SET_W_REG (code->dst.reg, res); | |
1140 | goto just_flags_inc16; | |
1141 | ||
1142 | case O (O_DEC, SL): | |
1143 | rd = GET_L_REG (code->dst.reg); | |
1144 | ea = -code->src.literal; | |
1145 | res = rd + ea; | |
1146 | SET_L_REG (code->dst.reg, res); | |
1147 | goto just_flags_inc32; | |
1148 | ||
1149 | ||
1150 | case O (O_INC, SB): | |
1151 | rd = GET_B_REG (code->src.reg); | |
1152 | ea = 1; | |
1153 | res = rd + ea; | |
1154 | SET_B_REG (code->src.reg, res); | |
1155 | goto just_flags_inc8; | |
1156 | ||
1157 | case O (O_INC, SW): | |
1158 | rd = GET_W_REG (code->dst.reg); | |
1159 | ea = code->src.literal; | |
1160 | res = rd + ea; | |
1161 | SET_W_REG (code->dst.reg, res); | |
1162 | goto just_flags_inc16; | |
1163 | ||
1164 | case O (O_INC, SL): | |
1165 | rd = GET_L_REG (code->dst.reg); | |
1166 | ea = code->src.literal; | |
1167 | res = rd + ea; | |
1168 | SET_L_REG (code->dst.reg, res); | |
1169 | goto just_flags_inc32; | |
1170 | ||
1171 | ||
1172 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
1173 | ||
1174 | case O (O_ANDC, SB): | |
1175 | GET_CCR (rd); | |
1176 | ea = code->src.literal; | |
1177 | res = rd & ea; | |
1178 | goto setc; | |
1179 | ||
1180 | case O (O_ORC, SB): | |
1181 | GET_CCR (rd); | |
1182 | ea = code->src.literal; | |
1183 | res = rd | ea; | |
1184 | goto setc; | |
1185 | ||
1186 | case O (O_XORC, SB): | |
1187 | GET_CCR (rd); | |
1188 | ea = code->src.literal; | |
1189 | res = rd ^ ea; | |
1190 | goto setc; | |
1191 | ||
1192 | ||
1193 | case O (O_BRA, SB): | |
1194 | if (1) | |
1195 | goto condtrue; | |
1196 | goto next; | |
1197 | ||
1198 | case O (O_BRN, SB): | |
1199 | if (0) | |
1200 | goto condtrue; | |
1201 | goto next; | |
1202 | ||
1203 | case O (O_BHI, SB): | |
1204 | if ((C || Z) == 0) | |
1205 | goto condtrue; | |
1206 | goto next; | |
1207 | ||
1208 | ||
1209 | case O (O_BLS, SB): | |
1210 | if ((C || Z)) | |
1211 | goto condtrue; | |
1212 | goto next; | |
1213 | ||
1214 | case O (O_BCS, SB): | |
1215 | if ((C == 1)) | |
1216 | goto condtrue; | |
1217 | goto next; | |
1218 | ||
1219 | case O (O_BCC, SB): | |
1220 | if ((C == 0)) | |
1221 | goto condtrue; | |
1222 | goto next; | |
1223 | ||
1224 | case O (O_BEQ, SB): | |
1225 | if (Z) | |
1226 | goto condtrue; | |
1227 | goto next; | |
1228 | case O (O_BGT, SB): | |
1229 | if (((Z || (N ^ V)) == 0)) | |
1230 | goto condtrue; | |
1231 | goto next; | |
1232 | ||
1233 | ||
1234 | case O (O_BLE, SB): | |
1235 | if (((Z || (N ^ V)) == 1)) | |
1236 | goto condtrue; | |
1237 | goto next; | |
1238 | ||
1239 | case O (O_BGE, SB): | |
1240 | if ((N ^ V) == 0) | |
1241 | goto condtrue; | |
1242 | goto next; | |
1243 | case O (O_BLT, SB): | |
1244 | if ((N ^ V)) | |
1245 | goto condtrue; | |
1246 | goto next; | |
1247 | case O (O_BMI, SB): | |
1248 | if ((N)) | |
1249 | goto condtrue; | |
1250 | goto next; | |
1251 | case O (O_BNE, SB): | |
1252 | if ((Z == 0)) | |
1253 | goto condtrue; | |
1254 | goto next; | |
1255 | ||
1256 | case O (O_BPL, SB): | |
1257 | if (N == 0) | |
1258 | goto condtrue; | |
1259 | goto next; | |
1260 | case O (O_BVC, SB): | |
1261 | if ((V == 0)) | |
1262 | goto condtrue; | |
1263 | goto next; | |
1264 | case O (O_BVS, SB): | |
1265 | if ((V == 1)) | |
1266 | goto condtrue; | |
1267 | goto next; | |
1268 | ||
1269 | case O (O_SYSCALL, SB): | |
1270 | { | |
1271 | char c = cpu.regs[2]; | |
1272 | sim_callback->write_stdout (sim_callback, &c, 1); | |
1273 | } | |
1274 | goto next; | |
1275 | ||
1276 | ONOT (O_NOT, rd = ~rd; v = 0;); | |
1277 | OSHIFTS (O_SHLL, | |
1278 | c = rd & hm; v = 0; rd <<= 1, | |
1279 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1280 | OSHIFTS (O_SHLR, | |
1281 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1282 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1283 | OSHIFTS (O_SHAL, | |
1284 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1285 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1286 | OSHIFTS (O_SHAR, | |
1287 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
1288 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 ); | |
1289 | OSHIFTS (O_ROTL, | |
1290 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
1291 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); | |
1292 | OSHIFTS (O_ROTR, | |
1293 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
1294 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); | |
1295 | OSHIFTS (O_ROTXL, | |
1296 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
1297 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); | |
1298 | OSHIFTS (O_ROTXR, | |
1299 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
1300 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); | |
1301 | ||
1302 | case O (O_JMP, SB): | |
1303 | { | |
1304 | pc = fetch (&code->src); | |
1305 | goto end; | |
1306 | ||
1307 | } | |
1308 | ||
1309 | case O (O_JSR, SB): | |
1310 | { | |
1311 | int tmp; | |
1312 | pc = fetch (&code->src); | |
1313 | call: | |
1314 | tmp = cpu.regs[7]; | |
1315 | ||
1316 | if (h8300hmode) | |
1317 | { | |
1318 | tmp -= 4; | |
1319 | SET_MEMORY_L (tmp, code->next_pc); | |
1320 | } | |
1321 | else | |
1322 | { | |
1323 | tmp -= 2; | |
1324 | SET_MEMORY_W (tmp, code->next_pc); | |
1325 | } | |
1326 | cpu.regs[7] = tmp; | |
1327 | ||
1328 | goto end; | |
1329 | } | |
1330 | case O (O_BSR, SB): | |
1331 | pc = code->src.literal; | |
1332 | goto call; | |
1333 | ||
1334 | case O (O_RTS, SN): | |
1335 | { | |
1336 | int tmp; | |
1337 | ||
1338 | tmp = cpu.regs[7]; | |
1339 | ||
1340 | if (h8300hmode) | |
1341 | { | |
1342 | pc = GET_MEMORY_L (tmp); | |
1343 | tmp += 4; | |
1344 | } | |
1345 | else | |
1346 | { | |
1347 | pc = GET_MEMORY_W (tmp); | |
1348 | tmp += 2; | |
1349 | } | |
1350 | ||
1351 | cpu.regs[7] = tmp; | |
1352 | goto end; | |
1353 | } | |
1354 | ||
1355 | case O (O_ILL, SB): | |
1356 | cpu.state = SIM_STATE_STOPPED; | |
1357 | cpu.exception = SIGILL; | |
1358 | goto end; | |
1359 | case O (O_SLEEP, SN): | |
c906108c SS |
1360 | /* FIXME: Doesn't this break for breakpoints when r0 |
1361 | contains just the right (er, wrong) value? */ | |
1362 | cpu.state = SIM_STATE_STOPPED; | |
97ee9e5a FCE |
1363 | /* The format of r0 is defined by target newlib. Expand |
1364 | the macros here instead of looking for .../sys/wait.h. */ | |
1365 | #define SIM_WIFEXITED(v) (((v) & 0xff) == 0) | |
1366 | #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f)) | |
1367 | if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0])) | |
c906108c SS |
1368 | cpu.exception = SIGILL; |
1369 | else | |
1370 | cpu.exception = SIGTRAP; | |
c906108c SS |
1371 | goto end; |
1372 | case O (O_BPT, SN): | |
1373 | cpu.state = SIM_STATE_STOPPED; | |
1374 | cpu.exception = SIGTRAP; | |
1375 | goto end; | |
1376 | ||
1377 | OBITOP (O_BNOT, 1, 1, ea ^= m); | |
1378 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1379 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1380 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1381 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1382 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1383 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1384 | if (C) ea |= m); | |
1385 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1386 | if (!C) ea |= m); | |
1387 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1388 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1389 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1390 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1391 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1392 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
1393 | ||
1394 | ||
1395 | #define MOP(bsize, signed) mop(code, bsize,signed); goto next; | |
1396 | ||
1397 | case O (O_MULS, SB): | |
1398 | MOP (1, 1); | |
1399 | break; | |
1400 | case O (O_MULS, SW): | |
1401 | MOP (0, 1); | |
1402 | break; | |
1403 | case O (O_MULU, SB): | |
1404 | MOP (1, 0); | |
1405 | break; | |
1406 | case O (O_MULU, SW): | |
1407 | MOP (0, 0); | |
1408 | break; | |
1409 | ||
1410 | ||
1411 | case O (O_DIVU, SB): | |
1412 | { | |
1413 | rd = GET_W_REG (code->dst.reg); | |
1414 | ea = GET_B_REG (code->src.reg); | |
1415 | if (ea) | |
1416 | { | |
1417 | tmp = (unsigned)rd % ea; | |
1418 | rd = (unsigned)rd / ea; | |
1419 | } | |
1420 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1421 | n = ea & 0x80; | |
1422 | nz = ea & 0xff; | |
1423 | ||
1424 | goto next; | |
1425 | } | |
1426 | case O (O_DIVU, SW): | |
1427 | { | |
1428 | rd = GET_L_REG (code->dst.reg); | |
1429 | ea = GET_W_REG (code->src.reg); | |
1430 | n = ea & 0x8000; | |
1431 | nz = ea & 0xffff; | |
1432 | if (ea) | |
1433 | { | |
1434 | tmp = (unsigned)rd % ea; | |
1435 | rd = (unsigned)rd / ea; | |
1436 | } | |
1437 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1438 | goto next; | |
1439 | } | |
1440 | ||
1441 | case O (O_DIVS, SB): | |
1442 | { | |
1443 | ||
1444 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); | |
1445 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1446 | if (ea) | |
1447 | { | |
1448 | tmp = (int) rd % (int) ea; | |
1449 | rd = (int) rd / (int) ea; | |
1450 | n = rd & 0x8000; | |
1451 | nz = 1; | |
1452 | } | |
1453 | else | |
1454 | nz = 0; | |
1455 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1456 | goto next; | |
1457 | } | |
1458 | case O (O_DIVS, SW): | |
1459 | { | |
1460 | rd = GET_L_REG (code->dst.reg); | |
1461 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1462 | if (ea) | |
1463 | { | |
1464 | tmp = (int) rd % (int) ea; | |
1465 | rd = (int) rd / (int) ea; | |
1466 | n = rd & 0x80000000; | |
1467 | nz = 1; | |
1468 | } | |
1469 | else | |
1470 | nz = 0; | |
1471 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1472 | goto next; | |
1473 | } | |
1474 | case O (O_EXTS, SW): | |
1475 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ | |
1476 | ea = rd & 0x80 ? -256 : 0; | |
1477 | res = rd + ea; | |
1478 | goto log16; | |
1479 | case O (O_EXTS, SL): | |
1480 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1481 | ea = rd & 0x8000 ? -65536 : 0; | |
1482 | res = rd + ea; | |
1483 | goto log32; | |
1484 | case O (O_EXTU, SW): | |
1485 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1486 | ea = 0; | |
1487 | res = rd + ea; | |
1488 | goto log16; | |
1489 | case O (O_EXTU, SL): | |
1490 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1491 | ea = 0; | |
1492 | res = rd + ea; | |
1493 | goto log32; | |
1494 | ||
1495 | case O (O_NOP, SN): | |
1496 | goto next; | |
1497 | ||
1498 | case O (O_STM, SL): | |
1499 | { | |
1500 | int nregs, firstreg, i; | |
1501 | ||
1502 | nregs = GET_MEMORY_B (pc + 1); | |
1503 | nregs >>= 4; | |
1504 | nregs &= 0xf; | |
1505 | firstreg = GET_MEMORY_B (pc + 3); | |
1506 | firstreg &= 0xf; | |
1507 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1508 | { | |
1509 | cpu.regs[7] -= 4; | |
1510 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1511 | } | |
1512 | } | |
1513 | goto next; | |
1514 | ||
1515 | case O (O_LDM, SL): | |
1516 | { | |
1517 | int nregs, firstreg, i; | |
1518 | ||
1519 | nregs = GET_MEMORY_B (pc + 1); | |
1520 | nregs >>= 4; | |
1521 | nregs &= 0xf; | |
1522 | firstreg = GET_MEMORY_B (pc + 3); | |
1523 | firstreg &= 0xf; | |
1524 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1525 | { | |
1526 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1527 | cpu.regs[7] += 4; | |
1528 | } | |
1529 | } | |
1530 | goto next; | |
1531 | ||
1532 | default: | |
1533 | cpu.state = SIM_STATE_STOPPED; | |
1534 | cpu.exception = SIGILL; | |
1535 | goto end; | |
1536 | ||
1537 | } | |
1538 | abort (); | |
1539 | ||
1540 | setc: | |
1541 | cpu.ccr = res; | |
1542 | GETSR (); | |
1543 | goto next; | |
1544 | ||
1545 | condtrue: | |
1546 | /* When a branch works */ | |
1547 | pc = code->src.literal; | |
1548 | goto end; | |
1549 | ||
1550 | /* Set the cond codes from res */ | |
1551 | bitop: | |
1552 | ||
1553 | /* Set the flags after an 8 bit inc/dec operation */ | |
1554 | just_flags_inc8: | |
1555 | n = res & 0x80; | |
1556 | nz = res & 0xff; | |
1557 | v = (rd & 0x7f) == 0x7f; | |
1558 | goto next; | |
1559 | ||
1560 | ||
1561 | /* Set the flags after an 16 bit inc/dec operation */ | |
1562 | just_flags_inc16: | |
1563 | n = res & 0x8000; | |
1564 | nz = res & 0xffff; | |
1565 | v = (rd & 0x7fff) == 0x7fff; | |
1566 | goto next; | |
1567 | ||
1568 | ||
1569 | /* Set the flags after an 32 bit inc/dec operation */ | |
1570 | just_flags_inc32: | |
1571 | n = res & 0x80000000; | |
1572 | nz = res & 0xffffffff; | |
1573 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1574 | goto next; | |
1575 | ||
1576 | ||
1577 | shift8: | |
1578 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ | |
1579 | n = (rd & 0x80); | |
1580 | nz = rd & 0xff; | |
1581 | SET_B_REG (code->src.reg, rd); | |
1582 | goto next; | |
1583 | ||
1584 | shift16: | |
1585 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ | |
1586 | n = (rd & 0x8000); | |
1587 | nz = rd & 0xffff; | |
1588 | SET_W_REG (code->src.reg, rd); | |
1589 | goto next; | |
1590 | ||
1591 | shift32: | |
1592 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ | |
1593 | n = (rd & 0x80000000); | |
1594 | nz = rd & 0xffffffff; | |
1595 | SET_L_REG (code->src.reg, rd); | |
1596 | goto next; | |
1597 | ||
1598 | log32: | |
1599 | store (&code->dst, res); | |
1600 | just_flags_log32: | |
1601 | /* flags after a 32bit logical operation */ | |
1602 | n = res & 0x80000000; | |
1603 | nz = res & 0xffffffff; | |
1604 | v = 0; | |
1605 | goto next; | |
1606 | ||
1607 | log16: | |
1608 | store (&code->dst, res); | |
1609 | just_flags_log16: | |
1610 | /* flags after a 16bit logical operation */ | |
1611 | n = res & 0x8000; | |
1612 | nz = res & 0xffff; | |
1613 | v = 0; | |
1614 | goto next; | |
1615 | ||
1616 | ||
1617 | log8: | |
1618 | store (&code->dst, res); | |
1619 | just_flags_log8: | |
1620 | n = res & 0x80; | |
1621 | nz = res & 0xff; | |
1622 | v = 0; | |
1623 | goto next; | |
1624 | ||
1625 | alu8: | |
1626 | SET_B_REG (code->dst.reg, res); | |
1627 | just_flags_alu8: | |
1628 | n = res & 0x80; | |
1629 | nz = res & 0xff; | |
1630 | c = (res & 0x100); | |
1631 | switch (code->opcode / 4) | |
1632 | { | |
1633 | case O_ADD: | |
1634 | v = ((rd & 0x80) == (ea & 0x80) | |
1635 | && (rd & 0x80) != (res & 0x80)); | |
1636 | break; | |
1637 | case O_SUB: | |
1638 | case O_CMP: | |
1639 | v = ((rd & 0x80) != (-ea & 0x80) | |
1640 | && (rd & 0x80) != (res & 0x80)); | |
1641 | break; | |
1642 | case O_NEG: | |
1643 | v = (rd == 0x80); | |
1644 | break; | |
1645 | } | |
1646 | goto next; | |
1647 | ||
1648 | alu16: | |
1649 | SET_W_REG (code->dst.reg, res); | |
1650 | just_flags_alu16: | |
1651 | n = res & 0x8000; | |
1652 | nz = res & 0xffff; | |
1653 | c = (res & 0x10000); | |
1654 | switch (code->opcode / 4) | |
1655 | { | |
1656 | case O_ADD: | |
1657 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1658 | && (rd & 0x8000) != (res & 0x8000)); | |
1659 | break; | |
1660 | case O_SUB: | |
1661 | case O_CMP: | |
1662 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1663 | && (rd & 0x8000) != (res & 0x8000)); | |
1664 | break; | |
1665 | case O_NEG: | |
1666 | v = (rd == 0x8000); | |
1667 | break; | |
1668 | } | |
1669 | goto next; | |
1670 | ||
1671 | alu32: | |
1672 | SET_L_REG (code->dst.reg, res); | |
1673 | just_flags_alu32: | |
1674 | n = res & 0x80000000; | |
1675 | nz = res & 0xffffffff; | |
1676 | switch (code->opcode / 4) | |
1677 | { | |
1678 | case O_ADD: | |
1679 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1680 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1681 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
1682 | break; | |
1683 | case O_SUB: | |
1684 | case O_CMP: | |
1685 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1686 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1687 | c = (unsigned) rd < (unsigned) -ea; | |
1688 | break; | |
1689 | case O_NEG: | |
1690 | v = (rd == 0x80000000); | |
1691 | c = res != 0; | |
1692 | break; | |
1693 | } | |
1694 | goto next; | |
1695 | ||
1696 | next:; | |
1697 | pc = code->next_pc; | |
1698 | ||
1699 | end: | |
1700 | ; | |
1701 | /* if (cpu.regs[8] ) abort(); */ | |
1702 | ||
1703 | if (--poll_count < 0) | |
1704 | { | |
7a292a7a | 1705 | poll_count = POLL_QUIT_INTERVAL; |
c906108c SS |
1706 | if ((*sim_callback->poll_quit) != NULL |
1707 | && (*sim_callback->poll_quit) (sim_callback)) | |
1708 | sim_stop (sd); | |
1709 | } | |
1710 | ||
1711 | } | |
1712 | while (cpu.state == SIM_STATE_RUNNING); | |
1713 | cpu.ticks += get_now () - tick_start; | |
1714 | cpu.cycles += cycles; | |
1715 | cpu.insts += insts; | |
1716 | ||
1717 | cpu.pc = pc; | |
1718 | BUILDSR (); | |
1719 | cpu.mask = oldmask; | |
1720 | signal (SIGINT, prev); | |
1721 | } | |
1722 | ||
1723 | int | |
1724 | sim_trace (sd) | |
1725 | SIM_DESC sd; | |
1726 | { | |
1727 | /* FIXME: unfinished */ | |
1728 | abort (); | |
1729 | } | |
1730 | ||
1731 | int | |
1732 | sim_write (sd, addr, buffer, size) | |
1733 | SIM_DESC sd; | |
1734 | SIM_ADDR addr; | |
1735 | unsigned char *buffer; | |
1736 | int size; | |
1737 | { | |
1738 | int i; | |
1739 | ||
1740 | init_pointers (); | |
1741 | if (addr < 0) | |
1742 | return 0; | |
1743 | for (i = 0; i < size; i++) | |
1744 | { | |
1745 | if (addr < memory_size) | |
1746 | { | |
1747 | cpu.memory[addr + i] = buffer[i]; | |
1748 | cpu.cache_idx[addr + i] = 0; | |
1749 | } | |
1750 | else | |
1751 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
1752 | } | |
1753 | return size; | |
1754 | } | |
1755 | ||
1756 | int | |
1757 | sim_read (sd, addr, buffer, size) | |
1758 | SIM_DESC sd; | |
1759 | SIM_ADDR addr; | |
1760 | unsigned char *buffer; | |
1761 | int size; | |
1762 | { | |
1763 | init_pointers (); | |
1764 | if (addr < 0) | |
1765 | return 0; | |
1766 | if (addr < memory_size) | |
1767 | memcpy (buffer, cpu.memory + addr, size); | |
1768 | else | |
1769 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
1770 | return size; | |
1771 | } | |
1772 | ||
1773 | ||
1774 | #define R0_REGNUM 0 | |
1775 | #define R1_REGNUM 1 | |
1776 | #define R2_REGNUM 2 | |
1777 | #define R3_REGNUM 3 | |
1778 | #define R4_REGNUM 4 | |
1779 | #define R5_REGNUM 5 | |
1780 | #define R6_REGNUM 6 | |
1781 | #define R7_REGNUM 7 | |
1782 | ||
1783 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1784 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
1785 | * stack frame */ | |
1786 | ||
1787 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1788 | #define PC_REGNUM 9 /* Contains program counter */ | |
1789 | ||
1790 | #define CYCLE_REGNUM 10 | |
1791 | #define INST_REGNUM 11 | |
1792 | #define TICK_REGNUM 12 | |
1793 | ||
1794 | ||
1795 | int | |
1796 | sim_store_register (sd, rn, value, length) | |
1797 | SIM_DESC sd; | |
1798 | int rn; | |
1799 | unsigned char *value; | |
1800 | int length; | |
1801 | { | |
1802 | int longval; | |
1803 | int shortval; | |
1804 | int intval; | |
1805 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; | |
1806 | shortval = (value[0] << 8) | (value[1]); | |
1807 | intval = h8300hmode ? longval : shortval; | |
1808 | ||
1809 | init_pointers (); | |
1810 | switch (rn) | |
1811 | { | |
1812 | case PC_REGNUM: | |
1813 | cpu.pc = intval; | |
1814 | break; | |
1815 | default: | |
1816 | abort (); | |
1817 | case R0_REGNUM: | |
1818 | case R1_REGNUM: | |
1819 | case R2_REGNUM: | |
1820 | case R3_REGNUM: | |
1821 | case R4_REGNUM: | |
1822 | case R5_REGNUM: | |
1823 | case R6_REGNUM: | |
1824 | case R7_REGNUM: | |
1825 | cpu.regs[rn] = intval; | |
1826 | break; | |
1827 | case CCR_REGNUM: | |
1828 | cpu.ccr = intval; | |
1829 | break; | |
1830 | case CYCLE_REGNUM: | |
1831 | cpu.cycles = longval; | |
1832 | break; | |
1833 | ||
1834 | case INST_REGNUM: | |
1835 | cpu.insts = longval; | |
1836 | break; | |
1837 | ||
1838 | case TICK_REGNUM: | |
1839 | cpu.ticks = longval; | |
1840 | break; | |
1841 | } | |
1842 | return -1; | |
1843 | } | |
1844 | ||
1845 | int | |
1846 | sim_fetch_register (sd, rn, buf, length) | |
1847 | SIM_DESC sd; | |
1848 | int rn; | |
1849 | unsigned char *buf; | |
1850 | int length; | |
1851 | { | |
1852 | int v; | |
1853 | int longreg = 0; | |
1854 | ||
1855 | init_pointers (); | |
1856 | ||
1857 | switch (rn) | |
1858 | { | |
1859 | default: | |
1860 | abort (); | |
1861 | case 8: | |
1862 | v = cpu.ccr; | |
1863 | break; | |
1864 | case 9: | |
1865 | v = cpu.pc; | |
1866 | break; | |
1867 | case R0_REGNUM: | |
1868 | case R1_REGNUM: | |
1869 | case R2_REGNUM: | |
1870 | case R3_REGNUM: | |
1871 | case R4_REGNUM: | |
1872 | case R5_REGNUM: | |
1873 | case R6_REGNUM: | |
1874 | case R7_REGNUM: | |
1875 | v = cpu.regs[rn]; | |
1876 | break; | |
1877 | case 10: | |
1878 | v = cpu.cycles; | |
1879 | longreg = 1; | |
1880 | break; | |
1881 | case 11: | |
1882 | v = cpu.ticks; | |
1883 | longreg = 1; | |
1884 | break; | |
1885 | case 12: | |
1886 | v = cpu.insts; | |
1887 | longreg = 1; | |
1888 | break; | |
1889 | } | |
1890 | if (h8300hmode || longreg) | |
1891 | { | |
1892 | buf[0] = v >> 24; | |
1893 | buf[1] = v >> 16; | |
1894 | buf[2] = v >> 8; | |
1895 | buf[3] = v >> 0; | |
1896 | } | |
1897 | else | |
1898 | { | |
1899 | buf[0] = v >> 8; | |
1900 | buf[1] = v; | |
1901 | } | |
1902 | return -1; | |
1903 | } | |
1904 | ||
1905 | void | |
1906 | sim_stop_reason (sd, reason, sigrc) | |
1907 | SIM_DESC sd; | |
1908 | enum sim_stop *reason; | |
1909 | int *sigrc; | |
1910 | { | |
1911 | #if 0 /* FIXME: This should work but we can't use it. | |
1912 | grep for SLEEP above. */ | |
1913 | switch (cpu.state) | |
1914 | { | |
1915 | case SIM_STATE_EXITED : *reason = sim_exited; break; | |
1916 | case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; | |
1917 | case SIM_STATE_STOPPED : *reason = sim_stopped; break; | |
1918 | default : abort (); | |
1919 | } | |
1920 | #else | |
1921 | *reason = sim_stopped; | |
1922 | #endif | |
1923 | *sigrc = cpu.exception; | |
1924 | } | |
1925 | ||
1926 | /* FIXME: Rename to sim_set_mem_size. */ | |
1927 | ||
1928 | void | |
1929 | sim_size (n) | |
1930 | int n; | |
1931 | { | |
1932 | /* Memory size is fixed. */ | |
1933 | } | |
1934 | ||
1935 | void | |
1936 | sim_set_simcache_size (n) | |
1937 | { | |
1938 | if (cpu.cache) | |
1939 | free (cpu.cache); | |
1940 | if (n < 2) | |
1941 | n = 2; | |
1942 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1943 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1944 | cpu.csize = n; | |
1945 | } | |
1946 | ||
1947 | ||
1948 | void | |
1949 | sim_info (sd, verbose) | |
1950 | SIM_DESC sd; | |
1951 | int verbose; | |
1952 | { | |
1953 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1954 | double virttime = cpu.cycles / 10.0e6; | |
1955 | ||
1956 | (*sim_callback->printf_filtered) (sim_callback, | |
1957 | "\n\n#instructions executed %10d\n", | |
1958 | cpu.insts); | |
1959 | (*sim_callback->printf_filtered) (sim_callback, | |
1960 | "#cycles (v approximate) %10d\n", | |
1961 | cpu.cycles); | |
1962 | (*sim_callback->printf_filtered) (sim_callback, | |
1963 | "#real time taken %10.4f\n", | |
1964 | timetaken); | |
1965 | (*sim_callback->printf_filtered) (sim_callback, | |
1966 | "#virtual time taked %10.4f\n", | |
1967 | virttime); | |
1968 | if (timetaken != 0.0) | |
1969 | (*sim_callback->printf_filtered) (sim_callback, | |
1970 | "#simulation ratio %10.4f\n", | |
1971 | virttime / timetaken); | |
1972 | (*sim_callback->printf_filtered) (sim_callback, | |
1973 | "#compiles %10d\n", | |
1974 | cpu.compiles); | |
1975 | (*sim_callback->printf_filtered) (sim_callback, | |
1976 | "#cache size %10d\n", | |
1977 | cpu.csize); | |
1978 | ||
1979 | #ifdef ADEBUG | |
1980 | /* This to be conditional on `what' (aka `verbose'), | |
1981 | however it was never passed as non-zero. */ | |
1982 | if (1) | |
1983 | { | |
1984 | int i; | |
1985 | for (i = 0; i < O_LAST; i++) | |
1986 | { | |
1987 | if (cpu.stats[i]) | |
1988 | (*sim_callback->printf_filtered) (sim_callback, | |
1989 | "%d: %d\n", i, cpu.stats[i]); | |
1990 | } | |
1991 | } | |
1992 | #endif | |
1993 | } | |
1994 | ||
1995 | /* Indicate whether the cpu is an h8/300 or h8/300h. | |
1996 | FLAG is non-zero for the h8/300h. */ | |
1997 | ||
1998 | void | |
1999 | set_h8300h (flag) | |
2000 | int flag; | |
2001 | { | |
2002 | /* FIXME: Much of the code in sim_load can be moved to sim_open. | |
2003 | This function being replaced by a sim_open:ARGV configuration | |
2004 | option */ | |
2005 | h8300hmode = flag; | |
2006 | } | |
2007 | ||
2008 | SIM_DESC | |
2009 | sim_open (kind, ptr, abfd, argv) | |
2010 | SIM_OPEN_KIND kind; | |
2011 | struct host_callback_struct *ptr; | |
2012 | struct _bfd *abfd; | |
2013 | char **argv; | |
2014 | { | |
2015 | /* FIXME: Much of the code in sim_load can be moved here */ | |
2016 | ||
2017 | sim_kind = kind; | |
2018 | myname = argv[0]; | |
2019 | sim_callback = ptr; | |
2020 | /* fudge our descriptor */ | |
2021 | return (SIM_DESC) 1; | |
2022 | } | |
2023 | ||
2024 | void | |
2025 | sim_close (sd, quitting) | |
2026 | SIM_DESC sd; | |
2027 | int quitting; | |
2028 | { | |
2029 | /* nothing to do */ | |
2030 | } | |
2031 | ||
2032 | /* Called by gdb to load a program into memory. */ | |
2033 | ||
2034 | SIM_RC | |
2035 | sim_load (sd, prog, abfd, from_tty) | |
2036 | SIM_DESC sd; | |
2037 | char *prog; | |
2038 | bfd *abfd; | |
2039 | int from_tty; | |
2040 | { | |
2041 | bfd *prog_bfd; | |
2042 | ||
2043 | /* FIXME: The code below that sets a specific variant of the h8/300 | |
2044 | being simulated should be moved to sim_open(). */ | |
2045 | ||
2046 | /* See if the file is for the h8/300 or h8/300h. */ | |
2047 | /* ??? This may not be the most efficient way. The z8k simulator | |
2048 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
2049 | if (abfd != NULL) | |
2050 | prog_bfd = abfd; | |
2051 | else | |
2052 | prog_bfd = bfd_openr (prog, "coff-h8300"); | |
2053 | if (prog_bfd != NULL) | |
2054 | { | |
2055 | /* Set the cpu type. We ignore failure from bfd_check_format | |
2056 | and bfd_openr as sim_load_file checks too. */ | |
2057 | if (bfd_check_format (prog_bfd, bfd_object)) | |
2058 | { | |
2059 | unsigned long mach = bfd_get_mach (prog_bfd); | |
2060 | set_h8300h (mach == bfd_mach_h8300h | |
2061 | || mach == bfd_mach_h8300s); | |
2062 | } | |
2063 | } | |
2064 | ||
2065 | /* If we're using gdb attached to the simulator, then we have to | |
2066 | reallocate memory for the simulator. | |
2067 | ||
2068 | When gdb first starts, it calls fetch_registers (among other | |
2069 | functions), which in turn calls init_pointers, which allocates | |
2070 | simulator memory. | |
2071 | ||
2072 | The problem is when we do that, we don't know whether we're | |
2073 | debugging an h8/300 or h8/300h program. | |
2074 | ||
2075 | This is the first point at which we can make that determination, | |
2076 | so we just reallocate memory now; this will also allow us to handle | |
2077 | switching between h8/300 and h8/300h programs without exiting | |
2078 | gdb. */ | |
2079 | if (h8300hmode) | |
2080 | memory_size = H8300H_MSIZE; | |
2081 | else | |
2082 | memory_size = H8300_MSIZE; | |
2083 | ||
2084 | if (cpu.memory) | |
2085 | free (cpu.memory); | |
2086 | if (cpu.cache_idx) | |
2087 | free (cpu.cache_idx); | |
2088 | if (cpu.eightbit) | |
2089 | free (cpu.eightbit); | |
2090 | ||
2091 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2092 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2093 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2094 | ||
2095 | /* `msize' must be a power of two */ | |
2096 | if ((memory_size & (memory_size - 1)) != 0) | |
2097 | abort (); | |
2098 | cpu.mask = memory_size - 1; | |
2099 | ||
2100 | if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, | |
2101 | sim_kind == SIM_OPEN_DEBUG, | |
2102 | 0, sim_write) | |
2103 | == NULL) | |
2104 | { | |
2105 | /* Close the bfd if we opened it. */ | |
2106 | if (abfd == NULL && prog_bfd != NULL) | |
2107 | bfd_close (prog_bfd); | |
2108 | return SIM_RC_FAIL; | |
2109 | } | |
2110 | ||
2111 | /* Close the bfd if we opened it. */ | |
2112 | if (abfd == NULL && prog_bfd != NULL) | |
2113 | bfd_close (prog_bfd); | |
2114 | return SIM_RC_OK; | |
2115 | } | |
2116 | ||
2117 | SIM_RC | |
2118 | sim_create_inferior (sd, abfd, argv, env) | |
2119 | SIM_DESC sd; | |
2120 | struct _bfd *abfd; | |
2121 | char **argv; | |
2122 | char **env; | |
2123 | { | |
2124 | if (abfd != NULL) | |
2125 | cpu.pc = bfd_get_start_address (abfd); | |
2126 | else | |
2127 | cpu.pc = 0; | |
2128 | return SIM_RC_OK; | |
2129 | } | |
2130 | ||
2131 | void | |
2132 | sim_do_command (sd, cmd) | |
2133 | SIM_DESC sd; | |
2134 | char *cmd; | |
2135 | { | |
2136 | (*sim_callback->printf_filtered) (sim_callback, | |
2137 | "This simulator does not accept any commands.\n"); | |
2138 | } | |
2139 | ||
2140 | void | |
2141 | sim_set_callbacks (ptr) | |
2142 | struct host_callback_struct *ptr; | |
2143 | { | |
2144 | sim_callback = ptr; | |
2145 | } |