[thirdparty/binutils-gdb.git] / sim / m68hc11 / interp.c

/* interp.c -- Simulator for Motorola 68HC11/68HC12
   Copyright (C) 1999-2015 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "sim-main.h"
#include "sim-assert.h"
#include "sim-hw.h"
#include "sim-options.h"
#include "hw-tree.h"
#include "hw-device.h"
#include "hw-ports.h"
#include "elf32-m68hc1x.h"

#ifndef MONITOR_BASE
# define MONITOR_BASE (0x0C000)
# define MONITOR_SIZE (0x04000)
#endif

static void sim_get_info (SIM_DESC sd, char *cmd);


char *interrupt_names[] = {
  "reset",
  "nmi",
  "int",
  NULL
};

#ifndef INLINE
#if defined(__GNUC__) && defined(__OPTIMIZE__)
#define INLINE __inline__
#else
#define INLINE
#endif
#endif

struct sim_info_list
{
  const char *name;
  const char *device;
};

struct sim_info_list dev_list_68hc11[] = {
  {"cpu", "/m68hc11"},
  {"timer", "/m68hc11/m68hc11tim"},
  {"sio", "/m68hc11/m68hc11sio"},
  {"spi", "/m68hc11/m68hc11spi"},
  {"eeprom", "/m68hc11/m68hc11eepr"},
  {0, 0}
};

struct sim_info_list dev_list_68hc12[] = {
  {"cpu", "/m68hc12"},
  {"timer", "/m68hc12/m68hc12tim"},
  {"sio", "/m68hc12/m68hc12sio"},
  {"spi", "/m68hc12/m68hc12spi"},
  {"eeprom", "/m68hc12/m68hc12eepr"},
  {0, 0}
};

/* Cover function of sim_state_free to free the cpu buffers as well.  */

static void
free_state (SIM_DESC sd)
{
  if (STATE_MODULES (sd) != NULL)
    sim_module_uninstall (sd);

  sim_state_free (sd);
}

/* Give some information about the simulator.  */
static void
sim_get_info (SIM_DESC sd, char *cmd)
{
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);
  if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
    {
      int i;
      struct hw *hw_dev;
      struct sim_info_list *dev_list;
      const struct bfd_arch_info *arch;

      arch = STATE_ARCHITECTURE (sd);
      cmd++;

      if (arch->arch == bfd_arch_m68hc11)
        dev_list = dev_list_68hc11;
      else
        dev_list = dev_list_68hc12;

      for (i = 0; dev_list[i].name; i++)
	if (strcmp (cmd, dev_list[i].name) == 0)
	  break;

      if (dev_list[i].name == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	  sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	  return;
	}
      hw_dev = sim_hw_parse (sd, dev_list[i].device);
      if (hw_dev == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	  return;
	}
      hw_ioctl (hw_dev, 23, 0);
      return;
    }

  cpu_info (sd, cpu);
  interrupts_info (sd, &cpu->cpu_interrupts);
}


void
sim_board_reset (SIM_DESC sd)
{
  struct hw *hw_cpu;
  sim_cpu *cpu;
  const struct bfd_arch_info *arch;
  const char *cpu_type;

  cpu = STATE_CPU (sd, 0);
  arch = STATE_ARCHITECTURE (sd);

  /*  hw_cpu = sim_hw_parse (sd, "/"); */
  if (arch->arch == bfd_arch_m68hc11)
    {
      cpu->cpu_type = CPU_M6811;
      cpu_type = "/m68hc11";
    }
  else
    {
      cpu->cpu_type = CPU_M6812;
      cpu_type = "/m68hc12";
    }
  
  hw_cpu = sim_hw_parse (sd, cpu_type);
  if (hw_cpu == 0)
    {
      sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
      return;
    }

  cpu_reset (cpu);
  hw_port_event (hw_cpu, 3, 0);
  cpu_restart (cpu);
}

static int
sim_hw_configure (SIM_DESC sd)
{
  const struct bfd_arch_info *arch;
  struct hw *device_tree;
  sim_cpu *cpu;
  
  arch = STATE_ARCHITECTURE (sd);
  if (arch == 0)
    return 0;

  cpu = STATE_CPU (sd, 0);
  cpu->cpu_configured_arch = arch;
  device_tree = sim_hw_parse (sd, "/");
  if (arch->arch == bfd_arch_m68hc11)
    {
      cpu->cpu_interpretor = cpu_interp_m6811;
      if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	{
	  /* Allocate core managed memory */

	  /* the monitor  */
	  sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
			   /* MONITOR_BASE, MONITOR_SIZE */
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
	  sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
          if (cpu->bank_start < cpu->bank_end)
            {
              sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
                               cpu->bank_virtual, M6811_RAM_LEVEL);
              sim_hw_parse (sd, "/m68hc11/use_bank 1");
            }
	}
      if (cpu->cpu_start_mode)
        {
          sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode);
        }
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
          sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	  sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	  sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	  /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	}
      sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
      cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
    }
  else
    {
      cpu->cpu_interpretor = cpu_interp_m6812;
      if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	{
	  /* Allocate core external memory.  */
	  sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
          if (cpu->bank_start < cpu->bank_end)
            {
              sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
                               cpu->bank_virtual, M6811_RAM_LEVEL);
              sim_hw_parse (sd, "/m68hc12/use_bank 1");
            }
	  sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	}

      if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
          sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	  sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	  sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	}

      sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
      cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
    }
  return 1;
}

/* Get the memory bank parameters by looking at the global symbols
   defined by the linker.  */
static int
sim_get_bank_parameters (SIM_DESC sd, bfd* abfd)
{
  sim_cpu *cpu;
  long symsize;
  long symbol_count, i;
  unsigned size;
  asymbol** asymbols;
  asymbol** current;

  cpu = STATE_CPU (sd, 0);

  symsize = bfd_get_symtab_upper_bound (abfd);
  if (symsize < 0)
    {
      sim_io_eprintf (sd, "Cannot read symbols of program");
      return 0;
    }
  asymbols = (asymbol **) xmalloc (symsize);
  symbol_count = bfd_canonicalize_symtab (abfd, asymbols);
  if (symbol_count < 0)
    {
      sim_io_eprintf (sd, "Cannot read symbols of program");
      return 0;
    }

  size = 0;
  for (i = 0, current = asymbols; i < symbol_count; i++, current++)
    {
      const char* name = bfd_asymbol_name (*current);

      if (strcmp (name, BFD_M68HC11_BANK_START_NAME) == 0)
        {
          cpu->bank_start = bfd_asymbol_value (*current);
        }
      else if (strcmp (name, BFD_M68HC11_BANK_SIZE_NAME) == 0)
        {
          size = bfd_asymbol_value (*current);
        }
      else if (strcmp (name, BFD_M68HC11_BANK_VIRTUAL_NAME) == 0)
        {
          cpu->bank_virtual = bfd_asymbol_value (*current);
        }
    }
  free (asymbols);

  cpu->bank_end = cpu->bank_start + size;
  cpu->bank_shift = 0;
  for (; size > 1; size >>= 1)
    cpu->bank_shift++;

  return 0;
}

static int
sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
{
  sim_cpu *cpu;
  int elf_flags = 0;

  cpu = STATE_CPU (sd, 0);

  if (abfd != NULL)
    {
      asection *s;

      if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
        elf_flags = elf_elfheader (abfd)->e_flags;

      cpu->cpu_elf_start = bfd_get_start_address (abfd);
      /* See if any section sets the reset address */
      cpu->cpu_use_elf_start = 1;
      for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next) 
        {
          if (s->flags & SEC_LOAD)
            {
              bfd_size_type size;

              size = bfd_get_section_size (s);
              if (size > 0)
                {
                  bfd_vma lma;

                  if (STATE_LOAD_AT_LMA_P (sd))
                    lma = bfd_section_lma (abfd, s);
                  else
                    lma = bfd_section_vma (abfd, s);

                  if (lma <= 0xFFFE && lma+size >= 0x10000)
                    cpu->cpu_use_elf_start = 0;
                }
            }
        }

      if (elf_flags & E_M68HC12_BANKS)
        {
          if (sim_get_bank_parameters (sd, abfd) != 0)
            sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
        }
    }

  if (!sim_hw_configure (sd))
    return SIM_RC_FAIL;

  /* reset all state information */
  sim_board_reset (sd);

  return SIM_RC_OK;
}

SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
          bfd *abfd, char **argv)
{
  SIM_DESC sd;
  sim_cpu *cpu;

  sd = sim_state_alloc (kind, callback);
  cpu = STATE_CPU (sd, 0);

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* for compatibility */
  current_alignment = NONSTRICT_ALIGNMENT;
  current_target_byte_order = BIG_ENDIAN;

  cpu_initialize (sd, cpu);

  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* getopt will print the error message so we just have to exit if this fails.
     FIXME: Hmmm...  in the case of gdb we need getopt to call
     print_filtered.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }

  /* Check for/establish the a reference program image.  */
  if (sim_analyze_program (sd,
			   (STATE_PROG_ARGV (sd) != NULL
			    ? *STATE_PROG_ARGV (sd)
			    : NULL), abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Establish any remaining configuration options.  */
  if (sim_config (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }
  if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }      

  /* Fudge our descriptor.  */
  return sd;
}


void
sim_close (SIM_DESC sd, int quitting)
{
  /* shut down modules */
  sim_module_uninstall (sd);

  /* Ensure that any resources allocated through the callback
     mechanism are released: */
  sim_io_shutdown (sd);

  /* FIXME - free SD */
  sim_state_free (sd);
  return;
}

/* Generic implementation of sim_engine_run that works within the
   sim_engine setjmp/longjmp framework. */

void
sim_engine_run (SIM_DESC sd,
                int next_cpu_nr,	/* ignore */
		int nr_cpus,	/* ignore */
		int siggnal)	/* ignore */
{
  sim_cpu *cpu;

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  cpu = STATE_CPU (sd, 0);
  while (1)
    {
      cpu_single_step (cpu);

      /* process any events */
      if (sim_events_tickn (sd, cpu->cpu_current_cycle))
	{
	  sim_events_process (sd);
	}
    }
}

void
sim_info (SIM_DESC sd, int verbose)
{
  const char *cpu_type;
  const struct bfd_arch_info *arch;

  /* Nothing to do if there is no verbose flag set.  */
  if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
    return;

  arch = STATE_ARCHITECTURE (sd);
  if (arch->arch == bfd_arch_m68hc11)
    cpu_type = "68HC11";
  else
    cpu_type = "68HC12";

  sim_io_eprintf (sd, "Simulator info:\n");
  sim_io_eprintf (sd, "  CPU Motorola %s\n", cpu_type);
  sim_get_info (sd, 0);
  sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
}

SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
                     char **argv, char **env)
{
  return sim_prepare_for_program (sd, abfd);
}

int
sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
{
  sim_cpu *cpu;
  uint16 val;
  int size = 2;

  cpu = STATE_CPU (sd, 0);
  switch (rn)
    {
    case A_REGNUM:
      val = cpu_get_a (cpu);
      size = 1;
      break;

    case B_REGNUM:
      val = cpu_get_b (cpu);
      size = 1;
      break;

    case D_REGNUM:
      val = cpu_get_d (cpu);
      break;

    case X_REGNUM:
      val = cpu_get_x (cpu);
      break;

    case Y_REGNUM:
      val = cpu_get_y (cpu);
      break;

    case SP_REGNUM:
      val = cpu_get_sp (cpu);
      break;

    case PC_REGNUM:
      val = cpu_get_pc (cpu);
      break;

    case PSW_REGNUM:
      val = cpu_get_ccr (cpu);
      size = 1;
      break;

    case PAGE_REGNUM:
      val = cpu_get_page (cpu);
      size = 1;
      break;

    default:
      val = 0;
      break;
    }
  if (size == 1)
    {
      memory[0] = val;
    }
  else
    {
      memory[0] = val >> 8;
      memory[1] = val & 0x0FF;
    }
  return size;
}

int
sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
{
  uint16 val;
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);

  val = *memory++;
  if (length == 2)
    val = (val << 8) | *memory;

  switch (rn)
    {
    case D_REGNUM:
      cpu_set_d (cpu, val);
      break;

    case A_REGNUM:
      cpu_set_a (cpu, val);
      return 1;

    case B_REGNUM:
      cpu_set_b (cpu, val);
      return 1;

    case X_REGNUM:
      cpu_set_x (cpu, val);
      break;

    case Y_REGNUM:
      cpu_set_y (cpu, val);
      break;

    case SP_REGNUM:
      cpu_set_sp (cpu, val);
      break;

    case PC_REGNUM:
      cpu_set_pc (cpu, val);
      break;

    case PSW_REGNUM:
      cpu_set_ccr (cpu, val);
      return 1;

    case PAGE_REGNUM:
      cpu_set_page (cpu, val);
      return 1;

    default:
      break;
    }

  return 2;
}

sim_cia
sim_pc_get (sim_cpu *cpu)
{
  return CIA_GET (cpu);
}

/* Halt the simulator after just one instruction */

static void
has_stepped (SIM_DESC sd,
	     void *data)
{
  ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP);
}


/* Generic resume - assumes the existance of sim_engine_run */

void
sim_resume (SIM_DESC sd,
	    int step,
	    int siggnal)
{
  sim_engine *engine = STATE_ENGINE (sd);
  jmp_buf buf;
  int jmpval;

  ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* we only want to be single stepping the simulator once */
  if (engine->stepper != NULL)
    {
      sim_events_deschedule (sd, engine->stepper);
      engine->stepper = NULL;
    }
  sim_module_resume (sd);

  /* run/resume the simulator */
  engine->jmpbuf = &buf;
  jmpval = setjmp (buf);
  if (jmpval == sim_engine_start_jmpval
      || jmpval == sim_engine_restart_jmpval)
    {
      int last_cpu_nr = sim_engine_last_cpu_nr (sd);
      int next_cpu_nr = sim_engine_next_cpu_nr (sd);
      int nr_cpus = sim_engine_nr_cpus (sd);

      sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus);
      if (next_cpu_nr >= nr_cpus)
	next_cpu_nr = 0;

      /* Only deliver the siggnal ]sic] the first time through - don't
         re-deliver any siggnal during a restart. */
      if (jmpval == sim_engine_restart_jmpval)
	siggnal = 0;

      /* Install the stepping event after having processed some
         pending events.  This is necessary for HC11/HC12 simulator
         because the tick counter is incremented by the number of cycles
         the instruction took.  Some pending ticks to process can still
         be recorded internally by the simulator and sim_events_preprocess
         will handle them.  If the stepping event is inserted before,
         these pending ticks will raise the event and the simulator will
         stop without having executed any instruction.  */
      if (step)
        engine->stepper = sim_events_schedule (sd, 0, has_stepped, sd);

#ifdef SIM_CPU_EXCEPTION_RESUME
      {
	sim_cpu* cpu = STATE_CPU (sd, next_cpu_nr);
	SIM_CPU_EXCEPTION_RESUME(sd, cpu, siggnal);
      }
#endif

      sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal);
    }
  engine->jmpbuf = NULL;

  sim_module_suspend (sd);
}
Commit	Line	Data
5abb9efa	1	/* interp.c -- Simulator for Motorola 68HC11/68HC12
32d0add0	2	Copyright (C) 1999-2015 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
e0709f50 AC	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
e0709f50 AC	19
	20	#include "sim-main.h"
	21	#include "sim-assert.h"
	22	#include "sim-hw.h"
	23	#include "sim-options.h"
	24	#include "hw-tree.h"
	25	#include "hw-device.h"
	26	#include "hw-ports.h"
77342e5e	27	#include "elf32-m68hc1x.h"
e0709f50 AC	28
	29	#ifndef MONITOR_BASE
	30	# define MONITOR_BASE (0x0C000)
	31	# define MONITOR_SIZE (0x04000)
	32	#endif
	33
	34	static void sim_get_info (SIM_DESC sd, char *cmd);
	35
	36
	37	char *interrupt_names[] = {
	38	"reset",
	39	"nmi",
	40	"int",
	41	NULL
	42	};
	43
	44	#ifndef INLINE
	45	#if defined(__GNUC__) && defined(__OPTIMIZE__)
	46	#define INLINE __inline__
	47	#else
	48	#define INLINE
	49	#endif
	50	#endif
	51
	52	struct sim_info_list
	53	{
	54	const char *name;
	55	const char *device;
	56	};
	57
81e09ed8	58	struct sim_info_list dev_list_68hc11[] = {
e0709f50 AC	59	{"cpu", "/m68hc11"},
	60	{"timer", "/m68hc11/m68hc11tim"},
	61	{"sio", "/m68hc11/m68hc11sio"},
	62	{"spi", "/m68hc11/m68hc11spi"},
	63	{"eeprom", "/m68hc11/m68hc11eepr"},
	64	{0, 0}
	65	};
	66
81e09ed8 SC	67	struct sim_info_list dev_list_68hc12[] = {
	68	{"cpu", "/m68hc12"},
	69	{"timer", "/m68hc12/m68hc12tim"},
	70	{"sio", "/m68hc12/m68hc12sio"},
	71	{"spi", "/m68hc12/m68hc12spi"},
	72	{"eeprom", "/m68hc12/m68hc12eepr"},
	73	{0, 0}
	74	};
	75
	76	/* Cover function of sim_state_free to free the cpu buffers as well. */
	77
	78	static void
	79	free_state (SIM_DESC sd)
	80	{
	81	if (STATE_MODULES (sd) != NULL)
	82	sim_module_uninstall (sd);
	83
	84	sim_state_free (sd);
	85	}
	86
e0709f50 AC	87	/* Give some information about the simulator. */
	88	static void
	89	sim_get_info (SIM_DESC sd, char *cmd)
	90	{
	91	sim_cpu *cpu;
	92
81e09ed8	93	cpu = STATE_CPU (sd, 0);
e0709f50 AC	94	if (cmd != 0 && (cmd[0] == ' ' \|\| cmd[0] == '-'))
	95	{
	96	int i;
	97	struct hw *hw_dev;
81e09ed8 SC	98	struct sim_info_list *dev_list;
	99	const struct bfd_arch_info *arch;
	100
	101	arch = STATE_ARCHITECTURE (sd);
e0709f50 AC	102	cmd++;
e0709f50 AC	103
81e09ed8 SC	104	if (arch->arch == bfd_arch_m68hc11)
	105	dev_list = dev_list_68hc11;
	106	else
	107	dev_list = dev_list_68hc12;
	108
e0709f50 AC	109	for (i = 0; dev_list[i].name; i++)
	110	if (strcmp (cmd, dev_list[i].name) == 0)
	111	break;
	112
	113	if (dev_list[i].name == 0)
	114	{
	115	sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	116	sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	117	return;
	118	}
	119	hw_dev = sim_hw_parse (sd, dev_list[i].device);
	120	if (hw_dev == 0)
	121	{
	122	sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	123	return;
	124	}
	125	hw_ioctl (hw_dev, 23, 0);
	126	return;
	127	}
	128
e0709f50 AC	129	cpu_info (sd, cpu);
	130	interrupts_info (sd, &cpu->cpu_interrupts);
	131	}
	132
	133
	134	void
	135	sim_board_reset (SIM_DESC sd)
	136	{
	137	struct hw *hw_cpu;
	138	sim_cpu *cpu;
81e09ed8 SC	139	const struct bfd_arch_info *arch;
81e09ed8 SC	140	const char *cpu_type;
e0709f50 AC	141
e0709f50 AC	142	cpu = STATE_CPU (sd, 0);
81e09ed8 SC	143	arch = STATE_ARCHITECTURE (sd);
81e09ed8 SC	144
e0709f50	145	/* hw_cpu = sim_hw_parse (sd, "/"); */
81e09ed8 SC	146	if (arch->arch == bfd_arch_m68hc11)
	147	{
	148	cpu->cpu_type = CPU_M6811;
	149	cpu_type = "/m68hc11";
	150	}
	151	else
	152	{
	153	cpu->cpu_type = CPU_M6812;
	154	cpu_type = "/m68hc12";
	155	}
	156
	157	hw_cpu = sim_hw_parse (sd, cpu_type);
e0709f50 AC	158	if (hw_cpu == 0)
e0709f50 AC	159	{
81e09ed8	160	sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
e0709f50 AC	161	return;
	162	}
	163
	164	cpu_reset (cpu);
	165	hw_port_event (hw_cpu, 3, 0);
	166	cpu_restart (cpu);
	167	}
	168
39762100	169	static int
81e09ed8 SC	170	sim_hw_configure (SIM_DESC sd)
	171	{
	172	const struct bfd_arch_info *arch;
	173	struct hw *device_tree;
81e09ed8 SC	174	sim_cpu *cpu;
	175
	176	arch = STATE_ARCHITECTURE (sd);
	177	if (arch == 0)
	178	return 0;
	179
	180	cpu = STATE_CPU (sd, 0);
	181	cpu->cpu_configured_arch = arch;
	182	device_tree = sim_hw_parse (sd, "/");
	183	if (arch->arch == bfd_arch_m68hc11)
	184	{
	185	cpu->cpu_interpretor = cpu_interp_m6811;
	186	if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	187	{
	188	/* Allocate core managed memory */
	189
	190	/* the monitor */
	191	sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
	192	/* MONITOR_BASE, MONITOR_SIZE */
	193	0x8000, M6811_RAM_LEVEL, 0x8000);
	194	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
	195	M6811_RAM_LEVEL);
	196	sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
77342e5e SC	197	if (cpu->bank_start < cpu->bank_end)
	198	{
	199	sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
	200	cpu->bank_virtual, M6811_RAM_LEVEL);
	201	sim_hw_parse (sd, "/m68hc11/use_bank 1");
	202	}
81e09ed8	203	}
77342e5e SC	204	if (cpu->cpu_start_mode)
	205	{
	206	sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode);
	207	}
81e09ed8 SC	208	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	209	{
	210	sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	211	sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	212	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	213	}
	214	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	215	{
	216	/* M68hc11 Timer configuration. */
	217	sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	218	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
827ec39a	219	sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
81e09ed8 SC	220	}
	221
	222	/* Create the SPI device. */
	223	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	224	{
	225	sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	226	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	227	}
	228	if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	229	{
	230	/* M68hc11 persistent ram configuration. */
	231	sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	232	sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	233	sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	234	/sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); /
	235	}
	236	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	237	{
	238	sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	239	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	240	}
dcceded2 SC	241	sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
	242	sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
	243	sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
	244	sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
827ec39a	245	cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
81e09ed8 SC	246	}
	247	else
	248	{
	249	cpu->cpu_interpretor = cpu_interp_m6812;
	250	if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	251	{
	252	/* Allocate core external memory. */
	253	sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
77342e5e	254	0x8000, M6811_RAM_LEVEL, 0x8000);
81e09ed8 SC	255	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
81e09ed8 SC	256	M6811_RAM_LEVEL);
77342e5e SC	257	if (cpu->bank_start < cpu->bank_end)
	258	{
	259	sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
	260	cpu->bank_virtual, M6811_RAM_LEVEL);
	261	sim_hw_parse (sd, "/m68hc12/use_bank 1");
	262	}
81e09ed8 SC	263	sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	264	}
	265
	266	if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	267	{
	268	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	269	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	270	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	271	}
81e09ed8 SC	272	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	273	{
	274	/* M68hc11 Timer configuration. */
	275	sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	276	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
dcceded2	277	sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
81e09ed8 SC	278	}
	279
	280	/* Create the SPI device. */
	281	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	282	{
	283	sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	284	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	285	}
	286	if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	287	{
	288	/* M68hc11 persistent ram configuration. */
	289	sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	290	sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	291	sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	292	}
	293	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	294	{
	295	sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	296	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	297	}
827ec39a	298
dcceded2 SC	299	sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
	300	sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
	301	sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
	302	sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
827ec39a	303	cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
81e09ed8	304	}
39762100	305	return 1;
81e09ed8 SC	306	}
81e09ed8 SC	307
77342e5e SC	308	/* Get the memory bank parameters by looking at the global symbols
77342e5e SC	309	defined by the linker. */
81e09ed8	310	static int
77342e5e	311	sim_get_bank_parameters (SIM_DESC sd, bfd* abfd)
81e09ed8 SC	312	{
81e09ed8 SC	313	sim_cpu *cpu;
77342e5e SC	314	long symsize;
	315	long symbol_count, i;
	316	unsigned size;
	317	asymbol** asymbols;
	318	asymbol** current;
81e09ed8 SC	319
	320	cpu = STATE_CPU (sd, 0);
	321
77342e5e SC	322	symsize = bfd_get_symtab_upper_bound (abfd);
	323	if (symsize < 0)
	324	{
	325	sim_io_eprintf (sd, "Cannot read symbols of program");
	326	return 0;
	327	}
	328	asymbols = (asymbol **) xmalloc (symsize);
	329	symbol_count = bfd_canonicalize_symtab (abfd, asymbols);
	330	if (symbol_count < 0)
	331	{
	332	sim_io_eprintf (sd, "Cannot read symbols of program");
	333	return 0;
	334	}
	335
	336	size = 0;
	337	for (i = 0, current = asymbols; i < symbol_count; i++, current++)
	338	{
	339	const char* name = bfd_asymbol_name (*current);
	340
	341	if (strcmp (name, BFD_M68HC11_BANK_START_NAME) == 0)
	342	{
	343	cpu->bank_start = bfd_asymbol_value (*current);
	344	}
	345	else if (strcmp (name, BFD_M68HC11_BANK_SIZE_NAME) == 0)
	346	{
	347	size = bfd_asymbol_value (*current);
	348	}
	349	else if (strcmp (name, BFD_M68HC11_BANK_VIRTUAL_NAME) == 0)
	350	{
	351	cpu->bank_virtual = bfd_asymbol_value (*current);
	352	}
	353	}
	354	free (asymbols);
	355
	356	cpu->bank_end = cpu->bank_start + size;
	357	cpu->bank_shift = 0;
	358	for (; size > 1; size >>= 1)
	359	cpu->bank_shift++;
	360
	361	return 0;
	362	}
	363
	364	static int
	365	sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
	366	{
	367	sim_cpu *cpu;
	368	int elf_flags = 0;
	369
	370	cpu = STATE_CPU (sd, 0);
39762100	371
81e09ed8 SC	372	if (abfd != NULL)
81e09ed8 SC	373	{
31c7c532	374	asection *s;
77342e5e SC	375
	376	if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
	377	elf_flags = elf_elfheader (abfd)->e_flags;
	378
81e09ed8	379	cpu->cpu_elf_start = bfd_get_start_address (abfd);
31c7c532 SC	380	/* See if any section sets the reset address */
	381	cpu->cpu_use_elf_start = 1;
	382	for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next)
	383	{
	384	if (s->flags & SEC_LOAD)
	385	{
	386	bfd_size_type size;
	387
84b11e2e	388	size = bfd_get_section_size (s);
31c7c532 SC	389	if (size > 0)
	390	{
	391	bfd_vma lma;
	392
	393	if (STATE_LOAD_AT_LMA_P (sd))
	394	lma = bfd_section_lma (abfd, s);
	395	else
	396	lma = bfd_section_vma (abfd, s);
	397
	398	if (lma <= 0xFFFE && lma+size >= 0x10000)
	399	cpu->cpu_use_elf_start = 0;
	400	}
	401	}
	402	}
77342e5e SC	403
	404	if (elf_flags & E_M68HC12_BANKS)
	405	{
	406	if (sim_get_bank_parameters (sd, abfd) != 0)
	407	sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
	408	}
81e09ed8 SC	409	}
81e09ed8 SC	410
77342e5e SC	411	if (!sim_hw_configure (sd))
	412	return SIM_RC_FAIL;
	413
81e09ed8 SC	414	/* reset all state information */
	415	sim_board_reset (sd);
	416
	417	return SIM_RC_OK;
	418	}
	419
e0709f50 AC	420	SIM_DESC
e0709f50 AC	421	sim_open (SIM_OPEN_KIND kind, host_callback *callback,
77342e5e	422	bfd abfd, char *argv)
e0709f50	423	{
e0709f50 AC	424	SIM_DESC sd;
e0709f50 AC	425	sim_cpu *cpu;
e0709f50 AC	426
	427	sd = sim_state_alloc (kind, callback);
	428	cpu = STATE_CPU (sd, 0);
	429
	430	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	431
	432	/* for compatibility */
	433	current_alignment = NONSTRICT_ALIGNMENT;
	434	current_target_byte_order = BIG_ENDIAN;
	435
	436	cpu_initialize (sd, cpu);
	437
e0709f50	438	if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
81e09ed8 SC	439	{
	440	free_state (sd);
	441	return 0;
	442	}
e0709f50 AC	443
	444	/* getopt will print the error message so we just have to exit if this fails.
	445	FIXME: Hmmm... in the case of gdb we need getopt to call
	446	print_filtered. */
	447	if (sim_parse_args (sd, argv) != SIM_RC_OK)
	448	{
	449	/* Uninstall the modules to avoid memory leaks,
	450	file descriptor leaks, etc. */
81e09ed8	451	free_state (sd);
e0709f50 AC	452	return 0;
	453	}
	454
e0709f50 AC	455	/* Check for/establish the a reference program image. */
	456	if (sim_analyze_program (sd,
	457	(STATE_PROG_ARGV (sd) != NULL
	458	? *STATE_PROG_ARGV (sd)
	459	: NULL), abfd) != SIM_RC_OK)
	460	{
81e09ed8	461	free_state (sd);
e0709f50 AC	462	return 0;
	463	}
	464
	465	/* Establish any remaining configuration options. */
	466	if (sim_config (sd) != SIM_RC_OK)
	467	{
81e09ed8	468	free_state (sd);
e0709f50 AC	469	return 0;
	470	}
	471
	472	if (sim_post_argv_init (sd) != SIM_RC_OK)
	473	{
	474	/* Uninstall the modules to avoid memory leaks,
	475	file descriptor leaks, etc. */
81e09ed8	476	free_state (sd);
e0709f50 AC	477	return 0;
e0709f50 AC	478	}
77342e5e SC	479	if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
	480	{
	481	free_state (sd);
	482	return 0;
	483	}
e0709f50 AC	484
	485	/* Fudge our descriptor. */
	486	return sd;
	487	}
	488
	489
	490	void
	491	sim_close (SIM_DESC sd, int quitting)
	492	{
	493	/* shut down modules */
	494	sim_module_uninstall (sd);
	495
	496	/* Ensure that any resources allocated through the callback
	497	mechanism are released: */
	498	sim_io_shutdown (sd);
	499
	500	/* FIXME - free SD */
81e09ed8	501	sim_state_free (sd);
e0709f50 AC	502	return;
	503	}
	504
e0709f50 AC	505	/* Generic implementation of sim_engine_run that works within the
	506	sim_engine setjmp/longjmp framework. */
	507
	508	void
	509	sim_engine_run (SIM_DESC sd,
	510	int next_cpu_nr, /* ignore */
	511	int nr_cpus, /* ignore */
	512	int siggnal) /* ignore */
	513	{
	514	sim_cpu *cpu;
	515
	516	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	517	cpu = STATE_CPU (sd, 0);
	518	while (1)
	519	{
	520	cpu_single_step (cpu);
	521
	522	/* process any events */
	523	if (sim_events_tickn (sd, cpu->cpu_current_cycle))
	524	{
	525	sim_events_process (sd);
	526	}
	527	}
	528	}
	529
e0709f50 AC	530	void
	531	sim_info (SIM_DESC sd, int verbose)
	532	{
81e09ed8 SC	533	const char *cpu_type;
	534	const struct bfd_arch_info *arch;
	535
00d0c012 SC	536	/* Nothing to do if there is no verbose flag set. */
	537	if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
	538	return;
	539
81e09ed8 SC	540	arch = STATE_ARCHITECTURE (sd);
	541	if (arch->arch == bfd_arch_m68hc11)
	542	cpu_type = "68HC11";
	543	else
	544	cpu_type = "68HC12";
	545
e0709f50	546	sim_io_eprintf (sd, "Simulator info:\n");
81e09ed8	547	sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
e0709f50 AC	548	sim_get_info (sd, 0);
	549	sim_module_info (sd, verbose \|\| STATE_VERBOSE_P (sd));
	550	}
	551
	552	SIM_RC
6b4a8935	553	sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
e0709f50 AC	554	char argv, char env)
e0709f50 AC	555	{
81e09ed8	556	return sim_prepare_for_program (sd, abfd);
e0709f50 AC	557	}
e0709f50 AC	558
e0709f50 AC	559	int
	560	sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
	561	{
	562	sim_cpu *cpu;
	563	uint16 val;
63f36def	564	int size = 2;
e0709f50 AC	565
	566	cpu = STATE_CPU (sd, 0);
	567	switch (rn)
	568	{
	569	case A_REGNUM:
	570	val = cpu_get_a (cpu);
63f36def	571	size = 1;
e0709f50 AC	572	break;
	573
	574	case B_REGNUM:
	575	val = cpu_get_b (cpu);
63f36def	576	size = 1;
e0709f50 AC	577	break;
	578
	579	case D_REGNUM:
	580	val = cpu_get_d (cpu);
	581	break;
	582
	583	case X_REGNUM:
	584	val = cpu_get_x (cpu);
	585	break;
	586
	587	case Y_REGNUM:
	588	val = cpu_get_y (cpu);
	589	break;
	590
	591	case SP_REGNUM:
	592	val = cpu_get_sp (cpu);
	593	break;
	594
	595	case PC_REGNUM:
	596	val = cpu_get_pc (cpu);
	597	break;
	598
	599	case PSW_REGNUM:
	600	val = cpu_get_ccr (cpu);
63f36def SC	601	size = 1;
	602	break;
	603
	604	case PAGE_REGNUM:
	605	val = cpu_get_page (cpu);
	606	size = 1;
e0709f50 AC	607	break;
e0709f50 AC	608
e0709f50	609	default:
9830501b	610	val = 0;
e0709f50 AC	611	break;
e0709f50 AC	612	}
00416c6e SC	613	if (size == 1)
	614	{
	615	memory[0] = val;
	616	}
	617	else
	618	{
	619	memory[0] = val >> 8;
	620	memory[1] = val & 0x0FF;
	621	}
63f36def	622	return size;
e0709f50 AC	623	}
	624
	625	int
	626	sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
	627	{
	628	uint16 val;
	629	sim_cpu *cpu;
	630
	631	cpu = STATE_CPU (sd, 0);
	632
	633	val = *memory++;
	634	if (length == 2)
	635	val = (val << 8) \| *memory;
	636
	637	switch (rn)
	638	{
	639	case D_REGNUM:
	640	cpu_set_d (cpu, val);
	641	break;
	642
	643	case A_REGNUM:
	644	cpu_set_a (cpu, val);
63f36def	645	return 1;
e0709f50 AC	646
	647	case B_REGNUM:
	648	cpu_set_b (cpu, val);
63f36def	649	return 1;
e0709f50 AC	650
	651	case X_REGNUM:
	652	cpu_set_x (cpu, val);
	653	break;
	654
	655	case Y_REGNUM:
	656	cpu_set_y (cpu, val);
	657	break;
	658
	659	case SP_REGNUM:
	660	cpu_set_sp (cpu, val);
	661	break;
	662
	663	case PC_REGNUM:
	664	cpu_set_pc (cpu, val);
	665	break;
	666
	667	case PSW_REGNUM:
	668	cpu_set_ccr (cpu, val);
63f36def SC	669	return 1;
	670
	671	case PAGE_REGNUM:
	672	cpu_set_page (cpu, val);
	673	return 1;
e0709f50	674
e0709f50	675	default:
e0709f50 AC	676	break;
	677	}
	678
	679	return 2;
	680	}
	681
05f53ed6 MF	682	sim_cia
	683	sim_pc_get (sim_cpu *cpu)
	684	{
	685	return CIA_GET (cpu);
	686	}
	687
00d0c012 SC	688	/* Halt the simulator after just one instruction */
	689
	690	static void
	691	has_stepped (SIM_DESC sd,
	692	void *data)
	693	{
	694	ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	695	sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP);
	696	}
	697
	698
	699	/* Generic resume - assumes the existance of sim_engine_run */
	700
	701	void
	702	sim_resume (SIM_DESC sd,
	703	int step,
	704	int siggnal)
	705	{
	706	sim_engine *engine = STATE_ENGINE (sd);
	707	jmp_buf buf;
	708	int jmpval;
	709
	710	ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	711
	712	/* we only want to be single stepping the simulator once */
	713	if (engine->stepper != NULL)
	714	{
	715	sim_events_deschedule (sd, engine->stepper);
	716	engine->stepper = NULL;
	717	}
	718	sim_module_resume (sd);
	719
	720	/* run/resume the simulator */
	721	engine->jmpbuf = &buf;
	722	jmpval = setjmp (buf);
	723	if (jmpval == sim_engine_start_jmpval
	724	\|\| jmpval == sim_engine_restart_jmpval)
	725	{
	726	int last_cpu_nr = sim_engine_last_cpu_nr (sd);
	727	int next_cpu_nr = sim_engine_next_cpu_nr (sd);
	728	int nr_cpus = sim_engine_nr_cpus (sd);
	729
	730	sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus);
	731	if (next_cpu_nr >= nr_cpus)
	732	next_cpu_nr = 0;
	733
	734	/* Only deliver the siggnal ]sic] the first time through - don't
	735	re-deliver any siggnal during a restart. */
	736	if (jmpval == sim_engine_restart_jmpval)
	737	siggnal = 0;
	738
	739	/* Install the stepping event after having processed some
	740	pending events. This is necessary for HC11/HC12 simulator
	741	because the tick counter is incremented by the number of cycles
	742	the instruction took. Some pending ticks to process can still
	743	be recorded internally by the simulator and sim_events_preprocess
	744	will handle them. If the stepping event is inserted before,
	745	these pending ticks will raise the event and the simulator will
	746	stop without having executed any instruction. */
	747	if (step)
	748	engine->stepper = sim_events_schedule (sd, 0, has_stepped, sd);
	749
	750	#ifdef SIM_CPU_EXCEPTION_RESUME
	751	{
752	sim_cpu* cpu = STATE_CPU (sd, next_cpu_nr);
753	SIM_CPU_EXCEPTION_RESUME(sd, cpu, siggnal);
754	}
755	#endif
756
757	sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal);
758	}
759	engine->jmpbuf = NULL;
760
761	sim_module_suspend (sd);
762	}