[thirdparty/binutils-gdb.git] / sim / m68hc11 / interp.c

/* interp.c -- Simulator for Motorola 68HC11/68HC12
   Copyright (C) 1999-2024 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This must come before any other includes.  */
#include "defs.h"

#include "bfd.h"

#include "sim-main.h"
#include "sim-assert.h"
#include "sim-hw.h"
#include "sim-options.h"
#include "hw-tree.h"
#include "hw-device.h"
#include "hw-ports.h"
#include "bfd/elf32-m68hc1x.h"

#include "m68hc11-sim.h"

#ifndef MONITOR_BASE
# define MONITOR_BASE (0x0C000)
# define MONITOR_SIZE (0x04000)
#endif

static void sim_get_info (SIM_DESC sd, char *cmd);

struct sim_info_list
{
  const char *name;
  const char *device;
};

struct sim_info_list dev_list_68hc11[] = {
  {"cpu", "/m68hc11"},
  {"timer", "/m68hc11/m68hc11tim"},
  {"sio", "/m68hc11/m68hc11sio"},
  {"spi", "/m68hc11/m68hc11spi"},
  {"eeprom", "/m68hc11/m68hc11eepr"},
  {0, 0}
};

struct sim_info_list dev_list_68hc12[] = {
  {"cpu", "/m68hc12"},
  {"timer", "/m68hc12/m68hc12tim"},
  {"sio", "/m68hc12/m68hc12sio"},
  {"spi", "/m68hc12/m68hc12spi"},
  {"eeprom", "/m68hc12/m68hc12eepr"},
  {0, 0}
};

/* Cover function of sim_state_free to free the cpu buffers as well.  */

static void
free_state (SIM_DESC sd)
{
  if (STATE_MODULES (sd) != NULL)
    sim_module_uninstall (sd);

  sim_state_free (sd);
}

/* Give some information about the simulator.  */
static void
sim_get_info (SIM_DESC sd, char *cmd)
{
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);
  if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
    {
      int i;
      struct hw *hw_dev;
      struct sim_info_list *dev_list;
      const struct bfd_arch_info *arch;

      arch = STATE_ARCHITECTURE (sd);
      cmd++;

      if (arch->arch == bfd_arch_m68hc11)
        dev_list = dev_list_68hc11;
      else
        dev_list = dev_list_68hc12;

      for (i = 0; dev_list[i].name; i++)
	if (strcmp (cmd, dev_list[i].name) == 0)
	  break;

      if (dev_list[i].name == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	  sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	  return;
	}
      hw_dev = sim_hw_parse (sd, "%s", dev_list[i].device);
      if (hw_dev == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	  return;
	}
      hw_ioctl (hw_dev, 23, 0);
      return;
    }

  cpu_info (sd, cpu);
  interrupts_info (sd, &M68HC11_SIM_CPU (cpu)->cpu_interrupts);
}


void
sim_board_reset (SIM_DESC sd)
{
  struct hw *hw_cpu;
  sim_cpu *cpu;
  struct m68hc11_sim_cpu *m68hc11_cpu;
  const struct bfd_arch_info *arch;
  const char *cpu_type;

  cpu = STATE_CPU (sd, 0);
  m68hc11_cpu = M68HC11_SIM_CPU (cpu);
  arch = STATE_ARCHITECTURE (sd);

  /*  hw_cpu = sim_hw_parse (sd, "/"); */
  if (arch->arch == bfd_arch_m68hc11)
    {
      m68hc11_cpu->cpu_type = CPU_M6811;
      cpu_type = "/m68hc11";
    }
  else
    {
      m68hc11_cpu->cpu_type = CPU_M6812;
      cpu_type = "/m68hc12";
    }
  
  hw_cpu = sim_hw_parse (sd, "%s", cpu_type);
  if (hw_cpu == 0)
    {
      sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
      return;
    }

  cpu_reset (cpu);
  hw_port_event (hw_cpu, 3, 0);
  cpu_restart (cpu);
}

static int
sim_hw_configure (SIM_DESC sd)
{
  const struct bfd_arch_info *arch;
  struct hw *device_tree;
  sim_cpu *cpu;
  struct m68hc11_sim_cpu *m68hc11_cpu;
  
  arch = STATE_ARCHITECTURE (sd);
  if (arch == 0)
    return 0;

  cpu = STATE_CPU (sd, 0);
  m68hc11_cpu = M68HC11_SIM_CPU (cpu);
  m68hc11_cpu->cpu_configured_arch = arch;
  device_tree = sim_hw_parse (sd, "/");
  if (arch->arch == bfd_arch_m68hc11)
    {
      m68hc11_cpu->cpu_interpretor = cpu_interp_m6811;
      if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	{
	  /* Allocate core managed memory */

	  /* the monitor  */
	  sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
			   /* MONITOR_BASE, MONITOR_SIZE */
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
	  sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
          if (m68hc11_cpu->bank_start < m68hc11_cpu->bank_end)
            {
              sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
                               m68hc11_cpu->bank_virtual, M6811_RAM_LEVEL);
              sim_hw_parse (sd, "/m68hc11/use_bank 1");
            }
	}
      if (m68hc11_cpu->cpu_start_mode)
        {
          sim_hw_parse (sd, "/m68hc11/mode %s", m68hc11_cpu->cpu_start_mode);
        }
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
          sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	  sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	  sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	  /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	}
      sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
      m68hc11_cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
    }
  else
    {
      m68hc11_cpu->cpu_interpretor = cpu_interp_m6812;
      if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	{
	  /* Allocate core external memory.  */
	  sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
          if (m68hc11_cpu->bank_start < m68hc11_cpu->bank_end)
            {
              sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
                               m68hc11_cpu->bank_virtual, M6811_RAM_LEVEL);
              sim_hw_parse (sd, "/m68hc12/use_bank 1");
            }
	  sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	}

      if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
          sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	  sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	  sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	}

      sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
      m68hc11_cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
    }
  return 1;
}

/* Get the memory bank parameters by looking at the global symbols
   defined by the linker.  */
static int
sim_get_bank_parameters (SIM_DESC sd)
{
  sim_cpu *cpu;
  struct m68hc11_sim_cpu *m68hc11_cpu;
  unsigned size;
  bfd_vma addr;

  cpu = STATE_CPU (sd, 0);
  m68hc11_cpu = M68HC11_SIM_CPU (cpu);

  addr = trace_sym_value (sd, BFD_M68HC11_BANK_START_NAME);
  if (addr != -1)
    m68hc11_cpu->bank_start = addr;

  size = trace_sym_value (sd, BFD_M68HC11_BANK_SIZE_NAME);
  if (size == -1)
    size = 0;

  addr = trace_sym_value (sd, BFD_M68HC11_BANK_VIRTUAL_NAME);
  if (addr != -1)
    m68hc11_cpu->bank_virtual = addr;

  m68hc11_cpu->bank_end = m68hc11_cpu->bank_start + size;
  m68hc11_cpu->bank_shift = 0;
  for (; size > 1; size >>= 1)
    m68hc11_cpu->bank_shift++;

  return 0;
}

static int
sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
{
  sim_cpu *cpu;
  struct m68hc11_sim_cpu *m68hc11_cpu;
  int elf_flags = 0;

  cpu = STATE_CPU (sd, 0);
  m68hc11_cpu = M68HC11_SIM_CPU (cpu);

  if (abfd != NULL)
    {
      asection *s;

      if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
        elf_flags = elf_elfheader (abfd)->e_flags;

      m68hc11_cpu->cpu_elf_start = bfd_get_start_address (abfd);
      /* See if any section sets the reset address */
      m68hc11_cpu->cpu_use_elf_start = 1;
      for (s = abfd->sections; s && m68hc11_cpu->cpu_use_elf_start; s = s->next)
        {
          if (s->flags & SEC_LOAD)
            {
              bfd_size_type size;

	      size = bfd_section_size (s);
              if (size > 0)
                {
                  bfd_vma lma;

                  if (STATE_LOAD_AT_LMA_P (sd))
		    lma = bfd_section_lma (s);
                  else
		    lma = bfd_section_vma (s);

                  if (lma <= 0xFFFE && lma+size >= 0x10000)
                    m68hc11_cpu->cpu_use_elf_start = 0;
                }
            }
        }

      if (elf_flags & E_M68HC12_BANKS)
        {
          if (sim_get_bank_parameters (sd) != 0)
            sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
        }
    }

  if (!sim_hw_configure (sd))
    return SIM_RC_FAIL;

  /* reset all state information */
  sim_board_reset (sd);

  return SIM_RC_OK;
}

static sim_cia
m68hc11_pc_get (sim_cpu *cpu)
{
  return cpu_get_pc (cpu);
}

static void
m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
{
  cpu_set_pc (cpu, pc);
}

static int m68hc11_reg_fetch (SIM_CPU *, int, void *, int);
static int m68hc11_reg_store (SIM_CPU *, int, const void *, int);

SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
	  bfd *abfd, char * const *argv)
{
  int i;
  SIM_DESC sd;
  sim_cpu *cpu;

  sd = sim_state_alloc (kind, callback);

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* Set default options before parsing user options.  */
  current_target_byte_order = BFD_ENDIAN_BIG;

  /* The cpu data is kept in a separately allocated chunk of memory.  */
  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct m68hc11_sim_cpu))
      != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  cpu = STATE_CPU (sd, 0);

  cpu_initialize (sd, cpu);

  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* The parser will print an error message for us, so we silently return.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }

  /* Check for/establish the a reference program image.  */
  if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Establish any remaining configuration options.  */
  if (sim_config (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }
  if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }      

  /* CPU specific initialization.  */
  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
    {
      cpu = STATE_CPU (sd, i);

      CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
      CPU_REG_STORE (cpu) = m68hc11_reg_store;
      CPU_PC_FETCH (cpu) = m68hc11_pc_get;
      CPU_PC_STORE (cpu) = m68hc11_pc_set;
    }

  return sd;
}

/* Generic implementation of sim_engine_run that works within the
   sim_engine setjmp/longjmp framework. */

void
sim_engine_run (SIM_DESC sd,
                int next_cpu_nr,	/* ignore */
		int nr_cpus,	/* ignore */
		int siggnal)	/* ignore */
{
  sim_cpu *cpu;

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  cpu = STATE_CPU (sd, 0);
  while (1)
    {
      cpu_single_step (cpu);

      /* process any events */
      if (sim_events_tickn (sd, M68HC11_SIM_CPU (cpu)->cpu_current_cycle))
	{
	  sim_events_process (sd);
	}
    }
}

void
sim_info (SIM_DESC sd, bool verbose)
{
  const char *cpu_type;
  const struct bfd_arch_info *arch;

  /* Nothing to do if there is no verbose flag set.  */
  if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
    return;

  arch = STATE_ARCHITECTURE (sd);
  if (arch->arch == bfd_arch_m68hc11)
    cpu_type = "68HC11";
  else
    cpu_type = "68HC12";

  sim_io_eprintf (sd, "Simulator info:\n");
  sim_io_eprintf (sd, "  CPU Motorola %s\n", cpu_type);
  sim_get_info (sd, 0);
  sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
}

SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
                     char * const *argv, char * const *env)
{
  return sim_prepare_for_program (sd, abfd);
}

static int
m68hc11_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length)
{
  unsigned char *memory = buf;
  uint16_t val;
  int size = 2;

  switch (rn)
    {
    case A_REGNUM:
      val = cpu_get_a (cpu);
      size = 1;
      break;

    case B_REGNUM:
      val = cpu_get_b (cpu);
      size = 1;
      break;

    case D_REGNUM:
      val = cpu_get_d (cpu);
      break;

    case X_REGNUM:
      val = cpu_get_x (cpu);
      break;

    case Y_REGNUM:
      val = cpu_get_y (cpu);
      break;

    case SP_REGNUM:
      val = cpu_get_sp (cpu);
      break;

    case PC_REGNUM:
      val = cpu_get_pc (cpu);
      break;

    case PSW_REGNUM:
      val = cpu_get_ccr (cpu);
      size = 1;
      break;

    case PAGE_REGNUM:
      val = cpu_get_page (cpu);
      size = 1;
      break;

    default:
      val = 0;
      break;
    }
  if (size == 1)
    {
      memory[0] = val;
    }
  else
    {
      memory[0] = val >> 8;
      memory[1] = val & 0x0FF;
    }
  return size;
}

static int
m68hc11_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length)
{
  const unsigned char *memory = buf;
  uint16_t val;

  val = *memory++;
  if (length == 2)
    val = (val << 8) | *memory;

  switch (rn)
    {
    case D_REGNUM:
      cpu_set_d (cpu, val);
      break;

    case A_REGNUM:
      cpu_set_a (cpu, val);
      return 1;

    case B_REGNUM:
      cpu_set_b (cpu, val);
      return 1;

    case X_REGNUM:
      cpu_set_x (cpu, val);
      break;

    case Y_REGNUM:
      cpu_set_y (cpu, val);
      break;

    case SP_REGNUM:
      cpu_set_sp (cpu, val);
      break;

    case PC_REGNUM:
      cpu_set_pc (cpu, val);
      break;

    case PSW_REGNUM:
      cpu_set_ccr (cpu, val);
      return 1;

    case PAGE_REGNUM:
      cpu_set_page (cpu, val);
      return 1;

    default:
      break;
    }

  return 2;
}
Commit	Line	Data
5abb9efa	1	/* interp.c -- Simulator for Motorola 68HC11/68HC12
1d506c26	2	Copyright (C) 1999-2024 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
e0709f50 AC	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
e0709f50	19
6df01ab8 MF	20	/* This must come before any other includes. */
	21	#include "defs.h"
	22
6cf3ddd2 MF	23	#include "bfd.h"
6cf3ddd2 MF	24
e0709f50 AC	25	#include "sim-main.h"
	26	#include "sim-assert.h"
	27	#include "sim-hw.h"
	28	#include "sim-options.h"
	29	#include "hw-tree.h"
	30	#include "hw-device.h"
	31	#include "hw-ports.h"
c217e3d5	32	#include "bfd/elf32-m68hc1x.h"
e0709f50	33
600ddfd5 MF	34	#include "m68hc11-sim.h"
600ddfd5 MF	35
e0709f50 AC	36	#ifndef MONITOR_BASE
	37	# define MONITOR_BASE (0x0C000)
	38	# define MONITOR_SIZE (0x04000)
	39	#endif
	40
	41	static void sim_get_info (SIM_DESC sd, char *cmd);
	42
e0709f50 AC	43	struct sim_info_list
	44	{
	45	const char *name;
	46	const char *device;
	47	};
	48
81e09ed8	49	struct sim_info_list dev_list_68hc11[] = {
e0709f50 AC	50	{"cpu", "/m68hc11"},
	51	{"timer", "/m68hc11/m68hc11tim"},
	52	{"sio", "/m68hc11/m68hc11sio"},
	53	{"spi", "/m68hc11/m68hc11spi"},
	54	{"eeprom", "/m68hc11/m68hc11eepr"},
	55	{0, 0}
	56	};
	57
81e09ed8 SC	58	struct sim_info_list dev_list_68hc12[] = {
	59	{"cpu", "/m68hc12"},
	60	{"timer", "/m68hc12/m68hc12tim"},
	61	{"sio", "/m68hc12/m68hc12sio"},
	62	{"spi", "/m68hc12/m68hc12spi"},
	63	{"eeprom", "/m68hc12/m68hc12eepr"},
	64	{0, 0}
	65	};
	66
	67	/* Cover function of sim_state_free to free the cpu buffers as well. */
	68
	69	static void
	70	free_state (SIM_DESC sd)
	71	{
	72	if (STATE_MODULES (sd) != NULL)
	73	sim_module_uninstall (sd);
	74
	75	sim_state_free (sd);
	76	}
	77
e0709f50 AC	78	/* Give some information about the simulator. */
	79	static void
	80	sim_get_info (SIM_DESC sd, char *cmd)
	81	{
	82	sim_cpu *cpu;
	83
81e09ed8	84	cpu = STATE_CPU (sd, 0);
e0709f50 AC	85	if (cmd != 0 && (cmd[0] == ' ' \|\| cmd[0] == '-'))
	86	{
	87	int i;
	88	struct hw *hw_dev;
81e09ed8 SC	89	struct sim_info_list *dev_list;
	90	const struct bfd_arch_info *arch;
	91
	92	arch = STATE_ARCHITECTURE (sd);
e0709f50 AC	93	cmd++;
e0709f50 AC	94
81e09ed8 SC	95	if (arch->arch == bfd_arch_m68hc11)
	96	dev_list = dev_list_68hc11;
	97	else
	98	dev_list = dev_list_68hc12;
	99
e0709f50 AC	100	for (i = 0; dev_list[i].name; i++)
	101	if (strcmp (cmd, dev_list[i].name) == 0)
	102	break;
	103
	104	if (dev_list[i].name == 0)
	105	{
	106	sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	107	sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	108	return;
	109	}
fb8d4e59	110	hw_dev = sim_hw_parse (sd, "%s", dev_list[i].device);
e0709f50 AC	111	if (hw_dev == 0)
	112	{
	113	sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	114	return;
	115	}
	116	hw_ioctl (hw_dev, 23, 0);
	117	return;
	118	}
	119
e0709f50	120	cpu_info (sd, cpu);
79d784ae	121	interrupts_info (sd, &M68HC11_SIM_CPU (cpu)->cpu_interrupts);
e0709f50 AC	122	}
	123
	124
	125	void
	126	sim_board_reset (SIM_DESC sd)
	127	{
	128	struct hw *hw_cpu;
	129	sim_cpu *cpu;
79d784ae	130	struct m68hc11_sim_cpu *m68hc11_cpu;
81e09ed8 SC	131	const struct bfd_arch_info *arch;
81e09ed8 SC	132	const char *cpu_type;
e0709f50 AC	133
e0709f50 AC	134	cpu = STATE_CPU (sd, 0);
79d784ae	135	m68hc11_cpu = M68HC11_SIM_CPU (cpu);
81e09ed8 SC	136	arch = STATE_ARCHITECTURE (sd);
81e09ed8 SC	137
e0709f50	138	/* hw_cpu = sim_hw_parse (sd, "/"); */
81e09ed8 SC	139	if (arch->arch == bfd_arch_m68hc11)
81e09ed8 SC	140	{
79d784ae	141	m68hc11_cpu->cpu_type = CPU_M6811;
81e09ed8 SC	142	cpu_type = "/m68hc11";
	143	}
	144	else
	145	{
79d784ae	146	m68hc11_cpu->cpu_type = CPU_M6812;
81e09ed8 SC	147	cpu_type = "/m68hc12";
	148	}
	149
fb8d4e59	150	hw_cpu = sim_hw_parse (sd, "%s", cpu_type);
e0709f50 AC	151	if (hw_cpu == 0)
e0709f50 AC	152	{
81e09ed8	153	sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
e0709f50 AC	154	return;
	155	}
	156
	157	cpu_reset (cpu);
	158	hw_port_event (hw_cpu, 3, 0);
	159	cpu_restart (cpu);
	160	}
	161
39762100	162	static int
81e09ed8 SC	163	sim_hw_configure (SIM_DESC sd)
	164	{
	165	const struct bfd_arch_info *arch;
	166	struct hw *device_tree;
81e09ed8	167	sim_cpu *cpu;
79d784ae	168	struct m68hc11_sim_cpu *m68hc11_cpu;
81e09ed8 SC	169
	170	arch = STATE_ARCHITECTURE (sd);
	171	if (arch == 0)
	172	return 0;
	173
	174	cpu = STATE_CPU (sd, 0);
79d784ae MF	175	m68hc11_cpu = M68HC11_SIM_CPU (cpu);
79d784ae MF	176	m68hc11_cpu->cpu_configured_arch = arch;
81e09ed8 SC	177	device_tree = sim_hw_parse (sd, "/");
	178	if (arch->arch == bfd_arch_m68hc11)
	179	{
79d784ae	180	m68hc11_cpu->cpu_interpretor = cpu_interp_m6811;
81e09ed8 SC	181	if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	182	{
	183	/* Allocate core managed memory */
	184
	185	/* the monitor */
8e78e9b9	186	sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
81e09ed8 SC	187	/* MONITOR_BASE, MONITOR_SIZE */
	188	0x8000, M6811_RAM_LEVEL, 0x8000);
	189	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
	190	M6811_RAM_LEVEL);
	191	sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
79d784ae	192	if (m68hc11_cpu->bank_start < m68hc11_cpu->bank_end)
77342e5e	193	{
8e78e9b9	194	sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
79d784ae	195	m68hc11_cpu->bank_virtual, M6811_RAM_LEVEL);
77342e5e SC	196	sim_hw_parse (sd, "/m68hc11/use_bank 1");
77342e5e SC	197	}
81e09ed8	198	}
79d784ae	199	if (m68hc11_cpu->cpu_start_mode)
77342e5e	200	{
79d784ae	201	sim_hw_parse (sd, "/m68hc11/mode %s", m68hc11_cpu->cpu_start_mode);
77342e5e	202	}
81e09ed8 SC	203	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	204	{
	205	sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	206	sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	207	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	208	}
	209	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	210	{
	211	/* M68hc11 Timer configuration. */
	212	sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	213	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
827ec39a	214	sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
81e09ed8 SC	215	}
	216
	217	/* Create the SPI device. */
	218	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	219	{
	220	sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	221	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	222	}
	223	if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	224	{
	225	/* M68hc11 persistent ram configuration. */
	226	sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	227	sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	228	sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	229	/sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); /
	230	}
	231	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	232	{
	233	sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	234	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	235	}
dcceded2 SC	236	sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
	237	sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
	238	sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
	239	sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
79d784ae	240	m68hc11_cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
81e09ed8 SC	241	}
	242	else
	243	{
79d784ae	244	m68hc11_cpu->cpu_interpretor = cpu_interp_m6812;
81e09ed8 SC	245	if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	246	{
	247	/* Allocate core external memory. */
8e78e9b9	248	sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
77342e5e	249	0x8000, M6811_RAM_LEVEL, 0x8000);
81e09ed8 SC	250	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
81e09ed8 SC	251	M6811_RAM_LEVEL);
79d784ae	252	if (m68hc11_cpu->bank_start < m68hc11_cpu->bank_end)
77342e5e	253	{
8e78e9b9	254	sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
79d784ae	255	m68hc11_cpu->bank_virtual, M6811_RAM_LEVEL);
77342e5e SC	256	sim_hw_parse (sd, "/m68hc12/use_bank 1");
77342e5e SC	257	}
81e09ed8 SC	258	sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	259	}
	260
	261	if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	262	{
	263	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	264	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	265	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	266	}
81e09ed8 SC	267	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	268	{
	269	/* M68hc11 Timer configuration. */
	270	sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	271	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
dcceded2	272	sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
81e09ed8 SC	273	}
	274
	275	/* Create the SPI device. */
	276	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	277	{
	278	sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	279	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	280	}
	281	if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	282	{
	283	/* M68hc11 persistent ram configuration. */
	284	sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	285	sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	286	sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	287	}
	288	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	289	{
	290	sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	291	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	292	}
827ec39a	293
dcceded2 SC	294	sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
	295	sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
	296	sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
	297	sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
79d784ae	298	m68hc11_cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
81e09ed8	299	}
39762100	300	return 1;
81e09ed8 SC	301	}
81e09ed8 SC	302
77342e5e SC	303	/* Get the memory bank parameters by looking at the global symbols
77342e5e SC	304	defined by the linker. */
81e09ed8	305	static int
5357150c	306	sim_get_bank_parameters (SIM_DESC sd)
81e09ed8 SC	307	{
81e09ed8 SC	308	sim_cpu *cpu;
79d784ae	309	struct m68hc11_sim_cpu *m68hc11_cpu;
77342e5e	310	unsigned size;
5357150c	311	bfd_vma addr;
81e09ed8 SC	312
81e09ed8 SC	313	cpu = STATE_CPU (sd, 0);
79d784ae	314	m68hc11_cpu = M68HC11_SIM_CPU (cpu);
81e09ed8	315
5357150c MF	316	addr = trace_sym_value (sd, BFD_M68HC11_BANK_START_NAME);
5357150c MF	317	if (addr != -1)
79d784ae	318	m68hc11_cpu->bank_start = addr;
77342e5e	319
5357150c MF	320	size = trace_sym_value (sd, BFD_M68HC11_BANK_SIZE_NAME);
	321	if (size == -1)
	322	size = 0;
77342e5e	323
5357150c MF	324	addr = trace_sym_value (sd, BFD_M68HC11_BANK_VIRTUAL_NAME);
5357150c MF	325	if (addr != -1)
79d784ae	326	m68hc11_cpu->bank_virtual = addr;
77342e5e	327
79d784ae MF	328	m68hc11_cpu->bank_end = m68hc11_cpu->bank_start + size;
79d784ae MF	329	m68hc11_cpu->bank_shift = 0;
77342e5e	330	for (; size > 1; size >>= 1)
79d784ae	331	m68hc11_cpu->bank_shift++;
77342e5e SC	332
	333	return 0;
	334	}
	335
	336	static int
	337	sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
	338	{
	339	sim_cpu *cpu;
79d784ae	340	struct m68hc11_sim_cpu *m68hc11_cpu;
77342e5e SC	341	int elf_flags = 0;
	342
	343	cpu = STATE_CPU (sd, 0);
79d784ae	344	m68hc11_cpu = M68HC11_SIM_CPU (cpu);
39762100	345
81e09ed8 SC	346	if (abfd != NULL)
81e09ed8 SC	347	{
31c7c532	348	asection *s;
77342e5e SC	349
	350	if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
	351	elf_flags = elf_elfheader (abfd)->e_flags;
	352
79d784ae	353	m68hc11_cpu->cpu_elf_start = bfd_get_start_address (abfd);
31c7c532	354	/* See if any section sets the reset address */
79d784ae MF	355	m68hc11_cpu->cpu_use_elf_start = 1;
79d784ae MF	356	for (s = abfd->sections; s && m68hc11_cpu->cpu_use_elf_start; s = s->next)
31c7c532 SC	357	{
	358	if (s->flags & SEC_LOAD)
	359	{
	360	bfd_size_type size;
	361
fd361982	362	size = bfd_section_size (s);
31c7c532 SC	363	if (size > 0)
	364	{
	365	bfd_vma lma;
	366
	367	if (STATE_LOAD_AT_LMA_P (sd))
fd361982	368	lma = bfd_section_lma (s);
31c7c532	369	else
fd361982	370	lma = bfd_section_vma (s);
31c7c532 SC	371
31c7c532 SC	372	if (lma <= 0xFFFE && lma+size >= 0x10000)
79d784ae	373	m68hc11_cpu->cpu_use_elf_start = 0;
31c7c532 SC	374	}
	375	}
	376	}
77342e5e SC	377
	378	if (elf_flags & E_M68HC12_BANKS)
	379	{
5357150c	380	if (sim_get_bank_parameters (sd) != 0)
77342e5e SC	381	sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
77342e5e SC	382	}
81e09ed8 SC	383	}
81e09ed8 SC	384
77342e5e SC	385	if (!sim_hw_configure (sd))
	386	return SIM_RC_FAIL;
	387
81e09ed8 SC	388	/* reset all state information */
	389	sim_board_reset (sd);
	390
	391	return SIM_RC_OK;
	392	}
	393
bea3f671 MF	394	static sim_cia
	395	m68hc11_pc_get (sim_cpu *cpu)
	396	{
	397	return cpu_get_pc (cpu);
	398	}
	399
	400	static void
	401	m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
	402	{
	403	cpu_set_pc (cpu, pc);
	404	}
	405
ee1cffd3 MF	406	static int m68hc11_reg_fetch (SIM_CPU , int, void , int);
ee1cffd3 MF	407	static int m68hc11_reg_store (SIM_CPU , int, const void , int);
e1211e55	408
e0709f50 AC	409	SIM_DESC
e0709f50 AC	410	sim_open (SIM_OPEN_KIND kind, host_callback *callback,
2e3d4f4d	411	bfd abfd, char const *argv)
e0709f50	412	{
bea3f671	413	int i;
e0709f50 AC	414	SIM_DESC sd;
e0709f50 AC	415	sim_cpu *cpu;
e0709f50 AC	416
e0709f50 AC	417	sd = sim_state_alloc (kind, callback);
e0709f50 AC	418
	419	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	420
f9a4d543 MF	421	/* Set default options before parsing user options. */
	422	current_target_byte_order = BFD_ENDIAN_BIG;
	423
bea3f671	424	/* The cpu data is kept in a separately allocated chunk of memory. */
883be197	425	if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct m68hc11_sim_cpu))
79d784ae	426	!= SIM_RC_OK)
bea3f671 MF	427	{
	428	free_state (sd);
	429	return 0;
	430	}
	431
	432	cpu = STATE_CPU (sd, 0);
	433
e0709f50 AC	434	cpu_initialize (sd, cpu);
e0709f50 AC	435
e0709f50	436	if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
81e09ed8 SC	437	{
	438	free_state (sd);
	439	return 0;
	440	}
e0709f50	441
77cf2ef5	442	/* The parser will print an error message for us, so we silently return. */
e0709f50 AC	443	if (sim_parse_args (sd, argv) != SIM_RC_OK)
	444	{
	445	/* Uninstall the modules to avoid memory leaks,
	446	file descriptor leaks, etc. */
81e09ed8	447	free_state (sd);
e0709f50 AC	448	return 0;
	449	}
	450
e0709f50	451	/* Check for/establish the a reference program image. */
e8f20a28	452	if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
e0709f50	453	{
81e09ed8	454	free_state (sd);
e0709f50 AC	455	return 0;
	456	}
	457
	458	/* Establish any remaining configuration options. */
	459	if (sim_config (sd) != SIM_RC_OK)
	460	{
81e09ed8	461	free_state (sd);
e0709f50 AC	462	return 0;
	463	}
	464
	465	if (sim_post_argv_init (sd) != SIM_RC_OK)
	466	{
	467	/* Uninstall the modules to avoid memory leaks,
	468	file descriptor leaks, etc. */
81e09ed8	469	free_state (sd);
e0709f50 AC	470	return 0;
e0709f50 AC	471	}
77342e5e SC	472	if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
	473	{
	474	free_state (sd);
	475	return 0;
	476	}
e0709f50	477
bea3f671 MF	478	/* CPU specific initialization. */
	479	for (i = 0; i < MAX_NR_PROCESSORS; ++i)
	480	{
c6f30b87	481	cpu = STATE_CPU (sd, i);
bea3f671	482
e1211e55 MF	483	CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
e1211e55 MF	484	CPU_REG_STORE (cpu) = m68hc11_reg_store;
bea3f671 MF	485	CPU_PC_FETCH (cpu) = m68hc11_pc_get;
	486	CPU_PC_STORE (cpu) = m68hc11_pc_set;
	487	}
	488
e0709f50 AC	489	return sd;
	490	}
	491
e0709f50 AC	492	/* Generic implementation of sim_engine_run that works within the
	493	sim_engine setjmp/longjmp framework. */
	494
	495	void
	496	sim_engine_run (SIM_DESC sd,
	497	int next_cpu_nr, /* ignore */
	498	int nr_cpus, /* ignore */
	499	int siggnal) /* ignore */
	500	{
	501	sim_cpu *cpu;
	502
	503	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	504	cpu = STATE_CPU (sd, 0);
	505	while (1)
	506	{
	507	cpu_single_step (cpu);
	508
	509	/* process any events */
79d784ae	510	if (sim_events_tickn (sd, M68HC11_SIM_CPU (cpu)->cpu_current_cycle))
e0709f50 AC	511	{
	512	sim_events_process (sd);
	513	}
	514	}
	515	}
	516
e0709f50	517	void
cc67f780	518	sim_info (SIM_DESC sd, bool verbose)
e0709f50	519	{
81e09ed8 SC	520	const char *cpu_type;
	521	const struct bfd_arch_info *arch;
	522
00d0c012 SC	523	/* Nothing to do if there is no verbose flag set. */
	524	if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
	525	return;
	526
81e09ed8 SC	527	arch = STATE_ARCHITECTURE (sd);
	528	if (arch->arch == bfd_arch_m68hc11)
	529	cpu_type = "68HC11";
	530	else
	531	cpu_type = "68HC12";
	532
e0709f50	533	sim_io_eprintf (sd, "Simulator info:\n");
81e09ed8	534	sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
e0709f50 AC	535	sim_get_info (sd, 0);
	536	sim_module_info (sd, verbose \|\| STATE_VERBOSE_P (sd));
	537	}
	538
	539	SIM_RC
6b4a8935	540	sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
2e3d4f4d	541	char * const argv, char const *env)
e0709f50	542	{
81e09ed8	543	return sim_prepare_for_program (sd, abfd);
e0709f50 AC	544	}
e0709f50 AC	545
e1211e55	546	static int
ee1cffd3	547	m68hc11_reg_fetch (SIM_CPU cpu, int rn, void buf, int length)
e0709f50	548	{
ee1cffd3	549	unsigned char *memory = buf;
7606e1a3	550	uint16_t val;
63f36def	551	int size = 2;
e0709f50	552
e0709f50 AC	553	switch (rn)
	554	{
	555	case A_REGNUM:
	556	val = cpu_get_a (cpu);
63f36def	557	size = 1;
e0709f50 AC	558	break;
	559
	560	case B_REGNUM:
	561	val = cpu_get_b (cpu);
63f36def	562	size = 1;
e0709f50 AC	563	break;
	564
	565	case D_REGNUM:
	566	val = cpu_get_d (cpu);
	567	break;
	568
	569	case X_REGNUM:
	570	val = cpu_get_x (cpu);
	571	break;
	572
	573	case Y_REGNUM:
	574	val = cpu_get_y (cpu);
	575	break;
	576
	577	case SP_REGNUM:
	578	val = cpu_get_sp (cpu);
	579	break;
	580
	581	case PC_REGNUM:
	582	val = cpu_get_pc (cpu);
	583	break;
	584
	585	case PSW_REGNUM:
	586	val = cpu_get_ccr (cpu);
63f36def SC	587	size = 1;
	588	break;
	589
	590	case PAGE_REGNUM:
	591	val = cpu_get_page (cpu);
	592	size = 1;
e0709f50 AC	593	break;
e0709f50 AC	594
e0709f50	595	default:
9830501b	596	val = 0;
e0709f50 AC	597	break;
e0709f50 AC	598	}
00416c6e SC	599	if (size == 1)
	600	{
	601	memory[0] = val;
	602	}
	603	else
	604	{
	605	memory[0] = val >> 8;
	606	memory[1] = val & 0x0FF;
	607	}
63f36def	608	return size;
e0709f50 AC	609	}
e0709f50 AC	610
e1211e55	611	static int
ee1cffd3	612	m68hc11_reg_store (SIM_CPU cpu, int rn, const void buf, int length)
e0709f50	613	{
ee1cffd3	614	const unsigned char *memory = buf;
7606e1a3	615	uint16_t val;
e0709f50 AC	616
	617	val = *memory++;
	618	if (length == 2)
	619	val = (val << 8) \| *memory;
	620
	621	switch (rn)
	622	{
	623	case D_REGNUM:
	624	cpu_set_d (cpu, val);
	625	break;
	626
	627	case A_REGNUM:
	628	cpu_set_a (cpu, val);
63f36def	629	return 1;
e0709f50 AC	630
	631	case B_REGNUM:
	632	cpu_set_b (cpu, val);
63f36def	633	return 1;
e0709f50 AC	634
	635	case X_REGNUM:
	636	cpu_set_x (cpu, val);
	637	break;
	638
	639	case Y_REGNUM:
	640	cpu_set_y (cpu, val);
	641	break;
	642
	643	case SP_REGNUM:
	644	cpu_set_sp (cpu, val);
	645	break;
	646
	647	case PC_REGNUM:
	648	cpu_set_pc (cpu, val);
	649	break;
	650
	651	case PSW_REGNUM:
	652	cpu_set_ccr (cpu, val);
63f36def SC	653	return 1;
	654
	655	case PAGE_REGNUM:
	656	cpu_set_page (cpu, val);
	657	return 1;
e0709f50	658
e0709f50	659	default:
e0709f50 AC	660	break;
	661	}
	662
	663	return 2;
	664	}