[thirdparty/binutils-gdb.git] / sim / m68hc11 / sim-main.h

/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   Copyright (C) 1999-2016 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef _SIM_MAIN_H
#define _SIM_MAIN_H

#include "sim-basics.h"
#include "sim-signal.h"
#include "sim-base.h"

#include "bfd.h"

#include "opcode/m68hc11.h"

#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include "opcode/m68hc11.h"
#include "sim-types.h"

typedef unsigned8 uint8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;

struct _sim_cpu;

#include "interrupts.h"
#include <setjmp.h>

/* Specifies the level of mapping for the IO, EEprom, nvram and external
   RAM.  IO registers are mapped over everything and the external RAM
   is last (ie, it can be hidden by everything above it in the list).  */
enum m68hc11_map_level
{
  M6811_IO_LEVEL,
  M6811_EEPROM_LEVEL,
  M6811_NVRAM_LEVEL,
  M6811_RAM_LEVEL
};

enum cpu_type
{
  CPU_M6811,
  CPU_M6812
};

#define X_REGNUM 	0
#define D_REGNUM	1
#define Y_REGNUM        2
#define SP_REGNUM 	3
#define PC_REGNUM 	4
#define A_REGNUM        5
#define B_REGNUM        6
#define PSW_REGNUM 	7
#define PAGE_REGNUM     8
#define Z_REGNUM        9

typedef struct m6811_regs {
    unsigned short      d;
    unsigned short      ix;
    unsigned short      iy;
    unsigned short      sp;
    unsigned short      pc;
    unsigned char       ccr;
  unsigned short      page;
} m6811_regs;


/* Description of 68HC11 IO registers.  Such description is only provided
   for the info command to display the current setting of IO registers
   from GDB.  */
struct io_reg_desc
{
  int        mask;
  const char *short_name;
  const char *long_name;
};
typedef struct io_reg_desc io_reg_desc;

extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
			       int mode);
extern void print_io_byte (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint8 val, uint16 addr);
extern void print_io_word (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint16 val, uint16 addr);


/* List of special 68HC11&68HC12 instructions that are not handled by the
   'gencode.c' generator.  These complex instructions are implemented
   by 'cpu_special'.  */
enum M6811_Special
{
  /* 68HC11 instructions.  */
  M6811_DAA,
  M6811_EMUL_SYSCALL,
  M6811_ILLEGAL,
  M6811_RTI,
  M6811_STOP,
  M6811_SWI,
  M6811_TEST,
  M6811_WAI,

  /* 68HC12 instructions.  */
  M6812_BGND,
  M6812_CALL,
  M6812_CALL_INDIRECT,
  M6812_IDIVS,
  M6812_EDIV,
  M6812_EDIVS,
  M6812_EMACS,
  M6812_EMUL,
  M6812_EMULS,
  M6812_ETBL,
  M6812_MEM,
  M6812_REV,
  M6812_REVW,
  M6812_RTC,
  M6812_RTI,
  M6812_WAV
};

#define M6811_MAX_PORTS (0x03f+1)
#define M6812_MAX_PORTS (0x3ff+1)
#define MAX_PORTS       (M6812_MAX_PORTS)

struct _sim_cpu;

typedef void (* cpu_interp) (struct _sim_cpu*);

struct _sim_cpu {
  /* CPU registers.  */
  struct m6811_regs     cpu_regs;

  /* CPU interrupts.  */
  struct interrupts     cpu_interrupts;

  /* Pointer to the interpretor routine.  */
  cpu_interp            cpu_interpretor;

  /* Pointer to the architecture currently configured in the simulator.  */
  const struct bfd_arch_info  *cpu_configured_arch;
  
  /* CPU absolute cycle time.  The cycle time is updated after
     each instruction, by the number of cycles taken by the instruction.
     It is cleared only when reset occurs.  */
  signed64              cpu_absolute_cycle;

  /* Number of cycles to increment after the current instruction.
     This is also the number of ticks for the generic event scheduler.  */
  uint8                 cpu_current_cycle;
  int                   cpu_emul_syscall;
  int                   cpu_is_initialized;
  int                   cpu_running;
  int                   cpu_check_memory;
  int                   cpu_stop_on_interrupt;

  /* When this is set, start execution of program at address specified
     in the ELF header.  This is used for testing some programs that do not
     have an interrupt table linked with them.  Programs created during the
     GCC validation are like this. A normal 68HC11 does not behave like
     this (unless there is some OS or downloadable feature).  */
  int                   cpu_use_elf_start;

  /* The starting address specified in ELF header.  */
  int                   cpu_elf_start;
  
  uint16                cpu_insn_pc;

  /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
     get the cycle time.  This is used for the timer rate and for the baud
     rate generation.  */
  unsigned long         cpu_frequency;

  /* The mode in which the CPU is configured (MODA and MODB pins).  */
  unsigned int          cpu_mode;
  const char*           cpu_start_mode;

  /* The cpu being configured.  */
  enum cpu_type         cpu_type;
  
  /* Initial value of the CONFIG register.  */
  uint8                 cpu_config;
  uint8                 cpu_use_local_config;
  
  uint8                 ios[MAX_PORTS];

  /* Memory bank parameters which describe how the memory bank window
     is mapped in memory and how to convert it in virtual address.  */
  uint16                bank_start;
  uint16                bank_end;
  address_word          bank_virtual;
  unsigned              bank_shift;
  

  struct hw            *hw_cpu;

  /* ... base type ... */
  sim_cpu_base base;
};

/* Returns the cpu absolute cycle time (A virtual counter incremented
   at each 68HC11 E clock).  */
#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
#define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
#define cpu_is_running(PROC)    ((PROC)->cpu_running)

/* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
#define cpu_get_io_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
#define cpu_get_reg_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)

/* Returns the different CPU registers.  */
#define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
#define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
#define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
#define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
#define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
#define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
#define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
#define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
#define cpu_get_page(PROC)         ((PROC)->cpu_regs.page)

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_get_tmp3(PROC)         (0)
#define cpu_get_tmp2(PROC)         (0)

#define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
#define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
#define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
#define cpu_set_page(PROC,VAL)     (((PROC)->cpu_regs.page) = (VAL))

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_set_tmp3(PROC,VAL)     (0)
#define cpu_set_tmp2(PROC,VAL)     (void) (0)

#if 0
/* This is a function in m68hc11_sim.c to keep track of the frame.  */
#define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
#endif

#define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))

#define cpu_set_a(PROC,VAL)  \
      cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
#define cpu_set_b(PROC,VAL)  \
      cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))

#define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
#define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
#define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
#define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
#define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
#define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
#define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
#define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
#define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)

#define cpu_set_ccr_flag(S,B,V) \
cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))

#define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
#define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
#define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
#define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
#define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
#define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
#define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
#define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)

#undef inline
#define inline static __inline__

extern void cpu_memory_exception (struct _sim_cpu *proc,
                                  SIM_SIGNAL excep,
                                  uint16 addr,
                                  const char *message);

inline address_word
phys_to_virt (sim_cpu *cpu, address_word addr)
{
  if (addr >= cpu->bank_start && addr < cpu->bank_end)
    return ((address_word) (addr - cpu->bank_start)
            + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
            + cpu->bank_virtual);
  else
    return (address_word) (addr);
}

inline uint8
memory_read8 (sim_cpu *cpu, uint16 addr)
{
  uint8 val;

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return val;
}

inline void
memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
{
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}

inline uint16
memory_read16 (sim_cpu *cpu, uint16 addr)
{
  uint8 b[2];

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
}

inline void
memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
{
  uint8 b[2];

  b[0] = val >> 8;
  b[1] = val;
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}
extern void
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);

     inline void
cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_V (proc, 0);
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
}

     inline void
cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
{
  cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

     inline void
cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

inline void
cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}


inline void
cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}

inline void
cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

inline void
cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

/* Push and pop instructions for 68HC11 (next-available stack mode).  */
inline void
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline void
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp - 1;

  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline uint8
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Push and pop instructions for 68HC12 (last-used stack mode).  */
inline void
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr --;
  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline void
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr -= 2;
  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline uint8
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Fetch a 8/16 bit value and update the PC.  */
inline uint8
cpu_fetch8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.pc = addr + 1;
  return val;
}

inline uint16
cpu_fetch16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.pc = addr + 2;
  return val;
}

extern void cpu_call (sim_cpu* proc, uint16 addr);
extern void cpu_exg (sim_cpu* proc, uint8 code);
extern void cpu_dbcc (sim_cpu* proc);
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
extern void cpu_move8 (sim_cpu *proc, uint8 op);
extern void cpu_move16 (sim_cpu *proc, uint8 op);

extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
extern void cpu_push_all (sim_cpu *proc);
extern void cpu_single_step (sim_cpu *proc);

extern void cpu_info (SIM_DESC sd, sim_cpu *proc);

extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);

/* Returns the address of a 68HC12 indexed operand.
   Pre and post modifications are handled on the source register.  */
extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);

extern void cpu_return (sim_cpu *cpu);
extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
extern int cpu_reset (sim_cpu *cpu);
extern int cpu_restart (sim_cpu *cpu);
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
                              uint16 addr, const char *message, ...);
extern void emul_os (int op, sim_cpu *cpu);
extern void cpu_interp_m6811 (sim_cpu *cpu);
extern void cpu_interp_m6812 (sim_cpu *cpu);

extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
				      double ton, double toff,
				      signed64 repeat);
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
				 unsigned addr, uint8 val);

/* The current state of the processor; registers, memory, etc.  */

struct sim_state {
  sim_cpu        *cpu[MAX_NR_PROCESSORS];
  device         *devices;
  sim_state_base base;
};

extern void sim_board_reset (SIM_DESC sd);

#define PRINT_TIME  0x01
#define PRINT_CYCLE 0x02
extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);

#endif
Commit	Line	Data
81e09ed8	1	/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
618f726f	2	Copyright (C) 1999-2016 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
e0709f50 AC	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
e0709f50 AC	19
	20	#ifndef _SIM_MAIN_H
	21	#define _SIM_MAIN_H
	22
e0709f50	23	#include "sim-basics.h"
e0709f50 AC	24	#include "sim-signal.h"
	25	#include "sim-base.h"
	26
	27	#include "bfd.h"
	28
	29	#include "opcode/m68hc11.h"
	30
3c25f8c7 AC	31	#include "gdb/callback.h"
3c25f8c7 AC	32	#include "gdb/remote-sim.h"
e0709f50 AC	33	#include "opcode/m68hc11.h"
	34	#include "sim-types.h"
	35
	36	typedef unsigned8 uint8;
	37	typedef unsigned16 uint16;
	38	typedef signed16 int16;
	39	typedef unsigned32 uint32;
	40	typedef signed32 int32;
	41	typedef unsigned64 uint64;
	42	typedef signed64 int64;
	43
	44	struct _sim_cpu;
	45
	46	#include "interrupts.h"
	47	#include <setjmp.h>
	48
63348d04 SC	49	/* Specifies the level of mapping for the IO, EEprom, nvram and external
	50	RAM. IO registers are mapped over everything and the external RAM
	51	is last (ie, it can be hidden by everything above it in the list). */
	52	enum m68hc11_map_level
	53	{
	54	M6811_IO_LEVEL,
	55	M6811_EEPROM_LEVEL,
	56	M6811_NVRAM_LEVEL,
	57	M6811_RAM_LEVEL
	58	};
	59
81e09ed8 SC	60	enum cpu_type
	61	{
	62	CPU_M6811,
	63	CPU_M6812
	64	};
63348d04	65
e0709f50 AC	66	#define X_REGNUM 0
	67	#define D_REGNUM 1
	68	#define Y_REGNUM 2
	69	#define SP_REGNUM 3
	70	#define PC_REGNUM 4
	71	#define A_REGNUM 5
	72	#define B_REGNUM 6
	73	#define PSW_REGNUM 7
53b3cd22 SC	74	#define PAGE_REGNUM 8
53b3cd22 SC	75	#define Z_REGNUM 9
e0709f50 AC	76
	77	typedef struct m6811_regs {
	78	unsigned short d;
	79	unsigned short ix;
	80	unsigned short iy;
	81	unsigned short sp;
	82	unsigned short pc;
	83	unsigned char ccr;
63f36def	84	unsigned short page;
e0709f50 AC	85	} m6811_regs;
	86
	87
	88	/* Description of 68HC11 IO registers. Such description is only provided
	89	for the info command to display the current setting of IO registers
	90	from GDB. */
	91	struct io_reg_desc
	92	{
	93	int mask;
	94	const char *short_name;
	95	const char *long_name;
	96	};
	97	typedef struct io_reg_desc io_reg_desc;
	98
	99	extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
	100	int mode);
	101	extern void print_io_byte (SIM_DESC sd, const char *name,
	102	io_reg_desc *desc, uint8 val, uint16 addr);
962e9d85 SC	103	extern void print_io_word (SIM_DESC sd, const char *name,
962e9d85 SC	104	io_reg_desc *desc, uint16 val, uint16 addr);
e0709f50 AC	105
e0709f50 AC	106
81e09ed8	107	/* List of special 68HC11&68HC12 instructions that are not handled by the
e0709f50 AC	108	'gencode.c' generator. These complex instructions are implemented
	109	by 'cpu_special'. */
	110	enum M6811_Special
	111	{
81e09ed8 SC	112	/* 68HC11 instructions. */
	113	M6811_DAA,
	114	M6811_EMUL_SYSCALL,
	115	M6811_ILLEGAL,
e0709f50	116	M6811_RTI,
81e09ed8	117	M6811_STOP,
e0709f50 AC	118	M6811_SWI,
e0709f50 AC	119	M6811_TEST,
81e09ed8 SC	120	M6811_WAI,
	121
	122	/* 68HC12 instructions. */
	123	M6812_BGND,
	124	M6812_CALL,
63f36def	125	M6812_CALL_INDIRECT,
81e09ed8 SC	126	M6812_IDIVS,
	127	M6812_EDIV,
	128	M6812_EDIVS,
	129	M6812_EMACS,
	130	M6812_EMUL,
	131	M6812_EMULS,
	132	M6812_ETBL,
	133	M6812_MEM,
	134	M6812_REV,
	135	M6812_REVW,
	136	M6812_RTC,
	137	M6812_RTI,
	138	M6812_WAV
e0709f50 AC	139	};
e0709f50 AC	140
81e09ed8 SC	141	#define M6811_MAX_PORTS (0x03f+1)
	142	#define M6812_MAX_PORTS (0x3ff+1)
	143	#define MAX_PORTS (M6812_MAX_PORTS)
e0709f50	144
81e09ed8 SC	145	struct _sim_cpu;
	146
	147	typedef void (* cpu_interp) (struct _sim_cpu*);
	148
e0709f50 AC	149	struct _sim_cpu {
	150	/* CPU registers. */
	151	struct m6811_regs cpu_regs;
	152
	153	/* CPU interrupts. */
	154	struct interrupts cpu_interrupts;
	155
81e09ed8 SC	156	/* Pointer to the interpretor routine. */
	157	cpu_interp cpu_interpretor;
	158
	159	/* Pointer to the architecture currently configured in the simulator. */
	160	const struct bfd_arch_info *cpu_configured_arch;
	161
e0709f50 AC	162	/* CPU absolute cycle time. The cycle time is updated after
	163	each instruction, by the number of cycles taken by the instruction.
	164	It is cleared only when reset occurs. */
	165	signed64 cpu_absolute_cycle;
	166
	167	/* Number of cycles to increment after the current instruction.
	168	This is also the number of ticks for the generic event scheduler. */
	169	uint8 cpu_current_cycle;
	170	int cpu_emul_syscall;
	171	int cpu_is_initialized;
	172	int cpu_running;
	173	int cpu_check_memory;
	174	int cpu_stop_on_interrupt;
	175
	176	/* When this is set, start execution of program at address specified
	177	in the ELF header. This is used for testing some programs that do not
	178	have an interrupt table linked with them. Programs created during the
	179	GCC validation are like this. A normal 68HC11 does not behave like
	180	this (unless there is some OS or downloadable feature). */
	181	int cpu_use_elf_start;
	182
	183	/* The starting address specified in ELF header. */
	184	int cpu_elf_start;
	185
	186	uint16 cpu_insn_pc;
e0709f50 AC	187
	188	/* CPU frequency. This is the quartz frequency. It is divided by 4 to
	189	get the cycle time. This is used for the timer rate and for the baud
	190	rate generation. */
	191	unsigned long cpu_frequency;
	192
	193	/* The mode in which the CPU is configured (MODA and MODB pins). */
	194	unsigned int cpu_mode;
a685700c	195	const char* cpu_start_mode;
e0709f50	196
81e09ed8 SC	197	/* The cpu being configured. */
	198	enum cpu_type cpu_type;
	199
e0709f50 AC	200	/* Initial value of the CONFIG register. */
	201	uint8 cpu_config;
	202	uint8 cpu_use_local_config;
	203
81e09ed8	204	uint8 ios[MAX_PORTS];
827ec39a	205
77342e5e SC	206	/* Memory bank parameters which describe how the memory bank window
	207	is mapped in memory and how to convert it in virtual address. */
	208	uint16 bank_start;
	209	uint16 bank_end;
	210	address_word bank_virtual;
	211	unsigned bank_shift;
	212
	213
827ec39a SC	214	struct hw *hw_cpu;
827ec39a SC	215
e0709f50 AC	216	/* ... base type ... */
	217	sim_cpu_base base;
	218	};
	219
	220	/* Returns the cpu absolute cycle time (A virtual counter incremented
	221	at each 68HC11 E clock). */
	222	#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
	223	#define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
	224	#define cpu_is_running(PROC) ((PROC)->cpu_running)
	225
	226	/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
	227	#define cpu_get_io_base(PROC) \
	228	(((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
	229	#define cpu_get_reg_base(PROC) \
	230	(((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
	231
	232	/* Returns the different CPU registers. */
	233	#define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
	234	#define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
	235	#define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
	236	#define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
	237	#define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
	238	#define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
	239	#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
	240	#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
77342e5e	241	#define cpu_get_page(PROC) ((PROC)->cpu_regs.page)
e0709f50	242
81e09ed8 SC	243	/* 68HC12 specific and Motorola internal registers. */
	244	#define cpu_get_tmp3(PROC) (0)
	245	#define cpu_get_tmp2(PROC) (0)
	246
e0709f50 AC	247	#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
	248	#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
	249	#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
77342e5e	250	#define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL))
e0709f50	251
81e09ed8 SC	252	/* 68HC12 specific and Motorola internal registers. */
81e09ed8 SC	253	#define cpu_set_tmp3(PROC,VAL) (0)
63f36def	254	#define cpu_set_tmp2(PROC,VAL) (void) (0)
81e09ed8	255
e0709f50 AC	256	#if 0
	257	/* This is a function in m68hc11_sim.c to keep track of the frame. */
	258	#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
	259	#endif
	260
	261	#define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
	262
	263	#define cpu_set_a(PROC,VAL) \
	264	cpu_set_d(PROC,((VAL) << 8) \| cpu_get_b(PROC))
	265	#define cpu_set_b(PROC,VAL) \
	266	cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)\|(VAL & 0x0FF))
	267
	268	#define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
	269	#define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
	270	#define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
	271	#define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
	272	#define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
	273	#define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
	274	#define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
	275	#define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
	276	#define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
	277
	278	#define cpu_set_ccr_flag(S,B,V) \
	279	cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) \| ((V) ? B : 0))
	280
	281	#define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
	282	#define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
	283	#define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
	284	#define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
	285	#define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
	286	#define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
	287	#define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
	288	#define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
	289
	290	#undef inline
	291	#define inline static __inline__
	292
	293	extern void cpu_memory_exception (struct _sim_cpu *proc,
	294	SIM_SIGNAL excep,
	295	uint16 addr,
	296	const char *message);
	297
63f36def SC	298	inline address_word
	299	phys_to_virt (sim_cpu *cpu, address_word addr)
	300	{
77342e5e SC	301	if (addr >= cpu->bank_start && addr < cpu->bank_end)
	302	return ((address_word) (addr - cpu->bank_start)
	303	+ (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
	304	+ cpu->bank_virtual);
63f36def SC	305	else
	306	return (address_word) (addr);
	307	}
	308
e0709f50 AC	309	inline uint8
	310	memory_read8 (sim_cpu *cpu, uint16 addr)
	311	{
	312	uint8 val;
63f36def	313
e0709f50 AC	314	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	315	{
	316	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	317	"Read error");
	318	}
	319	return val;
	320	}
	321
	322	inline void
	323	memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
	324	{
	325	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	326	{
	327	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	328	"Write error");
	329	}
	330	}
	331
	332	inline uint16
	333	memory_read16 (sim_cpu *cpu, uint16 addr)
	334	{
	335	uint8 b[2];
63f36def	336
e0709f50 AC	337	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	338	{
	339	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	340	"Read error");
	341	}
	342	return (((uint16) (b[0])) << 8) \| ((uint16) b[1]);
	343	}
	344
	345	inline void
	346	memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
	347	{
	348	uint8 b[2];
	349
	350	b[0] = val >> 8;
	351	b[1] = val;
	352	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	353	{
	354	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	355	"Write error");
	356	}
	357	}
	358	extern void
	359	cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
	360
	361	inline void
	362	cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
	363	{
	364	cpu_set_ccr_V (proc, 0);
	365	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	366	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	367	}
	368
	369	inline void
	370	cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
	371	{
	372	cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
	373	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	374	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	375	}
	376
	377	inline void
	378	cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
	379	{
	380	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	381	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	382	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	383	}
	384
	385	inline void
	386	cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	387	{
	388	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x80 ? 1 : 0);
	389	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x80 ? 1 : 0);
	390	cpu_set_ccr_Z (proc, r == 0);
	391	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
	392	}
	393
	394
	395	inline void
	396	cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	397	{
	398	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x80 ? 1 : 0);
	399	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x80 ? 1 : 0);
	400	cpu_set_ccr_Z (proc, r == 0);
401	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
402	}
403
404	inline void
405	cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
406	{
407	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x8000 ? 1 : 0);
408	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x8000 ? 1 : 0);
409	cpu_set_ccr_Z (proc, r == 0);
410	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
411	}
412
413	inline void
414	cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
415	{
416	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x8000 ? 1 : 0);
417	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x8000 ? 1 : 0);
418	cpu_set_ccr_Z (proc, r == 0);
419	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
420	}
421
81e09ed8	422	/* Push and pop instructions for 68HC11 (next-available stack mode). */
e0709f50	423	inline void
81e09ed8	424	cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
e0709f50 AC	425	{
	426	uint16 addr = proc->cpu_regs.sp;
	427
	428	memory_write8 (proc, addr, val);
	429	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	430	}
	431
	432	inline void
81e09ed8	433	cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
e0709f50 AC	434	{
	435	uint16 addr = proc->cpu_regs.sp - 1;
	436
	437	memory_write16 (proc, addr, val);
	438	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	439	}
	440
	441	inline uint8
81e09ed8	442	cpu_m68hc11_pop_uint8 (sim_cpu *proc)
e0709f50 AC	443	{
	444	uint16 addr = proc->cpu_regs.sp;
	445	uint8 val;
	446
	447	val = memory_read8 (proc, addr + 1);
	448	proc->cpu_regs.sp = addr + 1;
e0709f50 AC	449	return val;
	450	}
	451
	452	inline uint16
81e09ed8	453	cpu_m68hc11_pop_uint16 (sim_cpu *proc)
e0709f50 AC	454	{
	455	uint16 addr = proc->cpu_regs.sp;
	456	uint16 val;
	457
	458	val = memory_read16 (proc, addr + 1);
	459	proc->cpu_regs.sp = addr + 2;
e0709f50 AC	460	return val;
	461	}
	462
81e09ed8 SC	463	/* Push and pop instructions for 68HC12 (last-used stack mode). */
	464	inline void
	465	cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
	466	{
	467	uint16 addr = proc->cpu_regs.sp;
	468
	469	addr --;
	470	memory_write8 (proc, addr, val);
	471	proc->cpu_regs.sp = addr;
81e09ed8 SC	472	}
	473
	474	inline void
	475	cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
	476	{
	477	uint16 addr = proc->cpu_regs.sp;
	478
	479	addr -= 2;
	480	memory_write16 (proc, addr, val);
	481	proc->cpu_regs.sp = addr;
81e09ed8 SC	482	}
	483
	484	inline uint8
	485	cpu_m68hc12_pop_uint8 (sim_cpu *proc)
	486	{
	487	uint16 addr = proc->cpu_regs.sp;
	488	uint8 val;
	489
	490	val = memory_read8 (proc, addr);
	491	proc->cpu_regs.sp = addr + 1;
81e09ed8 SC	492	return val;
	493	}
	494
	495	inline uint16
	496	cpu_m68hc12_pop_uint16 (sim_cpu *proc)
	497	{
	498	uint16 addr = proc->cpu_regs.sp;
	499	uint16 val;
	500
	501	val = memory_read16 (proc, addr);
	502	proc->cpu_regs.sp = addr + 2;
81e09ed8 SC	503	return val;
	504	}
	505
	506	/* Fetch a 8/16 bit value and update the PC. */
e0709f50 AC	507	inline uint8
	508	cpu_fetch8 (sim_cpu *proc)
	509	{
	510	uint16 addr = proc->cpu_regs.pc;
	511	uint8 val;
	512
	513	val = memory_read8 (proc, addr);
	514	proc->cpu_regs.pc = addr + 1;
	515	return val;
	516	}
	517
	518	inline uint16
	519	cpu_fetch16 (sim_cpu *proc)
	520	{
	521	uint16 addr = proc->cpu_regs.pc;
	522	uint16 val;
	523
	524	val = memory_read16 (proc, addr);
	525	proc->cpu_regs.pc = addr + 2;
	526	return val;
	527	}
	528
	529	extern void cpu_call (sim_cpu* proc, uint16 addr);
81e09ed8 SC	530	extern void cpu_exg (sim_cpu* proc, uint8 code);
81e09ed8 SC	531	extern void cpu_dbcc (sim_cpu* proc);
e0709f50	532	extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
81e09ed8 SC	533	extern void cpu_move8 (sim_cpu *proc, uint8 op);
81e09ed8 SC	534	extern void cpu_move16 (sim_cpu *proc, uint8 op);
e0709f50 AC	535
e0709f50 AC	536	extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
81e09ed8	537	extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
e0709f50 AC	538	extern void cpu_push_all (sim_cpu *proc);
	539	extern void cpu_single_step (sim_cpu *proc);
	540
	541	extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
	542
	543	extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
	544
63f36def SC	545	/* Returns the address of a 68HC12 indexed operand.
63f36def SC	546	Pre and post modifications are handled on the source register. */
2b6ca062	547	extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
63f36def SC	548
63f36def SC	549	extern void cpu_return (sim_cpu *cpu);
e0709f50	550	extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
e0709f50 AC	551	extern int cpu_reset (sim_cpu *cpu);
	552	extern int cpu_restart (sim_cpu *cpu);
	553	extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
	554	uint16 addr, const char *message, ...);
	555	extern void emul_os (int op, sim_cpu *cpu);
81e09ed8 SC	556	extern void cpu_interp_m6811 (sim_cpu *cpu);
81e09ed8 SC	557	extern void cpu_interp_m6812 (sim_cpu *cpu);
e0709f50	558
827ec39a SC	559	extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
	560	double ton, double toff,
	561	signed64 repeat);
	562	extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
	563	extern void m68hc11cpu_set_port (struct hw me, sim_cpu cpu,
	564	unsigned addr, uint8 val);
	565
e0709f50 AC	566	/* The current state of the processor; registers, memory, etc. */
e0709f50 AC	567
e0709f50	568	struct sim_state {
bea3f671	569	sim_cpu *cpu[MAX_NR_PROCESSORS];
e0709f50 AC	570	device *devices;
	571	sim_state_base base;
	572	};
	573
e0709f50 AC	574	extern void sim_board_reset (SIM_DESC sd);
e0709f50 AC	575
a685700c SC	576	#define PRINT_TIME 0x01
	577	#define PRINT_CYCLE 0x02
	578	extern const char cycle_to_string (sim_cpu cpu, signed64 t, int flags);
2990a9f4	579
e0709f50 AC	580	#endif
	581
	582