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0fda6bd2 | 1 | /* Simulator for Motorola's MCore processor |
3666a048 | 2 | Copyright (C) 1999-2021 Free Software Foundation, Inc. |
2d514e6f SS |
3 | Contributed by Cygnus Solutions. |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
2d514e6f SS |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
2d514e6f | 19 | |
6df01ab8 MF |
20 | /* This must come before any other includes. */ |
21 | #include "defs.h" | |
22 | ||
2d514e6f | 23 | #include <signal.h> |
dc049bf4 MF |
24 | #include <stdlib.h> |
25 | #include <string.h> | |
2d514e6f | 26 | #include <sys/param.h> |
4185814e | 27 | #include <unistd.h> |
2d514e6f | 28 | #include "bfd.h" |
df68e12b | 29 | #include "sim/callback.h" |
2d514e6f | 30 | #include "libiberty.h" |
df68e12b | 31 | #include "sim/sim.h" |
2d514e6f | 32 | |
ea6b7543 MF |
33 | #include "sim-main.h" |
34 | #include "sim-base.h" | |
1fef66b0 | 35 | #include "sim-signal.h" |
61a0c964 | 36 | #include "sim-syscall.h" |
ea6b7543 MF |
37 | #include "sim-options.h" |
38 | ||
ea6b7543 | 39 | #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) |
2d514e6f SS |
40 | |
41 | ||
feb703b3 MF |
42 | static unsigned long |
43 | mcore_extract_unsigned_integer (unsigned char *addr, int len) | |
2d514e6f SS |
44 | { |
45 | unsigned long retval; | |
46 | unsigned char * p; | |
47 | unsigned char * startaddr = (unsigned char *)addr; | |
48 | unsigned char * endaddr = startaddr + len; | |
ba14f941 | 49 | |
2d514e6f | 50 | if (len > (int) sizeof (unsigned long)) |
feb703b3 | 51 | printf ("That operation is not available on integers of more than %zu bytes.", |
2d514e6f | 52 | sizeof (unsigned long)); |
ba14f941 | 53 | |
2d514e6f SS |
54 | /* Start at the most significant end of the integer, and work towards |
55 | the least significant. */ | |
56 | retval = 0; | |
cd0fc7c3 | 57 | |
63a027a3 NC |
58 | if (! target_big_endian) |
59 | { | |
60 | for (p = endaddr; p > startaddr;) | |
61 | retval = (retval << 8) | * -- p; | |
62 | } | |
63 | else | |
cd0fc7c3 SS |
64 | { |
65 | for (p = startaddr; p < endaddr;) | |
66 | retval = (retval << 8) | * p ++; | |
67 | } | |
ba14f941 | 68 | |
2d514e6f SS |
69 | return retval; |
70 | } | |
71 | ||
feb703b3 MF |
72 | static void |
73 | mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val) | |
2d514e6f SS |
74 | { |
75 | unsigned char * p; | |
76 | unsigned char * startaddr = (unsigned char *)addr; | |
77 | unsigned char * endaddr = startaddr + len; | |
cd0fc7c3 | 78 | |
63a027a3 NC |
79 | if (! target_big_endian) |
80 | { | |
81 | for (p = startaddr; p < endaddr;) | |
82 | { | |
83 | * p ++ = val & 0xff; | |
84 | val >>= 8; | |
85 | } | |
86 | } | |
87 | else | |
2d514e6f | 88 | { |
cd0fc7c3 SS |
89 | for (p = endaddr; p > startaddr;) |
90 | { | |
91 | * -- p = val & 0xff; | |
92 | val >>= 8; | |
93 | } | |
2d514e6f SS |
94 | } |
95 | } | |
96 | ||
ea6b7543 | 97 | static int memcycles = 1; |
2d514e6f | 98 | |
7eed1055 MF |
99 | #define gr cpu->active_gregs |
100 | #define cr cpu->regs.cregs | |
101 | #define sr cr[0] | |
102 | #define vbr cr[1] | |
103 | #define esr cr[2] | |
104 | #define fsr cr[3] | |
105 | #define epc cr[4] | |
106 | #define fpc cr[5] | |
107 | #define ss0 cr[6] | |
108 | #define ss1 cr[7] | |
109 | #define ss2 cr[8] | |
110 | #define ss3 cr[9] | |
111 | #define ss4 cr[10] | |
112 | #define gcr cr[11] | |
113 | #define gsr cr[12] | |
2d514e6f SS |
114 | |
115 | /* maniuplate the carry bit */ | |
7eed1055 MF |
116 | #define C_ON() (sr & 1) |
117 | #define C_VALUE() (sr & 1) | |
118 | #define C_OFF() ((sr & 1) == 0) | |
119 | #define SET_C() {sr |= 1;} | |
120 | #define CLR_C() {sr &= 0xfffffffe;} | |
121 | #define NEW_C(v) {CLR_C(); sr |= ((v) & 1);} | |
122 | ||
123 | #define SR_AF() ((sr >> 1) & 1) | |
124 | static void set_active_regs (SIM_CPU *cpu) | |
125 | { | |
126 | if (SR_AF()) | |
127 | cpu->active_gregs = cpu->regs.alt_gregs; | |
128 | else | |
129 | cpu->active_gregs = cpu->regs.gregs; | |
130 | } | |
2d514e6f SS |
131 | |
132 | #define TRAPCODE 1 /* r1 holds which function we want */ | |
133 | #define PARM1 2 /* first parameter */ | |
134 | #define PARM2 3 | |
135 | #define PARM3 4 | |
136 | #define PARM4 5 | |
137 | #define RET1 2 /* register for return values. */ | |
138 | ||
4cd93614 | 139 | /* Default to a 8 Mbyte (== 2^23) memory space. */ |
f63036b8 | 140 | #define DEFAULT_MEMORY_SIZE 0x800000 |
2d514e6f SS |
141 | |
142 | static void | |
7eed1055 | 143 | set_initial_gprs (SIM_CPU *cpu) |
2d514e6f | 144 | { |
2d514e6f | 145 | /* Set up machine just out of reset. */ |
7eed1055 MF |
146 | CPU_PC_SET (cpu, 0); |
147 | sr = 0; | |
ba14f941 | 148 | |
2d514e6f | 149 | /* Clean out the GPRs and alternate GPRs. */ |
7eed1055 MF |
150 | memset (&cpu->regs.gregs, 0, sizeof(cpu->regs.gregs)); |
151 | memset (&cpu->regs.alt_gregs, 0, sizeof(cpu->regs.alt_gregs)); | |
ba14f941 | 152 | |
2d514e6f | 153 | /* Make our register set point to the right place. */ |
7eed1055 | 154 | set_active_regs (cpu); |
ba14f941 | 155 | |
2d514e6f | 156 | /* ABI specifies initial values for these registers. */ |
7eed1055 | 157 | gr[0] = DEFAULT_MEMORY_SIZE - 4; |
ba14f941 | 158 | |
2d514e6f | 159 | /* dac fix, the stack address must be 8-byte aligned! */ |
7eed1055 MF |
160 | gr[0] = gr[0] - gr[0] % 8; |
161 | gr[PARM1] = 0; | |
162 | gr[PARM2] = 0; | |
163 | gr[PARM3] = 0; | |
164 | gr[PARM4] = gr[0]; | |
2d514e6f SS |
165 | } |
166 | ||
767e68f1 MF |
167 | /* Simulate a monitor trap. */ |
168 | ||
2d514e6f | 169 | static void |
7eed1055 | 170 | handle_trap1 (SIM_DESC sd, SIM_CPU *cpu) |
2d514e6f | 171 | { |
767e68f1 | 172 | /* XXX: We don't pass back the actual errno value. */ |
7eed1055 MF |
173 | gr[RET1] = sim_syscall (cpu, gr[TRAPCODE], gr[PARM1], gr[PARM2], gr[PARM3], |
174 | gr[PARM4]); | |
2d514e6f SS |
175 | } |
176 | ||
177 | static void | |
7eed1055 | 178 | process_stub (SIM_DESC sd, SIM_CPU *cpu, int what) |
2d514e6f SS |
179 | { |
180 | /* These values should match those in libgloss/mcore/syscalls.s. */ | |
181 | switch (what) | |
182 | { | |
183 | case 3: /* _read */ | |
cd0fc7c3 | 184 | case 4: /* _write */ |
2d514e6f SS |
185 | case 5: /* _open */ |
186 | case 6: /* _close */ | |
187 | case 10: /* _unlink */ | |
188 | case 19: /* _lseek */ | |
189 | case 43: /* _times */ | |
7eed1055 MF |
190 | gr[TRAPCODE] = what; |
191 | handle_trap1 (sd, cpu); | |
2d514e6f | 192 | break; |
ba14f941 | 193 | |
2d514e6f | 194 | default: |
f63036b8 | 195 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
196 | fprintf (stderr, "Unhandled stub opcode: %d\n", what); |
197 | break; | |
198 | } | |
199 | } | |
200 | ||
201 | static void | |
7eed1055 | 202 | util (SIM_DESC sd, SIM_CPU *cpu, unsigned what) |
2d514e6f SS |
203 | { |
204 | switch (what) | |
205 | { | |
206 | case 0: /* exit */ | |
7eed1055 | 207 | sim_engine_halt (sd, cpu, NULL, cpu->regs.pc, sim_exited, gr[PARM1]); |
2d514e6f SS |
208 | break; |
209 | ||
210 | case 1: /* printf */ | |
f63036b8 MF |
211 | if (STATE_VERBOSE_P (sd)) |
212 | fprintf (stderr, "WARNING: printf unimplemented\n"); | |
2d514e6f | 213 | break; |
ba14f941 | 214 | |
2d514e6f | 215 | case 2: /* scanf */ |
f63036b8 | 216 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
217 | fprintf (stderr, "WARNING: scanf unimplemented\n"); |
218 | break; | |
ba14f941 | 219 | |
2d514e6f | 220 | case 3: /* utime */ |
7eed1055 | 221 | gr[RET1] = cpu->insts; |
2d514e6f SS |
222 | break; |
223 | ||
224 | case 0xFF: | |
7eed1055 | 225 | process_stub (sd, cpu, gr[1]); |
2d514e6f | 226 | break; |
ba14f941 | 227 | |
2d514e6f | 228 | default: |
f63036b8 | 229 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
230 | fprintf (stderr, "Unhandled util code: %x\n", what); |
231 | break; | |
232 | } | |
ba14f941 | 233 | } |
2d514e6f SS |
234 | |
235 | /* For figuring out whether we carried; addc/subc use this. */ | |
236 | static int | |
feb703b3 | 237 | iu_carry (unsigned long a, unsigned long b, int cin) |
2d514e6f SS |
238 | { |
239 | unsigned long x; | |
ba14f941 | 240 | |
2d514e6f SS |
241 | x = (a & 0xffff) + (b & 0xffff) + cin; |
242 | x = (x >> 16) + (a >> 16) + (b >> 16); | |
243 | x >>= 16; | |
244 | ||
245 | return (x != 0); | |
246 | } | |
247 | ||
e53e5aab MF |
248 | /* TODO: Convert to common watchpoints. */ |
249 | #undef WATCHFUNCTIONS | |
2d514e6f SS |
250 | #ifdef WATCHFUNCTIONS |
251 | ||
252 | #define MAXWL 80 | |
253 | word WL[MAXWL]; | |
254 | char * WLstr[MAXWL]; | |
255 | ||
256 | int ENDWL=0; | |
257 | int WLincyc; | |
258 | int WLcyc[MAXWL]; | |
259 | int WLcnts[MAXWL]; | |
260 | int WLmax[MAXWL]; | |
261 | int WLmin[MAXWL]; | |
262 | word WLendpc; | |
263 | int WLbcyc; | |
264 | int WLW; | |
265 | #endif | |
266 | ||
267 | #define RD (inst & 0xF) | |
268 | #define RS ((inst >> 4) & 0xF) | |
269 | #define RX ((inst >> 8) & 0xF) | |
270 | #define IMM5 ((inst >> 4) & 0x1F) | |
271 | #define IMM4 ((inst) & 0xF) | |
272 | ||
7eed1055 MF |
273 | #define rbat(X) sim_core_read_1 (cpu, 0, read_map, X) |
274 | #define rhat(X) sim_core_read_2 (cpu, 0, read_map, X) | |
275 | #define rlat(X) sim_core_read_4 (cpu, 0, read_map, X) | |
276 | #define wbat(X, D) sim_core_write_1 (cpu, 0, write_map, X, D) | |
277 | #define what(X, D) sim_core_write_2 (cpu, 0, write_map, X, D) | |
278 | #define wlat(X, D) sim_core_write_4 (cpu, 0, write_map, X, D) | |
f63036b8 | 279 | |
2d514e6f SS |
280 | static int tracing = 0; |
281 | ||
02962cd9 | 282 | #define ILLEGAL() \ |
7eed1055 | 283 | sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL) |
02962cd9 MF |
284 | |
285 | static void | |
7eed1055 | 286 | step_once (SIM_DESC sd, SIM_CPU *cpu) |
2d514e6f SS |
287 | { |
288 | int needfetch; | |
289 | word ibuf; | |
290 | word pc; | |
291 | unsigned short inst; | |
2d514e6f SS |
292 | int memops; |
293 | int bonus_cycles; | |
294 | int insts; | |
295 | int w; | |
296 | int cycs; | |
e53e5aab | 297 | #ifdef WATCHFUNCTIONS |
2d514e6f | 298 | word WLhash; |
e53e5aab | 299 | #endif |
2d514e6f | 300 | |
7eed1055 | 301 | pc = CPU_PC_GET (cpu); |
2d514e6f | 302 | |
cd0fc7c3 | 303 | /* Fetch the initial instructions that we'll decode. */ |
2d514e6f SS |
304 | ibuf = rlat (pc & 0xFFFFFFFC); |
305 | needfetch = 0; | |
306 | ||
307 | memops = 0; | |
308 | bonus_cycles = 0; | |
309 | insts = 0; | |
ba14f941 | 310 | |
2d514e6f | 311 | /* make our register set point to the right place */ |
7eed1055 | 312 | set_active_regs (cpu); |
ba14f941 | 313 | |
e53e5aab | 314 | #ifdef WATCHFUNCTIONS |
2d514e6f SS |
315 | /* make a hash to speed exec loop, hope it's nonzero */ |
316 | WLhash = 0xFFFFFFFF; | |
317 | ||
318 | for (w = 1; w <= ENDWL; w++) | |
319 | WLhash = WLhash & WL[w]; | |
e53e5aab | 320 | #endif |
2d514e6f | 321 | |
02962cd9 | 322 | /* TODO: Unindent this block. */ |
2d514e6f | 323 | { |
cd0fc7c3 | 324 | word oldpc; |
ba14f941 | 325 | |
2d514e6f | 326 | insts ++; |
ba14f941 | 327 | |
2d514e6f SS |
328 | if (pc & 02) |
329 | { | |
63a027a3 NC |
330 | if (! target_big_endian) |
331 | inst = ibuf >> 16; | |
332 | else | |
cd0fc7c3 | 333 | inst = ibuf & 0xFFFF; |
2d514e6f SS |
334 | needfetch = 1; |
335 | } | |
336 | else | |
337 | { | |
63a027a3 NC |
338 | if (! target_big_endian) |
339 | inst = ibuf & 0xFFFF; | |
340 | else | |
cd0fc7c3 | 341 | inst = ibuf >> 16; |
2d514e6f SS |
342 | } |
343 | ||
344 | #ifdef WATCHFUNCTIONS | |
345 | /* now scan list of watch addresses, if match, count it and | |
346 | note return address and count cycles until pc=return address */ | |
ba14f941 | 347 | |
2d514e6f SS |
348 | if ((WLincyc == 1) && (pc == WLendpc)) |
349 | { | |
7eed1055 | 350 | cycs = (cpu->cycles + (insts + bonus_cycles + |
2d514e6f | 351 | (memops * memcycles)) - WLbcyc); |
ba14f941 | 352 | |
2d514e6f SS |
353 | if (WLcnts[WLW] == 1) |
354 | { | |
355 | WLmax[WLW] = cycs; | |
356 | WLmin[WLW] = cycs; | |
357 | WLcyc[WLW] = 0; | |
358 | } | |
ba14f941 | 359 | |
2d514e6f SS |
360 | if (cycs > WLmax[WLW]) |
361 | { | |
362 | WLmax[WLW] = cycs; | |
363 | } | |
ba14f941 | 364 | |
2d514e6f SS |
365 | if (cycs < WLmin[WLW]) |
366 | { | |
367 | WLmin[WLW] = cycs; | |
368 | } | |
ba14f941 | 369 | |
2d514e6f SS |
370 | WLcyc[WLW] += cycs; |
371 | WLincyc = 0; | |
372 | WLendpc = 0; | |
ba14f941 | 373 | } |
2d514e6f | 374 | |
cd0fc7c3 | 375 | /* Optimize with a hash to speed loop. */ |
2d514e6f SS |
376 | if (WLincyc == 0) |
377 | { | |
378 | if ((WLhash == 0) || ((WLhash & pc) != 0)) | |
379 | { | |
380 | for (w=1; w <= ENDWL; w++) | |
381 | { | |
382 | if (pc == WL[w]) | |
383 | { | |
384 | WLcnts[w]++; | |
7eed1055 | 385 | WLbcyc = cpu->cycles + insts |
2d514e6f | 386 | + bonus_cycles + (memops * memcycles); |
7eed1055 | 387 | WLendpc = gr[15]; |
2d514e6f SS |
388 | WLincyc = 1; |
389 | WLW = w; | |
390 | break; | |
391 | } | |
392 | } | |
393 | } | |
394 | } | |
395 | #endif | |
396 | ||
397 | if (tracing) | |
43236bb2 | 398 | fprintf (stderr, "%.4lx: inst = %.4x ", pc, inst); |
cd0fc7c3 SS |
399 | |
400 | oldpc = pc; | |
ba14f941 | 401 | |
2d514e6f | 402 | pc += 2; |
ba14f941 | 403 | |
2d514e6f SS |
404 | switch (inst >> 8) |
405 | { | |
406 | case 0x00: | |
407 | switch RS | |
408 | { | |
409 | case 0x0: | |
410 | switch RD | |
411 | { | |
412 | case 0x0: /* bkpt */ | |
9e086581 | 413 | pc -= 2; |
7eed1055 | 414 | sim_engine_halt (sd, cpu, NULL, pc - 2, |
02962cd9 | 415 | sim_stopped, SIM_SIGTRAP); |
2d514e6f | 416 | break; |
ba14f941 | 417 | |
2d514e6f SS |
418 | case 0x1: /* sync */ |
419 | break; | |
ba14f941 | 420 | |
2d514e6f | 421 | case 0x2: /* rte */ |
7eed1055 MF |
422 | pc = epc; |
423 | sr = esr; | |
2d514e6f | 424 | needfetch = 1; |
ba14f941 | 425 | |
7eed1055 | 426 | set_active_regs (cpu); |
2d514e6f SS |
427 | break; |
428 | ||
429 | case 0x3: /* rfi */ | |
7eed1055 MF |
430 | pc = fpc; |
431 | sr = fsr; | |
2d514e6f SS |
432 | needfetch = 1; |
433 | ||
7eed1055 | 434 | set_active_regs (cpu); |
2d514e6f | 435 | break; |
ba14f941 | 436 | |
2d514e6f | 437 | case 0x4: /* stop */ |
f63036b8 | 438 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
439 | fprintf (stderr, "WARNING: stop unimplemented\n"); |
440 | break; | |
ba14f941 | 441 | |
2d514e6f | 442 | case 0x5: /* wait */ |
f63036b8 | 443 | if (STATE_VERBOSE_P (sd)) |
2d514e6f SS |
444 | fprintf (stderr, "WARNING: wait unimplemented\n"); |
445 | break; | |
ba14f941 | 446 | |
2d514e6f | 447 | case 0x6: /* doze */ |
f63036b8 | 448 | if (STATE_VERBOSE_P (sd)) |
cd0fc7c3 | 449 | fprintf (stderr, "WARNING: doze unimplemented\n"); |
2d514e6f | 450 | break; |
ba14f941 | 451 | |
2d514e6f | 452 | case 0x7: |
02962cd9 | 453 | ILLEGAL (); /* illegal */ |
2d514e6f | 454 | break; |
ba14f941 | 455 | |
2d514e6f SS |
456 | case 0x8: /* trap 0 */ |
457 | case 0xA: /* trap 2 */ | |
458 | case 0xB: /* trap 3 */ | |
7eed1055 | 459 | sim_engine_halt (sd, cpu, NULL, pc, |
02962cd9 | 460 | sim_stopped, SIM_SIGTRAP); |
2d514e6f | 461 | break; |
ba14f941 | 462 | |
2d514e6f SS |
463 | case 0xC: /* trap 4 */ |
464 | case 0xD: /* trap 5 */ | |
465 | case 0xE: /* trap 6 */ | |
02962cd9 | 466 | ILLEGAL (); /* illegal */ |
2d514e6f | 467 | break; |
ba14f941 | 468 | |
2d514e6f | 469 | case 0xF: /* trap 7 */ |
7eed1055 | 470 | sim_engine_halt (sd, cpu, NULL, pc, /* integer div-by-0 */ |
02962cd9 | 471 | sim_stopped, SIM_SIGTRAP); |
2d514e6f | 472 | break; |
ba14f941 | 473 | |
2d514e6f | 474 | case 0x9: /* trap 1 */ |
7eed1055 | 475 | handle_trap1 (sd, cpu); |
2d514e6f SS |
476 | break; |
477 | } | |
478 | break; | |
ba14f941 | 479 | |
2d514e6f | 480 | case 0x1: |
02962cd9 | 481 | ILLEGAL (); /* illegal */ |
2d514e6f | 482 | break; |
ba14f941 | 483 | |
2d514e6f | 484 | case 0x2: /* mvc */ |
7eed1055 | 485 | gr[RD] = C_VALUE(); |
2d514e6f SS |
486 | break; |
487 | case 0x3: /* mvcv */ | |
7eed1055 | 488 | gr[RD] = C_OFF(); |
2d514e6f SS |
489 | break; |
490 | case 0x4: /* ldq */ | |
491 | { | |
7eed1055 | 492 | word addr = gr[RD]; |
2d514e6f | 493 | int regno = 4; /* always r4-r7 */ |
ba14f941 | 494 | |
2d514e6f SS |
495 | bonus_cycles++; |
496 | memops += 4; | |
497 | do | |
498 | { | |
7eed1055 | 499 | gr[regno] = rlat (addr); |
2d514e6f SS |
500 | addr += 4; |
501 | regno++; | |
502 | } | |
503 | while ((regno&0x3) != 0); | |
504 | } | |
505 | break; | |
506 | case 0x5: /* stq */ | |
507 | { | |
7eed1055 | 508 | word addr = gr[RD]; |
2d514e6f | 509 | int regno = 4; /* always r4-r7 */ |
ba14f941 | 510 | |
2d514e6f SS |
511 | memops += 4; |
512 | bonus_cycles++; | |
513 | do | |
514 | { | |
7eed1055 | 515 | wlat (addr, gr[regno]); |
2d514e6f SS |
516 | addr += 4; |
517 | regno++; | |
518 | } | |
519 | while ((regno & 0x3) != 0); | |
520 | } | |
521 | break; | |
522 | case 0x6: /* ldm */ | |
523 | { | |
7eed1055 | 524 | word addr = gr[0]; |
2d514e6f | 525 | int regno = RD; |
ba14f941 | 526 | |
2d514e6f SS |
527 | /* bonus cycle is really only needed if |
528 | the next insn shifts the last reg loaded. | |
ba14f941 | 529 | |
2d514e6f SS |
530 | bonus_cycles++; |
531 | */ | |
532 | memops += 16-regno; | |
533 | while (regno <= 0xF) | |
534 | { | |
7eed1055 | 535 | gr[regno] = rlat (addr); |
2d514e6f SS |
536 | addr += 4; |
537 | regno++; | |
538 | } | |
539 | } | |
540 | break; | |
541 | case 0x7: /* stm */ | |
542 | { | |
7eed1055 | 543 | word addr = gr[0]; |
2d514e6f | 544 | int regno = RD; |
ba14f941 | 545 | |
2d514e6f SS |
546 | /* this should be removed! */ |
547 | /* bonus_cycles ++; */ | |
548 | ||
549 | memops += 16 - regno; | |
550 | while (regno <= 0xF) | |
551 | { | |
7eed1055 | 552 | wlat (addr, gr[regno]); |
2d514e6f SS |
553 | addr += 4; |
554 | regno++; | |
555 | } | |
556 | } | |
557 | break; | |
558 | ||
559 | case 0x8: /* dect */ | |
7eed1055 | 560 | gr[RD] -= C_VALUE(); |
2d514e6f SS |
561 | break; |
562 | case 0x9: /* decf */ | |
7eed1055 | 563 | gr[RD] -= C_OFF(); |
2d514e6f SS |
564 | break; |
565 | case 0xA: /* inct */ | |
7eed1055 | 566 | gr[RD] += C_VALUE(); |
2d514e6f SS |
567 | break; |
568 | case 0xB: /* incf */ | |
7eed1055 | 569 | gr[RD] += C_OFF(); |
2d514e6f SS |
570 | break; |
571 | case 0xC: /* jmp */ | |
7eed1055 | 572 | pc = gr[RD]; |
392a587b | 573 | if (tracing && RD == 15) |
43236bb2 | 574 | fprintf (stderr, "Func return, r2 = %lxx, r3 = %lx\n", |
7eed1055 | 575 | gr[2], gr[3]); |
2d514e6f SS |
576 | bonus_cycles++; |
577 | needfetch = 1; | |
578 | break; | |
579 | case 0xD: /* jsr */ | |
7eed1055 MF |
580 | gr[15] = pc; |
581 | pc = gr[RD]; | |
2d514e6f SS |
582 | bonus_cycles++; |
583 | needfetch = 1; | |
584 | break; | |
585 | case 0xE: /* ff1 */ | |
586 | { | |
587 | word tmp, i; | |
7eed1055 | 588 | tmp = gr[RD]; |
2d514e6f SS |
589 | for (i = 0; !(tmp & 0x80000000) && i < 32; i++) |
590 | tmp <<= 1; | |
7eed1055 | 591 | gr[RD] = i; |
2d514e6f SS |
592 | } |
593 | break; | |
594 | case 0xF: /* brev */ | |
595 | { | |
596 | word tmp; | |
7eed1055 | 597 | tmp = gr[RD]; |
2d514e6f SS |
598 | tmp = ((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1); |
599 | tmp = ((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2); | |
600 | tmp = ((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4); | |
601 | tmp = ((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8); | |
7eed1055 | 602 | gr[RD] = ((tmp & 0xffff0000) >> 16) | ((tmp & 0x0000ffff) << 16); |
2d514e6f SS |
603 | } |
604 | break; | |
605 | } | |
606 | break; | |
607 | case 0x01: | |
608 | switch RS | |
609 | { | |
ba14f941 | 610 | case 0x0: /* xtrb3 */ |
7eed1055 MF |
611 | gr[1] = (gr[RD]) & 0xFF; |
612 | NEW_C (gr[RD] != 0); | |
2d514e6f SS |
613 | break; |
614 | case 0x1: /* xtrb2 */ | |
7eed1055 MF |
615 | gr[1] = (gr[RD]>>8) & 0xFF; |
616 | NEW_C (gr[RD] != 0); | |
2d514e6f SS |
617 | break; |
618 | case 0x2: /* xtrb1 */ | |
7eed1055 MF |
619 | gr[1] = (gr[RD]>>16) & 0xFF; |
620 | NEW_C (gr[RD] != 0); | |
2d514e6f SS |
621 | break; |
622 | case 0x3: /* xtrb0 */ | |
7eed1055 MF |
623 | gr[1] = (gr[RD]>>24) & 0xFF; |
624 | NEW_C (gr[RD] != 0); | |
2d514e6f SS |
625 | break; |
626 | case 0x4: /* zextb */ | |
7eed1055 | 627 | gr[RD] &= 0x000000FF; |
2d514e6f SS |
628 | break; |
629 | case 0x5: /* sextb */ | |
630 | { | |
631 | long tmp; | |
7eed1055 | 632 | tmp = gr[RD]; |
2d514e6f SS |
633 | tmp <<= 24; |
634 | tmp >>= 24; | |
7eed1055 | 635 | gr[RD] = tmp; |
2d514e6f SS |
636 | } |
637 | break; | |
638 | case 0x6: /* zexth */ | |
7eed1055 | 639 | gr[RD] &= 0x0000FFFF; |
2d514e6f SS |
640 | break; |
641 | case 0x7: /* sexth */ | |
642 | { | |
643 | long tmp; | |
7eed1055 | 644 | tmp = gr[RD]; |
2d514e6f SS |
645 | tmp <<= 16; |
646 | tmp >>= 16; | |
7eed1055 | 647 | gr[RD] = tmp; |
2d514e6f SS |
648 | } |
649 | break; | |
ba14f941 | 650 | case 0x8: /* declt */ |
7eed1055 MF |
651 | --gr[RD]; |
652 | NEW_C ((long)gr[RD] < 0); | |
2d514e6f SS |
653 | break; |
654 | case 0x9: /* tstnbz */ | |
655 | { | |
7eed1055 | 656 | word tmp = gr[RD]; |
2d514e6f SS |
657 | NEW_C ((tmp & 0xFF000000) != 0 && |
658 | (tmp & 0x00FF0000) != 0 && (tmp & 0x0000FF00) != 0 && | |
659 | (tmp & 0x000000FF) != 0); | |
660 | } | |
ba14f941 | 661 | break; |
2d514e6f | 662 | case 0xA: /* decgt */ |
7eed1055 MF |
663 | --gr[RD]; |
664 | NEW_C ((long)gr[RD] > 0); | |
2d514e6f SS |
665 | break; |
666 | case 0xB: /* decne */ | |
7eed1055 MF |
667 | --gr[RD]; |
668 | NEW_C ((long)gr[RD] != 0); | |
2d514e6f SS |
669 | break; |
670 | case 0xC: /* clrt */ | |
671 | if (C_ON()) | |
7eed1055 | 672 | gr[RD] = 0; |
2d514e6f SS |
673 | break; |
674 | case 0xD: /* clrf */ | |
675 | if (C_OFF()) | |
7eed1055 | 676 | gr[RD] = 0; |
2d514e6f SS |
677 | break; |
678 | case 0xE: /* abs */ | |
7eed1055 MF |
679 | if (gr[RD] & 0x80000000) |
680 | gr[RD] = ~gr[RD] + 1; | |
2d514e6f SS |
681 | break; |
682 | case 0xF: /* not */ | |
7eed1055 | 683 | gr[RD] = ~gr[RD]; |
2d514e6f SS |
684 | break; |
685 | } | |
686 | break; | |
687 | case 0x02: /* movt */ | |
688 | if (C_ON()) | |
7eed1055 | 689 | gr[RD] = gr[RS]; |
2d514e6f SS |
690 | break; |
691 | case 0x03: /* mult */ | |
692 | /* consume 2 bits per cycle from rs, until rs is 0 */ | |
693 | { | |
7eed1055 | 694 | unsigned int t = gr[RS]; |
2d514e6f | 695 | int ticks; |
ba14f941 | 696 | for (ticks = 0; t != 0 ; t >>= 2) |
2d514e6f SS |
697 | ticks++; |
698 | bonus_cycles += ticks; | |
699 | } | |
700 | bonus_cycles += 2; /* min. is 3, so add 2, plus ticks above */ | |
392a587b | 701 | if (tracing) |
43236bb2 | 702 | fprintf (stderr, " mult %lx by %lx to give %lx", |
7eed1055 MF |
703 | gr[RD], gr[RS], gr[RD] * gr[RS]); |
704 | gr[RD] = gr[RD] * gr[RS]; | |
2d514e6f SS |
705 | break; |
706 | case 0x04: /* loopt */ | |
707 | if (C_ON()) | |
708 | { | |
709 | pc += (IMM4 << 1) - 32; | |
710 | bonus_cycles ++; | |
711 | needfetch = 1; | |
712 | } | |
7eed1055 MF |
713 | --gr[RS]; /* not RD! */ |
714 | NEW_C (((long)gr[RS]) > 0); | |
ba14f941 | 715 | break; |
2d514e6f | 716 | case 0x05: /* subu */ |
7eed1055 | 717 | gr[RD] -= gr[RS]; |
2d514e6f SS |
718 | break; |
719 | case 0x06: /* addc */ | |
720 | { | |
721 | unsigned long tmp, a, b; | |
7eed1055 MF |
722 | a = gr[RD]; |
723 | b = gr[RS]; | |
724 | gr[RD] = a + b + C_VALUE (); | |
2d514e6f SS |
725 | tmp = iu_carry (a, b, C_VALUE ()); |
726 | NEW_C (tmp); | |
727 | } | |
728 | break; | |
729 | case 0x07: /* subc */ | |
730 | { | |
731 | unsigned long tmp, a, b; | |
7eed1055 MF |
732 | a = gr[RD]; |
733 | b = gr[RS]; | |
734 | gr[RD] = a - b + C_VALUE () - 1; | |
2d514e6f SS |
735 | tmp = iu_carry (a,~b, C_VALUE ()); |
736 | NEW_C (tmp); | |
737 | } | |
738 | break; | |
739 | case 0x08: /* illegal */ | |
740 | case 0x09: /* illegal*/ | |
02962cd9 | 741 | ILLEGAL (); |
2d514e6f SS |
742 | break; |
743 | case 0x0A: /* movf */ | |
744 | if (C_OFF()) | |
7eed1055 | 745 | gr[RD] = gr[RS]; |
2d514e6f SS |
746 | break; |
747 | case 0x0B: /* lsr */ | |
ba14f941 | 748 | { |
2d514e6f | 749 | unsigned long dst, src; |
7eed1055 MF |
750 | dst = gr[RD]; |
751 | src = gr[RS]; | |
c5394b80 JM |
752 | /* We must not rely solely upon the native shift operations, since they |
753 | may not match the M*Core's behaviour on boundary conditions. */ | |
754 | dst = src > 31 ? 0 : dst >> src; | |
7eed1055 | 755 | gr[RD] = dst; |
2d514e6f SS |
756 | } |
757 | break; | |
758 | case 0x0C: /* cmphs */ | |
7eed1055 MF |
759 | NEW_C ((unsigned long )gr[RD] >= |
760 | (unsigned long)gr[RS]); | |
2d514e6f SS |
761 | break; |
762 | case 0x0D: /* cmplt */ | |
7eed1055 | 763 | NEW_C ((long)gr[RD] < (long)gr[RS]); |
2d514e6f SS |
764 | break; |
765 | case 0x0E: /* tst */ | |
7eed1055 | 766 | NEW_C ((gr[RD] & gr[RS]) != 0); |
2d514e6f SS |
767 | break; |
768 | case 0x0F: /* cmpne */ | |
7eed1055 | 769 | NEW_C (gr[RD] != gr[RS]); |
2d514e6f SS |
770 | break; |
771 | case 0x10: case 0x11: /* mfcr */ | |
772 | { | |
773 | unsigned r; | |
774 | r = IMM5; | |
775 | if (r <= LAST_VALID_CREG) | |
7eed1055 | 776 | gr[RD] = cr[r]; |
2d514e6f | 777 | else |
02962cd9 | 778 | ILLEGAL (); |
2d514e6f SS |
779 | } |
780 | break; | |
781 | ||
782 | case 0x12: /* mov */ | |
7eed1055 | 783 | gr[RD] = gr[RS]; |
392a587b | 784 | if (tracing) |
7eed1055 | 785 | fprintf (stderr, "MOV %lx into reg %d", gr[RD], RD); |
2d514e6f SS |
786 | break; |
787 | ||
788 | case 0x13: /* bgenr */ | |
7eed1055 MF |
789 | if (gr[RS] & 0x20) |
790 | gr[RD] = 0; | |
2d514e6f | 791 | else |
7eed1055 | 792 | gr[RD] = 1 << (gr[RS] & 0x1F); |
2d514e6f SS |
793 | break; |
794 | ||
795 | case 0x14: /* rsub */ | |
7eed1055 | 796 | gr[RD] = gr[RS] - gr[RD]; |
2d514e6f SS |
797 | break; |
798 | ||
799 | case 0x15: /* ixw */ | |
7eed1055 | 800 | gr[RD] += gr[RS]<<2; |
2d514e6f SS |
801 | break; |
802 | ||
803 | case 0x16: /* and */ | |
7eed1055 | 804 | gr[RD] &= gr[RS]; |
2d514e6f SS |
805 | break; |
806 | ||
807 | case 0x17: /* xor */ | |
7eed1055 | 808 | gr[RD] ^= gr[RS]; |
2d514e6f SS |
809 | break; |
810 | ||
811 | case 0x18: case 0x19: /* mtcr */ | |
812 | { | |
813 | unsigned r; | |
814 | r = IMM5; | |
815 | if (r <= LAST_VALID_CREG) | |
7eed1055 | 816 | cr[r] = gr[RD]; |
2d514e6f | 817 | else |
02962cd9 | 818 | ILLEGAL (); |
ba14f941 | 819 | |
2d514e6f | 820 | /* we might have changed register sets... */ |
7eed1055 | 821 | set_active_regs (cpu); |
2d514e6f SS |
822 | } |
823 | break; | |
824 | ||
825 | case 0x1A: /* asr */ | |
c5394b80 JM |
826 | /* We must not rely solely upon the native shift operations, since they |
827 | may not match the M*Core's behaviour on boundary conditions. */ | |
7eed1055 MF |
828 | if (gr[RS] > 30) |
829 | gr[RD] = ((long) gr[RD]) < 0 ? -1 : 0; | |
c5394b80 | 830 | else |
7eed1055 | 831 | gr[RD] = (long) gr[RD] >> gr[RS]; |
2d514e6f SS |
832 | break; |
833 | ||
834 | case 0x1B: /* lsl */ | |
c5394b80 JM |
835 | /* We must not rely solely upon the native shift operations, since they |
836 | may not match the M*Core's behaviour on boundary conditions. */ | |
7eed1055 | 837 | gr[RD] = gr[RS] > 31 ? 0 : gr[RD] << gr[RS]; |
2d514e6f SS |
838 | break; |
839 | ||
840 | case 0x1C: /* addu */ | |
7eed1055 | 841 | gr[RD] += gr[RS]; |
2d514e6f SS |
842 | break; |
843 | ||
844 | case 0x1D: /* ixh */ | |
7eed1055 | 845 | gr[RD] += gr[RS] << 1; |
2d514e6f SS |
846 | break; |
847 | ||
848 | case 0x1E: /* or */ | |
7eed1055 | 849 | gr[RD] |= gr[RS]; |
2d514e6f SS |
850 | break; |
851 | ||
852 | case 0x1F: /* andn */ | |
7eed1055 | 853 | gr[RD] &= ~gr[RS]; |
2d514e6f SS |
854 | break; |
855 | case 0x20: case 0x21: /* addi */ | |
7eed1055 MF |
856 | gr[RD] = |
857 | gr[RD] + (IMM5 + 1); | |
2d514e6f SS |
858 | break; |
859 | case 0x22: case 0x23: /* cmplti */ | |
860 | { | |
861 | int tmp = (IMM5 + 1); | |
7eed1055 | 862 | if (gr[RD] < tmp) |
2d514e6f SS |
863 | { |
864 | SET_C(); | |
865 | } | |
866 | else | |
867 | { | |
868 | CLR_C(); | |
869 | } | |
870 | } | |
871 | break; | |
872 | case 0x24: case 0x25: /* subi */ | |
7eed1055 MF |
873 | gr[RD] = |
874 | gr[RD] - (IMM5 + 1); | |
2d514e6f SS |
875 | break; |
876 | case 0x26: case 0x27: /* illegal */ | |
02962cd9 | 877 | ILLEGAL (); |
2d514e6f SS |
878 | break; |
879 | case 0x28: case 0x29: /* rsubi */ | |
7eed1055 MF |
880 | gr[RD] = |
881 | IMM5 - gr[RD]; | |
2d514e6f SS |
882 | break; |
883 | case 0x2A: case 0x2B: /* cmpnei */ | |
7eed1055 | 884 | if (gr[RD] != IMM5) |
2d514e6f SS |
885 | { |
886 | SET_C(); | |
887 | } | |
888 | else | |
889 | { | |
890 | CLR_C(); | |
891 | } | |
892 | break; | |
ba14f941 | 893 | |
2d514e6f SS |
894 | case 0x2C: case 0x2D: /* bmaski, divu */ |
895 | { | |
896 | unsigned imm = IMM5; | |
ba14f941 | 897 | |
2d514e6f SS |
898 | if (imm == 1) |
899 | { | |
900 | int exe; | |
901 | int rxnlz, r1nlz; | |
902 | unsigned int rx, r1; | |
903 | ||
7eed1055 MF |
904 | rx = gr[RD]; |
905 | r1 = gr[1]; | |
2d514e6f SS |
906 | exe = 0; |
907 | ||
908 | /* unsigned divide */ | |
7eed1055 | 909 | gr[RD] = (word) ((unsigned int) gr[RD] / (unsigned int)gr[1] ); |
ba14f941 | 910 | |
2d514e6f SS |
911 | /* compute bonus_cycles for divu */ |
912 | for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32); r1nlz ++) | |
913 | r1 = r1 << 1; | |
914 | ||
915 | for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32); rxnlz ++) | |
916 | rx = rx << 1; | |
917 | ||
918 | if (r1nlz < rxnlz) | |
919 | exe += 4; | |
920 | else | |
921 | exe += 5 + r1nlz - rxnlz; | |
922 | ||
923 | if (exe >= (2 * memcycles - 1)) | |
924 | { | |
925 | bonus_cycles += exe - (2 * memcycles) + 1; | |
926 | } | |
927 | } | |
928 | else if (imm == 0 || imm >= 8) | |
929 | { | |
930 | /* bmaski */ | |
931 | if (imm == 0) | |
7eed1055 | 932 | gr[RD] = -1; |
2d514e6f | 933 | else |
7eed1055 | 934 | gr[RD] = (1 << imm) - 1; |
2d514e6f SS |
935 | } |
936 | else | |
937 | { | |
938 | /* illegal */ | |
02962cd9 | 939 | ILLEGAL (); |
2d514e6f SS |
940 | } |
941 | } | |
942 | break; | |
943 | case 0x2E: case 0x2F: /* andi */ | |
7eed1055 | 944 | gr[RD] = gr[RD] & IMM5; |
2d514e6f SS |
945 | break; |
946 | case 0x30: case 0x31: /* bclri */ | |
7eed1055 | 947 | gr[RD] = gr[RD] & ~(1<<IMM5); |
2d514e6f SS |
948 | break; |
949 | case 0x32: case 0x33: /* bgeni, divs */ | |
950 | { | |
951 | unsigned imm = IMM5; | |
952 | if (imm == 1) | |
953 | { | |
954 | int exe,sc; | |
955 | int rxnlz, r1nlz; | |
956 | signed int rx, r1; | |
ba14f941 | 957 | |
2d514e6f | 958 | /* compute bonus_cycles for divu */ |
7eed1055 MF |
959 | rx = gr[RD]; |
960 | r1 = gr[1]; | |
2d514e6f | 961 | exe = 0; |
ba14f941 | 962 | |
2d514e6f SS |
963 | if (((rx < 0) && (r1 > 0)) || ((rx >= 0) && (r1 < 0))) |
964 | sc = 1; | |
965 | else | |
966 | sc = 0; | |
ba14f941 | 967 | |
2d514e6f SS |
968 | rx = abs (rx); |
969 | r1 = abs (r1); | |
ba14f941 | 970 | |
2d514e6f | 971 | /* signed divide, general registers are of type int, so / op is OK */ |
7eed1055 | 972 | gr[RD] = gr[RD] / gr[1]; |
ba14f941 | 973 | |
2d514e6f SS |
974 | for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32) ; r1nlz ++ ) |
975 | r1 = r1 << 1; | |
ba14f941 | 976 | |
2d514e6f SS |
977 | for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32) ; rxnlz ++ ) |
978 | rx = rx << 1; | |
ba14f941 | 979 | |
2d514e6f SS |
980 | if (r1nlz < rxnlz) |
981 | exe += 5; | |
982 | else | |
983 | exe += 6 + r1nlz - rxnlz + sc; | |
ba14f941 | 984 | |
2d514e6f SS |
985 | if (exe >= (2 * memcycles - 1)) |
986 | { | |
987 | bonus_cycles += exe - (2 * memcycles) + 1; | |
988 | } | |
989 | } | |
990 | else if (imm >= 7) | |
991 | { | |
992 | /* bgeni */ | |
7eed1055 | 993 | gr[RD] = (1 << IMM5); |
2d514e6f SS |
994 | } |
995 | else | |
996 | { | |
997 | /* illegal */ | |
02962cd9 | 998 | ILLEGAL (); |
2d514e6f SS |
999 | } |
1000 | break; | |
1001 | } | |
1002 | case 0x34: case 0x35: /* bseti */ | |
7eed1055 | 1003 | gr[RD] = gr[RD] | (1 << IMM5); |
2d514e6f SS |
1004 | break; |
1005 | case 0x36: case 0x37: /* btsti */ | |
7eed1055 | 1006 | NEW_C (gr[RD] >> IMM5); |
2d514e6f SS |
1007 | break; |
1008 | case 0x38: case 0x39: /* xsr, rotli */ | |
1009 | { | |
1010 | unsigned imm = IMM5; | |
7eed1055 | 1011 | unsigned long tmp = gr[RD]; |
2d514e6f SS |
1012 | if (imm == 0) |
1013 | { | |
1014 | word cbit; | |
1015 | cbit = C_VALUE(); | |
1016 | NEW_C (tmp); | |
7eed1055 | 1017 | gr[RD] = (cbit << 31) | (tmp >> 1); |
2d514e6f SS |
1018 | } |
1019 | else | |
7eed1055 | 1020 | gr[RD] = (tmp << imm) | (tmp >> (32 - imm)); |
2d514e6f SS |
1021 | } |
1022 | break; | |
1023 | case 0x3A: case 0x3B: /* asrc, asri */ | |
1024 | { | |
1025 | unsigned imm = IMM5; | |
7eed1055 | 1026 | long tmp = gr[RD]; |
2d514e6f SS |
1027 | if (imm == 0) |
1028 | { | |
1029 | NEW_C (tmp); | |
7eed1055 | 1030 | gr[RD] = tmp >> 1; |
2d514e6f SS |
1031 | } |
1032 | else | |
7eed1055 | 1033 | gr[RD] = tmp >> imm; |
2d514e6f SS |
1034 | } |
1035 | break; | |
1036 | case 0x3C: case 0x3D: /* lslc, lsli */ | |
1037 | { | |
1038 | unsigned imm = IMM5; | |
7eed1055 | 1039 | unsigned long tmp = gr[RD]; |
2d514e6f SS |
1040 | if (imm == 0) |
1041 | { | |
1042 | NEW_C (tmp >> 31); | |
7eed1055 | 1043 | gr[RD] = tmp << 1; |
2d514e6f SS |
1044 | } |
1045 | else | |
7eed1055 | 1046 | gr[RD] = tmp << imm; |
2d514e6f SS |
1047 | } |
1048 | break; | |
1049 | case 0x3E: case 0x3F: /* lsrc, lsri */ | |
1050 | { | |
1051 | unsigned imm = IMM5; | |
7eed1055 | 1052 | unsigned long tmp = gr[RD]; |
2d514e6f SS |
1053 | if (imm == 0) |
1054 | { | |
1055 | NEW_C (tmp); | |
7eed1055 | 1056 | gr[RD] = tmp >> 1; |
2d514e6f SS |
1057 | } |
1058 | else | |
7eed1055 | 1059 | gr[RD] = tmp >> imm; |
2d514e6f SS |
1060 | } |
1061 | break; | |
1062 | case 0x40: case 0x41: case 0x42: case 0x43: | |
1063 | case 0x44: case 0x45: case 0x46: case 0x47: | |
1064 | case 0x48: case 0x49: case 0x4A: case 0x4B: | |
1065 | case 0x4C: case 0x4D: case 0x4E: case 0x4F: | |
02962cd9 | 1066 | ILLEGAL (); |
2d514e6f SS |
1067 | break; |
1068 | case 0x50: | |
7eed1055 | 1069 | util (sd, cpu, inst & 0xFF); |
2d514e6f SS |
1070 | break; |
1071 | case 0x51: case 0x52: case 0x53: | |
1072 | case 0x54: case 0x55: case 0x56: case 0x57: | |
1073 | case 0x58: case 0x59: case 0x5A: case 0x5B: | |
1074 | case 0x5C: case 0x5D: case 0x5E: case 0x5F: | |
02962cd9 | 1075 | ILLEGAL (); |
2d514e6f SS |
1076 | break; |
1077 | case 0x60: case 0x61: case 0x62: case 0x63: /* movi */ | |
1078 | case 0x64: case 0x65: case 0x66: case 0x67: | |
7eed1055 | 1079 | gr[RD] = (inst >> 4) & 0x7F; |
2d514e6f SS |
1080 | break; |
1081 | case 0x68: case 0x69: case 0x6A: case 0x6B: | |
1082 | case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */ | |
02962cd9 | 1083 | ILLEGAL (); |
2d514e6f SS |
1084 | break; |
1085 | case 0x71: case 0x72: case 0x73: | |
1086 | case 0x74: case 0x75: case 0x76: case 0x77: | |
1087 | case 0x78: case 0x79: case 0x7A: case 0x7B: | |
1088 | case 0x7C: case 0x7D: case 0x7E: /* lrw */ | |
7eed1055 | 1089 | gr[RX] = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); |
2d514e6f | 1090 | if (tracing) |
43236bb2 | 1091 | fprintf (stderr, "LRW of 0x%x from 0x%lx to reg %d", |
2d514e6f SS |
1092 | rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC), |
1093 | (pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC, RX); | |
1094 | memops++; | |
1095 | break; | |
1096 | case 0x7F: /* jsri */ | |
7eed1055 | 1097 | gr[15] = pc; |
392a587b | 1098 | if (tracing) |
43236bb2 MF |
1099 | fprintf (stderr, |
1100 | "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n", | |
7eed1055 | 1101 | gr[2], gr[3], gr[4], gr[5], gr[6], gr[7]); |
2d514e6f SS |
1102 | case 0x70: /* jmpi */ |
1103 | pc = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); | |
1104 | memops++; | |
1105 | bonus_cycles++; | |
1106 | needfetch = 1; | |
1107 | break; | |
1108 | ||
1109 | case 0x80: case 0x81: case 0x82: case 0x83: | |
1110 | case 0x84: case 0x85: case 0x86: case 0x87: | |
1111 | case 0x88: case 0x89: case 0x8A: case 0x8B: | |
1112 | case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */ | |
7eed1055 | 1113 | gr[RX] = rlat (gr[RD] + ((inst >> 2) & 0x003C)); |
2d514e6f | 1114 | if (tracing) |
43236bb2 | 1115 | fprintf (stderr, "load reg %d from 0x%lx with 0x%lx", |
2d514e6f | 1116 | RX, |
7eed1055 | 1117 | gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); |
2d514e6f SS |
1118 | memops++; |
1119 | break; | |
1120 | case 0x90: case 0x91: case 0x92: case 0x93: | |
1121 | case 0x94: case 0x95: case 0x96: case 0x97: | |
1122 | case 0x98: case 0x99: case 0x9A: case 0x9B: | |
1123 | case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */ | |
7eed1055 | 1124 | wlat (gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); |
2d514e6f | 1125 | if (tracing) |
43236bb2 | 1126 | fprintf (stderr, "store reg %d (containing 0x%lx) to 0x%lx", |
7eed1055 MF |
1127 | RX, gr[RX], |
1128 | gr[RD] + ((inst >> 2) & 0x003C)); | |
2d514e6f SS |
1129 | memops++; |
1130 | break; | |
1131 | case 0xA0: case 0xA1: case 0xA2: case 0xA3: | |
1132 | case 0xA4: case 0xA5: case 0xA6: case 0xA7: | |
1133 | case 0xA8: case 0xA9: case 0xAA: case 0xAB: | |
1134 | case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */ | |
7eed1055 | 1135 | gr[RX] = rbat (gr[RD] + RS); |
2d514e6f SS |
1136 | memops++; |
1137 | break; | |
1138 | case 0xB0: case 0xB1: case 0xB2: case 0xB3: | |
1139 | case 0xB4: case 0xB5: case 0xB6: case 0xB7: | |
1140 | case 0xB8: case 0xB9: case 0xBA: case 0xBB: | |
1141 | case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */ | |
7eed1055 | 1142 | wbat (gr[RD] + RS, gr[RX]); |
2d514e6f SS |
1143 | memops++; |
1144 | break; | |
1145 | case 0xC0: case 0xC1: case 0xC2: case 0xC3: | |
1146 | case 0xC4: case 0xC5: case 0xC6: case 0xC7: | |
1147 | case 0xC8: case 0xC9: case 0xCA: case 0xCB: | |
1148 | case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */ | |
7eed1055 | 1149 | gr[RX] = rhat (gr[RD] + ((inst >> 3) & 0x001E)); |
2d514e6f SS |
1150 | memops++; |
1151 | break; | |
1152 | case 0xD0: case 0xD1: case 0xD2: case 0xD3: | |
1153 | case 0xD4: case 0xD5: case 0xD6: case 0xD7: | |
1154 | case 0xD8: case 0xD9: case 0xDA: case 0xDB: | |
1155 | case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */ | |
7eed1055 | 1156 | what (gr[RD] + ((inst >> 3) & 0x001E), gr[RX]); |
2d514e6f SS |
1157 | memops++; |
1158 | break; | |
1159 | case 0xE8: case 0xE9: case 0xEA: case 0xEB: | |
ba14f941 | 1160 | case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */ |
2d514e6f SS |
1161 | if (C_OFF()) |
1162 | { | |
1163 | int disp; | |
1164 | disp = inst & 0x03FF; | |
1165 | if (inst & 0x0400) | |
1166 | disp |= 0xFFFFFC00; | |
1167 | pc += disp<<1; | |
1168 | bonus_cycles++; | |
1169 | needfetch = 1; | |
1170 | } | |
1171 | break; | |
1172 | case 0xE0: case 0xE1: case 0xE2: case 0xE3: | |
1173 | case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */ | |
1174 | if (C_ON()) | |
1175 | { | |
1176 | int disp; | |
1177 | disp = inst & 0x03FF; | |
1178 | if (inst & 0x0400) | |
1179 | disp |= 0xFFFFFC00; | |
1180 | pc += disp<<1; | |
1181 | bonus_cycles++; | |
1182 | needfetch = 1; | |
1183 | } | |
1184 | break; | |
1185 | ||
1186 | case 0xF8: case 0xF9: case 0xFA: case 0xFB: | |
ba14f941 | 1187 | case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */ |
7eed1055 | 1188 | gr[15] = pc; |
2d514e6f SS |
1189 | case 0xF0: case 0xF1: case 0xF2: case 0xF3: |
1190 | case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */ | |
1191 | { | |
1192 | int disp; | |
1193 | disp = inst & 0x03FF; | |
1194 | if (inst & 0x0400) | |
1195 | disp |= 0xFFFFFC00; | |
1196 | pc += disp<<1; | |
1197 | bonus_cycles++; | |
1198 | needfetch = 1; | |
1199 | } | |
1200 | break; | |
1201 | ||
1202 | } | |
1203 | ||
1204 | if (tracing) | |
1205 | fprintf (stderr, "\n"); | |
cd0fc7c3 | 1206 | |
ba14f941 | 1207 | if (needfetch) |
2d514e6f | 1208 | { |
f63036b8 MF |
1209 | ibuf = rlat (pc & 0xFFFFFFFC); |
1210 | needfetch = 0; | |
2d514e6f SS |
1211 | } |
1212 | } | |
2d514e6f SS |
1213 | |
1214 | /* Hide away the things we've cached while executing. */ | |
7eed1055 MF |
1215 | CPU_PC_SET (cpu, pc); |
1216 | cpu->insts += insts; /* instructions done ... */ | |
1217 | cpu->cycles += insts; /* and each takes a cycle */ | |
1218 | cpu->cycles += bonus_cycles; /* and extra cycles for branches */ | |
1219 | cpu->cycles += memops * memcycles; /* and memop cycle delays */ | |
2d514e6f SS |
1220 | } |
1221 | ||
02962cd9 MF |
1222 | void |
1223 | sim_engine_run (SIM_DESC sd, | |
1224 | int next_cpu_nr, /* ignore */ | |
1225 | int nr_cpus, /* ignore */ | |
1226 | int siggnal) /* ignore */ | |
1227 | { | |
7eed1055 | 1228 | sim_cpu *cpu; |
02962cd9 MF |
1229 | |
1230 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
1231 | ||
7eed1055 | 1232 | cpu = STATE_CPU (sd, 0); |
02962cd9 MF |
1233 | |
1234 | while (1) | |
1235 | { | |
7eed1055 | 1236 | step_once (sd, cpu); |
02962cd9 MF |
1237 | if (sim_events_tick (sd)) |
1238 | sim_events_process (sd); | |
1239 | } | |
1240 | } | |
1241 | ||
9ef4651c | 1242 | static int |
7eed1055 | 1243 | mcore_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) |
2d514e6f | 1244 | { |
2d514e6f SS |
1245 | if (rn < NUM_MCORE_REGS && rn >= 0) |
1246 | { | |
1247 | if (length == 4) | |
1248 | { | |
2d514e6f | 1249 | long ival; |
ba14f941 | 1250 | |
cd0fc7c3 SS |
1251 | /* misalignment safe */ |
1252 | ival = mcore_extract_unsigned_integer (memory, 4); | |
7eed1055 | 1253 | cpu->asints[rn] = ival; |
2d514e6f SS |
1254 | } |
1255 | ||
1256 | return 4; | |
1257 | } | |
1258 | else | |
1259 | return 0; | |
1260 | } | |
1261 | ||
9ef4651c | 1262 | static int |
7eed1055 | 1263 | mcore_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) |
2d514e6f | 1264 | { |
2d514e6f SS |
1265 | if (rn < NUM_MCORE_REGS && rn >= 0) |
1266 | { | |
1267 | if (length == 4) | |
1268 | { | |
7eed1055 | 1269 | long ival = cpu->asints[rn]; |
cd0fc7c3 SS |
1270 | |
1271 | /* misalignment-safe */ | |
1272 | mcore_store_unsigned_integer (memory, 4, ival); | |
2d514e6f | 1273 | } |
ba14f941 | 1274 | |
2d514e6f SS |
1275 | return 4; |
1276 | } | |
1277 | else | |
1278 | return 0; | |
1279 | } | |
1280 | ||
2d514e6f | 1281 | void |
feb703b3 | 1282 | sim_info (SIM_DESC sd, int verbose) |
2d514e6f | 1283 | { |
7eed1055 | 1284 | SIM_CPU *cpu = STATE_CPU (sd, 0); |
2d514e6f SS |
1285 | #ifdef WATCHFUNCTIONS |
1286 | int w, wcyc; | |
1287 | #endif | |
7eed1055 | 1288 | double virttime = cpu->cycles / 36.0e6; |
ea6b7543 | 1289 | host_callback *callback = STATE_CALLBACK (sd); |
2d514e6f | 1290 | |
cd0fc7c3 | 1291 | callback->printf_filtered (callback, "\n\n# instructions executed %10d\n", |
7eed1055 | 1292 | cpu->insts); |
cd0fc7c3 | 1293 | callback->printf_filtered (callback, "# cycles %10d\n", |
7eed1055 | 1294 | cpu->cycles); |
cd0fc7c3 | 1295 | callback->printf_filtered (callback, "# pipeline stalls %10d\n", |
7eed1055 | 1296 | cpu->stalls); |
cd0fc7c3 SS |
1297 | callback->printf_filtered (callback, "# virtual time taken %10.4f\n", |
1298 | virttime); | |
2d514e6f SS |
1299 | |
1300 | #ifdef WATCHFUNCTIONS | |
cd0fc7c3 SS |
1301 | callback->printf_filtered (callback, "\nNumber of watched functions: %d\n", |
1302 | ENDWL); | |
2d514e6f SS |
1303 | |
1304 | wcyc = 0; | |
ba14f941 | 1305 | |
2d514e6f SS |
1306 | for (w = 1; w <= ENDWL; w++) |
1307 | { | |
1308 | callback->printf_filtered (callback, "WL = %s %8x\n",WLstr[w],WL[w]); | |
cd0fc7c3 SS |
1309 | callback->printf_filtered (callback, " calls = %d, cycles = %d\n", |
1310 | WLcnts[w],WLcyc[w]); | |
ba14f941 | 1311 | |
2d514e6f | 1312 | if (WLcnts[w] != 0) |
cd0fc7c3 SS |
1313 | callback->printf_filtered (callback, |
1314 | " maxcpc = %d, mincpc = %d, avecpc = %d\n", | |
1315 | WLmax[w],WLmin[w],WLcyc[w]/WLcnts[w]); | |
2d514e6f SS |
1316 | wcyc += WLcyc[w]; |
1317 | } | |
ba14f941 | 1318 | |
cd0fc7c3 SS |
1319 | callback->printf_filtered (callback, |
1320 | "Total cycles for watched functions: %d\n",wcyc); | |
2d514e6f SS |
1321 | #endif |
1322 | } | |
1323 | ||
4c0cab1e MF |
1324 | static sim_cia |
1325 | mcore_pc_get (sim_cpu *cpu) | |
1326 | { | |
7eed1055 | 1327 | return cpu->regs.pc; |
4c0cab1e MF |
1328 | } |
1329 | ||
1330 | static void | |
1331 | mcore_pc_set (sim_cpu *cpu, sim_cia pc) | |
1332 | { | |
7eed1055 | 1333 | cpu->regs.pc = pc; |
4c0cab1e MF |
1334 | } |
1335 | ||
ea6b7543 MF |
1336 | static void |
1337 | free_state (SIM_DESC sd) | |
1338 | { | |
1339 | if (STATE_MODULES (sd) != NULL) | |
1340 | sim_module_uninstall (sd); | |
1341 | sim_cpu_free_all (sd); | |
1342 | sim_state_free (sd); | |
1343 | } | |
1344 | ||
2d514e6f | 1345 | SIM_DESC |
2e3d4f4d MF |
1346 | sim_open (SIM_OPEN_KIND kind, host_callback *cb, |
1347 | struct bfd *abfd, char * const *argv) | |
2d514e6f | 1348 | { |
f63036b8 | 1349 | int i; |
ea6b7543 | 1350 | SIM_DESC sd = sim_state_alloc (kind, cb); |
ea6b7543 MF |
1351 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
1352 | ||
1353 | /* The cpu data is kept in a separately allocated chunk of memory. */ | |
d5a71b11 | 1354 | if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) |
ea6b7543 MF |
1355 | { |
1356 | free_state (sd); | |
1357 | return 0; | |
1358 | } | |
1359 | ||
1360 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
1361 | { | |
1362 | free_state (sd); | |
1363 | return 0; | |
1364 | } | |
1365 | ||
77cf2ef5 | 1366 | /* The parser will print an error message for us, so we silently return. */ |
ea6b7543 MF |
1367 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
1368 | { | |
1369 | free_state (sd); | |
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | /* Check for/establish the a reference program image. */ | |
1374 | if (sim_analyze_program (sd, | |
1375 | (STATE_PROG_ARGV (sd) != NULL | |
1376 | ? *STATE_PROG_ARGV (sd) | |
1377 | : NULL), abfd) != SIM_RC_OK) | |
1378 | { | |
1379 | free_state (sd); | |
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | /* Configure/verify the target byte order and other runtime | |
1384 | configuration options. */ | |
1385 | if (sim_config (sd) != SIM_RC_OK) | |
1386 | { | |
1387 | sim_module_uninstall (sd); | |
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
1392 | { | |
1393 | /* Uninstall the modules to avoid memory leaks, | |
1394 | file descriptor leaks, etc. */ | |
1395 | sim_module_uninstall (sd); | |
1396 | return 0; | |
1397 | } | |
1398 | ||
ea6b7543 MF |
1399 | /* CPU specific initialization. */ |
1400 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
1401 | { | |
1402 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
4c0cab1e | 1403 | |
9ef4651c MF |
1404 | CPU_REG_FETCH (cpu) = mcore_reg_fetch; |
1405 | CPU_REG_STORE (cpu) = mcore_reg_store; | |
4c0cab1e MF |
1406 | CPU_PC_FETCH (cpu) = mcore_pc_get; |
1407 | CPU_PC_STORE (cpu) = mcore_pc_set; | |
1408 | ||
ea6b7543 MF |
1409 | set_initial_gprs (cpu); /* Reset the GPR registers. */ |
1410 | } | |
ba14f941 | 1411 | |
f63036b8 MF |
1412 | /* Default to a 8 Mbyte (== 2^23) memory space. */ |
1413 | sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEMORY_SIZE); | |
1414 | ||
ea6b7543 | 1415 | return sd; |
2d514e6f SS |
1416 | } |
1417 | ||
2d514e6f | 1418 | SIM_RC |
2e3d4f4d MF |
1419 | sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, |
1420 | char * const *argv, char * const *env) | |
2d514e6f | 1421 | { |
7eed1055 | 1422 | SIM_CPU *cpu = STATE_CPU (sd, 0); |
91eea121 | 1423 | char * const *avp; |
2d514e6f SS |
1424 | int nargs = 0; |
1425 | int nenv = 0; | |
1426 | int s_length; | |
1427 | int l; | |
1428 | unsigned long strings; | |
1429 | unsigned long pointers; | |
1430 | unsigned long hi_stack; | |
1431 | ||
1432 | ||
1433 | /* Set the initial register set. */ | |
7eed1055 | 1434 | set_initial_gprs (cpu); |
ba14f941 | 1435 | |
f63036b8 | 1436 | hi_stack = DEFAULT_MEMORY_SIZE - 4; |
7eed1055 | 1437 | CPU_PC_SET (cpu, bfd_get_start_address (prog_bfd)); |
2d514e6f SS |
1438 | |
1439 | /* Calculate the argument and environment strings. */ | |
1440 | s_length = 0; | |
1441 | nargs = 0; | |
1442 | avp = argv; | |
1443 | while (avp && *avp) | |
1444 | { | |
1445 | l = strlen (*avp) + 1; /* include the null */ | |
1446 | s_length += (l + 3) & ~3; /* make it a 4 byte boundary */ | |
1447 | nargs++; avp++; | |
1448 | } | |
1449 | ||
1450 | nenv = 0; | |
1451 | avp = env; | |
1452 | while (avp && *avp) | |
1453 | { | |
1454 | l = strlen (*avp) + 1; /* include the null */ | |
1455 | s_length += (l + 3) & ~ 3;/* make it a 4 byte boundary */ | |
1456 | nenv++; avp++; | |
1457 | } | |
1458 | ||
1459 | /* Claim some memory for the pointers and strings. */ | |
1460 | pointers = hi_stack - sizeof(word) * (nenv+1+nargs+1); | |
1461 | pointers &= ~3; /* must be 4-byte aligned */ | |
7eed1055 | 1462 | gr[0] = pointers; |
2d514e6f | 1463 | |
7eed1055 | 1464 | strings = gr[0] - s_length; |
2d514e6f | 1465 | strings &= ~3; /* want to make it 4-byte aligned */ |
7eed1055 | 1466 | gr[0] = strings; |
2d514e6f | 1467 | /* dac fix, the stack address must be 8-byte aligned! */ |
7eed1055 | 1468 | gr[0] = gr[0] - gr[0] % 8; |
2d514e6f SS |
1469 | |
1470 | /* Loop through the arguments and fill them in. */ | |
7eed1055 | 1471 | gr[PARM1] = nargs; |
2d514e6f SS |
1472 | if (nargs == 0) |
1473 | { | |
1474 | /* No strings to fill in. */ | |
7eed1055 | 1475 | gr[PARM2] = 0; |
2d514e6f SS |
1476 | } |
1477 | else | |
1478 | { | |
7eed1055 | 1479 | gr[PARM2] = pointers; |
2d514e6f SS |
1480 | avp = argv; |
1481 | while (avp && *avp) | |
1482 | { | |
1483 | /* Save where we're putting it. */ | |
1484 | wlat (pointers, strings); | |
1485 | ||
1486 | /* Copy the string. */ | |
1487 | l = strlen (* avp) + 1; | |
7eed1055 | 1488 | sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l); |
2d514e6f SS |
1489 | |
1490 | /* Bump the pointers. */ | |
1491 | avp++; | |
1492 | pointers += 4; | |
1493 | strings += l+1; | |
1494 | } | |
ba14f941 | 1495 | |
2d514e6f SS |
1496 | /* A null to finish the list. */ |
1497 | wlat (pointers, 0); | |
1498 | pointers += 4; | |
1499 | } | |
1500 | ||
1501 | /* Now do the environment pointers. */ | |
1502 | if (nenv == 0) | |
1503 | { | |
1504 | /* No strings to fill in. */ | |
7eed1055 | 1505 | gr[PARM3] = 0; |
2d514e6f SS |
1506 | } |
1507 | else | |
1508 | { | |
7eed1055 | 1509 | gr[PARM3] = pointers; |
2d514e6f | 1510 | avp = env; |
ba14f941 | 1511 | |
2d514e6f SS |
1512 | while (avp && *avp) |
1513 | { | |
1514 | /* Save where we're putting it. */ | |
1515 | wlat (pointers, strings); | |
1516 | ||
1517 | /* Copy the string. */ | |
1518 | l = strlen (* avp) + 1; | |
7eed1055 | 1519 | sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l); |
2d514e6f SS |
1520 | |
1521 | /* Bump the pointers. */ | |
1522 | avp++; | |
1523 | pointers += 4; | |
1524 | strings += l+1; | |
1525 | } | |
ba14f941 | 1526 | |
2d514e6f SS |
1527 | /* A null to finish the list. */ |
1528 | wlat (pointers, 0); | |
1529 | pointers += 4; | |
1530 | } | |
ba14f941 | 1531 | |
2d514e6f SS |
1532 | return SIM_RC_OK; |
1533 | } |