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[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
43e526b9
JM		 1Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
2
3 * interp.c (sim_monitor): Flush output before reading input.
4
5Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
6
7 * tconfig.in (SIM_HANDLES_LMA): Always define.
8
9Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
10
11 From Mark Salter <msalter@cygnus.com>:
12 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
13 (sim_open): Add setup for BSP board.
14
9846de1b
JM		 15Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
16
17 * mips.igen (MULT, MULTU): Add syntax for two operand version.
18 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
19 them as unimplemented.
20
cd0fc7c3
SS		 211999-05-08 Felix Lee <flee@cygnus.com>
22
23 * configure: Regenerated to track ../common/aclocal.m4 changes.
24
7a292a7a
SS		 251999-04-21 Frank Ch. Eigler <fche@cygnus.com>
26
27 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
28
29Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
30
31 * configure.in: Any mips64vr5*-*-* target should have
32 -DTARGET_ENABLE_FR=1.
33 (default_endian): Any mips64vr*el-*-* target should default to
34 LITTLE_ENDIAN.
35 * configure: Re-generate.
36
371999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
38
39 * mips.igen (ldl): Extend from _16_, not 32.
40
41Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
42
43 * interp.c (sim_store_register): Force registers written to by GDB
44 into an un-interpreted state.
45
c906108c
SS		 461999-02-05 Frank Ch. Eigler <fche@cygnus.com>
47
48 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
49 CPU, start periodic background I/O polls.
50 (tx3904sio_poll): New function: periodic I/O poller.
51
521998-12-30 Frank Ch. Eigler <fche@cygnus.com>
53
54 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
55
56Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
57
58 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
59 case statement.
60
611998-12-29 Frank Ch. Eigler <fche@cygnus.com>
62
63 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
64 (load_word): Call SIM_CORE_SIGNAL hook on error.
65 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
66 starting. For exception dispatching, pass PC instead of NULL_CIA.
67 (decode_coproc): Use COP0_BADVADDR to store faulting address.
68 * sim-main.h (COP0_BADVADDR): Define.
69 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
70 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
71 (_sim_cpu): Add exc_* fields to store register value snapshots.
72 * mips.igen (*): Replace memory-related SignalException* calls
73 with references to SIM_CORE_SIGNAL hook.
74
75 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
76 fix.
77 * sim-main.c (*): Minor warning cleanups.
78
791998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
80
81 * m16.igen (DADDIU5): Correct type-o.
82
83Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
84
85 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
86 variables.
87
88Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
89
90 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
91 to include path.
92 (interp.o): Add dependency on itable.h
93 (oengine.c, gencode): Delete remaining references.
94 (BUILT_SRC_FROM_GEN): Clean up.
95
961998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
97
98 * vr4run.c: New.
99 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
100 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
101 tmp-run-hack) : New.
102 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
103 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
104 Drop the "64" qualifier to get the HACK generator working.
105 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
106 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
107 qualifier to get the hack generator working.
108 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
109 (DSLL): Use do_dsll.
110 (DSLLV): Use do_dsllv.
111 (DSRA): Use do_dsra.
112 (DSRL): Use do_dsrl.
113 (DSRLV): Use do_dsrlv.
114 (BC1): Move *vr4100 to get the HACK generator working.
115 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
116 get the HACK generator working.
117 (MACC) Rename to get the HACK generator working.
118 (DMACC,MACCS,DMACCS): Add the 64.
119
1201998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
121
122 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
123 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
124
1251998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
126
127 * mips/interp.c (DEBUG): Cleanups.
128
1291998-12-10 Frank Ch. Eigler <fche@cygnus.com>
130
131 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
132 (tx3904sio_tickle): fflush after a stdout character output.
133
1341998-12-03 Frank Ch. Eigler <fche@cygnus.com>
135
136 * interp.c (sim_close): Uninstall modules.
137
138Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
139
140 * sim-main.h, interp.c (sim_monitor): Change to global
141 function.
142
143Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
144
145 * configure.in (vr4100): Only include vr4100 instructions in
146 simulator.
147 * configure: Re-generate.
148 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
149
150Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
151
152 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
153 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
154 true alternative.
155
156 * configure.in (sim_default_gen, sim_use_gen): Replace with
157 sim_gen.
158 (--enable-sim-igen): Delete config option. Always using IGEN.
159 * configure: Re-generate.
160
161 * Makefile.in (gencode): Kill, kill, kill.
162 * gencode.c: Ditto.
163
164Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
165
166 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
167 bit mips16 igen simulator.
168 * configure: Re-generate.
169
170 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
171 as part of vr4100 ISA.
172 * vr.igen: Mark all instructions as 64 bit only.
173
174Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
175
176 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
177 Pacify GCC.
178
179Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
180
181 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
182 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
183 * configure: Re-generate.
184
185 * m16.igen (BREAK): Define breakpoint instruction.
186 (JALX32): Mark instruction as mips16 and not r3900.
187 * mips.igen (C.cond.fmt): Fix typo in instruction format.
188
189 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
190
191Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
192
193 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
194 insn as a debug breakpoint.
195
196 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
197 pending.slot_size.
198 (PENDING_SCHED): Clean up trace statement.
199 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
200 (PENDING_FILL): Delay write by only one cycle.
201 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
202
203 * sim-main.c (pending_tick): Clean up trace statements. Add trace
204 of pending writes.
205 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
206 32 & 64.
207 (pending_tick): Move incrementing of index to FOR statement.
208 (pending_tick): Only update PENDING_OUT after a write has occured.
209
210 * configure.in: Add explicit mips-lsi-* target. Use gencode to
211 build simulator.
212 * configure: Re-generate.
213
214 * interp.c (sim_engine_run OLD): Delete explicit call to
215 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
216
217Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
218
219 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
220 interrupt level number to match changed SignalExceptionInterrupt
221 macro.
222
223Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
224
225 * interp.c: #include "itable.h" if WITH_IGEN.
226 (get_insn_name): New function.
227 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
228 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
229
230Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
231
232 * configure: Rebuilt to inhale new common/aclocal.m4.
233
234Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
235
236 * dv-tx3904sio.c: Include sim-assert.h.
237
238Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
239
240 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
241 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
242 Reorganize target-specific sim-hardware checks.
243 * configure: rebuilt.
244 * interp.c (sim_open): For tx39 target boards, set
245 OPERATING_ENVIRONMENT, add tx3904sio devices.
246 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
247 ROM executables. Install dv-sockser into sim-modules list.
248
249 * dv-tx3904irc.c: Compiler warning clean-up.
250 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
251 frequent hw-trace messages.
252
253Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
254
255 * vr.igen (MulAcc): Identify as a vr4100 specific function.
256
257Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
258
259 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
260
261 * vr.igen: New file.
262 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
263 * mips.igen: Define vr4100 model. Include vr.igen.
264Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
265
266 * mips.igen (check_mf_hilo): Correct check.
267
268Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
269
270 * sim-main.h (interrupt_event): Add prototype.
271
272 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
273 register_ptr, register_value.
274 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
275
276 * sim-main.h (tracefh): Make extern.
277
278Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
279
280 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
281 Reduce unnecessarily high timer event frequency.
282 * dv-tx3904cpu.c: Ditto for interrupt event.
283
284Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
285
286 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
287 to allay warnings.
288 (interrupt_event): Made non-static.
289
290 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
291 interchange of configuration values for external vs. internal
292 clock dividers.
293
294Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
295
296 * mips.igen (BREAK): Moved code to here for
297 simulator-reserved break instructions.
298 * gencode.c (build_instruction): Ditto.
299 * interp.c (signal_exception): Code moved from here. Non-
300 reserved instructions now use exception vector, rather
301 than halting sim.
302 * sim-main.h: Moved magic constants to here.
303
304Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
305
306 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
307 register upon non-zero interrupt event level, clear upon zero
308 event value.
309 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
310 by passing zero event value.
311 (*_io_{read,write}_buffer): Endianness fixes.
312 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
313 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
314
315 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
316 serial I/O and timer module at base address 0xFFFF0000.
317
318Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
319
320 * mips.igen (SWC1) : Correct the handling of ReverseEndian
321 and BigEndianCPU.
322
323Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
324
325 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
326 parts.
327 * configure: Update.
328
329Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
330
331 * dv-tx3904tmr.c: New file - implements tx3904 timer.
332 * dv-tx3904{irc,cpu}.c: Mild reformatting.
333 * configure.in: Include tx3904tmr in hw_device list.
334 * configure: Rebuilt.
335 * interp.c (sim_open): Instantiate three timer instances.
336 Fix address typo of tx3904irc instance.
337
338Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
339
340 * interp.c (signal_exception): SystemCall exception now uses
341 the exception vector.
342
343Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
344
345 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
346 to allay warnings.
347
348Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
349
350 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
351
352Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
353
354 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
355
356 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
357 sim-main.h. Declare a struct hw_descriptor instead of struct
358 hw_device_descriptor.
359
360Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
361
362 * mips.igen (do_store_left, do_load_left): Compute nr of left and
363 right bits and then re-align left hand bytes to correct byte
364 lanes. Fix incorrect computation in do_store_left when loading
365 bytes from second word.
366
367Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
368
369 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
370 * interp.c (sim_open): Only create a device tree when HW is
371 enabled.
372
373 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
374 * interp.c (signal_exception): Ditto.
375
376Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
377
378 * gencode.c: Mark BEGEZALL as LIKELY.
379
380Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
381
382 * sim-main.h (ALU32_END): Sign extend 32 bit results.
383 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
384
385Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
386
387 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
388 modules. Recognize TX39 target with "mips*tx39" pattern.
389 * configure: Rebuilt.
390 * sim-main.h (*): Added many macros defining bits in
391 TX39 control registers.
392 (SignalInterrupt): Send actual PC instead of NULL.
393 (SignalNMIReset): New exception type.
394 * interp.c (board): New variable for future use to identify
395 a particular board being simulated.
396 (mips_option_handler,mips_options): Added "--board" option.
397 (interrupt_event): Send actual PC.
398 (sim_open): Make memory layout conditional on board setting.
399 (signal_exception): Initial implementation of hardware interrupt
400 handling. Accept another break instruction variant for simulator
401 exit.
402 (decode_coproc): Implement RFE instruction for TX39.
403 (mips.igen): Decode RFE instruction as such.
404 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
405 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
406 bbegin to implement memory map.
407 * dv-tx3904cpu.c: New file.
408 * dv-tx3904irc.c: New file.
409
410Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
411
412 * mips.igen (check_mt_hilo): Create a separate r3900 version.
413
414Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
415
416 * tx.igen (madd,maddu): Replace calls to check_op_hilo
417 with calls to check_div_hilo.
418
419Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
420
421 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
422 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
423 Add special r3900 version of do_mult_hilo.
424 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
425 with calls to check_mult_hilo.
426 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
427 with calls to check_div_hilo.
428
429Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
430
431 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
432 Document a replacement.
433
434Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
435
436 * interp.c (sim_monitor): Make mon_printf work.
437
438Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
439
440 * sim-main.h (INSN_NAME): New arg `cpu'.
441
442Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
443
444 * configure: Regenerated to track ../common/aclocal.m4 changes.
445
446Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
447
448 * configure: Regenerated to track ../common/aclocal.m4 changes.
449 * config.in: Ditto.
450
451Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
452
453 * acconfig.h: New file.
454 * configure.in: Reverted change of Apr 24; use sinclude again.
455
456Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
457
458 * configure: Regenerated to track ../common/aclocal.m4 changes.
459 * config.in: Ditto.
460
461Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
462
463 * configure.in: Don't call sinclude.
464
465Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
466
467 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
468
469Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
470
471 * mips.igen (ERET): Implement.
472
473 * interp.c (decode_coproc): Return sign-extended EPC.
474
475 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
476
477 * interp.c (signal_exception): Do not ignore Trap.
478 (signal_exception): On TRAP, restart at exception address.
479 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
480 (signal_exception): Update.
481 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
482 so that TRAP instructions are caught.
483
484Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
485
486 * sim-main.h (struct hilo_access, struct hilo_history): Define,
487 contains HI/LO access history.
488 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
489 (HIACCESS, LOACCESS): Delete, replace with
490 (HIHISTORY, LOHISTORY): New macros.
491 (CHECKHILO): Delete all, moved to mips.igen
492
493 * gencode.c (build_instruction): Do not generate checks for
494 correct HI/LO register usage.
495
496 * interp.c (old_engine_run): Delete checks for correct HI/LO
497 register usage.
498
499 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
500 check_mf_cycles): New functions.
501 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
502 do_divu, domultx, do_mult, do_multu): Use.
503
504 * tx.igen ("madd", "maddu"): Use.
505
506Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
507
508 * mips.igen (DSRAV): Use function do_dsrav.
509 (SRAV): Use new function do_srav.
510
511 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
512 (B): Sign extend 11 bit immediate.
513 (EXT-B*): Shift 16 bit immediate left by 1.
514 (ADDIU*): Don't sign extend immediate value.
515
516Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
517
518 * m16run.c (sim_engine_run): Restore CIA after handling an event.
519
520 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
521 functions.
522
523 * mips.igen (delayslot32, nullify_next_insn): New functions.
524 (m16.igen): Always include.
525 (do_*): Add more tracing.
526
527 * m16.igen (delayslot16): Add NIA argument, could be called by a
528 32 bit MIPS16 instruction.
529
530 * interp.c (ifetch16): Move function from here.
531 * sim-main.c (ifetch16): To here.
532
533 * sim-main.c (ifetch16, ifetch32): Update to match current
534 implementations of LH, LW.
535 (signal_exception): Don't print out incorrect hex value of illegal
536 instruction.
537
538Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
539
540 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
541 instruction.
542
543 * m16.igen: Implement MIPS16 instructions.
544
545 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
546 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
547 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
548 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
549 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
550 bodies of corresponding code from 32 bit insn to these. Also used
551 by MIPS16 versions of functions.
552
553 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
554 (IMEM16): Drop NR argument from macro.
555
556Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
557
558 * Makefile.in (SIM_OBJS): Add sim-main.o.
559
560 * sim-main.h (address_translation, load_memory, store_memory,
561 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
562 as INLINE_SIM_MAIN.
563 (pr_addr, pr_uword64): Declare.
564 (sim-main.c): Include when H_REVEALS_MODULE_P.
565
566 * interp.c (address_translation, load_memory, store_memory,
567 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
568 from here.
569 * sim-main.c: To here. Fix compilation problems.
570
571 * configure.in: Enable inlining.
572 * configure: Re-config.
573
574Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
575
576 * configure: Regenerated to track ../common/aclocal.m4 changes.
577
578Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
579
580 * mips.igen: Include tx.igen.
581 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
582 * tx.igen: New file, contains MADD and MADDU.
583
584 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
585 the hardwired constant `7'.
586 (store_memory): Ditto.
587 (LOADDRMASK): Move definition to sim-main.h.
588
589 mips.igen (MTC0): Enable for r3900.
590 (ADDU): Add trace.
591
592 mips.igen (do_load_byte): Delete.
593 (do_load, do_store, do_load_left, do_load_write, do_store_left,
594 do_store_right): New functions.
595 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
596
597 configure.in: Let the tx39 use igen again.
598 configure: Update.
599
600Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
601
602 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
603 not an address sized quantity. Return zero for cache sizes.
604
605Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
606
607 * mips.igen (r3900): r3900 does not support 64 bit integer
608 operations.
609
610Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
611
612 * configure.in (mipstx39*-*-*): Use gencode simulator rather
613 than igen one.
614 * configure : Rebuild.
615
616Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
617
618 * configure: Regenerated to track ../common/aclocal.m4 changes.
619
620Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
621
622 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
623
624Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
625
626 * configure: Regenerated to track ../common/aclocal.m4 changes.
627 * config.in: Regenerated to track ../common/aclocal.m4 changes.
628
629Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
630
631 * configure: Regenerated to track ../common/aclocal.m4 changes.
632
633Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
634
635 * interp.c (Max, Min): Comment out functions. Not yet used.
636
637Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
638
639 * configure: Regenerated to track ../common/aclocal.m4 changes.
640
641Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
642
643 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
644 configurable settings for stand-alone simulator.
645
646 * configure.in: Added X11 search, just in case.
647
648 * configure: Regenerated.
649
650Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
651
652 * interp.c (sim_write, sim_read, load_memory, store_memory):
653 Replace sim_core_*_map with read_map, write_map, exec_map resp.
654
655Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
656
657 * sim-main.h (GETFCC): Return an unsigned value.
658
659Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
660
661 * mips.igen (DIV): Fix check for -1 / MIN_INT.
662 (DADD): Result destination is RD not RT.
663
664Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
665
666 * sim-main.h (HIACCESS, LOACCESS): Always define.
667
668 * mdmx.igen (Maxi, Mini): Rename Max, Min.
669
670 * interp.c (sim_info): Delete.
671
672Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
673
674 * interp.c (DECLARE_OPTION_HANDLER): Use it.
675 (mips_option_handler): New argument `cpu'.
676 (sim_open): Update call to sim_add_option_table.
677
678Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
679
680 * mips.igen (CxC1): Add tracing.
681
682Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
683
684 * sim-main.h (Max, Min): Declare.
685
686 * interp.c (Max, Min): New functions.
687
688 * mips.igen (BC1): Add tracing.
689
690Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
691
692 * interp.c Added memory map for stack in vr4100
693
694Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
695
696 * interp.c (load_memory): Add missing "break"'s.
697
698Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
699
700 * interp.c (sim_store_register, sim_fetch_register): Pass in
701 length parameter. Return -1.
702
703Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
704
705 * interp.c: Added hardware init hook, fixed warnings.
706
707Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
708
709 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
710
711Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
712
713 * interp.c (ifetch16): New function.
714
715 * sim-main.h (IMEM32): Rename IMEM.
716 (IMEM16_IMMED): Define.
717 (IMEM16): Define.
718 (DELAY_SLOT): Update.
719
720 * m16run.c (sim_engine_run): New file.
721
722 * m16.igen: All instructions except LB.
723 (LB): Call do_load_byte.
724 * mips.igen (do_load_byte): New function.
725 (LB): Call do_load_byte.
726
727 * mips.igen: Move spec for insn bit size and high bit from here.
728 * Makefile.in (tmp-igen, tmp-m16): To here.
729
730 * m16.dc: New file, decode mips16 instructions.
731
732 * Makefile.in (SIM_NO_ALL): Define.
733 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
734
735Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
736
737 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
738 point unit to 32 bit registers.
739 * configure: Re-generate.
740
741Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
742
743 * configure.in (sim_use_gen): Make IGEN the default simulator
744 generator for generic 32 and 64 bit mips targets.
745 * configure: Re-generate.
746
747Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
748
749 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
750 bitsize.
751
752 * interp.c (sim_fetch_register, sim_store_register): Read/write
753 FGR from correct location.
754 (sim_open): Set size of FGR's according to
755 WITH_TARGET_FLOATING_POINT_BITSIZE.
756
757 * sim-main.h (FGR): Store floating point registers in a separate
758 array.
759
760Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
761
762 * configure: Regenerated to track ../common/aclocal.m4 changes.
763
764Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
765
766 * interp.c (ColdReset): Call PENDING_INVALIDATE.
767
768 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
769
770 * interp.c (pending_tick): New function. Deliver pending writes.
771
772 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
773 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
774 it can handle mixed sized quantites and single bits.
775
776Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
777
778 * interp.c (oengine.h): Do not include when building with IGEN.
779 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
780 (sim_info): Ditto for PROCESSOR_64BIT.
781 (sim_monitor): Replace ut_reg with unsigned_word.
782 (*): Ditto for t_reg.
783 (LOADDRMASK): Define.
784 (sim_open): Remove defunct check that host FP is IEEE compliant,
785 using software to emulate floating point.
786 (value_fpr, ...): Always compile, was conditional on HASFPU.
787
788Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
789
790 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
791 size.
792
793 * interp.c (SD, CPU): Define.
794 (mips_option_handler): Set flags in each CPU.
795 (interrupt_event): Assume CPU 0 is the one being iterrupted.
796 (sim_close): Do not clear STATE, deleted anyway.
797 (sim_write, sim_read): Assume CPU zero's vm should be used for
798 data transfers.
799 (sim_create_inferior): Set the PC for all processors.
800 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
801 argument.
802 (mips16_entry): Pass correct nr of args to store_word, load_word.
803 (ColdReset): Cold reset all cpu's.
804 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
805 (sim_monitor, load_memory, store_memory, signal_exception): Use
806 `CPU' instead of STATE_CPU.
807
808
809 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
810 SD or CPU_.
811
812 * sim-main.h (signal_exception): Add sim_cpu arg.
813 (SignalException*): Pass both SD and CPU to signal_exception.
814 * interp.c (signal_exception): Update.
815
816 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
817 Ditto
818 (sync_operation, prefetch, cache_op, store_memory, load_memory,
819 address_translation): Ditto
820 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
821
822Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
823
824 * configure: Regenerated to track ../common/aclocal.m4 changes.
825
826Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
827
828 * interp.c (sim_engine_run): Add `nr_cpus' argument.
829
830 * mips.igen (model): Map processor names onto BFD name.
831
832 * sim-main.h (CPU_CIA): Delete.
833 (SET_CIA, GET_CIA): Define
834
835Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
836
837 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
838 regiser.
839
840 * configure.in (default_endian): Configure a big-endian simulator
841 by default.
842 * configure: Re-generate.
843
844Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
845
846 * configure: Regenerated to track ../common/aclocal.m4 changes.
847
848Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
849
850 * interp.c (sim_monitor): Handle Densan monitor outbyte
851 and inbyte functions.
852
8531997-12-29 Felix Lee <flee@cygnus.com>
854
855 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
856
857Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
858
859 * Makefile.in (tmp-igen): Arrange for $zero to always be
860 reset to zero after every instruction.
861
862Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
863
864 * configure: Regenerated to track ../common/aclocal.m4 changes.
865 * config.in: Ditto.
866
867Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
868
869 * mips.igen (MSUB): Fix to work like MADD.
870 * gencode.c (MSUB): Similarly.
871
872Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
873
874 * configure: Regenerated to track ../common/aclocal.m4 changes.
875
876Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
877
878 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
879
880Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
881
882 * sim-main.h (sim-fpu.h): Include.
883
884 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
885 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
886 using host independant sim_fpu module.
887
888Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
889
890 * interp.c (signal_exception): Report internal errors with SIGABRT
891 not SIGQUIT.
892
893 * sim-main.h (C0_CONFIG): New register.
894 (signal.h): No longer include.
895
896 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
897
898Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
899
900 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
901
902Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
903
904 * mips.igen: Tag vr5000 instructions.
905 (ANDI): Was missing mipsIV model, fix assembler syntax.
906 (do_c_cond_fmt): New function.
907 (C.cond.fmt): Handle mips I-III which do not support CC field
908 separatly.
909 (bc1): Handle mips IV which do not have a delaed FCC separatly.
910 (SDR): Mask paddr when BigEndianMem, not the converse as specified
911 in IV3.2 spec.
912 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
913 vr5000 which saves LO in a GPR separatly.
914
915 * configure.in (enable-sim-igen): For vr5000, select vr5000
916 specific instructions.
917 * configure: Re-generate.
918
919Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * Makefile.in (SIM_OBJS): Add sim-fpu module.
922
923 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
924 fmt_uninterpreted_64 bit cases to switch. Convert to
925 fmt_formatted,
926
927 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
928
929 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
930 as specified in IV3.2 spec.
931 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
932
933Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
934
935 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
936 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
937 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
938 PENDING_FILL versions of instructions. Simplify.
939 (X): New function.
940 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
941 instructions.
942 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
943 a signed value.
944 (MTHI, MFHI): Disable code checking HI-LO.
945
946 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
947 global.
948 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
949
950Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
951
952 * gencode.c (build_mips16_operands): Replace IPC with cia.
953
954 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
955 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
956 IPC to `cia'.
957 (UndefinedResult): Replace function with macro/function
958 combination.
959 (sim_engine_run): Don't save PC in IPC.
960
961 * sim-main.h (IPC): Delete.
962
963
964 * interp.c (signal_exception, store_word, load_word,
965 address_translation, load_memory, store_memory, cache_op,
966 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
967 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
968 current instruction address - cia - argument.
969 (sim_read, sim_write): Call address_translation directly.
970 (sim_engine_run): Rename variable vaddr to cia.
971 (signal_exception): Pass cia to sim_monitor
972
973 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
974 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
975 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
976
977 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
978 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
979 SIM_ASSERT.
980
981 * interp.c (signal_exception): Pass restart address to
982 sim_engine_restart.
983
984 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
985 idecode.o): Add dependency.
986
987 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
988 Delete definitions
989 (DELAY_SLOT): Update NIA not PC with branch address.
990 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
991
992 * mips.igen: Use CIA not PC in branch calculations.
993 (illegal): Call SignalException.
994 (BEQ, ADDIU): Fix assembler.
995
996Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
997
998 * m16.igen (JALX): Was missing.
999
1000 * configure.in (enable-sim-igen): New configuration option.
1001 * configure: Re-generate.
1002
1003 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1004
1005 * interp.c (load_memory, store_memory): Delete parameter RAW.
1006 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1007 bypassing {load,store}_memory.
1008
1009 * sim-main.h (ByteSwapMem): Delete definition.
1010
1011 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1012
1013 * interp.c (sim_do_command, sim_commands): Delete mips specific
1014 commands. Handled by module sim-options.
1015
1016 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1017 (WITH_MODULO_MEMORY): Define.
1018
1019 * interp.c (sim_info): Delete code printing memory size.
1020
1021 * interp.c (mips_size): Nee sim_size, delete function.
1022 (power2): Delete.
1023 (monitor, monitor_base, monitor_size): Delete global variables.
1024 (sim_open, sim_close): Delete code creating monitor and other
1025 memory regions. Use sim-memopts module, via sim_do_commandf, to
1026 manage memory regions.
1027 (load_memory, store_memory): Use sim-core for memory model.
1028
1029 * interp.c (address_translation): Delete all memory map code
1030 except line forcing 32 bit addresses.
1031
1032Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1033
1034 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1035 trace options.
1036
1037 * interp.c (logfh, logfile): Delete globals.
1038 (sim_open, sim_close): Delete code opening & closing log file.
1039 (mips_option_handler): Delete -l and -n options.
1040 (OPTION mips_options): Ditto.
1041
1042 * interp.c (OPTION mips_options): Rename option trace to dinero.
1043 (mips_option_handler): Update.
1044
1045Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1046
1047 * interp.c (fetch_str): New function.
1048 (sim_monitor): Rewrite using sim_read & sim_write.
1049 (sim_open): Check magic number.
1050 (sim_open): Write monitor vectors into memory using sim_write.
1051 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1052 (sim_read, sim_write): Simplify - transfer data one byte at a
1053 time.
1054 (load_memory, store_memory): Clarify meaning of parameter RAW.
1055
1056 * sim-main.h (isHOST): Defete definition.
1057 (isTARGET): Mark as depreciated.
1058 (address_translation): Delete parameter HOST.
1059
1060 * interp.c (address_translation): Delete parameter HOST.
1061
1062Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1063
1064 * mips.igen:
1065
1066 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1067 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1068
1069Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1070
1071 * mips.igen: Add model filter field to records.
1072
1073Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1074
1075 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1076
1077 interp.c (sim_engine_run): Do not compile function sim_engine_run
1078 when WITH_IGEN == 1.
1079
1080 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1081 target architecture.
1082
1083 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1084 igen. Replace with configuration variables sim_igen_flags /
1085 sim_m16_flags.
1086
1087 * m16.igen: New file. Copy mips16 insns here.
1088 * mips.igen: From here.
1089
1090Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1091
1092 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1093 to top.
1094 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1095
1096Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1097
1098 * gencode.c (build_instruction): Follow sim_write's lead in using
1099 BigEndianMem instead of !ByteSwapMem.
1100
1101Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1102
1103 * configure.in (sim_gen): Dependent on target, select type of
1104 generator. Always select old style generator.
1105
1106 configure: Re-generate.
1107
1108 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1109 targets.
1110 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1111 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1112 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1113 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1114 SIM_@sim_gen@_*, set by autoconf.
1115
1116Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1117
1118 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1119
1120 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1121 CURRENT_FLOATING_POINT instead.
1122
1123 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1124 (address_translation): Raise exception InstructionFetch when
1125 translation fails and isINSTRUCTION.
1126
1127 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1128 sim_engine_run): Change type of of vaddr and paddr to
1129 address_word.
1130 (address_translation, prefetch, load_memory, store_memory,
1131 cache_op): Change type of vAddr and pAddr to address_word.
1132
1133 * gencode.c (build_instruction): Change type of vaddr and paddr to
1134 address_word.
1135
1136Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1137
1138 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1139 macro to obtain result of ALU op.
1140
1141Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1142
1143 * interp.c (sim_info): Call profile_print.
1144
1145Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1146
1147 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1148
1149 * sim-main.h (WITH_PROFILE): Do not define, defined in
1150 common/sim-config.h. Use sim-profile module.
1151 (simPROFILE): Delete defintion.
1152
1153 * interp.c (PROFILE): Delete definition.
1154 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1155 (sim_close): Delete code writing profile histogram.
1156 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1157 Delete.
1158 (sim_engine_run): Delete code profiling the PC.
1159
1160Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1161
1162 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1163
1164 * interp.c (sim_monitor): Make register pointers of type
1165 unsigned_word*.
1166
1167 * sim-main.h: Make registers of type unsigned_word not
1168 signed_word.
1169
1170Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1171
1172 * interp.c (sync_operation): Rename from SyncOperation, make
1173 global, add SD argument.
1174 (prefetch): Rename from Prefetch, make global, add SD argument.
1175 (decode_coproc): Make global.
1176
1177 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1178
1179 * gencode.c (build_instruction): Generate DecodeCoproc not
1180 decode_coproc calls.
1181
1182 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1183 (SizeFGR): Move to sim-main.h
1184 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1185 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1186 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1187 sim-main.h.
1188 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1189 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1190 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1191 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1192 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1193 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1194
1195 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1196 exception.
1197 (sim-alu.h): Include.
1198 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1199 (sim_cia): Typedef to instruction_address.
1200
1201Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1202
1203 * Makefile.in (interp.o): Rename generated file engine.c to
1204 oengine.c.
1205
1206 * interp.c: Update.
1207
1208Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1209
1210 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1211
1212Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1213
1214 * gencode.c (build_instruction): For "FPSQRT", output correct
1215 number of arguments to Recip.
1216
1217Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1218
1219 * Makefile.in (interp.o): Depends on sim-main.h
1220
1221 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1222
1223 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1224 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1225 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1226 STATE, DSSTATE): Define
1227 (GPR, FGRIDX, ..): Define.
1228
1229 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1230 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1231 (GPR, FGRIDX, ...): Delete macros.
1232
1233 * interp.c: Update names to match defines from sim-main.h
1234
1235Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1236
1237 * interp.c (sim_monitor): Add SD argument.
1238 (sim_warning): Delete. Replace calls with calls to
1239 sim_io_eprintf.
1240 (sim_error): Delete. Replace calls with sim_io_error.
1241 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1242 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1243 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1244 argument.
1245 (mips_size): Rename from sim_size. Add SD argument.
1246
1247 * interp.c (simulator): Delete global variable.
1248 (callback): Delete global variable.
1249 (mips_option_handler, sim_open, sim_write, sim_read,
1250 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1251 sim_size,sim_monitor): Use sim_io_* not callback->*.
1252 (sim_open): ZALLOC simulator struct.
1253 (PROFILE): Do not define.
1254
1255Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1256
1257 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1258 support.h with corresponding code.
1259
1260 * sim-main.h (word64, uword64), support.h: Move definition to
1261 sim-main.h.
1262 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1263
1264 * support.h: Delete
1265 * Makefile.in: Update dependencies
1266 * interp.c: Do not include.
1267
1268Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1269
1270 * interp.c (address_translation, load_memory, store_memory,
1271 cache_op): Rename to from AddressTranslation et.al., make global,
1272 add SD argument
1273
1274 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1275 CacheOp): Define.
1276
1277 * interp.c (SignalException): Rename to signal_exception, make
1278 global.
1279
1280 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1281
1282 * sim-main.h (SignalException, SignalExceptionInterrupt,
1283 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1284 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1285 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1286 Define.
1287
1288 * interp.c, support.h: Use.
1289
1290Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1291
1292 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1293 to value_fpr / store_fpr. Add SD argument.
1294 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1295 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1296
1297 * sim-main.h (ValueFPR, StoreFPR): Define.
1298
1299Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1300
1301 * interp.c (sim_engine_run): Check consistency between configure
1302 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1303 and HASFPU.
1304
1305 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1306 (mips_fpu): Configure WITH_FLOATING_POINT.
1307 (mips_endian): Configure WITH_TARGET_ENDIAN.
1308 * configure: Update.
1309
1310Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1311
1312 * configure: Regenerated to track ../common/aclocal.m4 changes.
1313
1314Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1315
1316 * configure: Regenerated.
1317
1318Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1319
1320 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1321
1322Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1323
1324 * gencode.c (print_igen_insn_models): Assume certain architectures
1325 include all mips* instructions.
1326 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1327 instruction.
1328
1329 * Makefile.in (tmp.igen): Add target. Generate igen input from
1330 gencode file.
1331
1332 * gencode.c (FEATURE_IGEN): Define.
1333 (main): Add --igen option. Generate output in igen format.
1334 (process_instructions): Format output according to igen option.
1335 (print_igen_insn_format): New function.
1336 (print_igen_insn_models): New function.
1337 (process_instructions): Only issue warnings and ignore
1338 instructions when no FEATURE_IGEN.
1339
1340Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1341
1342 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1343 MIPS targets.
1344
1345Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1346
1347 * configure: Regenerated to track ../common/aclocal.m4 changes.
1348
1349Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1350
1351 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1352 SIM_RESERVED_BITS): Delete, moved to common.
1353 (SIM_EXTRA_CFLAGS): Update.
1354
1355Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * configure.in: Configure non-strict memory alignment.
1358 * configure: Regenerated to track ../common/aclocal.m4 changes.
1359
1360Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1361
1362 * configure: Regenerated to track ../common/aclocal.m4 changes.
1363
1364Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1365
1366 * gencode.c (SDBBP,DERET): Added (3900) insns.
1367 (RFE): Turn on for 3900.
1368 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1369 (dsstate): Made global.
1370 (SUBTARGET_R3900): Added.
1371 (CANCELDELAYSLOT): New.
1372 (SignalException): Ignore SystemCall rather than ignore and
1373 terminate. Add DebugBreakPoint handling.
1374 (decode_coproc): New insns RFE, DERET; and new registers Debug
1375 and DEPC protected by SUBTARGET_R3900.
1376 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1377 bits explicitly.
1378 * Makefile.in,configure.in: Add mips subtarget option.
1379 * configure: Update.
1380
1381Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1382
1383 * gencode.c: Add r3900 (tx39).
1384
1385
1386Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1387
1388 * gencode.c (build_instruction): Don't need to subtract 4 for
1389 JALR, just 2.
1390
1391Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1392
1393 * interp.c: Correct some HASFPU problems.
1394
1395Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1396
1397 * configure: Regenerated to track ../common/aclocal.m4 changes.
1398
1399Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400
1401 * interp.c (mips_options): Fix samples option short form, should
1402 be `x'.
1403
1404Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1405
1406 * interp.c (sim_info): Enable info code. Was just returning.
1407
1408Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1409
1410 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1411 MFC0.
1412
1413Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1414
1415 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1416 constants.
1417 (build_instruction): Ditto for LL.
1418
1419Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1420
1421 * configure: Regenerated to track ../common/aclocal.m4 changes.
1422
1423Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * configure: Regenerated to track ../common/aclocal.m4 changes.
1426 * config.in: Ditto.
1427
1428Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * interp.c (sim_open): Add call to sim_analyze_program, update
1431 call to sim_config.
1432
1433Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * interp.c (sim_kill): Delete.
1436 (sim_create_inferior): Add ABFD argument. Set PC from same.
1437 (sim_load): Move code initializing trap handlers from here.
1438 (sim_open): To here.
1439 (sim_load): Delete, use sim-hload.c.
1440
1441 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1442
1443Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1444
1445 * configure: Regenerated to track ../common/aclocal.m4 changes.
1446 * config.in: Ditto.
1447
1448Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1449
1450 * interp.c (sim_open): Add ABFD argument.
1451 (sim_load): Move call to sim_config from here.
1452 (sim_open): To here. Check return status.
1453
1454Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1455
1456 * gencode.c (build_instruction): Two arg MADD should
1457 not assign result to $0.
1458
1459Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1460
1461 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1462 * sim/mips/configure.in: Regenerate.
1463
1464Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1465
1466 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1467 signed8, unsigned8 et.al. types.
1468
1469 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1470 hosts when selecting subreg.
1471
1472Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1473
1474 * interp.c (sim_engine_run): Reset the ZERO register to zero
1475 regardless of FEATURE_WARN_ZERO.
1476 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1477
1478Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1479
1480 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1481 (SignalException): For BreakPoints ignore any mode bits and just
1482 save the PC.
1483 (SignalException): Always set the CAUSE register.
1484
1485Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1486
1487 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1488 exception has been taken.
1489
1490 * interp.c: Implement the ERET and mt/f sr instructions.
1491
1492Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1493
1494 * interp.c (SignalException): Don't bother restarting an
1495 interrupt.
1496
1497Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1498
1499 * interp.c (SignalException): Really take an interrupt.
1500 (interrupt_event): Only deliver interrupts when enabled.
1501
1502Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1503
1504 * interp.c (sim_info): Only print info when verbose.
1505 (sim_info) Use sim_io_printf for output.
1506
1507Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1510 mips architectures.
1511
1512Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1513
1514 * interp.c (sim_do_command): Check for common commands if a
1515 simulator specific command fails.
1516
1517Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1518
1519 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1520 and simBE when DEBUG is defined.
1521
1522Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1523
1524 * interp.c (interrupt_event): New function. Pass exception event
1525 onto exception handler.
1526
1527 * configure.in: Check for stdlib.h.
1528 * configure: Regenerate.
1529
1530 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1531 variable declaration.
1532 (build_instruction): Initialize memval1.
1533 (build_instruction): Add UNUSED attribute to byte, bigend,
1534 reverse.
1535 (build_operands): Ditto.
1536
1537 * interp.c: Fix GCC warnings.
1538 (sim_get_quit_code): Delete.
1539
1540 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1541 * Makefile.in: Ditto.
1542 * configure: Re-generate.
1543
1544 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1545
1546Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * interp.c (mips_option_handler): New function parse argumes using
1549 sim-options.
1550 (myname): Replace with STATE_MY_NAME.
1551 (sim_open): Delete check for host endianness - performed by
1552 sim_config.
1553 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1554 (sim_open): Move much of the initialization from here.
1555 (sim_load): To here. After the image has been loaded and
1556 endianness set.
1557 (sim_open): Move ColdReset from here.
1558 (sim_create_inferior): To here.
1559 (sim_open): Make FP check less dependant on host endianness.
1560
1561 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1562 run.
1563 * interp.c (sim_set_callbacks): Delete.
1564
1565 * interp.c (membank, membank_base, membank_size): Replace with
1566 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1567 (sim_open): Remove call to callback->init. gdb/run do this.
1568
1569 * interp.c: Update
1570
1571 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1572
1573 * interp.c (big_endian_p): Delete, replaced by
1574 current_target_byte_order.
1575
1576Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1577
1578 * interp.c (host_read_long, host_read_word, host_swap_word,
1579 host_swap_long): Delete. Using common sim-endian.
1580 (sim_fetch_register, sim_store_register): Use H2T.
1581 (pipeline_ticks): Delete. Handled by sim-events.
1582 (sim_info): Update.
1583 (sim_engine_run): Update.
1584
1585Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1586
1587 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1588 reason from here.
1589 (SignalException): To here. Signal using sim_engine_halt.
1590 (sim_stop_reason): Delete, moved to common.
1591
1592Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1593
1594 * interp.c (sim_open): Add callback argument.
1595 (sim_set_callbacks): Delete SIM_DESC argument.
1596 (sim_size): Ditto.
1597
1598Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1599
1600 * Makefile.in (SIM_OBJS): Add common modules.
1601
1602 * interp.c (sim_set_callbacks): Also set SD callback.
1603 (set_endianness, xfer_*, swap_*): Delete.
1604 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1605 Change to functions using sim-endian macros.
1606 (control_c, sim_stop): Delete, use common version.
1607 (simulate): Convert into.
1608 (sim_engine_run): This function.
1609 (sim_resume): Delete.
1610
1611 * interp.c (simulation): New variable - the simulator object.
1612 (sim_kind): Delete global - merged into simulation.
1613 (sim_load): Cleanup. Move PC assignment from here.
1614 (sim_create_inferior): To here.
1615
1616 * sim-main.h: New file.
1617 * interp.c (sim-main.h): Include.
1618
1619Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1620
1621 * configure: Regenerated to track ../common/aclocal.m4 changes.
1622
1623Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1624
1625 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1626
1627Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1628
1629 * gencode.c (build_instruction): DIV instructions: check
1630 for division by zero and integer overflow before using
1631 host's division operation.
1632
1633Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1634
1635 * Makefile.in (SIM_OBJS): Add sim-load.o.
1636 * interp.c: #include bfd.h.
1637 (target_byte_order): Delete.
1638 (sim_kind, myname, big_endian_p): New static locals.
1639 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1640 after argument parsing. Recognize -E arg, set endianness accordingly.
1641 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1642 load file into simulator. Set PC from bfd.
1643 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1644 (set_endianness): Use big_endian_p instead of target_byte_order.
1645
1646Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1647
1648 * interp.c (sim_size): Delete prototype - conflicts with
1649 definition in remote-sim.h. Correct definition.
1650
1651Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1652
1653 * configure: Regenerated to track ../common/aclocal.m4 changes.
1654 * config.in: Ditto.
1655
1656Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1657
1658 * interp.c (sim_open): New arg `kind'.
1659
1660 * configure: Regenerated to track ../common/aclocal.m4 changes.
1661
1662Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1663
1664 * configure: Regenerated to track ../common/aclocal.m4 changes.
1665
1666Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1667
1668 * interp.c (sim_open): Set optind to 0 before calling getopt.
1669
1670Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1671
1672 * configure: Regenerated to track ../common/aclocal.m4 changes.
1673
1674Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1675
1676 * interp.c : Replace uses of pr_addr with pr_uword64
1677 where the bit length is always 64 independent of SIM_ADDR.
1678 (pr_uword64) : added.
1679
1680Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1681
1682 * configure: Re-generate.
1683
1684Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1685
1686 * configure: Regenerate to track ../common/aclocal.m4 changes.
1687
1688Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1689
1690 * interp.c (sim_open): New SIM_DESC result. Argument is now
1691 in argv form.
1692 (other sim_*): New SIM_DESC argument.
1693
1694Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1695
1696 * interp.c: Fix printing of addresses for non-64-bit targets.
1697 (pr_addr): Add function to print address based on size.
1698
1699Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1700
1701 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1702
1703Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1704
1705 * gencode.c (build_mips16_operands): Correct computation of base
1706 address for extended PC relative instruction.
1707
1708Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1709
1710 * interp.c (mips16_entry): Add support for floating point cases.
1711 (SignalException): Pass floating point cases to mips16_entry.
1712 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1713 registers.
1714 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1715 or fmt_word.
1716 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1717 and then set the state to fmt_uninterpreted.
1718 (COP_SW): Temporarily set the state to fmt_word while calling
1719 ValueFPR.
1720
1721Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1722
1723 * gencode.c (build_instruction): The high order may be set in the
1724 comparison flags at any ISA level, not just ISA 4.
1725
1726Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1727
1728 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1729 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1730 * configure.in: sinclude ../common/aclocal.m4.
1731 * configure: Regenerated.
1732
1733Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1734
1735 * configure: Rebuild after change to aclocal.m4.
1736
1737Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1738
1739 * configure configure.in Makefile.in: Update to new configure
1740 scheme which is more compatible with WinGDB builds.
1741 * configure.in: Improve comment on how to run autoconf.
1742 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1743 * Makefile.in: Use autoconf substitution to install common
1744 makefile fragment.
1745
1746Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1747
1748 * gencode.c (build_instruction): Use BigEndianCPU instead of
1749 ByteSwapMem.
1750
1751Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1752
1753 * interp.c (sim_monitor): Make output to stdout visible in
1754 wingdb's I/O log window.
1755
1756Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1757
1758 * support.h: Undo previous change to SIGTRAP
1759 and SIGQUIT values.
1760
1761Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1762
1763 * interp.c (store_word, load_word): New static functions.
1764 (mips16_entry): New static function.
1765 (SignalException): Look for mips16 entry and exit instructions.
1766 (simulate): Use the correct index when setting fpr_state after
1767 doing a pending move.
1768
1769Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1770
1771 * interp.c: Fix byte-swapping code throughout to work on
1772 both little- and big-endian hosts.
1773
1774Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1775
1776 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1777 with gdb/config/i386/xm-windows.h.
1778
1779Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1780
1781 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1782 that messes up arithmetic shifts.
1783
1784Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1785
1786 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1787 SIGTRAP and SIGQUIT for _WIN32.
1788
1789Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1790
1791 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1792 force a 64 bit multiplication.
1793 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1794 destination register is 0, since that is the default mips16 nop
1795 instruction.
1796
1797Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1798
1799 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1800 (build_endian_shift): Don't check proc64.
1801 (build_instruction): Always set memval to uword64. Cast op2 to
1802 uword64 when shifting it left in memory instructions. Always use
1803 the same code for stores--don't special case proc64.
1804
1805 * gencode.c (build_mips16_operands): Fix base PC value for PC
1806 relative operands.
1807 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1808 jal instruction.
1809 * interp.c (simJALDELAYSLOT): Define.
1810 (JALDELAYSLOT): Define.
1811 (INDELAYSLOT, INJALDELAYSLOT): Define.
1812 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1813
1814Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1815
1816 * interp.c (sim_open): add flush_cache as a PMON routine
1817 (sim_monitor): handle flush_cache by ignoring it
1818
1819Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1820
1821 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1822 BigEndianMem.
1823 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1824 (BigEndianMem): Rename to ByteSwapMem and change sense.
1825 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1826 BigEndianMem references to !ByteSwapMem.
1827 (set_endianness): New function, with prototype.
1828 (sim_open): Call set_endianness.
1829 (sim_info): Use simBE instead of BigEndianMem.
1830 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1831 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1832 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1833 ifdefs, keeping the prototype declaration.
1834 (swap_word): Rewrite correctly.
1835 (ColdReset): Delete references to CONFIG. Delete endianness related
1836 code; moved to set_endianness.
1837
1838Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1839
1840 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1841 * interp.c (CHECKHILO): Define away.
1842 (simSIGINT): New macro.
1843 (membank_size): Increase from 1MB to 2MB.
1844 (control_c): New function.
1845 (sim_resume): Rename parameter signal to signal_number. Add local
1846 variable prev. Call signal before and after simulate.
1847 (sim_stop_reason): Add simSIGINT support.
1848 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1849 functions always.
1850 (sim_warning): Delete call to SignalException. Do call printf_filtered
1851 if logfh is NULL.
1852 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1853 a call to sim_warning.
1854
1855Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1856
1857 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1858 16 bit instructions.
1859
1860Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1861
1862 Add support for mips16 (16 bit MIPS implementation):
1863 * gencode.c (inst_type): Add mips16 instruction encoding types.
1864 (GETDATASIZEINSN): Define.
1865 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1866 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1867 mtlo.
1868 (MIPS16_DECODE): New table, for mips16 instructions.
1869 (bitmap_val): New static function.
1870 (struct mips16_op): Define.
1871 (mips16_op_table): New table, for mips16 operands.
1872 (build_mips16_operands): New static function.
1873 (process_instructions): If PC is odd, decode a mips16
1874 instruction. Break out instruction handling into new
1875 build_instruction function.
1876 (build_instruction): New static function, broken out of
1877 process_instructions. Check modifiers rather than flags for SHIFT
1878 bit count and m[ft]{hi,lo} direction.
1879 (usage): Pass program name to fprintf.
1880 (main): Remove unused variable this_option_optind. Change
1881 ``*loptarg++'' to ``loptarg++''.
1882 (my_strtoul): Parenthesize && within ||.
1883 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1884 (simulate): If PC is odd, fetch a 16 bit instruction, and
1885 increment PC by 2 rather than 4.
1886 * configure.in: Add case for mips16*-*-*.
1887 * configure: Rebuild.
1888
1889Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1890
1891 * interp.c: Allow -t to enable tracing in standalone simulator.
1892 Fix garbage output in trace file and error messages.
1893
1894Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1895
1896 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1897 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1898 * configure.in: Simplify using macros in ../common/aclocal.m4.
1899 * configure: Regenerated.
1900 * tconfig.in: New file.
1901
1902Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1903
1904 * interp.c: Fix bugs in 64-bit port.
1905 Use ansi function declarations for msvc compiler.
1906 Initialize and test file pointer in trace code.
1907 Prevent duplicate definition of LAST_EMED_REGNUM.
1908
1909Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1910
1911 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1912
1913Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1914
1915 * interp.c (SignalException): Check for explicit terminating
1916 breakpoint value.
1917 * gencode.c: Pass instruction value through SignalException()
1918 calls for Trap, Breakpoint and Syscall.
1919
1920Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1921
1922 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1923 only used on those hosts that provide it.
1924 * configure.in: Add sqrt() to list of functions to be checked for.
1925 * config.in: Re-generated.
1926 * configure: Re-generated.
1927
1928Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1929
1930 * gencode.c (process_instructions): Call build_endian_shift when
1931 expanding STORE RIGHT, to fix swr.
1932 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1933 clear the high bits.
1934 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1935 Fix float to int conversions to produce signed values.
1936
1937Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1938
1939 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1940 (process_instructions): Correct handling of nor instruction.
1941 Correct shift count for 32 bit shift instructions. Correct sign
1942 extension for arithmetic shifts to not shift the number of bits in
1943 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1944 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1945 Fix madd.
1946 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1947 It's OK to have a mult follow a mult. What's not OK is to have a
1948 mult follow an mfhi.
1949 (Convert): Comment out incorrect rounding code.
1950
1951Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1952
1953 * interp.c (sim_monitor): Improved monitor printf
1954 simulation. Tidied up simulator warnings, and added "--log" option
1955 for directing warning message output.
1956 * gencode.c: Use sim_warning() rather than WARNING macro.
1957
1958Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1959
1960 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1961 getopt1.o, rather than on gencode.c. Link objects together.
1962 Don't link against -liberty.
1963 (gencode.o, getopt.o, getopt1.o): New targets.
1964 * gencode.c: Include <ctype.h> and "ansidecl.h".
1965 (AND): Undefine after including "ansidecl.h".
1966 (ULONG_MAX): Define if not defined.
1967 (OP_*): Don't define macros; now defined in opcode/mips.h.
1968 (main): Call my_strtoul rather than strtoul.
1969 (my_strtoul): New static function.
1970
1971Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1972
1973 * gencode.c (process_instructions): Generate word64 and uword64
1974 instead of `long long' and `unsigned long long' data types.
1975 * interp.c: #include sysdep.h to get signals, and define default
1976 for SIGBUS.
1977 * (Convert): Work around for Visual-C++ compiler bug with type
1978 conversion.
1979 * support.h: Make things compile under Visual-C++ by using
1980 __int64 instead of `long long'. Change many refs to long long
1981 into word64/uword64 typedefs.
1982
1983Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1984
1985 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1986 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1987 (docdir): Removed.
1988 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1989 (AC_PROG_INSTALL): Added.
1990 (AC_PROG_CC): Moved to before configure.host call.
1991 * configure: Rebuilt.
1992
1993Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
1994
1995 * configure.in: Define @SIMCONF@ depending on mips target.
1996 * configure: Rebuild.
1997 * Makefile.in (run): Add @SIMCONF@ to control simulator
1998 construction.
1999 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2000 * interp.c: Remove some debugging, provide more detailed error
2001 messages, update memory accesses to use LOADDRMASK.
2002
2003Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2004
2005 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2006 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2007 stamp-h.
2008 * configure: Rebuild.
2009 * config.in: New file, generated by autoheader.
2010 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2011 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2012 HAVE_ANINT and HAVE_AINT, as appropriate.
2013 * Makefile.in (run): Use @LIBS@ rather than -lm.
2014 (interp.o): Depend upon config.h.
2015 (Makefile): Just rebuild Makefile.
2016 (clean): Remove stamp-h.
2017 (mostlyclean): Make the same as clean, not as distclean.
2018 (config.h, stamp-h): New targets.
2019
2020Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2021
2022 * interp.c (ColdReset): Fix boolean test. Make all simulator
2023 globals static.
2024
2025Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2026
2027 * interp.c (xfer_direct_word, xfer_direct_long,
2028 swap_direct_word, swap_direct_long, xfer_big_word,
2029 xfer_big_long, xfer_little_word, xfer_little_long,
2030 swap_word,swap_long): Added.
2031 * interp.c (ColdReset): Provide function indirection to
2032 host<->simulated_target transfer routines.
2033 * interp.c (sim_store_register, sim_fetch_register): Updated to
2034 make use of indirected transfer routines.
2035
2036Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2037
2038 * gencode.c (process_instructions): Ensure FP ABS instruction
2039 recognised.
2040 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2041 system call support.
2042
2043Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2044
2045 * interp.c (sim_do_command): Complain if callback structure not
2046 initialised.
2047
2048Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2049
2050 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2051 support for Sun hosts.
2052 * Makefile.in (gencode): Ensure the host compiler and libraries
2053 used for cross-hosted build.
2054
2055Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2056
2057 * interp.c, gencode.c: Some more (TODO) tidying.
2058
2059Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2060
2061 * gencode.c, interp.c: Replaced explicit long long references with
2062 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2063 * support.h (SET64LO, SET64HI): Macros added.
2064
2065Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2066
2067 * configure: Regenerate with autoconf 2.7.
2068
2069Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2070
2071 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2072 * support.h: Remove superfluous "1" from #if.
2073 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2074
2075Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2076
2077 * interp.c (StoreFPR): Control UndefinedResult() call on
2078 WARN_RESULT manifest.
2079
2080Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2081
2082 * gencode.c: Tidied instruction decoding, and added FP instruction
2083 support.
2084
2085 * interp.c: Added dineroIII, and BSD profiling support. Also
2086 run-time FP handling.
2087
2088Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2089
2090 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2091 gencode.c, interp.c, support.h: created.
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