1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27 #include "safe-ctype.h"
29 #include "opcode/arc.h"
30 #include "opcode/arc-attrs.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 #ifndef TARGET_WITH_CPU
52 #define TARGET_WITH_CPU "arc700"
53 #endif /* TARGET_WITH_CPU */
55 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57 #define streq(a, b) (strcmp (a, b) == 0)
59 /* Enum used to enumerate the relaxable ins operands. */
64 REGISTER_S
, /* Register for short instruction(s). */
65 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
66 REGISTER_DUP
, /* Duplication of previous operand of type register. */
100 #define regno(x) ((x) & 0x3F)
101 #define is_ir_num(x) (((x) & ~0x3F) == 0)
102 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103 #define is_spfp_p(op) (((sc) == SPX))
104 #define is_dpfp_p(op) (((sc) == DPX))
105 #define is_fpuda_p(op) (((sc) == DPA))
106 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
118 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
119 #define is_nps400_p(op) (((sc) == NPS400))
121 /* Generic assembler global variables which must be defined by all
124 /* Characters which always start a comment. */
125 const char comment_chars
[] = "#;";
127 /* Characters which start a comment at the beginning of a line. */
128 const char line_comment_chars
[] = "#";
130 /* Characters which may be used to separate multiple commands on a
132 const char line_separator_chars
[] = "`";
134 /* Characters which are used to indicate an exponent in a floating
136 const char EXP_CHARS
[] = "eE";
138 /* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
140 const char FLT_CHARS
[] = "rRsSfFdD";
143 extern int target_big_endian
;
144 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
145 static int byte_order
= DEFAULT_BYTE_ORDER
;
147 /* Arc extension section. */
148 static segT arcext_section
;
150 /* By default relaxation is disabled. */
151 static int relaxation_state
= 0;
153 extern int arc_get_mach (char *);
155 /* Forward declarations. */
156 static void arc_lcomm (int);
157 static void arc_option (int);
158 static void arc_extra_reloc (int);
159 static void arc_extinsn (int);
160 static void arc_extcorereg (int);
161 static void arc_attribute (int);
163 const pseudo_typeS md_pseudo_table
[] =
165 /* Make sure that .word is 32 bits. */
168 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm
, 0 },
170 { "lcommon", arc_lcomm
, 0 },
171 { "cpu", arc_option
, 0 },
173 { "arc_attribute", arc_attribute
, 0 },
174 { "extinstruction", arc_extinsn
, 0 },
175 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
176 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
177 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
179 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
180 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
185 const char *md_shortopts
= "";
189 OPTION_EB
= OPTION_MD_BASE
,
207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
231 struct option md_longopts
[] =
233 { "EB", no_argument
, NULL
, OPTION_EB
},
234 { "EL", no_argument
, NULL
, OPTION_EL
},
235 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
236 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
237 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
238 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
239 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
240 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
241 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
242 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
243 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
244 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
245 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
247 /* Floating point options */
248 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
249 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
250 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
251 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
252 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
253 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
254 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
255 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
256 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
257 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
258 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
263 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
264 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
265 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
266 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
267 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
268 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
269 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
270 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
271 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
272 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
273 { "mea", no_argument
, NULL
, OPTION_EA
},
274 { "mEA", no_argument
, NULL
, OPTION_EA
},
275 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
276 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
277 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
278 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
279 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
280 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
281 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
282 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
283 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
284 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
285 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
286 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
287 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
288 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
289 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
291 { NULL
, no_argument
, NULL
, 0 }
294 size_t md_longopts_size
= sizeof (md_longopts
);
296 /* Local data and data types. */
298 /* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300 typedef int extended_bfd_reloc_code_real_type
;
306 extended_bfd_reloc_code_real_type reloc
;
308 /* index into arc_operands. */
309 unsigned int opindex
;
311 /* PC-relative, used by internals fixups. */
314 /* TRUE if this fixup is for LIMM operand. */
320 unsigned long long int insn
;
322 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
324 unsigned int len
; /* Length of instruction in bytes. */
325 bfd_boolean has_limm
; /* Boolean value: TRUE if limm field is
327 bfd_boolean relax
; /* Boolean value: TRUE if needs
331 /* Structure to hold any last two instructions. */
332 static struct arc_last_insn
334 /* Saved instruction opcode. */
335 const struct arc_opcode
*opcode
;
337 /* Boolean value: TRUE if current insn is short. */
338 bfd_boolean has_limm
;
340 /* Boolean value: TRUE if current insn has delay slot. */
341 bfd_boolean has_delay_slot
;
344 /* Extension instruction suffix classes. */
352 static const attributes_t suffixclass
[] =
354 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
355 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
356 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
359 /* Extension instruction syntax classes. */
360 static const attributes_t syntaxclass
[] =
362 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
363 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
364 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
365 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
368 /* Extension instruction syntax classes modifiers. */
369 static const attributes_t syntaxclassmod
[] =
371 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
372 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
375 /* Extension register type. */
383 /* A structure to hold the additional conditional codes. */
386 struct arc_flag_operand
*arc_ext_condcode
;
388 } ext_condcode
= { NULL
, 0 };
390 /* Structure to hold an entry in ARC_OPCODE_HASH. */
391 struct arc_opcode_hash_entry
393 /* The number of pointers in the OPCODE list. */
396 /* Points to a list of opcode pointers. */
397 const struct arc_opcode
**opcode
;
400 /* Structure used for iterating through an arc_opcode_hash_entry. */
401 struct arc_opcode_hash_entry_iterator
403 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
406 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
407 returned by this iterator. */
408 const struct arc_opcode
*opcode
;
411 /* Forward declaration. */
412 static void assemble_insn
413 (const struct arc_opcode
*, const expressionS
*, int,
414 const struct arc_flags
*, int, struct arc_insn
*);
416 /* The selection of the machine type can come from different sources. This
417 enum is used to track how the selection was made in order to perform
419 enum mach_selection_type
422 MACH_SELECTION_FROM_DEFAULT
,
423 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
424 MACH_SELECTION_FROM_COMMAND_LINE
427 /* How the current machine type was selected. */
428 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
430 /* The hash table of instruction opcodes. */
431 static htab_t arc_opcode_hash
;
433 /* The hash table of register symbols. */
434 static htab_t arc_reg_hash
;
436 /* The hash table of aux register symbols. */
437 static htab_t arc_aux_hash
;
439 /* The hash table of address types. */
440 static htab_t arc_addrtype_hash
;
442 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
444 E_ARC_MACH_ARC600, EXTRA}
445 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
447 E_ARC_MACH_ARC700, EXTRA}
448 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
449 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
450 EF_ARC_CPU_ARCV2EM, EXTRA}
451 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
452 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
453 EF_ARC_CPU_ARCV2HS, EXTRA}
454 #define ARC_CPU_TYPE_NONE \
457 /* A table of CPU names and opcode sets. */
458 static const struct cpu_type
468 #include "elf/arc-cpu.def"
471 /* Information about the cpu/variant we're assembling for. */
472 static struct cpu_type selected_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
474 /* TRUE if current assembly code uses RF16 only registers. */
475 static bfd_boolean rf16_only
= TRUE
;
478 static unsigned mpy_option
= 0;
481 static unsigned pic_option
= 0;
483 /* Use small data. */
484 static unsigned sda_option
= 0;
487 static unsigned tls_option
= 0;
489 /* Command line given features. */
490 static unsigned cl_features
= 0;
492 /* Used by the arc_reloc_op table. Order is important. */
493 #define O_gotoff O_md1 /* @gotoff relocation. */
494 #define O_gotpc O_md2 /* @gotpc relocation. */
495 #define O_plt O_md3 /* @plt relocation. */
496 #define O_sda O_md4 /* @sda relocation. */
497 #define O_pcl O_md5 /* @pcl relocation. */
498 #define O_tlsgd O_md6 /* @tlsgd relocation. */
499 #define O_tlsie O_md7 /* @tlsie relocation. */
500 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
501 #define O_tpoff O_md9 /* @tpoff relocation. */
502 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
503 #define O_dtpoff O_md11 /* @dtpoff relocation. */
504 #define O_last O_dtpoff
506 /* Used to define a bracket as operand in tokens. */
507 #define O_bracket O_md32
509 /* Used to define a colon as an operand in tokens. */
510 #define O_colon O_md31
512 /* Used to define address types in nps400. */
513 #define O_addrtype O_md30
515 /* Dummy relocation, to be sorted out. */
516 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
518 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
520 /* A table to map the spelling of a relocation operand into an appropriate
521 bfd_reloc_code_real_type type. The table is assumed to be ordered such
522 that op-O_literal indexes into it. */
523 #define ARC_RELOC_TABLE(op) \
524 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
526 : (int) (op) - (int) O_gotoff) ])
528 #define DEF(NAME, RELOC, REQ) \
529 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
531 static const struct arc_reloc_op_tag
533 /* String to lookup. */
535 /* Size of the string. */
537 /* Which operator to use. */
539 extended_bfd_reloc_code_real_type reloc
;
540 /* Allows complex relocation expression like identifier@reloc +
542 unsigned int complex_expr
: 1;
546 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
547 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
548 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
549 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
550 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
551 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
552 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
553 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
554 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
555 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
556 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
559 static const int arc_num_reloc_op
560 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
562 /* Structure for relaxable instruction that have to be swapped with a
563 smaller alternative instruction. */
564 struct arc_relaxable_ins
566 /* Mnemonic that should be checked. */
567 const char *mnemonic_r
;
569 /* Operands that should be checked.
570 Indexes of operands from operand array. */
571 enum rlx_operand_type operands
[6];
573 /* Flags that should be checked. */
574 unsigned flag_classes
[5];
576 /* Mnemonic (smaller) alternative to be used later for relaxation. */
577 const char *mnemonic_alt
;
579 /* Index of operand that generic relaxation has to check. */
582 /* Base subtype index used. */
583 enum arc_rlx_types subtype
;
586 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
587 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
588 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
592 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
593 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
594 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
599 /* ARC relaxation table. */
600 const relax_typeS md_relax_table
[] =
607 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
608 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
612 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
613 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
618 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
619 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
620 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
622 /* LD_S a, [b, u7] ->
623 LD<zz><.x><.aa><.di> a, [b, s9] ->
624 LD<zz><.x><.aa><.di> a, [b, limm] */
625 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
626 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
627 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
632 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
633 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
634 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
638 SUB<.f> a, b, limm. */
639 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
640 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
641 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
643 /* MPY<.f> a, b, u6 ->
644 MPY<.f> a, b, limm. */
645 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
646 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
648 /* MOV<.f><.cc> b, u6 ->
649 MOV<.f><.cc> b, limm. */
650 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
651 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
653 /* ADD<.f><.cc> b, b, u6 ->
654 ADD<.f><.cc> b, b, limm. */
655 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
656 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
659 /* Order of this table's entries matters! */
660 const struct arc_relaxable_ins arc_relaxable_insns
[] =
662 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
663 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
664 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
665 2, ARC_RLX_ADD_RRU6
},
666 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
668 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
670 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
671 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
672 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
673 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
674 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
675 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
676 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
677 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
679 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
681 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
685 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
687 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
688 symbolS
* GOT_symbol
= 0;
690 /* Set to TRUE when we assemble instructions. */
691 static bfd_boolean assembling_insn
= FALSE
;
693 /* List with attributes set explicitly. */
694 static bfd_boolean attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
696 /* Functions implementation. */
698 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
699 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
700 are no matching entries in ARC_OPCODE_HASH. */
702 static const struct arc_opcode_hash_entry
*
703 arc_find_opcode (const char *name
)
705 const struct arc_opcode_hash_entry
*entry
;
707 entry
= str_hash_find (arc_opcode_hash
, name
);
711 /* Initialise the iterator ITER. */
714 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
720 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
721 calls to this function. Return NULL when all ARC_OPCODE entries have
724 static const struct arc_opcode
*
725 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
726 struct arc_opcode_hash_entry_iterator
*iter
)
728 if (iter
->opcode
== NULL
&& iter
->index
== 0)
730 gas_assert (entry
->count
> 0);
731 iter
->opcode
= entry
->opcode
[iter
->index
];
733 else if (iter
->opcode
!= NULL
)
735 const char *old_name
= iter
->opcode
->name
;
738 if (iter
->opcode
->name
== NULL
739 || strcmp (old_name
, iter
->opcode
->name
) != 0)
742 if (iter
->index
== entry
->count
)
745 iter
->opcode
= entry
->opcode
[iter
->index
];
752 /* Insert an opcode into opcode hash structure. */
755 arc_insert_opcode (const struct arc_opcode
*opcode
)
758 struct arc_opcode_hash_entry
*entry
;
761 entry
= str_hash_find (arc_opcode_hash
, name
);
764 entry
= XNEW (struct arc_opcode_hash_entry
);
766 entry
->opcode
= NULL
;
768 if (str_hash_insert (arc_opcode_hash
, name
, entry
, 0) != NULL
)
769 as_fatal (_("duplicate %s"), name
);
772 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
775 entry
->opcode
[entry
->count
] = opcode
;
780 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
781 value, is encoded as 'middle-endian' for a little-endian target. This
782 function is used for regular 4, 6, and 8 byte instructions as well. */
785 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
790 md_number_to_chars (buf
, val
, n
);
793 md_number_to_chars (buf
, (val
& 0xffff00000000ull
) >> 32, 2);
794 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
797 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
798 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
801 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000ull
) >> 32, 4);
802 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
809 /* Check if a feature is allowed for a specific CPU. */
812 arc_check_feature (void)
816 if (!selected_cpu
.features
817 || !selected_cpu
.name
)
820 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
821 if ((selected_cpu
.features
& feature_list
[i
].feature
)
822 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
823 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
826 for (i
= 0; i
< ARRAY_SIZE (conflict_list
); i
++)
827 if ((selected_cpu
.features
& conflict_list
[i
]) == conflict_list
[i
])
828 as_bad(_("conflicting ISA extension attributes."));
831 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
832 the relevant static global variables. Parameter SEL describes where
833 this selection originated from. */
836 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
839 static struct cpu_type old_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
841 /* We should only set a default if we've not made a selection from some
843 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
844 || mach_selection_mode
== MACH_SELECTION_NONE
);
846 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
847 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
848 as_bad (_("Multiple .cpu directives found"));
850 /* Look for a matching entry in CPU_TYPES array. */
851 for (i
= 0; cpu_types
[i
].name
; ++i
)
853 if (!strcasecmp (cpu_types
[i
].name
, arg
))
855 /* If a previous selection was made on the command line, then we
856 allow later selections on the command line to override earlier
857 ones. However, a selection from a '.cpu NAME' directive must
858 match the command line selection, or we give a warning. */
859 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
861 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
862 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
863 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
864 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
866 as_warn (_("Command-line value overrides \".cpu\" directive"));
870 /* Initialise static global data about selected machine type. */
871 selected_cpu
.flags
= cpu_types
[i
].flags
;
872 selected_cpu
.name
= cpu_types
[i
].name
;
873 selected_cpu
.features
= cpu_types
[i
].features
| cl_features
;
874 selected_cpu
.mach
= cpu_types
[i
].mach
;
875 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_MACH_MSK
)
876 | cpu_types
[i
].eflags
);
881 if (!cpu_types
[i
].name
)
882 as_fatal (_("unknown architecture: %s\n"), arg
);
884 /* Check if set features are compatible with the chosen CPU. */
885 arc_check_feature ();
887 /* If we change the CPU, we need to re-init the bfd. */
888 if (mach_selection_mode
!= MACH_SELECTION_NONE
889 && (old_cpu
.mach
!= selected_cpu
.mach
))
891 bfd_find_target (arc_target_format
, stdoutput
);
892 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
893 as_warn (_("Could not set architecture and machine"));
896 mach_selection_mode
= sel
;
897 old_cpu
= selected_cpu
;
900 /* Here ends all the ARCompact extension instruction assembling
904 arc_extra_reloc (int r_type
)
907 symbolS
*sym
, *lab
= NULL
;
909 if (*input_line_pointer
== '@')
910 input_line_pointer
++;
911 c
= get_symbol_name (&sym_name
);
912 sym
= symbol_find_or_make (sym_name
);
913 restore_line_pointer (c
);
914 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
916 ++input_line_pointer
;
918 c
= get_symbol_name (&lab_name
);
919 lab
= symbol_find_or_make (lab_name
);
920 restore_line_pointer (c
);
923 /* These relocations exist as a mechanism for the compiler to tell the
924 linker how to patch the code if the tls model is optimised. However,
925 the relocation itself does not require any space within the assembler
926 fragment, and so we pass a size of 0.
928 The lines that generate these relocations look like this:
930 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
932 The '.tls_gd_ld @.tdata' is processed first and generates the
933 additional relocation, while the 'bl __tls_get_addr@plt' is processed
934 second and generates the additional branch.
936 It is possible that the additional relocation generated by the
937 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
938 while the 'bl __tls_get_addr@plt' will be generated as the first thing
939 in the next fragment. This will be fine; both relocations will still
940 appear to be at the same address in the generated object file.
941 However, this only works as the additional relocation is generated
942 with size of 0 bytes. */
944 = fix_new (frag_now
, /* Which frag? */
945 frag_now_fix (), /* Where in that frag? */
946 0, /* size: 1, 2, or 4 usually. */
947 sym
, /* X_add_symbol. */
948 0, /* X_add_number. */
949 FALSE
, /* TRUE if PC-relative relocation. */
950 r_type
/* Relocation type. */);
951 fixP
->fx_subsy
= lab
;
955 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
956 symbolS
*symbolP
, addressT size
)
961 if (*input_line_pointer
== ',')
963 align
= parse_align (1);
965 if (align
== (addressT
) -1)
980 bss_alloc (symbolP
, size
, align
);
981 S_CLEAR_EXTERNAL (symbolP
);
987 arc_lcomm (int ignore
)
989 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
992 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
995 /* Select the cpu we're assembling for. */
998 arc_option (int ignore ATTRIBUTE_UNUSED
)
1002 const char *cpu_name
;
1004 c
= get_symbol_name (&cpu
);
1007 if ((!strcmp ("ARC600", cpu
))
1008 || (!strcmp ("ARC601", cpu
))
1009 || (!strcmp ("A6", cpu
)))
1010 cpu_name
= "arc600";
1011 else if ((!strcmp ("ARC700", cpu
))
1012 || (!strcmp ("A7", cpu
)))
1013 cpu_name
= "arc700";
1014 else if (!strcmp ("EM", cpu
))
1016 else if (!strcmp ("HS", cpu
))
1018 else if (!strcmp ("NPS400", cpu
))
1019 cpu_name
= "nps400";
1021 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1023 restore_line_pointer (c
);
1024 demand_empty_rest_of_line ();
1027 /* Smartly print an expression. */
1030 debug_exp (expressionS
*t
)
1032 const char *name ATTRIBUTE_UNUSED
;
1033 const char *namemd ATTRIBUTE_UNUSED
;
1035 pr_debug ("debug_exp: ");
1039 default: name
= "unknown"; break;
1040 case O_illegal
: name
= "O_illegal"; break;
1041 case O_absent
: name
= "O_absent"; break;
1042 case O_constant
: name
= "O_constant"; break;
1043 case O_symbol
: name
= "O_symbol"; break;
1044 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1045 case O_register
: name
= "O_register"; break;
1046 case O_big
: name
= "O_big"; break;
1047 case O_uminus
: name
= "O_uminus"; break;
1048 case O_bit_not
: name
= "O_bit_not"; break;
1049 case O_logical_not
: name
= "O_logical_not"; break;
1050 case O_multiply
: name
= "O_multiply"; break;
1051 case O_divide
: name
= "O_divide"; break;
1052 case O_modulus
: name
= "O_modulus"; break;
1053 case O_left_shift
: name
= "O_left_shift"; break;
1054 case O_right_shift
: name
= "O_right_shift"; break;
1055 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1056 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1057 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1058 case O_bit_and
: name
= "O_bit_and"; break;
1059 case O_add
: name
= "O_add"; break;
1060 case O_subtract
: name
= "O_subtract"; break;
1061 case O_eq
: name
= "O_eq"; break;
1062 case O_ne
: name
= "O_ne"; break;
1063 case O_lt
: name
= "O_lt"; break;
1064 case O_le
: name
= "O_le"; break;
1065 case O_ge
: name
= "O_ge"; break;
1066 case O_gt
: name
= "O_gt"; break;
1067 case O_logical_and
: name
= "O_logical_and"; break;
1068 case O_logical_or
: name
= "O_logical_or"; break;
1069 case O_index
: name
= "O_index"; break;
1070 case O_bracket
: name
= "O_bracket"; break;
1071 case O_colon
: name
= "O_colon"; break;
1072 case O_addrtype
: name
= "O_addrtype"; break;
1077 default: namemd
= "unknown"; break;
1078 case O_gotoff
: namemd
= "O_gotoff"; break;
1079 case O_gotpc
: namemd
= "O_gotpc"; break;
1080 case O_plt
: namemd
= "O_plt"; break;
1081 case O_sda
: namemd
= "O_sda"; break;
1082 case O_pcl
: namemd
= "O_pcl"; break;
1083 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1084 case O_tlsie
: namemd
= "O_tlsie"; break;
1085 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1086 case O_tpoff
: namemd
= "O_tpoff"; break;
1087 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1088 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1091 pr_debug ("%s (%s, %s, %d, %s)", name
,
1092 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1093 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1094 (int) t
->X_add_number
,
1095 (t
->X_md
) ? namemd
: "--");
1100 /* Helper for parsing an argument, used for sorting out the relocation
1104 parse_reloc_symbol (expressionS
*resultP
)
1106 char *reloc_name
, c
, *sym_name
;
1109 const struct arc_reloc_op_tag
*r
;
1113 /* A relocation operand has the following form
1114 @identifier@relocation_type. The identifier is already in
1116 if (resultP
->X_op
!= O_symbol
)
1118 as_bad (_("No valid label relocation operand"));
1119 resultP
->X_op
= O_illegal
;
1123 /* Parse @relocation_type. */
1124 input_line_pointer
++;
1125 c
= get_symbol_name (&reloc_name
);
1126 len
= input_line_pointer
- reloc_name
;
1129 as_bad (_("No relocation operand"));
1130 resultP
->X_op
= O_illegal
;
1134 /* Go through known relocation and try to find a match. */
1135 r
= &arc_reloc_op
[0];
1136 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1137 if (len
== r
->length
1138 && memcmp (reloc_name
, r
->name
, len
) == 0)
1142 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1143 resultP
->X_op
= O_illegal
;
1147 *input_line_pointer
= c
;
1148 SKIP_WHITESPACE_AFTER_NAME ();
1149 /* Extra check for TLS: base. */
1150 if (*input_line_pointer
== '@')
1152 if (resultP
->X_op_symbol
!= NULL
1153 || resultP
->X_op
!= O_symbol
)
1155 as_bad (_("Unable to parse TLS base: %s"),
1156 input_line_pointer
);
1157 resultP
->X_op
= O_illegal
;
1160 input_line_pointer
++;
1161 c
= get_symbol_name (&sym_name
);
1162 base
= symbol_find_or_make (sym_name
);
1163 resultP
->X_op
= O_subtract
;
1164 resultP
->X_op_symbol
= base
;
1165 restore_line_pointer (c
);
1166 right
.X_add_number
= 0;
1169 if ((*input_line_pointer
!= '+')
1170 && (*input_line_pointer
!= '-'))
1171 right
.X_add_number
= 0;
1174 /* Parse the constant of a complex relocation expression
1175 like @identifier@reloc +/- const. */
1176 if (! r
->complex_expr
)
1178 as_bad (_("@%s is not a complex relocation."), r
->name
);
1179 resultP
->X_op
= O_illegal
;
1182 expression (&right
);
1183 if (right
.X_op
!= O_constant
)
1185 as_bad (_("Bad expression: @%s + %s."),
1186 r
->name
, input_line_pointer
);
1187 resultP
->X_op
= O_illegal
;
1192 resultP
->X_md
= r
->op
;
1193 resultP
->X_add_number
= right
.X_add_number
;
1196 /* Parse the arguments to an opcode. */
1199 tokenize_arguments (char *str
,
1203 char *old_input_line_pointer
;
1204 bfd_boolean saw_comma
= FALSE
;
1205 bfd_boolean saw_arg
= FALSE
;
1209 memset (tok
, 0, sizeof (*tok
) * ntok
);
1211 /* Save and restore input_line_pointer around this function. */
1212 old_input_line_pointer
= input_line_pointer
;
1213 input_line_pointer
= str
;
1215 while (*input_line_pointer
)
1218 switch (*input_line_pointer
)
1224 input_line_pointer
++;
1225 if (saw_comma
|| !saw_arg
)
1232 ++input_line_pointer
;
1234 if (!saw_arg
|| num_args
== ntok
)
1236 tok
->X_op
= O_bracket
;
1243 input_line_pointer
++;
1244 if (brk_lvl
|| num_args
== ntok
)
1247 tok
->X_op
= O_bracket
;
1253 input_line_pointer
++;
1254 if (!saw_arg
|| num_args
== ntok
)
1256 tok
->X_op
= O_colon
;
1263 /* We have labels, function names and relocations, all
1264 starting with @ symbol. Sort them out. */
1265 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1269 input_line_pointer
++;
1270 tok
->X_op
= O_symbol
;
1271 tok
->X_md
= O_absent
;
1274 if (*input_line_pointer
== '@')
1275 parse_reloc_symbol (tok
);
1279 if (tok
->X_op
== O_illegal
1280 || tok
->X_op
== O_absent
1281 || num_args
== ntok
)
1291 /* Can be a register. */
1292 ++input_line_pointer
;
1296 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1299 tok
->X_op
= O_absent
;
1300 tok
->X_md
= O_absent
;
1303 /* Legacy: There are cases when we have
1304 identifier@relocation_type, if it is the case parse the
1305 relocation type as well. */
1306 if (*input_line_pointer
== '@')
1307 parse_reloc_symbol (tok
);
1311 if (tok
->X_op
== O_illegal
1312 || tok
->X_op
== O_absent
1313 || num_args
== ntok
)
1325 if (saw_comma
|| brk_lvl
)
1327 input_line_pointer
= old_input_line_pointer
;
1333 as_bad (_("Brackets in operand field incorrect"));
1335 as_bad (_("extra comma"));
1337 as_bad (_("missing argument"));
1339 as_bad (_("missing comma or colon"));
1340 input_line_pointer
= old_input_line_pointer
;
1344 /* Parse the flags to a structure. */
1347 tokenize_flags (const char *str
,
1348 struct arc_flags flags
[],
1351 char *old_input_line_pointer
;
1352 bfd_boolean saw_flg
= FALSE
;
1353 bfd_boolean saw_dot
= FALSE
;
1357 memset (flags
, 0, sizeof (*flags
) * nflg
);
1359 /* Save and restore input_line_pointer around this function. */
1360 old_input_line_pointer
= input_line_pointer
;
1361 input_line_pointer
= (char *) str
;
1363 while (*input_line_pointer
)
1365 switch (*input_line_pointer
)
1372 input_line_pointer
++;
1380 if (saw_flg
&& !saw_dot
)
1383 if (num_flags
>= nflg
)
1386 flgnamelen
= strspn (input_line_pointer
,
1387 "abcdefghijklmnopqrstuvwxyz0123456789");
1388 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1391 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1393 input_line_pointer
+= flgnamelen
;
1403 input_line_pointer
= old_input_line_pointer
;
1408 as_bad (_("extra dot"));
1410 as_bad (_("unrecognized flag"));
1412 as_bad (_("failed to parse flags"));
1413 input_line_pointer
= old_input_line_pointer
;
1417 /* Apply the fixups in order. */
1420 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1424 for (i
= 0; i
< insn
->nfixups
; i
++)
1426 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1427 int size
, pcrel
, offset
= 0;
1429 /* FIXME! the reloc size is wrong in the BFD file.
1430 When it is fixed please delete me. */
1431 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1436 /* Some fixups are only used internally, thus no howto. */
1437 if ((int) fixup
->reloc
== 0)
1438 as_fatal (_("Unhandled reloc type"));
1440 if ((int) fixup
->reloc
< 0)
1442 /* FIXME! the reloc size is wrong in the BFD file.
1443 When it is fixed please enable me.
1444 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1445 pcrel
= fixup
->pcrel
;
1449 reloc_howto_type
*reloc_howto
=
1450 bfd_reloc_type_lookup (stdoutput
,
1451 (bfd_reloc_code_real_type
) fixup
->reloc
);
1452 gas_assert (reloc_howto
);
1454 /* FIXME! the reloc size is wrong in the BFD file.
1455 When it is fixed please enable me.
1456 size = bfd_get_reloc_size (reloc_howto); */
1457 pcrel
= reloc_howto
->pc_relative
;
1460 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1462 fragP
->fr_file
, fragP
->fr_line
,
1463 (fixup
->reloc
< 0) ? "Internal" :
1464 bfd_get_reloc_code_name (fixup
->reloc
),
1467 fix_new_exp (fragP
, fix
+ offset
,
1468 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1470 /* Check for ZOLs, and update symbol info if any. */
1471 if (LP_INSN (insn
->insn
))
1473 gas_assert (fixup
->exp
.X_add_symbol
);
1474 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1479 /* Actually output an instruction with its fixup. */
1482 emit_insn0 (struct arc_insn
*insn
, char *where
, bfd_boolean relax
)
1487 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1488 pr_debug ("\tLength : %d\n", insn
->len
);
1489 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1491 /* Write out the instruction. */
1492 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1494 f
= frag_more (total_len
);
1496 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1499 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1500 dwarf2_emit_insn (total_len
);
1503 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1507 emit_insn1 (struct arc_insn
*insn
)
1509 /* How frag_var's args are currently configured:
1510 - rs_machine_dependent, to dictate it's a relaxation frag.
1511 - FRAG_MAX_GROWTH, maximum size of instruction
1512 - 0, variable size that might grow...unused by generic relaxation.
1513 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1514 - s, opand expression.
1515 - 0, offset but it's unused.
1516 - 0, opcode but it's unused. */
1517 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1518 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1520 if (frag_room () < FRAG_MAX_GROWTH
)
1522 /* Handle differently when frag literal memory is exhausted.
1523 This is used because when there's not enough memory left in
1524 the current frag, a new frag is created and the information
1525 we put into frag_now->tc_frag_data is disregarded. */
1527 struct arc_relax_type relax_info_copy
;
1528 relax_substateT subtype
= frag_now
->fr_subtype
;
1530 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1531 sizeof (struct arc_relax_type
));
1533 frag_wane (frag_now
);
1534 frag_grow (FRAG_MAX_GROWTH
);
1536 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1537 sizeof (struct arc_relax_type
));
1539 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1543 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1544 frag_now
->fr_subtype
, s
, 0, 0);
1548 emit_insn (struct arc_insn
*insn
)
1553 emit_insn0 (insn
, NULL
, FALSE
);
1556 /* Check whether a symbol involves a register. */
1559 contains_register (symbolS
*sym
)
1563 expressionS
*ex
= symbol_get_value_expression (sym
);
1565 return ((O_register
== ex
->X_op
)
1566 && !contains_register (ex
->X_add_symbol
)
1567 && !contains_register (ex
->X_op_symbol
));
1573 /* Returns the register number within a symbol. */
1576 get_register (symbolS
*sym
)
1578 if (!contains_register (sym
))
1581 expressionS
*ex
= symbol_get_value_expression (sym
);
1582 return regno (ex
->X_add_number
);
1585 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1586 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1589 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1596 case BFD_RELOC_ARC_SDA_LDST
:
1597 case BFD_RELOC_ARC_SDA_LDST1
:
1598 case BFD_RELOC_ARC_SDA_LDST2
:
1599 case BFD_RELOC_ARC_SDA16_LD
:
1600 case BFD_RELOC_ARC_SDA16_LD1
:
1601 case BFD_RELOC_ARC_SDA16_LD2
:
1602 case BFD_RELOC_ARC_SDA16_ST2
:
1603 case BFD_RELOC_ARC_SDA32_ME
:
1610 /* Allocates a tok entry. */
1613 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1615 if (ntok
> MAX_INSN_ARGS
- 2)
1616 return 0; /* No space left. */
1619 return 0; /* Incorrect args. */
1621 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1624 return 1; /* Success. */
1625 return allocate_tok (tok
, ntok
- 1, cidx
);
1628 /* Check if an particular ARC feature is enabled. */
1631 check_cpu_feature (insn_subclass_t sc
)
1633 if (is_code_density_p (sc
) && !(selected_cpu
.features
& CD
))
1636 if (is_spfp_p (sc
) && !(selected_cpu
.features
& SPX
))
1639 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& DPX
))
1642 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& DPA
))
1645 if (is_nps400_p (sc
) && !(selected_cpu
.features
& NPS400
))
1651 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1652 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1653 array and returns TRUE if the flag operands all match, otherwise,
1654 returns FALSE, in which case the FIRST_PFLAG array may have been
1658 parse_opcode_flags (const struct arc_opcode
*opcode
,
1660 struct arc_flags
*first_pflag
)
1663 const unsigned char *flgidx
;
1666 for (i
= 0; i
< nflgs
; i
++)
1667 first_pflag
[i
].flgp
= NULL
;
1669 /* Check the flags. Iterate over the valid flag classes. */
1670 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1672 /* Get a valid flag class. */
1673 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1674 const unsigned *flgopridx
;
1676 struct arc_flags
*pflag
= NULL
;
1678 /* Check if opcode has implicit flag classes. */
1679 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
1682 /* Check for extension conditional codes. */
1683 if (ext_condcode
.arc_ext_condcode
1684 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1686 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1689 pflag
= first_pflag
;
1690 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1692 if (!strcmp (pf
->name
, pflag
->name
))
1694 if (pflag
->flgp
!= NULL
)
1707 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1709 const struct arc_flag_operand
*flg_operand
;
1711 pflag
= first_pflag
;
1712 flg_operand
= &arc_flag_operands
[*flgopridx
];
1713 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1715 /* Match against the parsed flags. */
1716 if (!strcmp (flg_operand
->name
, pflag
->name
))
1718 if (pflag
->flgp
!= NULL
)
1721 pflag
->flgp
= flg_operand
;
1723 break; /* goto next flag class and parsed flag. */
1728 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1730 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1734 /* Did I check all the parsed flags? */
1735 return lnflg
? FALSE
: TRUE
;
1739 /* Search forward through all variants of an opcode looking for a
1742 static const struct arc_opcode
*
1743 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1746 struct arc_flags
*first_pflag
,
1749 const char **errmsg
)
1751 const struct arc_opcode
*opcode
;
1752 struct arc_opcode_hash_entry_iterator iter
;
1754 int got_cpu_match
= 0;
1755 expressionS bktok
[MAX_INSN_ARGS
];
1756 int bkntok
, maxerridx
= 0;
1758 const char *tmpmsg
= NULL
;
1760 arc_opcode_hash_entry_iterator_init (&iter
);
1761 memset (&emptyE
, 0, sizeof (emptyE
));
1762 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1765 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1767 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1769 const unsigned char *opidx
;
1771 const expressionS
*t
= &emptyE
;
1773 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1774 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1776 /* Don't match opcodes that don't exist on this
1778 if (!(opcode
->cpu
& selected_cpu
.flags
))
1781 if (!check_cpu_feature (opcode
->subclass
))
1787 /* Check the operands. */
1788 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1790 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1792 /* Only take input from real operands. */
1793 if (ARC_OPERAND_IS_FAKE (operand
))
1796 /* When we expect input, make sure we have it. */
1800 /* Match operand type with expression type. */
1801 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1803 case ARC_OPERAND_ADDRTYPE
:
1807 /* Check to be an address type. */
1808 if (tok
[tokidx
].X_op
!= O_addrtype
)
1811 /* All address type operands need to have an insert
1812 method in order to check that we have the correct
1814 gas_assert (operand
->insert
!= NULL
);
1815 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1822 case ARC_OPERAND_IR
:
1823 /* Check to be a register. */
1824 if ((tok
[tokidx
].X_op
!= O_register
1825 || !is_ir_num (tok
[tokidx
].X_add_number
))
1826 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1829 /* If expect duplicate, make sure it is duplicate. */
1830 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1832 /* Check for duplicate. */
1833 if (t
->X_op
!= O_register
1834 || !is_ir_num (t
->X_add_number
)
1835 || (regno (t
->X_add_number
) !=
1836 regno (tok
[tokidx
].X_add_number
)))
1840 /* Special handling? */
1841 if (operand
->insert
)
1844 (*operand
->insert
)(0,
1845 regno (tok
[tokidx
].X_add_number
),
1849 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1851 /* Missing argument, create one. */
1852 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1855 tok
[tokidx
].X_op
= O_absent
;
1866 case ARC_OPERAND_BRAKET
:
1867 /* Check if bracket is also in opcode table as
1869 if (tok
[tokidx
].X_op
!= O_bracket
)
1873 case ARC_OPERAND_COLON
:
1874 /* Check if colon is also in opcode table as operand. */
1875 if (tok
[tokidx
].X_op
!= O_colon
)
1879 case ARC_OPERAND_LIMM
:
1880 case ARC_OPERAND_SIGNED
:
1881 case ARC_OPERAND_UNSIGNED
:
1882 switch (tok
[tokidx
].X_op
)
1890 /* Got an (too) early bracket, check if it is an
1891 ignored operand. N.B. This procedure works only
1892 when bracket is the last operand! */
1893 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1895 /* Insert the missing operand. */
1896 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1899 tok
[tokidx
].X_op
= O_absent
;
1907 const struct arc_aux_reg
*auxr
;
1909 if (opcode
->insn_class
!= AUXREG
)
1911 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1913 /* For compatibility reasons, an aux register can
1914 be spelled with upper or lower case
1917 for (pp
= tmpp
; *pp
; ++pp
) *pp
= TOLOWER (*pp
);
1919 auxr
= str_hash_find (arc_aux_hash
, tmpp
);
1922 /* We modify the token array here, safe in the
1923 knowledge, that if this was the wrong
1924 choice then the original contents will be
1925 restored from BKTOK. */
1926 tok
[tokidx
].X_op
= O_constant
;
1927 tok
[tokidx
].X_add_number
= auxr
->address
;
1928 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1932 if (tok
[tokidx
].X_op
!= O_constant
)
1937 /* Check the range. */
1938 if (operand
->bits
!= 32
1939 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1941 offsetT min
, max
, val
;
1942 val
= tok
[tokidx
].X_add_number
;
1944 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1946 max
= (1 << (operand
->bits
- 1)) - 1;
1947 min
= -(1 << (operand
->bits
- 1));
1951 max
= (1 << operand
->bits
) - 1;
1955 if (val
< min
|| val
> max
)
1957 tmpmsg
= _("immediate is out of bounds");
1961 /* Check alignments. */
1962 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1965 tmpmsg
= _("immediate is not 32bit aligned");
1969 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1972 tmpmsg
= _("immediate is not 16bit aligned");
1976 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1978 if (operand
->insert
)
1981 (*operand
->insert
)(0,
1982 tok
[tokidx
].X_add_number
,
1987 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1993 /* Check if it is register range. */
1994 if ((tok
[tokidx
].X_add_number
== 0)
1995 && contains_register (tok
[tokidx
].X_add_symbol
)
1996 && contains_register (tok
[tokidx
].X_op_symbol
))
2000 regs
= get_register (tok
[tokidx
].X_add_symbol
);
2002 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
2003 if (operand
->insert
)
2006 (*operand
->insert
)(0,
2019 if (operand
->default_reloc
== 0)
2020 goto match_failed
; /* The operand needs relocation. */
2022 /* Relocs requiring long immediate. FIXME! make it
2023 generic and move it to a function. */
2024 switch (tok
[tokidx
].X_md
)
2033 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
2037 if (!generic_reloc_p (operand
->default_reloc
))
2045 /* If expect duplicate, make sure it is duplicate. */
2046 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
2048 if (t
->X_op
== O_illegal
2049 || t
->X_op
== O_absent
2050 || t
->X_op
== O_register
2051 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2053 tmpmsg
= _("operand is not duplicate of the "
2062 /* Everything else should have been fake. */
2070 /* Setup ready for flag parsing. */
2071 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2073 tmpmsg
= _("flag mismatch");
2078 /* Possible match -- did we use all of our input? */
2085 tmpmsg
= _("too many arguments");
2089 /* Restore the original parameters. */
2090 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2092 if (tokidx
>= maxerridx
2101 *pcpumatch
= got_cpu_match
;
2106 /* Swap operand tokens. */
2109 swap_operand (expressionS
*operand_array
,
2111 unsigned destination
)
2113 expressionS cpy_operand
;
2114 expressionS
*src_operand
;
2115 expressionS
*dst_operand
;
2118 if (source
== destination
)
2121 src_operand
= &operand_array
[source
];
2122 dst_operand
= &operand_array
[destination
];
2123 size
= sizeof (expressionS
);
2125 /* Make copy of operand to swap with and swap. */
2126 memcpy (&cpy_operand
, dst_operand
, size
);
2127 memcpy (dst_operand
, src_operand
, size
);
2128 memcpy (src_operand
, &cpy_operand
, size
);
2131 /* Check if *op matches *tok type.
2132 Returns FALSE if they don't match, TRUE if they match. */
2135 pseudo_operand_match (const expressionS
*tok
,
2136 const struct arc_operand_operation
*op
)
2138 offsetT min
, max
, val
;
2140 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2146 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2148 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2150 val
= tok
->X_add_number
+ op
->count
;
2151 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2153 max
= (1 << (operand_real
->bits
- 1)) - 1;
2154 min
= -(1 << (operand_real
->bits
- 1));
2158 max
= (1 << operand_real
->bits
) - 1;
2161 if (min
<= val
&& val
<= max
)
2167 /* Handle all symbols as long immediates or signed 9. */
2168 if (operand_real
->flags
& ARC_OPERAND_LIMM
2169 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2170 && operand_real
->bits
== 9))
2175 if (operand_real
->flags
& ARC_OPERAND_IR
)
2180 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2191 /* Find pseudo instruction in array. */
2193 static const struct arc_pseudo_insn
*
2194 find_pseudo_insn (const char *opname
,
2196 const expressionS
*tok
)
2198 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2199 const struct arc_operand_operation
*op
;
2203 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2205 pseudo_insn
= &arc_pseudo_insns
[i
];
2206 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2208 op
= pseudo_insn
->operand
;
2209 for (j
= 0; j
< ntok
; ++j
)
2210 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2213 /* Found the right instruction. */
2221 /* Assumes the expressionS *tok is of sufficient size. */
2223 static const struct arc_opcode_hash_entry
*
2224 find_special_case_pseudo (const char *opname
,
2228 struct arc_flags
*pflags
)
2230 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2231 const struct arc_operand_operation
*operand_pseudo
;
2232 const struct arc_operand
*operand_real
;
2234 char construct_operand
[MAX_CONSTR_STR
];
2236 /* Find whether opname is in pseudo instruction array. */
2237 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2239 if (pseudo_insn
== NULL
)
2242 /* Handle flag, Limited to one flag at the moment. */
2243 if (pseudo_insn
->flag_r
!= NULL
)
2244 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2245 MAX_INSN_FLGS
- *nflgs
);
2247 /* Handle operand operations. */
2248 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2250 operand_pseudo
= &pseudo_insn
->operand
[i
];
2251 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2253 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2254 && !operand_pseudo
->needs_insert
)
2257 /* Has to be inserted (i.e. this token does not exist yet). */
2258 if (operand_pseudo
->needs_insert
)
2260 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2262 tok
[i
].X_op
= O_bracket
;
2267 /* Check if operand is a register or constant and handle it
2269 if (operand_real
->flags
& ARC_OPERAND_IR
)
2270 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2271 operand_pseudo
->count
);
2273 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2274 operand_pseudo
->count
);
2276 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2280 else if (operand_pseudo
->count
)
2282 /* Operand number has to be adjusted accordingly (by operand
2284 switch (tok
[i
].X_op
)
2287 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2300 /* Swap operands if necessary. Only supports one swap at the
2302 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2304 operand_pseudo
= &pseudo_insn
->operand
[i
];
2306 if (operand_pseudo
->swap_operand_idx
== i
)
2309 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2311 /* Prevent a swap back later by breaking out. */
2315 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2318 static const struct arc_opcode_hash_entry
*
2319 find_special_case_flag (const char *opname
,
2321 struct arc_flags
*pflags
)
2325 unsigned flag_idx
, flag_arr_idx
;
2326 size_t flaglen
, oplen
;
2327 const struct arc_flag_special
*arc_flag_special_opcode
;
2328 const struct arc_opcode_hash_entry
*entry
;
2330 /* Search for special case instruction. */
2331 for (i
= 0; i
< arc_num_flag_special
; i
++)
2333 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2334 oplen
= strlen (arc_flag_special_opcode
->name
);
2336 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2339 /* Found a potential special case instruction, now test for
2341 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2343 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2345 break; /* End of array, nothing found. */
2347 flagnm
= arc_flag_operands
[flag_idx
].name
;
2348 flaglen
= strlen (flagnm
);
2349 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2351 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2353 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2355 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2356 pflags
[*nflgs
].name
[flaglen
] = '\0';
2365 /* Used to find special case opcode. */
2367 static const struct arc_opcode_hash_entry
*
2368 find_special_case (const char *opname
,
2370 struct arc_flags
*pflags
,
2374 const struct arc_opcode_hash_entry
*entry
;
2376 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2379 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2384 /* Autodetect cpu attribute list. */
2387 autodetect_attributes (const struct arc_opcode
*opcode
,
2388 const expressionS
*tok
,
2396 } mpy_list
[] = {{ MPY1E
, 1 }, { MPY6E
, 6 }, { MPY7E
, 7 }, { MPY8E
, 8 },
2399 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
2400 if (opcode
->subclass
== feature_list
[i
].feature
)
2401 selected_cpu
.features
|= feature_list
[i
].feature
;
2403 for (i
= 0; i
< ARRAY_SIZE (mpy_list
); i
++)
2404 if (opcode
->subclass
== mpy_list
[i
].feature
)
2405 mpy_option
= mpy_list
[i
].encoding
;
2407 for (i
= 0; i
< (unsigned) ntok
; i
++)
2409 switch (tok
[i
].X_md
)
2431 switch (tok
[i
].X_op
)
2434 if ((tok
[i
].X_add_number
>= 4 && tok
[i
].X_add_number
<= 9)
2435 || (tok
[i
].X_add_number
>= 16 && tok
[i
].X_add_number
<= 25))
2444 /* Given an opcode name, pre-tockenized set of argumenst and the
2445 opcode flags, take it all the way through emission. */
2448 assemble_tokens (const char *opname
,
2451 struct arc_flags
*pflags
,
2454 bfd_boolean found_something
= FALSE
;
2455 const struct arc_opcode_hash_entry
*entry
;
2457 const char *errmsg
= NULL
;
2459 /* Search opcodes. */
2460 entry
= arc_find_opcode (opname
);
2462 /* Couldn't find opcode conventional way, try special cases. */
2464 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2468 const struct arc_opcode
*opcode
;
2470 pr_debug ("%s:%d: assemble_tokens: %s\n",
2471 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2472 found_something
= TRUE
;
2473 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2474 nflgs
, &cpumatch
, &errmsg
);
2477 struct arc_insn insn
;
2479 autodetect_attributes (opcode
, tok
, ntok
);
2480 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2486 if (found_something
)
2490 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2492 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2494 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2498 as_bad (_("unknown opcode '%s'"), opname
);
2501 /* The public interface to the instruction assembler. */
2504 md_assemble (char *str
)
2507 expressionS tok
[MAX_INSN_ARGS
];
2510 struct arc_flags flags
[MAX_INSN_FLGS
];
2512 /* Split off the opcode. */
2513 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2514 opname
= xmemdup0 (str
, opnamelen
);
2516 /* Signalize we are assembling the instructions. */
2517 assembling_insn
= TRUE
;
2519 /* Tokenize the flags. */
2520 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2522 as_bad (_("syntax error"));
2526 /* Scan up to the end of the mnemonic which must end in space or end
2529 for (; *str
!= '\0'; str
++)
2533 /* Tokenize the rest of the line. */
2534 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2536 as_bad (_("syntax error"));
2540 /* Finish it off. */
2541 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2542 assembling_insn
= FALSE
;
2545 /* Callback to insert a register into the hash table. */
2548 declare_register (const char *name
, int number
)
2550 symbolS
*regS
= symbol_create (name
, reg_section
,
2551 &zero_address_frag
, number
);
2553 if (str_hash_insert (arc_reg_hash
, S_GET_NAME (regS
), regS
, 0) != NULL
)
2554 as_fatal (_("duplicate %s"), name
);
2557 /* Construct symbols for each of the general registers. */
2560 declare_register_set (void)
2563 for (i
= 0; i
< 64; ++i
)
2567 sprintf (name
, "r%d", i
);
2568 declare_register (name
, i
);
2569 if ((i
& 0x01) == 0)
2571 sprintf (name
, "r%dr%d", i
, i
+1);
2572 declare_register (name
, i
);
2577 /* Construct a symbol for an address type. */
2580 declare_addrtype (const char *name
, int number
)
2582 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2583 &zero_address_frag
, number
);
2585 if (str_hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
), addrtypeS
, 0))
2586 as_fatal (_("duplicate %s"), name
);
2589 /* Port-specific assembler initialization. This function is called
2590 once, at assembler startup time. */
2595 const struct arc_opcode
*opcode
= arc_opcodes
;
2597 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2598 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2600 /* The endianness can be chosen "at the factory". */
2601 target_big_endian
= byte_order
== BIG_ENDIAN
;
2603 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2604 as_warn (_("could not set architecture and machine"));
2606 /* Set elf header flags. */
2607 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2609 /* Set up a hash table for the instructions. */
2610 arc_opcode_hash
= str_htab_create ();
2612 /* Initialize the hash table with the insns. */
2615 const char *name
= opcode
->name
;
2617 arc_insert_opcode (opcode
);
2619 while (++opcode
&& opcode
->name
2620 && (opcode
->name
== name
2621 || !strcmp (opcode
->name
, name
)))
2623 }while (opcode
->name
);
2625 /* Register declaration. */
2626 arc_reg_hash
= str_htab_create ();
2628 declare_register_set ();
2629 declare_register ("gp", 26);
2630 declare_register ("fp", 27);
2631 declare_register ("sp", 28);
2632 declare_register ("ilink", 29);
2633 declare_register ("ilink1", 29);
2634 declare_register ("ilink2", 30);
2635 declare_register ("blink", 31);
2637 /* XY memory registers. */
2638 declare_register ("x0_u0", 32);
2639 declare_register ("x0_u1", 33);
2640 declare_register ("x1_u0", 34);
2641 declare_register ("x1_u1", 35);
2642 declare_register ("x2_u0", 36);
2643 declare_register ("x2_u1", 37);
2644 declare_register ("x3_u0", 38);
2645 declare_register ("x3_u1", 39);
2646 declare_register ("y0_u0", 40);
2647 declare_register ("y0_u1", 41);
2648 declare_register ("y1_u0", 42);
2649 declare_register ("y1_u1", 43);
2650 declare_register ("y2_u0", 44);
2651 declare_register ("y2_u1", 45);
2652 declare_register ("y3_u0", 46);
2653 declare_register ("y3_u1", 47);
2654 declare_register ("x0_nu", 48);
2655 declare_register ("x1_nu", 49);
2656 declare_register ("x2_nu", 50);
2657 declare_register ("x3_nu", 51);
2658 declare_register ("y0_nu", 52);
2659 declare_register ("y1_nu", 53);
2660 declare_register ("y2_nu", 54);
2661 declare_register ("y3_nu", 55);
2663 declare_register ("mlo", 57);
2664 declare_register ("mmid", 58);
2665 declare_register ("mhi", 59);
2667 declare_register ("acc1", 56);
2668 declare_register ("acc2", 57);
2670 declare_register ("lp_count", 60);
2671 declare_register ("pcl", 63);
2673 /* Initialize the last instructions. */
2674 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2676 /* Aux register declaration. */
2677 arc_aux_hash
= str_htab_create ();
2679 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2681 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2683 if (!(auxr
->cpu
& selected_cpu
.flags
))
2686 if ((auxr
->subclass
!= NONE
)
2687 && !check_cpu_feature (auxr
->subclass
))
2690 if (str_hash_insert (arc_aux_hash
, auxr
->name
, auxr
, 0) != 0)
2691 as_fatal (_("duplicate %s"), auxr
->name
);
2694 /* Address type declaration. */
2695 arc_addrtype_hash
= str_htab_create ();
2697 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2698 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2699 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2700 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2701 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2702 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2703 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2704 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2705 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2706 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2707 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2708 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2709 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2710 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2711 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2712 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2715 /* Write a value out to the object file, using the appropriate
2719 md_number_to_chars (char *buf
,
2723 if (target_big_endian
)
2724 number_to_chars_bigendian (buf
, val
, n
);
2726 number_to_chars_littleendian (buf
, val
, n
);
2729 /* Round up a section size to the appropriate boundary. */
2732 md_section_align (segT segment
,
2735 int align
= bfd_section_alignment (segment
);
2737 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2740 /* The location from which a PC relative jump should be calculated,
2741 given a PC relative reloc. */
2744 md_pcrel_from_section (fixS
*fixP
,
2747 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2749 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2751 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2752 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2753 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2755 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2757 /* The symbol is undefined (or is defined but not in this section).
2758 Let the linker figure it out. */
2762 if ((int) fixP
->fx_r_type
< 0)
2764 /* These are the "internal" relocations. Align them to
2765 32 bit boundary (PCL), for the moment. */
2770 switch (fixP
->fx_r_type
)
2772 case BFD_RELOC_ARC_PC32
:
2773 /* The hardware calculates relative to the start of the
2774 insn, but this relocation is relative to location of the
2775 LIMM, compensate. The base always needs to be
2776 subtracted by 4 as we do not support this type of PCrel
2777 relocation for short instructions. */
2780 case BFD_RELOC_ARC_PLT32
:
2781 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2782 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2783 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2784 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2786 case BFD_RELOC_ARC_S21H_PCREL
:
2787 case BFD_RELOC_ARC_S25H_PCREL
:
2788 case BFD_RELOC_ARC_S13_PCREL
:
2789 case BFD_RELOC_ARC_S21W_PCREL
:
2790 case BFD_RELOC_ARC_S25W_PCREL
:
2794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2795 _("unhandled reloc %s in md_pcrel_from_section"),
2796 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2801 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2802 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2803 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2804 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2805 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2810 /* Given a BFD relocation find the corresponding operand. */
2812 static const struct arc_operand
*
2813 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2817 for (i
= 0; i
< arc_num_operands
; i
++)
2818 if (arc_operands
[i
].default_reloc
== reloc
)
2819 return &arc_operands
[i
];
2823 /* Insert an operand value into an instruction. */
2825 static unsigned long long
2826 insert_operand (unsigned long long insn
,
2827 const struct arc_operand
*operand
,
2832 offsetT min
= 0, max
= 0;
2834 if (operand
->bits
!= 32
2835 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2836 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2838 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2840 max
= (1 << (operand
->bits
- 1)) - 1;
2841 min
= -(1 << (operand
->bits
- 1));
2845 max
= (1 << operand
->bits
) - 1;
2849 if (val
< min
|| val
> max
)
2850 as_bad_value_out_of_range (_("operand"),
2851 val
, min
, max
, file
, line
);
2854 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2855 min
, val
, max
, insn
);
2857 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2859 as_bad_where (file
, line
,
2860 _("Unaligned operand. Needs to be 32bit aligned"));
2862 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2864 as_bad_where (file
, line
,
2865 _("Unaligned operand. Needs to be 16bit aligned"));
2867 if (operand
->insert
)
2869 const char *errmsg
= NULL
;
2871 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2873 as_warn_where (file
, line
, "%s", errmsg
);
2877 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2879 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2881 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2884 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2889 /* Apply a fixup to the object code. At this point all symbol values
2890 should be fully resolved, and we attempt to completely resolve the
2891 reloc. If we can not do that, we determine the correct reloc code
2892 and put it back in the fixup. To indicate that a fixup has been
2893 eliminated, set fixP->fx_done. */
2896 md_apply_fix (fixS
*fixP
,
2900 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2901 valueT value
= *valP
;
2903 symbolS
*fx_addsy
, *fx_subsy
;
2905 segT add_symbol_segment
= absolute_section
;
2906 segT sub_symbol_segment
= absolute_section
;
2907 const struct arc_operand
*operand
= NULL
;
2908 extended_bfd_reloc_code_real_type reloc
;
2910 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2911 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2912 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2913 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2916 fx_addsy
= fixP
->fx_addsy
;
2917 fx_subsy
= fixP
->fx_subsy
;
2922 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2926 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2927 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2928 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2930 resolve_symbol_value (fx_subsy
);
2931 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2933 if (sub_symbol_segment
== absolute_section
)
2935 /* The symbol is really a constant. */
2936 fx_offset
-= S_GET_VALUE (fx_subsy
);
2941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2942 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2943 fx_addsy
? S_GET_NAME (fx_addsy
) : "0",
2944 segment_name (add_symbol_segment
),
2945 S_GET_NAME (fx_subsy
),
2946 segment_name (sub_symbol_segment
));
2952 && !S_IS_WEAK (fx_addsy
))
2954 if (add_symbol_segment
== seg
2957 value
+= S_GET_VALUE (fx_addsy
);
2958 value
-= md_pcrel_from_section (fixP
, seg
);
2960 fixP
->fx_pcrel
= FALSE
;
2962 else if (add_symbol_segment
== absolute_section
)
2964 value
= fixP
->fx_offset
;
2965 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2967 fixP
->fx_pcrel
= FALSE
;
2972 fixP
->fx_done
= TRUE
;
2977 && ((S_IS_DEFINED (fx_addsy
)
2978 && S_GET_SEGMENT (fx_addsy
) != seg
)
2979 || S_IS_WEAK (fx_addsy
)))
2980 value
+= md_pcrel_from_section (fixP
, seg
);
2982 switch (fixP
->fx_r_type
)
2984 case BFD_RELOC_ARC_32_ME
:
2985 /* This is a pc-relative value in a LIMM. Adjust it to the
2986 address of the instruction not to the address of the
2987 LIMM. Note: it is not any longer valid this affirmation as
2988 the linker consider ARC_PC32 a fixup to entire 64 bit
2990 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
2993 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
2995 case BFD_RELOC_ARC_PC32
:
2996 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2999 if ((int) fixP
->fx_r_type
< 0)
3000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3001 _("PC relative relocation not allowed for (internal)"
3008 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
3009 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
3010 ((int) fixP
->fx_r_type
< 0) ? "Internal":
3011 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
3015 /* Now check for TLS relocations. */
3016 reloc
= fixP
->fx_r_type
;
3019 case BFD_RELOC_ARC_TLS_DTPOFF
:
3020 case BFD_RELOC_ARC_TLS_LE_32
:
3024 case BFD_RELOC_ARC_TLS_GD_GOT
:
3025 case BFD_RELOC_ARC_TLS_IE_GOT
:
3026 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3029 case BFD_RELOC_ARC_TLS_GD_LD
:
3030 gas_assert (!fixP
->fx_offset
);
3033 = (S_GET_VALUE (fixP
->fx_subsy
)
3034 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
3035 fixP
->fx_subsy
= NULL
;
3037 case BFD_RELOC_ARC_TLS_GD_CALL
:
3038 /* These two relocs are there just to allow ld to change the tls
3039 model for this symbol, by patching the code. The offset -
3040 and scale, if any - will be installed by the linker. */
3041 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3044 case BFD_RELOC_ARC_TLS_LE_S9
:
3045 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
3046 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3058 /* Adjust the value if we have a constant. */
3061 /* For hosts with longs bigger than 32-bits make sure that the top
3062 bits of a 32-bit negative value read in by the parser are set,
3063 so that the correct comparisons are made. */
3064 if (value
& 0x80000000)
3065 value
|= (-1UL << 31);
3067 reloc
= fixP
->fx_r_type
;
3075 case BFD_RELOC_ARC_32_PCREL
:
3076 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3079 case BFD_RELOC_ARC_GOTPC32
:
3080 /* I cannot fix an GOTPC relocation because I need to relax it
3081 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3082 as_bad (_("Unsupported operation on reloc"));
3085 case BFD_RELOC_ARC_TLS_DTPOFF
:
3086 case BFD_RELOC_ARC_TLS_LE_32
:
3087 gas_assert (!fixP
->fx_addsy
);
3088 gas_assert (!fixP
->fx_subsy
);
3091 case BFD_RELOC_ARC_GOTOFF
:
3092 case BFD_RELOC_ARC_32_ME
:
3093 case BFD_RELOC_ARC_PC32
:
3094 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3097 case BFD_RELOC_ARC_PLT32
:
3098 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3101 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3102 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3105 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3106 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3109 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3110 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3113 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3114 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3117 case BFD_RELOC_ARC_S25W_PCREL
:
3118 case BFD_RELOC_ARC_S21W_PCREL
:
3119 case BFD_RELOC_ARC_S21H_PCREL
:
3120 case BFD_RELOC_ARC_S25H_PCREL
:
3121 case BFD_RELOC_ARC_S13_PCREL
:
3123 operand
= find_operand_for_reloc (reloc
);
3124 gas_assert (operand
);
3129 if ((int) fixP
->fx_r_type
>= 0)
3130 as_fatal (_("unhandled relocation type %s"),
3131 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3133 /* The rest of these fixups needs to be completely resolved as
3135 if (fixP
->fx_addsy
!= 0
3136 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3138 _("non-absolute expression in constant field"));
3140 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3141 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3146 if (target_big_endian
)
3148 switch (fixP
->fx_size
)
3151 insn
= bfd_getb32 (fixpos
);
3154 insn
= bfd_getb16 (fixpos
);
3157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3158 _("unknown fixup size"));
3164 switch (fixP
->fx_size
)
3167 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3170 insn
= bfd_getl16 (fixpos
);
3173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3174 _("unknown fixup size"));
3178 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3179 fixP
->fx_file
, fixP
->fx_line
);
3181 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3184 /* Prepare machine-dependent frags for relaxation.
3186 Called just before relaxation starts. Any symbol that is now undefined
3187 will not become defined.
3189 Return the correct fr_subtype in the frag.
3191 Return the initial "guess for fr_var" to caller. The guess for fr_var
3192 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3193 or fr_var contributes to our returned value.
3195 Although it may not be explicit in the frag, pretend
3196 fr_var starts with a value. */
3199 md_estimate_size_before_relax (fragS
*fragP
,
3204 /* If the symbol is not located within the same section AND it's not
3205 an absolute section, use the maximum. OR if the symbol is a
3206 constant AND the insn is by nature not pc-rel, use the maximum.
3207 OR if the symbol is being equated against another symbol, use the
3208 maximum. OR if the symbol is weak use the maximum. */
3209 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3210 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3211 || (symbol_constant_p (fragP
->fr_symbol
)
3212 && !fragP
->tc_frag_data
.pcrel
)
3213 || symbol_equated_p (fragP
->fr_symbol
)
3214 || S_IS_WEAK (fragP
->fr_symbol
))
3216 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3217 ++fragP
->fr_subtype
;
3220 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3221 fragP
->fr_var
= growth
;
3223 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3224 fragP
->fr_file
, fragP
->fr_line
, growth
);
3229 /* Translate internal representation of relocation info to BFD target
3233 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3237 bfd_reloc_code_real_type code
;
3239 reloc
= XNEW (arelent
);
3240 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3241 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3242 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3244 /* Make sure none of our internal relocations make it this far.
3245 They'd better have been fully resolved by this point. */
3246 gas_assert ((int) fixP
->fx_r_type
> 0);
3248 code
= fixP
->fx_r_type
;
3250 /* if we have something like add gp, pcl,
3251 _GLOBAL_OFFSET_TABLE_@gotpc. */
3252 if (code
== BFD_RELOC_ARC_GOTPC32
3254 && fixP
->fx_addsy
== GOT_symbol
)
3255 code
= BFD_RELOC_ARC_GOTPC
;
3257 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3258 if (reloc
->howto
== NULL
)
3260 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3261 _("cannot represent `%s' relocation in object file"),
3262 bfd_get_reloc_code_name (code
));
3266 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3267 as_fatal (_("internal error? cannot generate `%s' relocation"),
3268 bfd_get_reloc_code_name (code
));
3270 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3272 reloc
->addend
= fixP
->fx_offset
;
3277 /* Perform post-processing of machine-dependent frags after relaxation.
3278 Called after relaxation is finished.
3279 In: Address of frag.
3280 fr_type == rs_machine_dependent.
3281 fr_subtype is what the address relaxed to.
3283 Out: Any fixS:s and constants are set up. */
3286 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3287 segT segment ATTRIBUTE_UNUSED
,
3290 const relax_typeS
*table_entry
;
3292 const struct arc_opcode
*opcode
;
3293 struct arc_insn insn
;
3295 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3297 fix
= fragP
->fr_fix
;
3298 dest
= fragP
->fr_literal
+ fix
;
3299 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3301 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3302 "var: %"BFD_VMA_FMT
"d\n",
3303 fragP
->fr_file
, fragP
->fr_line
,
3304 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3306 if (fragP
->fr_subtype
<= 0
3307 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3308 as_fatal (_("no relaxation found for this instruction."));
3310 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3312 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3313 relax_arg
->nflg
, &insn
);
3315 apply_fixups (&insn
, fragP
, fix
);
3317 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3318 gas_assert (table_entry
->rlx_length
== size
);
3319 emit_insn0 (&insn
, dest
, TRUE
);
3321 fragP
->fr_fix
+= table_entry
->rlx_length
;
3325 /* We have no need to default values of symbols. We could catch
3326 register names here, but that is handled by inserting them all in
3327 the symbol table to begin with. */
3330 md_undefined_symbol (char *name
)
3332 /* The arc abi demands that a GOT[0] should be referencible as
3333 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3334 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3336 && (*(name
+1) == 'G')
3337 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)))
3341 if (symbol_find (name
))
3342 as_bad ("GOT already in symbol table");
3344 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3345 &zero_address_frag
, 0);
3352 /* Turn a string in input_line_pointer into a floating point constant
3353 of type type, and store the appropriate bytes in *litP. The number
3354 of LITTLENUMS emitted is stored in *sizeP. An error message is
3355 returned, or NULL on OK. */
3358 md_atof (int type
, char *litP
, int *sizeP
)
3360 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3363 /* Called for any expression that can not be recognized. When the
3364 function is called, `input_line_pointer' will point to the start of
3365 the expression. We use it when we have complex operations like
3366 @label1 - @label2. */
3369 md_operand (expressionS
*expressionP
)
3371 char *p
= input_line_pointer
;
3374 input_line_pointer
++;
3375 expressionP
->X_op
= O_symbol
;
3376 expressionP
->X_md
= O_absent
;
3377 expression (expressionP
);
3381 /* This function is called from the function 'expression', it attempts
3382 to parse special names (in our case register names). It fills in
3383 the expression with the identified register. It returns TRUE if
3384 it is a register and FALSE otherwise. */
3387 arc_parse_name (const char *name
,
3388 struct expressionS
*e
)
3392 if (!assembling_insn
)
3395 if (e
->X_op
== O_symbol
3396 && e
->X_md
== O_absent
)
3399 sym
= str_hash_find (arc_reg_hash
, name
);
3402 e
->X_op
= O_register
;
3403 e
->X_add_number
= S_GET_VALUE (sym
);
3407 sym
= str_hash_find (arc_addrtype_hash
, name
);
3410 e
->X_op
= O_addrtype
;
3411 e
->X_add_number
= S_GET_VALUE (sym
);
3419 Invocation line includes a switch not recognized by the base assembler.
3420 See if it's a processor-specific option.
3422 New options (supported) are:
3424 -mcpu=<cpu name> Assemble for selected processor
3425 -EB/-mbig-endian Big-endian
3426 -EL/-mlittle-endian Little-endian
3427 -mrelax Enable relaxation
3429 The following CPU names are recognized:
3430 arc600, arc700, arcem, archs, nps400. */
3433 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3439 return md_parse_option (OPTION_MCPU
, "arc600");
3442 return md_parse_option (OPTION_MCPU
, "arc700");
3445 return md_parse_option (OPTION_MCPU
, "arcem");
3448 return md_parse_option (OPTION_MCPU
, "archs");
3452 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3457 arc_target_format
= "elf32-bigarc";
3458 byte_order
= BIG_ENDIAN
;
3462 arc_target_format
= "elf32-littlearc";
3463 byte_order
= LITTLE_ENDIAN
;
3467 selected_cpu
.features
|= CD
;
3469 arc_check_feature ();
3473 relaxation_state
= 1;
3477 selected_cpu
.features
|= NPS400
;
3478 cl_features
|= NPS400
;
3479 arc_check_feature ();
3483 selected_cpu
.features
|= SPX
;
3485 arc_check_feature ();
3489 selected_cpu
.features
|= DPX
;
3491 arc_check_feature ();
3495 selected_cpu
.features
|= DPA
;
3497 arc_check_feature ();
3500 /* Dummy options are accepted but have no effect. */
3501 case OPTION_USER_MODE
:
3502 case OPTION_LD_EXT_MASK
:
3505 case OPTION_BARREL_SHIFT
:
3506 case OPTION_MIN_MAX
:
3511 case OPTION_XMAC_D16
:
3512 case OPTION_XMAC_24
:
3513 case OPTION_DSP_PACKA
:
3516 case OPTION_TELEPHONY
:
3517 case OPTION_XYMEMORY
:
3530 /* Display the list of cpu names for use in the help text. */
3533 arc_show_cpu_list (FILE *stream
)
3536 static const char *space_buf
= " ";
3538 fprintf (stream
, "%s", space_buf
);
3539 offset
= strlen (space_buf
);
3540 for (i
= 0; cpu_types
[i
].name
!= NULL
; ++i
)
3542 bfd_boolean last
= (cpu_types
[i
+ 1].name
== NULL
);
3544 /* If displaying the new cpu name string, and the ', ' (for all
3545 but the last one) will take us past a target width of 80
3546 characters, then it's time for a new line. */
3547 if (offset
+ strlen (cpu_types
[i
].name
) + (last
? 0 : 2) > 80)
3549 fprintf (stream
, "\n%s", space_buf
);
3550 offset
= strlen (space_buf
);
3553 fprintf (stream
, "%s%s", cpu_types
[i
].name
, (last
? "\n" : ", "));
3554 offset
+= strlen (cpu_types
[i
].name
) + (last
? 0 : 2);
3559 md_show_usage (FILE *stream
)
3561 fprintf (stream
, _("ARC-specific assembler options:\n"));
3563 fprintf (stream
, " -mcpu=<cpu name>\t (default: %s), assemble for"
3564 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU
);
3565 arc_show_cpu_list (stream
);
3566 fprintf (stream
, "\n");
3567 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3568 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3569 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3570 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3572 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3573 fprintf (stream
, " -mspfp\t\t enable single-precision floating point"
3575 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point"
3577 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3578 "point\n\t\t\t instructions for ARC EM\n");
3581 " -mcode-density\t enable code density option for ARC EM\n");
3583 fprintf (stream
, _("\
3584 -EB assemble code for a big-endian cpu\n"));
3585 fprintf (stream
, _("\
3586 -EL assemble code for a little-endian cpu\n"));
3587 fprintf (stream
, _("\
3588 -mrelax enable relaxation\n"));
3590 fprintf (stream
, _("The following ARC-specific assembler options are "
3591 "deprecated and are accepted\nfor compatibility only:\n"));
3593 fprintf (stream
, _(" -mEA\n"
3594 " -mbarrel-shifter\n"
3595 " -mbarrel_shifter\n"
3600 " -mld-extension-reg-mask\n"
3616 " -muser-mode-only\n"
3620 /* Find the proper relocation for the given opcode. */
3622 static extended_bfd_reloc_code_real_type
3623 find_reloc (const char *name
,
3624 const char *opcodename
,
3625 const struct arc_flags
*pflags
,
3627 extended_bfd_reloc_code_real_type reloc
)
3631 bfd_boolean found_flag
, tmp
;
3632 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3634 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3636 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3638 /* Find the entry. */
3639 if (strcmp (name
, r
->name
))
3641 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3648 unsigned * psflg
= (unsigned *)r
->flags
;
3652 for (j
= 0; j
< nflg
; j
++)
3653 if (!strcmp (pflags
[j
].name
,
3654 arc_flag_operands
[*psflg
].name
))
3675 if (reloc
!= r
->oldreloc
)
3682 if (ret
== BFD_RELOC_UNUSED
)
3683 as_bad (_("Unable to find %s relocation for instruction %s"),
3688 /* All the symbol types that are allowed to be used for
3692 may_relax_expr (expressionS tok
)
3694 /* Check if we have unrelaxable relocs. */
3719 /* Checks if flags are in line with relaxable insn. */
3722 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3723 const struct arc_flags
*pflags
,
3726 unsigned flag_class
,
3731 const struct arc_flag_operand
*flag_opand
;
3732 int i
, counttrue
= 0;
3734 /* Iterate through flags classes. */
3735 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3737 /* Iterate through flags in flag class. */
3738 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3741 flag_opand
= &arc_flag_operands
[flag
];
3742 /* Iterate through flags in ins to compare. */
3743 for (i
= 0; i
< nflgs
; ++i
)
3745 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3756 /* If counttrue == nflgs, then all flags have been found. */
3757 return (counttrue
== nflgs
? TRUE
: FALSE
);
3760 /* Checks if operands are in line with relaxable insn. */
3763 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3764 const expressionS
*tok
,
3767 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3770 while (*operand
!= EMPTY
)
3772 const expressionS
*epr
= &tok
[i
];
3774 if (i
!= 0 && i
>= ntok
)
3780 if (!(epr
->X_op
== O_multiply
3781 || epr
->X_op
== O_divide
3782 || epr
->X_op
== O_modulus
3783 || epr
->X_op
== O_add
3784 || epr
->X_op
== O_subtract
3785 || epr
->X_op
== O_symbol
))
3791 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3795 if (epr
->X_op
!= O_register
)
3800 if (epr
->X_op
!= O_register
)
3803 switch (epr
->X_add_number
)
3805 case 0: case 1: case 2: case 3:
3806 case 12: case 13: case 14: case 15:
3813 case REGISTER_NO_GP
:
3814 if ((epr
->X_op
!= O_register
)
3815 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3820 if (epr
->X_op
!= O_bracket
)
3825 /* Don't understand, bail out. */
3831 operand
= &ins
->operands
[i
];
3834 return (i
== ntok
? TRUE
: FALSE
);
3837 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3840 relax_insn_p (const struct arc_opcode
*opcode
,
3841 const expressionS
*tok
,
3843 const struct arc_flags
*pflags
,
3847 bfd_boolean rv
= FALSE
;
3849 /* Check the relaxation table. */
3850 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3852 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3854 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3855 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3856 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3857 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3860 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3861 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3862 sizeof (expressionS
) * ntok
);
3863 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3864 sizeof (struct arc_flags
) * nflg
);
3865 frag_now
->tc_frag_data
.nflg
= nflg
;
3866 frag_now
->tc_frag_data
.ntok
= ntok
;
3874 /* Turn an opcode description and a set of arguments into
3875 an instruction and a fixup. */
3878 assemble_insn (const struct arc_opcode
*opcode
,
3879 const expressionS
*tok
,
3881 const struct arc_flags
*pflags
,
3883 struct arc_insn
*insn
)
3885 const expressionS
*reloc_exp
= NULL
;
3886 unsigned long long image
;
3887 const unsigned char *argidx
;
3890 unsigned char pcrel
= 0;
3891 bfd_boolean needGOTSymbol
;
3892 bfd_boolean has_delay_slot
= FALSE
;
3893 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3895 memset (insn
, 0, sizeof (*insn
));
3896 image
= opcode
->opcode
;
3898 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3899 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3902 /* Handle operands. */
3903 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3905 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3906 const expressionS
*t
= (const expressionS
*) 0;
3908 if (ARC_OPERAND_IS_FAKE (operand
))
3911 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3913 /* Duplicate operand, already inserted. */
3925 /* Regardless if we have a reloc or not mark the instruction
3926 limm if it is the case. */
3927 if (operand
->flags
& ARC_OPERAND_LIMM
)
3928 insn
->has_limm
= TRUE
;
3933 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3938 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3940 if (operand
->flags
& ARC_OPERAND_LIMM
)
3941 insn
->limm
= t
->X_add_number
;
3947 /* Ignore brackets, colons, and address types. */
3951 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3955 /* Maybe register range. */
3956 if ((t
->X_add_number
== 0)
3957 && contains_register (t
->X_add_symbol
)
3958 && contains_register (t
->X_op_symbol
))
3962 regs
= get_register (t
->X_add_symbol
);
3964 regs
|= get_register (t
->X_op_symbol
);
3965 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3971 /* This operand needs a relocation. */
3972 needGOTSymbol
= FALSE
;
3977 if (opcode
->insn_class
== JUMP
)
3978 as_bad (_("Unable to use @plt relocation for insn %s"),
3980 needGOTSymbol
= TRUE
;
3981 reloc
= find_reloc ("plt", opcode
->name
,
3983 operand
->default_reloc
);
3988 needGOTSymbol
= TRUE
;
3989 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3992 if (operand
->flags
& ARC_OPERAND_LIMM
)
3994 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
3995 if (arc_opcode_len (opcode
) == 2
3996 || opcode
->insn_class
== JUMP
)
3997 as_bad (_("Unable to use @pcl relocation for insn %s"),
4002 /* This is a relaxed operand which initially was
4003 limm, choose whatever we have defined in the
4005 reloc
= operand
->default_reloc
;
4009 reloc
= find_reloc ("sda", opcode
->name
,
4011 operand
->default_reloc
);
4015 needGOTSymbol
= TRUE
;
4020 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
4023 case O_tpoff9
: /*FIXME! Check for the conditionality of
4025 case O_dtpoff9
: /*FIXME! Check for the conditionality of
4027 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4031 /* Just consider the default relocation. */
4032 reloc
= operand
->default_reloc
;
4036 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
4037 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4044 /* sanity checks. */
4045 reloc_howto_type
*reloc_howto
4046 = bfd_reloc_type_lookup (stdoutput
,
4047 (bfd_reloc_code_real_type
) reloc
);
4048 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
4049 if (reloc_howto
->rightshift
)
4050 reloc_bitsize
-= reloc_howto
->rightshift
;
4051 if (reloc_bitsize
!= operand
->bits
)
4053 as_bad (_("invalid relocation %s for field"),
4054 bfd_get_reloc_code_name (reloc
));
4059 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4060 as_fatal (_("too many fixups"));
4062 struct arc_fixup
*fixup
;
4063 fixup
= &insn
->fixups
[insn
->nfixups
++];
4065 fixup
->reloc
= reloc
;
4066 if ((int) reloc
< 0)
4067 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
4070 reloc_howto_type
*reloc_howto
=
4071 bfd_reloc_type_lookup (stdoutput
,
4072 (bfd_reloc_code_real_type
) fixup
->reloc
);
4073 pcrel
= reloc_howto
->pc_relative
;
4075 fixup
->pcrel
= pcrel
;
4076 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) ?
4083 for (i
= 0; i
< nflg
; i
++)
4085 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
4087 /* Check if the instruction has a delay slot. */
4088 if (!strcmp (flg_operand
->name
, "d"))
4089 has_delay_slot
= TRUE
;
4091 /* There is an exceptional case when we cannot insert a flag just as
4092 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4093 relation with the relative address. Unfortunately, some of the
4094 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4095 handled in the normal way.
4097 Flag operands don't have an architecture field, so we can't
4098 directly validate that FLAG_OPERAND is valid for the current
4099 architecture, what we do instead is just validate that we're
4100 assembling for an ARCv2 architecture. */
4101 if ((selected_cpu
.flags
& ARC_OPCODE_ARCV2
)
4102 && (!strcmp (flg_operand
->name
, "t")
4103 || !strcmp (flg_operand
->name
, "nt")))
4105 unsigned bitYoperand
= 0;
4106 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4107 if (!strcmp (flg_operand
->name
, "t"))
4108 if (!strcmp (opcode
->name
, "bbit0")
4109 || !strcmp (opcode
->name
, "bbit1"))
4110 bitYoperand
= arc_NToperand
;
4112 bitYoperand
= arc_Toperand
;
4114 if (!strcmp (opcode
->name
, "bbit0")
4115 || !strcmp (opcode
->name
, "bbit1"))
4116 bitYoperand
= arc_Toperand
;
4118 bitYoperand
= arc_NToperand
;
4120 gas_assert (reloc_exp
!= NULL
);
4121 if (reloc_exp
->X_op
== O_constant
)
4123 /* Check if we have a constant and solved it
4125 offsetT val
= reloc_exp
->X_add_number
;
4126 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4131 struct arc_fixup
*fixup
;
4133 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4134 as_fatal (_("too many fixups"));
4136 fixup
= &insn
->fixups
[insn
->nfixups
++];
4137 fixup
->exp
= *reloc_exp
;
4138 fixup
->reloc
= -bitYoperand
;
4139 fixup
->pcrel
= pcrel
;
4140 fixup
->islong
= FALSE
;
4144 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4145 << flg_operand
->shift
;
4148 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4150 /* Instruction length. */
4151 insn
->len
= arc_opcode_len (opcode
);
4155 /* Update last insn status. */
4156 arc_last_insns
[1] = arc_last_insns
[0];
4157 arc_last_insns
[0].opcode
= opcode
;
4158 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4159 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4161 /* Check if the current instruction is legally used. */
4162 if (arc_last_insns
[1].has_delay_slot
4163 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4164 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4165 arc_last_insns
[1].opcode
->name
,
4166 arc_last_insns
[0].opcode
->name
);
4167 if (arc_last_insns
[1].has_delay_slot
4168 && arc_last_insns
[0].has_limm
)
4169 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4170 arc_last_insns
[1].opcode
->name
,
4171 arc_last_insns
[0].opcode
->name
);
4175 arc_handle_align (fragS
* fragP
)
4177 if ((fragP
)->fr_type
== rs_align_code
)
4179 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4180 valueT count
= ((fragP
)->fr_next
->fr_address
4181 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4183 (fragP
)->fr_var
= 2;
4185 if (count
& 1)/* Padding in the gap till the next 2-byte
4186 boundary with 0s. */
4191 /* Writing nop_s. */
4192 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4196 /* Here we decide which fixups can be adjusted to make them relative
4197 to the beginning of the section instead of the symbol. Basically
4198 we need to make sure that the dynamic relocations are done
4199 correctly, so in some cases we force the original symbol to be
4203 tc_arc_fix_adjustable (fixS
*fixP
)
4206 /* Prevent all adjustments to global symbols. */
4207 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4209 if (S_IS_WEAK (fixP
->fx_addsy
))
4212 /* Adjust_reloc_syms doesn't know about the GOT. */
4213 switch (fixP
->fx_r_type
)
4215 case BFD_RELOC_ARC_GOTPC32
:
4216 case BFD_RELOC_ARC_PLT32
:
4217 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4218 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4219 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4220 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4230 /* Compute the reloc type of an expression EXP. */
4233 arc_check_reloc (expressionS
*exp
,
4234 bfd_reloc_code_real_type
*r_type_p
)
4236 if (*r_type_p
== BFD_RELOC_32
4237 && exp
->X_op
== O_subtract
4238 && exp
->X_op_symbol
!= NULL
4239 && S_GET_SEGMENT (exp
->X_op_symbol
) == now_seg
)
4240 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4244 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4247 arc_cons_fix_new (fragS
*frag
,
4251 bfd_reloc_code_real_type r_type
)
4253 r_type
= BFD_RELOC_UNUSED
;
4258 r_type
= BFD_RELOC_8
;
4262 r_type
= BFD_RELOC_16
;
4266 r_type
= BFD_RELOC_24
;
4270 r_type
= BFD_RELOC_32
;
4271 arc_check_reloc (exp
, &r_type
);
4275 r_type
= BFD_RELOC_64
;
4279 as_bad (_("unsupported BFD relocation size %u"), size
);
4280 r_type
= BFD_RELOC_UNUSED
;
4283 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4286 /* The actual routine that checks the ZOL conditions. */
4289 check_zol (symbolS
*s
)
4291 switch (selected_cpu
.mach
)
4293 case bfd_mach_arc_arcv2
:
4294 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4297 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4298 || arc_last_insns
[1].has_delay_slot
)
4299 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4303 case bfd_mach_arc_arc600
:
4305 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4306 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4309 if (arc_last_insns
[0].has_limm
4310 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4311 as_bad (_("A jump instruction with long immediate detected at the \
4312 end of the ZOL label @%s"), S_GET_NAME (s
));
4315 case bfd_mach_arc_arc700
:
4316 if (arc_last_insns
[0].has_delay_slot
)
4317 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4326 /* If ZOL end check the last two instruction for illegals. */
4328 arc_frob_label (symbolS
* sym
)
4330 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4333 dwarf2_emit_label (sym
);
4336 /* Used because generic relaxation assumes a pc-rel value whilst we
4337 also relax instructions that use an absolute value resolved out of
4338 relative values (if that makes any sense). An example: 'add r1,
4339 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4340 but if they're in the same section we can subtract the section
4341 offset relocation which ends up in a resolved value. So if @.L2 is
4342 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4343 .text + 0x40 = 0x10. */
4345 arc_pcrel_adjust (fragS
*fragP
)
4347 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4348 fragP
->fr_address
, fragP
->fr_fix
,
4349 fragP
->tc_frag_data
.pcrel
? "Y" : "N");
4351 if (!fragP
->tc_frag_data
.pcrel
)
4352 return fragP
->fr_address
+ fragP
->fr_fix
;
4354 /* Take into account the PCL rounding. */
4355 return (fragP
->fr_address
+ fragP
->fr_fix
) & 0x03;
4358 /* Initialize the DWARF-2 unwind information for this procedure. */
4361 tc_arc_frame_initial_instructions (void)
4363 /* Stack pointer is register 28. */
4364 cfi_add_CFA_def_cfa (28, 0);
4368 tc_arc_regname_to_dw2regnum (char *regname
)
4372 sym
= str_hash_find (arc_reg_hash
, regname
);
4374 return S_GET_VALUE (sym
);
4379 /* Adjust the symbol table. Delete found AUX register symbols. */
4382 arc_adjust_symtab (void)
4386 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4388 /* I've created a symbol during parsing process. Now, remove
4389 the symbol as it is found to be an AUX register. */
4390 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4391 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4394 /* Now do generic ELF adjustments. */
4395 elf_adjust_symtab ();
4399 tokenize_extinsn (extInstruction_t
*einsn
)
4403 unsigned char major_opcode
;
4404 unsigned char sub_opcode
;
4405 unsigned char syntax_class
= 0;
4406 unsigned char syntax_class_modifiers
= 0;
4407 unsigned char suffix_class
= 0;
4412 /* 1st: get instruction name. */
4413 p
= input_line_pointer
;
4414 c
= get_symbol_name (&p
);
4416 insn_name
= xstrdup (p
);
4417 restore_line_pointer (c
);
4419 /* Convert to lower case. */
4420 for (p
= insn_name
; *p
; ++p
)
4423 /* 2nd: get major opcode. */
4424 if (*input_line_pointer
!= ',')
4426 as_bad (_("expected comma after instruction name"));
4427 ignore_rest_of_line ();
4430 input_line_pointer
++;
4431 major_opcode
= get_absolute_expression ();
4433 /* 3rd: get sub-opcode. */
4436 if (*input_line_pointer
!= ',')
4438 as_bad (_("expected comma after major opcode"));
4439 ignore_rest_of_line ();
4442 input_line_pointer
++;
4443 sub_opcode
= get_absolute_expression ();
4445 /* 4th: get suffix class. */
4448 if (*input_line_pointer
!= ',')
4450 as_bad ("expected comma after sub opcode");
4451 ignore_rest_of_line ();
4454 input_line_pointer
++;
4460 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4462 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4463 suffixclass
[i
].len
))
4465 suffix_class
|= suffixclass
[i
].attr_class
;
4466 input_line_pointer
+= suffixclass
[i
].len
;
4471 if (i
== ARRAY_SIZE (suffixclass
))
4473 as_bad ("invalid suffix class");
4474 ignore_rest_of_line ();
4480 if (*input_line_pointer
== '|')
4481 input_line_pointer
++;
4486 /* 5th: get syntax class and syntax class modifiers. */
4487 if (*input_line_pointer
!= ',')
4489 as_bad ("expected comma after suffix class");
4490 ignore_rest_of_line ();
4493 input_line_pointer
++;
4499 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4501 if (!strncmp (syntaxclassmod
[i
].name
,
4503 syntaxclassmod
[i
].len
))
4505 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4506 input_line_pointer
+= syntaxclassmod
[i
].len
;
4511 if (i
== ARRAY_SIZE (syntaxclassmod
))
4513 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4515 if (!strncmp (syntaxclass
[i
].name
,
4517 syntaxclass
[i
].len
))
4519 syntax_class
|= syntaxclass
[i
].attr_class
;
4520 input_line_pointer
+= syntaxclass
[i
].len
;
4525 if (i
== ARRAY_SIZE (syntaxclass
))
4527 as_bad ("missing syntax class");
4528 ignore_rest_of_line ();
4535 if (*input_line_pointer
== '|')
4536 input_line_pointer
++;
4541 demand_empty_rest_of_line ();
4543 einsn
->name
= insn_name
;
4544 einsn
->major
= major_opcode
;
4545 einsn
->minor
= sub_opcode
;
4546 einsn
->syntax
= syntax_class
;
4547 einsn
->modsyn
= syntax_class_modifiers
;
4548 einsn
->suffix
= suffix_class
;
4549 einsn
->flags
= syntax_class
4550 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4553 /* Generate an extension section. */
4556 arc_set_ext_seg (void)
4558 if (!arcext_section
)
4560 arcext_section
= subseg_new (".arcextmap", 0);
4561 bfd_set_section_flags (arcext_section
, SEC_READONLY
| SEC_HAS_CONTENTS
);
4564 subseg_set (arcext_section
, 0);
4568 /* Create an extension instruction description in the arc extension
4569 section of the output file.
4570 The structure for an instruction is like this:
4571 [0]: Length of the record.
4572 [1]: Type of the record.
4576 [4]: Syntax (flags).
4577 [5]+ Name instruction.
4579 The sequence is terminated by an empty entry. */
4582 create_extinst_section (extInstruction_t
*einsn
)
4585 segT old_sec
= now_seg
;
4586 int old_subsec
= now_subseg
;
4588 int name_len
= strlen (einsn
->name
);
4593 *p
= 5 + name_len
+ 1;
4595 *p
= EXT_INSTRUCTION
;
4602 p
= frag_more (name_len
+ 1);
4603 strcpy (p
, einsn
->name
);
4605 subseg_set (old_sec
, old_subsec
);
4608 /* Handler .extinstruction pseudo-op. */
4611 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4613 extInstruction_t einsn
;
4614 struct arc_opcode
*arc_ext_opcodes
;
4615 const char *errmsg
= NULL
;
4616 unsigned char moplow
, mophigh
;
4618 memset (&einsn
, 0, sizeof (einsn
));
4619 tokenize_extinsn (&einsn
);
4621 /* Check if the name is already used. */
4622 if (arc_find_opcode (einsn
.name
))
4623 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4625 /* Check the opcode ranges. */
4627 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4628 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4630 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4631 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4633 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4634 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4635 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4637 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4639 case ARC_SYNTAX_3OP
:
4640 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4641 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4643 case ARC_SYNTAX_2OP
:
4644 case ARC_SYNTAX_1OP
:
4645 case ARC_SYNTAX_NOP
:
4646 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4647 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4653 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4654 if (arc_ext_opcodes
== NULL
)
4657 as_fatal ("%s", errmsg
);
4659 as_fatal (_("Couldn't generate extension instruction opcodes"));
4662 as_warn ("%s", errmsg
);
4664 /* Insert the extension instruction. */
4665 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4667 create_extinst_section (&einsn
);
4671 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4677 int number
, imode
= 0;
4678 bfd_boolean isCore_p
= (opertype
== EXT_CORE_REGISTER
) ? TRUE
: FALSE
;
4679 bfd_boolean isReg_p
= (opertype
== EXT_CORE_REGISTER
4680 || opertype
== EXT_AUX_REGISTER
) ? TRUE
: FALSE
;
4682 /* 1st: get register name. */
4684 p
= input_line_pointer
;
4685 c
= get_symbol_name (&p
);
4688 restore_line_pointer (c
);
4690 /* 2nd: get register number. */
4693 if (*input_line_pointer
!= ',')
4695 as_bad (_("expected comma after name"));
4696 ignore_rest_of_line ();
4700 input_line_pointer
++;
4701 number
= get_absolute_expression ();
4704 && (opertype
!= EXT_AUX_REGISTER
))
4706 as_bad (_("%s second argument cannot be a negative number %d"),
4707 isCore_p
? "extCoreRegister's" : "extCondCode's",
4709 ignore_rest_of_line ();
4716 /* 3rd: get register mode. */
4719 if (*input_line_pointer
!= ',')
4721 as_bad (_("expected comma after register number"));
4722 ignore_rest_of_line ();
4727 input_line_pointer
++;
4728 mode
= input_line_pointer
;
4730 if (!strncmp (mode
, "r|w", 3))
4733 input_line_pointer
+= 3;
4735 else if (!strncmp (mode
, "r", 1))
4737 imode
= ARC_REGISTER_READONLY
;
4738 input_line_pointer
+= 1;
4740 else if (strncmp (mode
, "w", 1))
4742 as_bad (_("invalid mode"));
4743 ignore_rest_of_line ();
4749 imode
= ARC_REGISTER_WRITEONLY
;
4750 input_line_pointer
+= 1;
4756 /* 4th: get core register shortcut. */
4758 if (*input_line_pointer
!= ',')
4760 as_bad (_("expected comma after register mode"));
4761 ignore_rest_of_line ();
4766 input_line_pointer
++;
4768 if (!strncmp (input_line_pointer
, "cannot_shortcut", 15))
4770 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4771 input_line_pointer
+= 15;
4773 else if (strncmp (input_line_pointer
, "can_shortcut", 12))
4775 as_bad (_("shortcut designator invalid"));
4776 ignore_rest_of_line ();
4782 input_line_pointer
+= 12;
4785 demand_empty_rest_of_line ();
4788 ereg
->number
= number
;
4789 ereg
->imode
= imode
;
4793 /* Create an extension register/condition description in the arc
4794 extension section of the output file.
4796 The structure for an instruction is like this:
4797 [0]: Length of the record.
4798 [1]: Type of the record.
4800 For core regs and condition codes:
4804 For auxiliary registers:
4808 The sequence is terminated by an empty entry. */
4811 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4813 segT old_sec
= now_seg
;
4814 int old_subsec
= now_subseg
;
4816 int name_len
= strlen (ereg
->name
);
4823 case EXT_CORE_REGISTER
:
4825 *p
= 3 + name_len
+ 1;
4831 case EXT_AUX_REGISTER
:
4833 *p
= 6 + name_len
+ 1;
4835 *p
= EXT_AUX_REGISTER
;
4837 *p
= (ereg
->number
>> 24) & 0xff;
4839 *p
= (ereg
->number
>> 16) & 0xff;
4841 *p
= (ereg
->number
>> 8) & 0xff;
4843 *p
= (ereg
->number
) & 0xff;
4849 p
= frag_more (name_len
+ 1);
4850 strcpy (p
, ereg
->name
);
4852 subseg_set (old_sec
, old_subsec
);
4855 /* Handler .extCoreRegister pseudo-op. */
4858 arc_extcorereg (int opertype
)
4861 struct arc_aux_reg
*auxr
;
4862 struct arc_flag_operand
*ccode
;
4864 memset (&ereg
, 0, sizeof (ereg
));
4865 if (!tokenize_extregister (&ereg
, opertype
))
4870 case EXT_CORE_REGISTER
:
4871 /* Core register. */
4872 if (ereg
.number
> 60)
4873 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4875 declare_register (ereg
.name
, ereg
.number
);
4877 case EXT_AUX_REGISTER
:
4878 /* Auxiliary register. */
4879 auxr
= XNEW (struct arc_aux_reg
);
4880 auxr
->name
= ereg
.name
;
4881 auxr
->cpu
= selected_cpu
.flags
;
4882 auxr
->subclass
= NONE
;
4883 auxr
->address
= ereg
.number
;
4884 if (str_hash_insert (arc_aux_hash
, auxr
->name
, auxr
, 0) != NULL
)
4885 as_bad (_("duplicate aux register %s"), auxr
->name
);
4888 /* Condition code. */
4889 if (ereg
.number
> 31)
4890 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4892 ext_condcode
.size
++;
4893 ext_condcode
.arc_ext_condcode
=
4894 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4895 ext_condcode
.size
+ 1);
4897 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4898 ccode
->name
= ereg
.name
;
4899 ccode
->code
= ereg
.number
;
4902 ccode
->favail
= 0; /* not used. */
4904 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4907 as_bad (_("Unknown extension"));
4910 create_extcore_section (&ereg
, opertype
);
4913 /* Parse a .arc_attribute directive. */
4916 arc_attribute (int ignored ATTRIBUTE_UNUSED
)
4918 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4920 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4921 attributes_set_explicitly
[tag
] = TRUE
;
4924 /* Set an attribute if it has not already been set by the user. */
4927 arc_set_attribute_int (int tag
, int value
)
4930 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4931 || !attributes_set_explicitly
[tag
])
4932 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
4936 arc_set_attribute_string (int tag
, const char *value
)
4939 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4940 || !attributes_set_explicitly
[tag
])
4941 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
4944 /* Allocate and concatenate two strings. s1 can be NULL but not
4945 s2. s1 pointer is freed at end of this procedure. */
4948 arc_stralloc (char * s1
, const char * s2
)
4954 len
= strlen (s1
) + 1;
4956 /* Only s1 can be null. */
4958 len
+= strlen (s2
) + 1;
4960 p
= (char *) xmalloc (len
);
4975 /* Set the public ARC object attributes. */
4978 arc_set_public_attributes (void)
4984 /* Tag_ARC_CPU_name. */
4985 arc_set_attribute_string (Tag_ARC_CPU_name
, selected_cpu
.name
);
4987 /* Tag_ARC_CPU_base. */
4988 switch (selected_cpu
.eflags
& EF_ARC_MACH_MSK
)
4990 case E_ARC_MACH_ARC600
:
4991 case E_ARC_MACH_ARC601
:
4992 base
= TAG_CPU_ARC6xx
;
4994 case E_ARC_MACH_ARC700
:
4995 base
= TAG_CPU_ARC7xx
;
4997 case EF_ARC_CPU_ARCV2EM
:
4998 base
= TAG_CPU_ARCEM
;
5000 case EF_ARC_CPU_ARCV2HS
:
5001 base
= TAG_CPU_ARCHS
;
5007 if (attributes_set_explicitly
[Tag_ARC_CPU_base
]
5008 && (base
!= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5010 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5011 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_CPU_base
, base
);
5013 /* Tag_ARC_ABI_osver. */
5014 if (attributes_set_explicitly
[Tag_ARC_ABI_osver
])
5016 int val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5019 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_OSABI_MSK
)
5020 | (val
& 0x0f << 8));
5024 arc_set_attribute_int (Tag_ARC_ABI_osver
, E_ARC_OSABI_CURRENT
>> 8);
5027 /* Tag_ARC_ISA_config. */
5028 arc_check_feature();
5030 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
5031 if (selected_cpu
.features
& feature_list
[i
].feature
)
5032 s
= arc_stralloc (s
, feature_list
[i
].attr
);
5035 arc_set_attribute_string (Tag_ARC_ISA_config
, s
);
5037 /* Tag_ARC_ISA_mpy_option. */
5038 arc_set_attribute_int (Tag_ARC_ISA_mpy_option
, mpy_option
);
5040 /* Tag_ARC_ABI_pic. */
5041 arc_set_attribute_int (Tag_ARC_ABI_pic
, pic_option
);
5043 /* Tag_ARC_ABI_sda. */
5044 arc_set_attribute_int (Tag_ARC_ABI_sda
, sda_option
);
5046 /* Tag_ARC_ABI_tls. */
5047 arc_set_attribute_int (Tag_ARC_ABI_tls
, tls_option
);
5049 /* Tag_ARC_ATR_version. */
5050 arc_set_attribute_int (Tag_ARC_ATR_version
, 1);
5052 /* Tag_ARC_ABI_rf16. */
5053 if (attributes_set_explicitly
[Tag_ARC_ABI_rf16
]
5054 && bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5058 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5060 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_ABI_rf16
, 0);
5064 /* Add the default contents for the .ARC.attributes section. */
5069 arc_set_public_attributes ();
5071 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
5072 as_fatal (_("could not set architecture and machine"));
5074 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
5077 void arc_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
5079 ARC_GET_FLAG (dest
) = ARC_GET_FLAG (src
);
5082 int arc_convert_symbolic_attribute (const char *name
)
5091 #define T(tag) {#tag, tag}
5092 T (Tag_ARC_PCS_config
),
5093 T (Tag_ARC_CPU_base
),
5094 T (Tag_ARC_CPU_variation
),
5095 T (Tag_ARC_CPU_name
),
5096 T (Tag_ARC_ABI_rf16
),
5097 T (Tag_ARC_ABI_osver
),
5098 T (Tag_ARC_ABI_sda
),
5099 T (Tag_ARC_ABI_pic
),
5100 T (Tag_ARC_ABI_tls
),
5101 T (Tag_ARC_ABI_enumsize
),
5102 T (Tag_ARC_ABI_exceptions
),
5103 T (Tag_ARC_ABI_double_size
),
5104 T (Tag_ARC_ISA_config
),
5105 T (Tag_ARC_ISA_apex
),
5106 T (Tag_ARC_ISA_mpy_option
),
5107 T (Tag_ARC_ATR_version
)
5115 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
5116 if (streq (name
, attribute_table
[i
].name
))
5117 return attribute_table
[i
].tag
;
5123 eval: (c-set-style "gnu")