1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 FLOAT_ABI_DEFAULT
= -1,
101 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
103 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
104 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
106 static unsigned elf_flags
= 0;
108 /* Set the default_isa_spec. Return 0 if the input spec string isn't
109 supported. Otherwise, return 1. */
112 riscv_set_default_isa_spec (const char *s
)
114 enum riscv_isa_spec_class
class;
115 if (!riscv_get_isa_spec_class (s
, &class))
117 as_bad ("Unknown default ISA spec `%s' set by "
118 "-misa-spec or --with-isa-spec", s
);
122 default_isa_spec
= class;
126 /* Set the default_priv_spec, assembler will find the suitable CSR address
127 according to default_priv_spec. We will try to check priv attributes if
128 the input string is NULL. Return 0 if the input priv spec string isn't
129 supported. Otherwise, return 1. */
132 riscv_set_default_priv_spec (const char *s
)
134 enum riscv_priv_spec_class
class;
135 unsigned major
, minor
, revision
;
138 /* Find the corresponding priv spec class. */
139 if (riscv_get_priv_spec_class (s
, &class))
141 default_priv_spec
= class;
147 as_bad (_("Unknown default privilege spec `%s' set by "
148 "-mpriv-spec or --with-priv-spec"), s
);
152 /* Try to set the default_priv_spec according to the priv attributes. */
153 attr
= elf_known_obj_attributes_proc (stdoutput
);
154 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
155 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
156 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
158 if (riscv_get_priv_spec_class_from_numbers (major
,
163 /* The priv attributes setting 0.0.0 is meaningless. We should have set
164 the default_priv_spec by md_parse_option and riscv_after_parse_args,
165 so just skip the following setting. */
166 if (class == PRIV_SPEC_CLASS_NONE
)
169 default_priv_spec
= class;
173 /* Still can not find the priv spec class. */
174 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
175 "privilege attributes"), major
, minor
, revision
);
179 /* This is the set of options which the .option pseudo-op may modify. */
181 struct riscv_set_options
183 int pic
; /* Generate position-independent code. */
184 int rvc
; /* Generate RVC code. */
185 int rve
; /* Generate RVE code. */
186 int relax
; /* Emit relocs the linker is allowed to relax. */
187 int arch_attr
; /* Emit arch attribute. */
188 int csr_check
; /* Enable the CSR checking. */
191 static struct riscv_set_options riscv_opts
=
197 DEFAULT_RISCV_ATTR
, /* arch_attr */
202 riscv_set_rvc (bfd_boolean rvc_value
)
205 elf_flags
|= EF_RISCV_RVC
;
207 riscv_opts
.rvc
= rvc_value
;
211 riscv_set_rve (bfd_boolean rve_value
)
213 riscv_opts
.rve
= rve_value
;
216 static riscv_subset_list_t riscv_subsets
;
219 riscv_subset_supports (const char *feature
)
221 struct riscv_subset_t
*subset
;
223 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
226 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
230 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
234 case INSN_CLASS_I
: return riscv_subset_supports ("i");
235 case INSN_CLASS_C
: return riscv_subset_supports ("c");
236 case INSN_CLASS_A
: return riscv_subset_supports ("a");
237 case INSN_CLASS_M
: return riscv_subset_supports ("m");
238 case INSN_CLASS_F
: return riscv_subset_supports ("f");
239 case INSN_CLASS_D
: return riscv_subset_supports ("d");
240 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
242 case INSN_CLASS_F_AND_C
:
243 return (riscv_subset_supports ("f")
244 && riscv_subset_supports ("c"));
245 case INSN_CLASS_D_AND_C
:
246 return (riscv_subset_supports ("d")
247 && riscv_subset_supports ("c"));
249 case INSN_CLASS_ZICSR
:
250 return riscv_subset_supports ("zicsr");
251 case INSN_CLASS_ZIFENCEI
:
252 return riscv_subset_supports ("zifencei");
255 as_fatal ("Unreachable");
260 /* Handle of the extension with version hash table. */
261 static htab_t ext_version_hash
= NULL
;
264 init_ext_version_hash (const struct riscv_ext_version
*table
)
267 htab_t hash
= str_htab_create ();
269 while (table
[i
].name
)
271 const char *name
= table
[i
].name
;
272 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
273 as_fatal (_("duplicate %s"), name
);
277 && strcmp (table
[i
].name
, name
) == 0)
285 riscv_get_default_ext_version (const char *name
,
289 struct riscv_ext_version
*ext
;
291 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
294 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
297 && strcmp (ext
->name
, name
) == 0)
299 if (ext
->isa_spec_class
== default_isa_spec
)
301 *major_version
= ext
->major_version
;
302 *minor_version
= ext
->minor_version
;
309 /* Set which ISA and extensions are available. */
312 riscv_set_arch (const char *s
)
314 riscv_parse_subset_t rps
;
315 rps
.subset_list
= &riscv_subsets
;
316 rps
.error_handler
= as_bad
;
318 rps
.get_default_version
= riscv_get_default_ext_version
;
323 riscv_release_subset_list (&riscv_subsets
);
324 riscv_parse_subset (&rps
, s
);
327 /* Indicate -mabi= option is explictly set. */
328 static bfd_boolean explicit_mabi
= FALSE
;
331 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
334 float_abi
= new_float_abi
;
338 /* If the -mabi option isn't set, then we set the abi according to the arch
339 string. Otherwise, check if there are conflicts between architecture
343 riscv_set_abi_by_arch (void)
347 if (riscv_subset_supports ("q"))
348 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, FALSE
);
349 else if (riscv_subset_supports ("d"))
350 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, FALSE
);
352 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, FALSE
);
356 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
358 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
359 else if (abi_xlen
< xlen
)
360 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
363 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
364 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
365 elf_flags
|= float_abi
<< 1;
368 elf_flags
|= EF_RISCV_RVE
;
371 /* Handle of the OPCODE hash table. */
372 static htab_t op_hash
= NULL
;
374 /* Handle of the type of .insn hash table. */
375 static htab_t insn_type_hash
= NULL
;
377 /* This array holds the chars that always start a comment. If the
378 pre-processor is disabled, these aren't very useful */
379 const char comment_chars
[] = "#";
381 /* This array holds the chars that only start a comment at the beginning of
382 a line. If the line seems to have the form '# 123 filename'
383 .line and .file directives will appear in the pre-processed output */
384 /* Note that input_file.c hand checks for '#' at the beginning of the
385 first line of the input file. This is because the compiler outputs
386 #NO_APP at the beginning of its output. */
387 /* Also note that C style comments are always supported. */
388 const char line_comment_chars
[] = "#";
390 /* This array holds machine specific line separator characters. */
391 const char line_separator_chars
[] = ";";
393 /* Chars that can be used to separate mant from exp in floating point nums */
394 const char EXP_CHARS
[] = "eE";
396 /* Chars that mean this number is a floating point constant */
399 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
401 /* Indicate we are already assemble any instructions or not. */
402 static bfd_boolean start_assemble
= FALSE
;
404 /* Indicate ELF attributes are explictly set. */
405 static bfd_boolean explicit_attr
= FALSE
;
407 /* Indicate CSR or priv instructions are explictly used. */
408 static bfd_boolean explicit_priv_attr
= FALSE
;
410 /* Macros for encoding relaxation state for RVC branches and far jumps. */
411 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
414 | ((uncond) ? 1 : 0) \
417 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
418 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
419 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
420 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
422 /* Is the given value a sign-extended 32-bit value? */
423 #define IS_SEXT_32BIT_NUM(x) \
424 (((x) &~ (offsetT) 0x7fffffff) == 0 \
425 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
427 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
428 #define IS_ZEXT_32BIT_NUM(x) \
429 (((x) &~ (offsetT) 0xffffffff) == 0 \
430 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
432 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
433 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
434 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
435 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
437 /* Determine if an instruction matches an opcode. */
438 #define OPCODE_MATCHES(OPCODE, OP) \
439 (((OPCODE) & MASK_##OP) == MATCH_##OP)
441 static char *expr_end
;
443 /* The default target format to use. */
446 riscv_target_format (void)
448 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
451 /* Return the length of instruction INSN. */
453 static inline unsigned int
454 insn_length (const struct riscv_cl_insn
*insn
)
456 return riscv_insn_length (insn
->insn_opcode
);
459 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
462 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
465 insn
->insn_opcode
= mo
->match
;
471 /* Install INSN at the location specified by its "frag" and "where" fields. */
474 install_insn (const struct riscv_cl_insn
*insn
)
476 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
477 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
480 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
481 and install the opcode in the new location. */
484 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
488 if (insn
->fixp
!= NULL
)
490 insn
->fixp
->fx_frag
= frag
;
491 insn
->fixp
->fx_where
= where
;
496 /* Add INSN to the end of the output. */
499 add_fixed_insn (struct riscv_cl_insn
*insn
)
501 char *f
= frag_more (insn_length (insn
));
502 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
506 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
507 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
509 frag_grow (max_chars
);
510 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
511 frag_var (rs_machine_dependent
, max_chars
, var
,
512 subtype
, symbol
, offset
, NULL
);
515 /* Compute the length of a branch sequence, and adjust the stored length
516 accordingly. If FRAGP is NULL, the worst-case length is returned. */
519 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
521 int jump
, rvc
, length
= 8;
526 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
527 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
528 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
530 /* Assume jumps are in range; the linker will catch any that aren't. */
531 length
= jump
? 4 : 8;
533 if (fragp
->fr_symbol
!= NULL
534 && S_IS_DEFINED (fragp
->fr_symbol
)
535 && !S_IS_WEAK (fragp
->fr_symbol
)
536 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
538 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
539 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
540 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
542 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
544 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
546 else if (!jump
&& rvc
)
551 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
556 /* Information about an opcode name, mnemonics and its value. */
563 /* List for all supported opcode name. */
564 static const struct opcode_name_t opcode_name_list
[] =
609 /* Hash table for lookup opcode name. */
610 static htab_t opcode_names_hash
= NULL
;
612 /* Initialization for hash table of opcode name. */
614 init_opcode_names_hash (void)
616 const struct opcode_name_t
*opcode
;
618 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
619 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
620 as_fatal (_("duplicate %s"), opcode
->name
);
623 /* Find `s` is a valid opcode name or not,
624 return the opcode name info if found. */
625 static const struct opcode_name_t
*
626 opcode_name_lookup (char **s
)
630 struct opcode_name_t
*o
;
632 /* Find end of name. */
634 if (is_name_beginner (*e
))
636 while (is_part_of_name (*e
))
639 /* Terminate name. */
643 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
645 /* Advance to next token if one was recognized. */
664 static htab_t reg_names_hash
= NULL
;
665 static htab_t csr_extra_hash
= NULL
;
667 #define ENCODE_REG_HASH(cls, n) \
668 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
669 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
670 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
673 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
675 void *hash
= ENCODE_REG_HASH (class, n
);
676 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
677 as_fatal (_("duplicate %s"), name
);
681 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
685 for (i
= 0; i
< n
; i
++)
686 hash_reg_name (class, names
[i
], i
);
689 /* Init hash table csr_extra_hash to handle CSR. */
691 riscv_init_csr_hash (const char *name
,
693 enum riscv_csr_class
class,
694 enum riscv_priv_spec_class define_version
,
695 enum riscv_priv_spec_class abort_version
)
697 struct riscv_csr_extra
*entry
, *pre_entry
;
698 bfd_boolean need_enrty
= TRUE
;
701 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
702 while (need_enrty
&& entry
!= NULL
)
704 if (entry
->csr_class
== class
705 && entry
->address
== address
706 && entry
->define_version
== define_version
707 && entry
->abort_version
== abort_version
)
713 /* Duplicate setting for the CSR, just return and do nothing. */
717 entry
= XNEW (struct riscv_csr_extra
);
718 entry
->csr_class
= class;
719 entry
->address
= address
;
720 entry
->define_version
= define_version
;
721 entry
->abort_version
= abort_version
;
724 /* If the CSR hasn't been inserted in the hash table, then insert it.
725 Otherwise, attach the extra information to the entry which is already
726 in the hash table. */
727 if (pre_entry
== NULL
)
728 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
730 pre_entry
->next
= entry
;
733 /* Return the suitable CSR address after checking the ISA dependency and
734 priv spec versions. */
737 riscv_csr_address (const char *csr_name
,
738 struct riscv_csr_extra
*entry
)
740 struct riscv_csr_extra
*saved_entry
= entry
;
741 enum riscv_csr_class csr_class
= entry
->csr_class
;
742 bfd_boolean need_check_version
= TRUE
;
743 bfd_boolean result
= TRUE
;
748 result
= riscv_subset_supports ("i");
751 result
= (xlen
== 32 && riscv_subset_supports ("i"));
754 result
= riscv_subset_supports ("f");
755 need_check_version
= FALSE
;
757 case CSR_CLASS_DEBUG
:
758 need_check_version
= FALSE
;
761 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
764 /* Don't report the ISA conflict when -mcsr-check isn't set. */
765 if (riscv_opts
.csr_check
&& !result
)
766 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name
);
768 while (entry
!= NULL
)
770 if (!need_check_version
771 || (default_priv_spec
>= entry
->define_version
772 && default_priv_spec
< entry
->abort_version
))
774 /* Find the suitable CSR according to the specific version. */
775 return entry
->address
;
780 /* We can not find the suitable CSR address according to the privilege
781 version. Therefore, we use the last defined value. Report the warning
782 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
783 otherwise, you may get the unexpected CSR address. */
784 if (riscv_opts
.csr_check
)
786 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
788 if (priv_name
!= NULL
)
789 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
790 csr_name
, priv_name
);
793 return saved_entry
->address
;
796 /* Once the CSR is defined, including the old privilege spec, then we call
797 riscv_csr_class_check and riscv_csr_version_check to do the further checking
798 and get the corresponding address. Return -1 if the CSR is never been
799 defined. Otherwise, return the address. */
802 reg_csr_lookup_internal (const char *s
)
804 struct riscv_csr_extra
*r
=
805 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
810 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
811 the CSR was defined, but isn't allowed for the current ISA setting or
812 the privilege spec. If the CSR is never been defined, then assembler
813 will regard it as a "Unknown CSR" and report error. If user use number
814 to set the CSR, but over the range (> 0xfff), then assembler will report
815 "Improper CSR" error for it. */
816 return riscv_csr_address (s
, r
);
820 reg_lookup_internal (const char *s
, enum reg_class
class)
824 if (class == RCLASS_CSR
)
825 return reg_csr_lookup_internal (s
);
827 r
= str_hash_find (reg_names_hash
, s
);
828 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
831 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
834 return DECODE_REG_NUM (r
);
838 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
844 /* Find end of name. */
846 if (is_name_beginner (*e
))
848 while (is_part_of_name (*e
))
851 /* Terminate name. */
855 /* Look for the register. Advance to next token if one was recognized. */
856 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
866 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
868 const char *p
= strchr (*s
, ',');
869 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
874 for (i
= 0; i
< size
; i
++)
875 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
885 /* For consistency checking, verify that all bits are specified either
886 by the match/mask part of the instruction definition, or by the
889 `length` could be 0, 4 or 8, 0 for auto detection. */
891 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
893 const char *p
= opc
->args
;
895 insn_t used_bits
= opc
->mask
;
897 insn_t required_bits
;
900 insn_width
= 8 * riscv_insn_length (opc
->match
);
902 insn_width
= 8 * length
;
904 required_bits
= ~0ULL >> (64 - insn_width
);
906 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
908 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
909 opc
->name
, opc
->args
);
913 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
920 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
921 case 'c': break; /* RS1, constrained to equal sp */
922 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
923 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
924 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
925 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
926 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
927 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
928 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
929 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
930 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
931 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
932 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
933 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
934 case 'w': break; /* RS1S, constrained to equal RD */
935 case 'x': break; /* RS2S, constrained to equal RD */
936 case 'z': break; /* RS2S, contrained to be x0 */
937 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
938 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
939 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
940 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
941 case 'U': break; /* RS1, constrained to equal RD */
942 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
943 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
944 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
945 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
946 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
947 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
948 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
949 case 'F': /* funct */
952 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
953 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
954 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
955 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
957 as_bad (_("internal: bad RISC-V opcode"
958 " (unknown operand type `CF%c'): %s %s"),
959 c
, opc
->name
, opc
->args
);
964 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
965 c
, opc
->name
, opc
->args
);
972 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
973 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
975 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
976 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
977 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
979 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
980 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
981 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
982 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
983 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
984 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
985 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
986 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
987 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
988 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
989 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
991 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
992 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
993 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
994 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
995 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1001 case 'F': /* funct */
1004 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1005 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1006 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1008 as_bad (_("internal: bad RISC-V opcode"
1009 " (unknown operand type `F%c'): %s %s"),
1010 c
, opc
->name
, opc
->args
);
1014 case 'O': /* opcode */
1017 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1018 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1020 as_bad (_("internal: bad RISC-V opcode"
1021 " (unknown operand type `F%c'): %s %s"),
1022 c
, opc
->name
, opc
->args
);
1027 as_bad (_("internal: bad RISC-V opcode "
1028 "(unknown operand type `%c'): %s %s"),
1029 c
, opc
->name
, opc
->args
);
1033 if (used_bits
!= required_bits
)
1035 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1036 ~(unsigned long)(used_bits
& required_bits
),
1037 opc
->name
, opc
->args
);
1043 struct percent_op_match
1046 bfd_reloc_code_real_type reloc
;
1049 /* Common hash table initialization function for
1050 instruction and .insn directive. */
1052 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1053 bfd_boolean insn_directive_p
)
1057 htab_t hash
= str_htab_create ();
1058 while (opcodes
[i
].name
)
1060 const char *name
= opcodes
[i
].name
;
1061 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1062 as_fatal (_("duplicate %s"), name
);
1066 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1068 if (insn_directive_p
)
1069 length
= ((name
[0] == 'c') ? 2 : 4);
1071 length
= 0; /* Let assembler determine the length. */
1072 if (!validate_riscv_insn (&opcodes
[i
], length
))
1073 as_fatal (_("Broken assembler. No assembly attempted."));
1076 gas_assert (!insn_directive_p
);
1079 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1085 /* This function is called once, at assembler startup time. It should set up
1086 all the tables, etc. that the MD part of the assembler will need. */
1091 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1093 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1094 as_warn (_("Could not set architecture and machine"));
1096 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1097 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1099 reg_names_hash
= str_htab_create ();
1100 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1101 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1102 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1103 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1104 /* Add "fp" as an alias for "s0". */
1105 hash_reg_name (RCLASS_GPR
, "fp", 8);
1107 /* Create and insert CSR hash tables. */
1108 csr_extra_hash
= str_htab_create ();
1109 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1110 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1111 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1112 DECLARE_CSR(name, num, class, define_version, abort_version);
1113 #include "opcode/riscv-opc.h"
1116 opcode_names_hash
= str_htab_create ();
1117 init_opcode_names_hash ();
1119 /* Set the default alignment for the text section. */
1120 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1124 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1131 case BFD_RELOC_RISCV_HI20
:
1132 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1134 case BFD_RELOC_RISCV_LO12_S
:
1135 return ENCODE_STYPE_IMM (value
);
1137 case BFD_RELOC_RISCV_LO12_I
:
1138 return ENCODE_ITYPE_IMM (value
);
1145 /* Output an instruction. IP is the instruction information.
1146 ADDRESS_EXPR is an operand of the instruction to be used with
1150 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1151 bfd_reloc_code_real_type reloc_type
)
1153 dwarf2_emit_insn (0);
1155 if (reloc_type
!= BFD_RELOC_UNUSED
)
1157 reloc_howto_type
*howto
;
1159 gas_assert (address_expr
);
1160 if (reloc_type
== BFD_RELOC_12_PCREL
1161 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1163 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1164 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1165 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1167 if (now_seg
== absolute_section
)
1169 as_bad (_("relaxable branches not supported in absolute section"));
1173 add_relaxed_insn (ip
, worst_case
, best_case
,
1174 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1175 address_expr
->X_add_symbol
,
1176 address_expr
->X_add_number
);
1181 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1183 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1185 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1186 bfd_get_reloc_size (howto
),
1187 address_expr
, FALSE
, reloc_type
);
1189 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1193 add_fixed_insn (ip
);
1196 /* We need to start a new frag after any instruction that can be
1197 optimized away or compressed by the linker during relaxation, to prevent
1198 the assembler from computing static offsets across such an instruction.
1199 This is necessary to get correct EH info. */
1200 if (reloc_type
== BFD_RELOC_RISCV_HI20
1201 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1202 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1203 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1205 frag_wane (frag_now
);
1210 /* Build an instruction created by a macro expansion. This is passed
1211 a pointer to the count of instructions created so far, an
1212 expression, the name of the instruction to build, an operand format
1213 string, and corresponding arguments. */
1216 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1218 const struct riscv_opcode
*mo
;
1219 struct riscv_cl_insn insn
;
1220 bfd_reloc_code_real_type r
;
1223 va_start (args
, fmt
);
1225 r
= BFD_RELOC_UNUSED
;
1226 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1229 /* Find a non-RVC variant of the instruction. append_insn will compress
1231 while (riscv_insn_length (mo
->match
) < 4)
1233 gas_assert (strcmp (name
, mo
->name
) == 0);
1235 create_insn (&insn
, mo
);
1241 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1245 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1249 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1253 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1259 gas_assert (ep
!= NULL
);
1260 r
= va_arg (args
, int);
1268 as_fatal (_("internal error: invalid macro"));
1273 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1275 append_insn (&insn
, ep
, r
);
1278 /* Build an instruction created by a macro expansion. Like md_assemble but
1279 accept a printf-style format string and arguments. */
1282 md_assemblef (const char *format
, ...)
1288 va_start (ap
, format
);
1290 r
= vasprintf (&buf
, format
, ap
);
1293 as_fatal (_("internal error: vasprintf failed"));
1301 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1304 normalize_constant_expr (expressionS
*ex
)
1308 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1309 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1310 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1314 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1315 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1318 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1319 bfd_boolean maybe_csr
)
1321 if (ex
->X_op
== O_big
)
1322 as_bad (_("unsupported large constant"));
1323 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1324 as_bad (_("unknown CSR `%s'"),
1325 S_GET_NAME (ex
->X_add_symbol
));
1326 else if (ex
->X_op
!= O_constant
)
1327 as_bad (_("Instruction %s requires absolute expression"),
1329 normalize_constant_expr (ex
);
1333 make_internal_label (void)
1335 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1339 /* Load an entry from the GOT. */
1341 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1342 const char *lo_insn
, const char *lo_pattern
,
1343 bfd_reloc_code_real_type hi_reloc
,
1344 bfd_reloc_code_real_type lo_reloc
)
1347 ep2
.X_op
= O_symbol
;
1348 ep2
.X_add_symbol
= make_internal_label ();
1349 ep2
.X_add_number
= 0;
1351 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1352 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1356 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1357 bfd_reloc_code_real_type hi_reloc
,
1358 bfd_reloc_code_real_type lo_reloc
)
1360 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1364 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1365 bfd_reloc_code_real_type hi_reloc
,
1366 bfd_reloc_code_real_type lo_reloc
)
1368 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1371 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1373 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1374 bfd_reloc_code_real_type reloc
)
1376 /* Ensure the jalr is emitted to the same frag as the auipc. */
1378 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1379 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1380 /* See comment at end of append_insn. */
1381 frag_wane (frag_now
);
1385 /* Load an integer constant into a register. */
1388 load_const (int reg
, expressionS
*ep
)
1390 int shift
= RISCV_IMM_BITS
;
1391 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1392 expressionS upper
= *ep
, lower
= *ep
;
1393 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1394 upper
.X_add_number
-= lower
.X_add_number
;
1396 if (ep
->X_op
!= O_constant
)
1398 as_bad (_("unsupported large constant"));
1402 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1404 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1405 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1408 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1409 load_const (reg
, &upper
);
1411 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1412 if (lower
.X_add_number
!= 0)
1413 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1414 lower
.X_add_number
);
1418 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1421 if (upper
.X_add_number
!= 0)
1423 /* Discard low part and zero-extend upper immediate. */
1424 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1426 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1430 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1431 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1432 lower
.X_add_number
);
1436 /* Zero extend and sign extend byte/half-word/word. */
1439 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bfd_boolean sign
)
1443 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1444 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1448 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1449 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1453 /* Expand RISC-V assembly macros into one or more instructions. */
1455 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1456 bfd_reloc_code_real_type
*imm_reloc
)
1458 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1459 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1460 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1461 int mask
= ip
->insn_mo
->mask
;
1466 load_const (rd
, imm_expr
);
1471 /* Load the address of a symbol into a register. */
1472 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1473 as_bad (_("offset too large"));
1475 if (imm_expr
->X_op
== O_constant
)
1476 load_const (rd
, imm_expr
);
1477 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1478 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1479 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1480 else /* Local PIC symbol, or any non-PIC symbol */
1481 pcrel_load (rd
, rd
, imm_expr
, "addi",
1482 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1486 pcrel_load (rd
, rd
, imm_expr
, "addi",
1487 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1491 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1492 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1496 pcrel_load (rd
, rd
, imm_expr
, "lb",
1497 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1501 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1502 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1506 pcrel_load (rd
, rd
, imm_expr
, "lh",
1507 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1511 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1512 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1516 pcrel_load (rd
, rd
, imm_expr
, "lw",
1517 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1521 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1522 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1526 pcrel_load (rd
, rd
, imm_expr
, "ld",
1527 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1531 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1532 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1536 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1537 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1541 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1542 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1546 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1547 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1551 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1552 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1556 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1557 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1561 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1562 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1566 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1567 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1571 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1575 riscv_ext (rd
, rs1
, xlen
- 16, FALSE
);
1579 riscv_ext (rd
, rs1
, xlen
- 32, FALSE
);
1583 riscv_ext (rd
, rs1
, xlen
- 8, TRUE
);
1587 riscv_ext (rd
, rs1
, xlen
- 16, TRUE
);
1591 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1596 static const struct percent_op_match percent_op_utype
[] =
1598 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1599 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1600 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1601 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1602 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1603 {"%hi", BFD_RELOC_RISCV_HI20
},
1607 static const struct percent_op_match percent_op_itype
[] =
1609 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1610 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1611 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1615 static const struct percent_op_match percent_op_stype
[] =
1617 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1618 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1619 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1623 static const struct percent_op_match percent_op_rtype
[] =
1625 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1629 static const struct percent_op_match percent_op_null
[] =
1634 /* Return true if *STR points to a relocation operator. When returning true,
1635 move *STR over the operator and store its relocation code in *RELOC.
1636 Leave both *STR and *RELOC alone when returning false. */
1639 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1640 const struct percent_op_match
*percent_op
)
1642 for ( ; percent_op
->str
; percent_op
++)
1643 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1645 int len
= strlen (percent_op
->str
);
1647 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1650 *str
+= strlen (percent_op
->str
);
1651 *reloc
= percent_op
->reloc
;
1653 /* Check whether the output BFD supports this relocation.
1654 If not, issue an error and fall back on something safe. */
1655 if (*reloc
!= BFD_RELOC_UNUSED
1656 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1658 as_bad ("relocation %s isn't supported by the current ABI",
1660 *reloc
= BFD_RELOC_UNUSED
;
1668 my_getExpression (expressionS
*ep
, char *str
)
1672 save_in
= input_line_pointer
;
1673 input_line_pointer
= str
;
1675 expr_end
= input_line_pointer
;
1676 input_line_pointer
= save_in
;
1679 /* Parse string STR as a 16-bit relocatable operand. Store the
1680 expression in *EP and the relocation, if any, in RELOC.
1681 Return the number of relocation operators used (0 or 1).
1683 On exit, EXPR_END points to the first character after the expression. */
1686 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1687 char *str
, const struct percent_op_match
*percent_op
)
1690 unsigned crux_depth
, str_depth
, regno
;
1693 /* First, check for integer registers. No callers can accept a reg, but
1694 we need to avoid accidentally creating a useless undefined symbol below,
1695 if this is an instruction pattern that can't match. A glibc build fails
1696 if this is removed. */
1697 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1699 ep
->X_op
= O_register
;
1700 ep
->X_add_number
= regno
;
1705 /* Search for the start of the main expression.
1706 End the loop with CRUX pointing to the start
1707 of the main expression and with CRUX_DEPTH containing the number
1708 of open brackets at that point. */
1715 crux_depth
= str_depth
;
1717 /* Skip over whitespace and brackets, keeping count of the number
1719 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1725 && parse_relocation (&str
, reloc
, percent_op
));
1727 my_getExpression (ep
, crux
);
1730 /* Match every open bracket. */
1731 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1736 as_bad ("unclosed '('");
1743 /* Parse opcode name, could be an mnemonics or number. */
1745 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1746 char *str
, const struct percent_op_match
*percent_op
)
1748 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1752 ep
->X_op
= O_constant
;
1753 ep
->X_add_number
= o
->val
;
1757 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1760 /* Detect and handle implicitly zero load-store offsets. For example,
1761 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1762 an implicit offset was detected. */
1765 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1767 /* Check whether there is only a single bracketed expression left.
1768 If so, it must be the base register and the constant must be zero. */
1769 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1771 ep
->X_op
= O_constant
;
1772 ep
->X_add_number
= 0;
1779 /* All RISC-V CSR instructions belong to one of these classes. */
1789 /* Return which CSR instruction is checking. */
1791 static enum csr_insn_type
1792 riscv_csr_insn_type (insn_t insn
)
1794 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1795 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1797 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1798 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1800 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1801 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1804 return INSN_NOT_CSR
;
1807 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1808 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1809 CSR address is 0x3. */
1812 riscv_csr_read_only_check (insn_t insn
)
1814 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1815 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1816 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1817 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1820 && (((csr_insn
== INSN_CSRRS
1821 || csr_insn
== INSN_CSRRC
)
1823 || csr_insn
== INSN_CSRRW
))
1829 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1831 uret is actually a N-ext instruction. So it is better to regard it as
1832 an user instruction rather than the priv instruction.
1834 hret is used to return from traps in H-mode. H-mode is removed since
1835 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1836 Therefore, hret should be controlled by the hypervisor spec rather than
1837 priv spec in the future.
1839 dret is defined in the debug spec, so it should be checked in the future,
1843 riscv_is_priv_insn (insn_t insn
)
1845 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1846 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1847 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1848 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1849 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1850 check it here to keep the compatible. Maybe we should issue warning
1851 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1852 We already have a similar check for CSR, but not yet for instructions.
1853 It would be good if we could check the spec versions both for CSR and
1854 instructions, but not here. */
1855 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1858 /* This routine assembles an instruction into its binary format. As a
1859 side effect, it sets the global variable imm_reloc to the type of
1860 relocation to do if one of the operands is an address expression. */
1863 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1864 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1869 struct riscv_opcode
*insn
;
1874 const struct percent_op_match
*p
;
1875 const char *error
= "unrecognized opcode";
1876 /* Indicate we are assembling instruction with CSR. */
1877 bfd_boolean insn_with_csr
= FALSE
;
1879 /* Parse the name of the instruction. Terminate the string if whitespace
1880 is found so that str_hash_find only sees the name part of the string. */
1881 for (s
= str
; *s
!= '\0'; ++s
)
1889 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1892 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1894 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1897 if (!riscv_multi_subset_supports (insn
->insn_class
))
1900 create_insn (ip
, insn
);
1903 imm_expr
->X_op
= O_absent
;
1904 *imm_reloc
= BFD_RELOC_UNUSED
;
1905 p
= percent_op_itype
;
1907 for (args
= insn
->args
;; ++args
)
1909 s
+= strspn (s
, " \t");
1912 case '\0': /* End of args. */
1913 if (insn
->pinfo
!= INSN_MACRO
)
1915 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1918 /* For .insn, insn->match and insn->mask are 0. */
1919 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1925 if (riscv_is_priv_insn (ip
->insn_opcode
))
1926 explicit_priv_attr
= TRUE
;
1928 /* Check if we write a read-only CSR by the CSR
1931 && riscv_opts
.csr_check
1932 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1934 /* Restore the character in advance, since we want to
1935 report the detailed warning message here. */
1937 *(argsStart
- 1) = save_c
;
1938 as_warn (_("Read-only CSR is written `%s'"), str
);
1939 insn_with_csr
= FALSE
;
1944 /* Successful assembly. */
1946 insn_with_csr
= FALSE
;
1952 case 's': /* RS1 x8-x15 */
1953 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1954 || !(regno
>= 8 && regno
<= 15))
1956 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1958 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1959 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1960 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1963 case 't': /* RS2 x8-x15 */
1964 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1965 || !(regno
>= 8 && regno
<= 15))
1967 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1969 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1970 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1971 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1974 case 'U': /* RS1, constrained to equal RD. */
1975 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1976 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1980 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1982 INSERT_OPERAND (CRS2
, *ip
, regno
);
1984 case 'c': /* RS1, constrained to equal sp. */
1985 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1989 case 'z': /* RS2, contrained to equal x0. */
1990 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1995 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1996 || imm_expr
->X_op
!= O_constant
1997 || imm_expr
->X_add_number
<= 0
1998 || imm_expr
->X_add_number
>= 64)
2000 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2003 imm_expr
->X_op
= O_absent
;
2006 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2007 || imm_expr
->X_op
!= O_constant
2008 || imm_expr
->X_add_number
<= 0
2009 || imm_expr
->X_add_number
>= 32
2010 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2012 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2015 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2016 || imm_expr
->X_op
!= O_constant
2017 || imm_expr
->X_add_number
< 0
2018 || imm_expr
->X_add_number
>= 256
2019 || !VALID_RVC_UIMM8 ((valueT
) imm_expr
->X_add_number
))
2021 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
2024 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2025 || imm_expr
->X_op
!= O_constant
2026 || imm_expr
->X_add_number
== 0
2027 || !VALID_RVC_SIMM3 ((valueT
) imm_expr
->X_add_number
))
2029 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
2032 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2033 || imm_expr
->X_op
!= O_constant
2034 || imm_expr
->X_add_number
== 0
2035 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2037 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2040 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2042 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2043 || imm_expr
->X_op
!= O_constant
2044 || !VALID_RVC_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2046 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
2049 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2051 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2052 || imm_expr
->X_op
!= O_constant
2053 || !VALID_RVC_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2055 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
2058 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2060 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2061 || imm_expr
->X_op
!= O_constant
2062 || !VALID_RVC_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2065 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2068 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2070 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2071 || imm_expr
->X_op
!= O_constant
2072 || !VALID_RVC_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2075 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2078 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2079 || imm_expr
->X_op
!= O_constant
2080 /* C.addiw, c.li, and c.andi allow zero immediate.
2081 C.addi allows zero immediate as hint. Otherwise this
2083 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2085 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2088 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2089 || imm_expr
->X_op
!= O_constant
2090 || imm_expr
->X_add_number
== 0
2091 || !VALID_RVC_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2094 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2097 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2098 || imm_expr
->X_op
!= O_constant
2099 || imm_expr
->X_add_number
== 0
2100 || !VALID_RVC_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2103 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2106 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2108 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2109 || imm_expr
->X_op
!= O_constant
2110 || !VALID_RVC_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2113 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2116 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2118 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2119 || imm_expr
->X_op
!= O_constant
2120 || !VALID_RVC_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2123 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2126 p
= percent_op_utype
;
2127 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2130 if (imm_expr
->X_op
!= O_constant
2131 || imm_expr
->X_add_number
<= 0
2132 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2133 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2134 && (imm_expr
->X_add_number
<
2135 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2137 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2140 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2141 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2142 || ((int32_t)imm_expr
->X_add_number
2143 != imm_expr
->X_add_number
))
2145 imm_expr
->X_add_number
=
2146 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2152 case 'S': /* Floating-point RS1 x8-x15. */
2153 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2154 || !(regno
>= 8 && regno
<= 15))
2156 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2158 case 'D': /* Floating-point RS2 x8-x15. */
2159 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2160 || !(regno
>= 8 && regno
<= 15))
2162 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2164 case 'T': /* Floating-point RS2. */
2165 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2167 INSERT_OPERAND (CRS2
, *ip
, regno
);
2173 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2174 || imm_expr
->X_op
!= O_constant
2175 || imm_expr
->X_add_number
< 0
2176 || imm_expr
->X_add_number
>= 64)
2178 as_bad (_("bad value for funct6 field, "
2179 "value must be 0...64"));
2183 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2184 imm_expr
->X_op
= O_absent
;
2188 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2189 || imm_expr
->X_op
!= O_constant
2190 || imm_expr
->X_add_number
< 0
2191 || imm_expr
->X_add_number
>= 16)
2193 as_bad (_("bad value for funct4 field, "
2194 "value must be 0...15"));
2198 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2199 imm_expr
->X_op
= O_absent
;
2203 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2204 || imm_expr
->X_op
!= O_constant
2205 || imm_expr
->X_add_number
< 0
2206 || imm_expr
->X_add_number
>= 8)
2208 as_bad (_("bad value for funct3 field, "
2209 "value must be 0...7"));
2212 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2213 imm_expr
->X_op
= O_absent
;
2217 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2218 || imm_expr
->X_op
!= O_constant
2219 || imm_expr
->X_add_number
< 0
2220 || imm_expr
->X_add_number
>= 4)
2222 as_bad (_("bad value for funct2 field, "
2223 "value must be 0...3"));
2226 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2227 imm_expr
->X_op
= O_absent
;
2231 as_bad (_("bad compressed FUNCT field"
2232 " specifier 'CF%c'\n"),
2238 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2257 case '<': /* Shift amount, 0 - 31. */
2258 my_getExpression (imm_expr
, s
);
2259 check_absolute_expr (ip
, imm_expr
, FALSE
);
2260 if ((unsigned long) imm_expr
->X_add_number
> 31)
2261 as_bad (_("Improper shift amount (%lu)"),
2262 (unsigned long) imm_expr
->X_add_number
);
2263 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2264 imm_expr
->X_op
= O_absent
;
2268 case '>': /* Shift amount, 0 - (XLEN-1). */
2269 my_getExpression (imm_expr
, s
);
2270 check_absolute_expr (ip
, imm_expr
, FALSE
);
2271 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2272 as_bad (_("Improper shift amount (%lu)"),
2273 (unsigned long) imm_expr
->X_add_number
);
2274 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2275 imm_expr
->X_op
= O_absent
;
2279 case 'Z': /* CSRRxI immediate. */
2280 my_getExpression (imm_expr
, s
);
2281 check_absolute_expr (ip
, imm_expr
, FALSE
);
2282 if ((unsigned long) imm_expr
->X_add_number
> 31)
2283 as_bad (_("Improper CSRxI immediate (%lu)"),
2284 (unsigned long) imm_expr
->X_add_number
);
2285 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2286 imm_expr
->X_op
= O_absent
;
2290 case 'E': /* Control register. */
2291 insn_with_csr
= TRUE
;
2292 explicit_priv_attr
= TRUE
;
2293 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2294 INSERT_OPERAND (CSR
, *ip
, regno
);
2297 my_getExpression (imm_expr
, s
);
2298 check_absolute_expr (ip
, imm_expr
, TRUE
);
2299 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2300 as_bad (_("Improper CSR address (%lu)"),
2301 (unsigned long) imm_expr
->X_add_number
);
2302 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2303 imm_expr
->X_op
= O_absent
;
2308 case 'm': /* Rounding mode. */
2309 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2311 INSERT_OPERAND (RM
, *ip
, regno
);
2317 case 'Q': /* Fence predecessor/successor. */
2318 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2322 INSERT_OPERAND (PRED
, *ip
, regno
);
2324 INSERT_OPERAND (SUCC
, *ip
, regno
);
2329 case 'd': /* Destination register. */
2330 case 's': /* Source register. */
2331 case 't': /* Target register. */
2332 case 'r': /* rs3. */
2333 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2339 /* Now that we have assembled one operand, we use the args
2340 string to figure out where it goes in the instruction. */
2344 INSERT_OPERAND (RS1
, *ip
, regno
);
2347 INSERT_OPERAND (RD
, *ip
, regno
);
2350 INSERT_OPERAND (RS2
, *ip
, regno
);
2353 INSERT_OPERAND (RS3
, *ip
, regno
);
2360 case 'D': /* Floating point rd. */
2361 case 'S': /* Floating point rs1. */
2362 case 'T': /* Floating point rs2. */
2363 case 'U': /* Floating point rs1 and rs2. */
2364 case 'R': /* Floating point rs3. */
2365 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2373 INSERT_OPERAND (RD
, *ip
, regno
);
2376 INSERT_OPERAND (RS1
, *ip
, regno
);
2379 INSERT_OPERAND (RS1
, *ip
, regno
);
2382 INSERT_OPERAND (RS2
, *ip
, regno
);
2385 INSERT_OPERAND (RS3
, *ip
, regno
);
2394 my_getExpression (imm_expr
, s
);
2395 if (imm_expr
->X_op
!= O_big
2396 && imm_expr
->X_op
!= O_constant
)
2398 normalize_constant_expr (imm_expr
);
2403 my_getExpression (imm_expr
, s
);
2404 normalize_constant_expr (imm_expr
);
2405 /* The 'A' format specifier must be a symbol. */
2406 if (imm_expr
->X_op
!= O_symbol
)
2408 *imm_reloc
= BFD_RELOC_32
;
2413 my_getExpression (imm_expr
, s
);
2414 normalize_constant_expr (imm_expr
);
2415 /* The 'B' format specifier must be a symbol or a constant. */
2416 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2418 if (imm_expr
->X_op
== O_symbol
)
2419 *imm_reloc
= BFD_RELOC_32
;
2423 case 'j': /* Sign-extended immediate. */
2424 p
= percent_op_itype
;
2425 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2427 case 'q': /* Store displacement. */
2428 p
= percent_op_stype
;
2429 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2431 case 'o': /* Load displacement. */
2432 p
= percent_op_itype
;
2433 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2435 case '1': /* 4-operand add, must be %tprel_add. */
2436 p
= percent_op_rtype
;
2438 case '0': /* AMO "displacement," which must be zero. */
2439 p
= percent_op_null
;
2441 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2444 /* If this value won't fit into a 16 bit offset, then go
2445 find a macro that will generate the 32 bit offset
2447 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2449 normalize_constant_expr (imm_expr
);
2450 if (imm_expr
->X_op
!= O_constant
2451 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2453 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2454 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2461 case 'p': /* PC-relative offset. */
2463 *imm_reloc
= BFD_RELOC_12_PCREL
;
2464 my_getExpression (imm_expr
, s
);
2468 case 'u': /* Upper 20 bits. */
2469 p
= percent_op_utype
;
2470 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2472 if (imm_expr
->X_op
!= O_constant
)
2475 if (imm_expr
->X_add_number
< 0
2476 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2477 as_bad (_("lui expression not in range 0..1048575"));
2479 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2480 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2485 case 'a': /* 20-bit PC-relative offset. */
2487 my_getExpression (imm_expr
, s
);
2489 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2493 my_getExpression (imm_expr
, s
);
2495 if (strcmp (s
, "@plt") == 0)
2497 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2501 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2507 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2508 || imm_expr
->X_op
!= O_constant
2509 || imm_expr
->X_add_number
< 0
2510 || imm_expr
->X_add_number
>= 128
2511 || (imm_expr
->X_add_number
& 0x3) != 3)
2513 as_bad (_("bad value for opcode field, "
2514 "value must be 0...127 and "
2515 "lower 2 bits must be 0x3"));
2519 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2520 imm_expr
->X_op
= O_absent
;
2524 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2525 || imm_expr
->X_op
!= O_constant
2526 || imm_expr
->X_add_number
< 0
2527 || imm_expr
->X_add_number
>= 3)
2529 as_bad (_("bad value for opcode field, "
2530 "value must be 0...2"));
2534 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2535 imm_expr
->X_op
= O_absent
;
2539 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2547 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2548 || imm_expr
->X_op
!= O_constant
2549 || imm_expr
->X_add_number
< 0
2550 || imm_expr
->X_add_number
>= 128)
2552 as_bad (_("bad value for funct7 field, "
2553 "value must be 0...127"));
2557 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2558 imm_expr
->X_op
= O_absent
;
2562 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2563 || imm_expr
->X_op
!= O_constant
2564 || imm_expr
->X_add_number
< 0
2565 || imm_expr
->X_add_number
>= 8)
2567 as_bad (_("bad value for funct3 field, "
2568 "value must be 0...7"));
2572 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2573 imm_expr
->X_op
= O_absent
;
2577 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2578 || imm_expr
->X_op
!= O_constant
2579 || imm_expr
->X_add_number
< 0
2580 || imm_expr
->X_add_number
>= 4)
2582 as_bad (_("bad value for funct2 field, "
2583 "value must be 0...3"));
2587 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2588 imm_expr
->X_op
= O_absent
;
2593 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2598 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2599 || imm_expr
->X_op
!= O_constant
2600 || imm_expr
->X_add_number
!= 0)
2603 imm_expr
->X_op
= O_absent
;
2607 as_fatal (_("internal error: bad argument type %c"), *args
);
2612 error
= _("illegal operands");
2613 insn_with_csr
= FALSE
;
2617 /* Restore the character we might have clobbered above. */
2619 *(argsStart
- 1) = save_c
;
2625 md_assemble (char *str
)
2627 struct riscv_cl_insn insn
;
2628 expressionS imm_expr
;
2629 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2631 /* The arch and priv attributes should be set before assembling. */
2632 if (!start_assemble
)
2634 start_assemble
= TRUE
;
2635 riscv_set_abi_by_arch ();
2637 /* Set the default_priv_spec according to the priv attributes. */
2638 if (!riscv_set_default_priv_spec (NULL
))
2642 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2646 as_bad ("%s `%s'", error
, str
);
2650 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2651 macro (&insn
, &imm_expr
, &imm_reloc
);
2653 append_insn (&insn
, &imm_expr
, imm_reloc
);
2657 md_atof (int type
, char *litP
, int *sizeP
)
2659 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2663 md_number_to_chars (char *buf
, valueT val
, int n
)
2665 number_to_chars_littleendian (buf
, val
, n
);
2668 const char *md_shortopts
= "O::g::G:";
2672 OPTION_MARCH
= OPTION_MD_BASE
,
2679 OPTION_NO_ARCH_ATTR
,
2681 OPTION_NO_CSR_CHECK
,
2687 struct option md_longopts
[] =
2689 {"march", required_argument
, NULL
, OPTION_MARCH
},
2690 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2691 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2692 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2693 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2694 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2695 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2696 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2697 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2698 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2699 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2700 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2701 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2703 {NULL
, no_argument
, NULL
, 0}
2705 size_t md_longopts_size
= sizeof (md_longopts
);
2708 md_parse_option (int c
, const char *arg
)
2713 /* riscv_after_parse_args will call riscv_set_arch to parse
2714 the architecture. */
2715 default_arch_with_ext
= arg
;
2719 riscv_opts
.pic
= FALSE
;
2723 riscv_opts
.pic
= TRUE
;
2727 if (strcmp (arg
, "ilp32") == 0)
2728 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2729 else if (strcmp (arg
, "ilp32e") == 0)
2730 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2731 else if (strcmp (arg
, "ilp32f") == 0)
2732 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2733 else if (strcmp (arg
, "ilp32d") == 0)
2734 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2735 else if (strcmp (arg
, "ilp32q") == 0)
2736 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2737 else if (strcmp (arg
, "lp64") == 0)
2738 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2739 else if (strcmp (arg
, "lp64f") == 0)
2740 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2741 else if (strcmp (arg
, "lp64d") == 0)
2742 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2743 else if (strcmp (arg
, "lp64q") == 0)
2744 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2747 explicit_mabi
= TRUE
;
2751 riscv_opts
.relax
= TRUE
;
2754 case OPTION_NO_RELAX
:
2755 riscv_opts
.relax
= FALSE
;
2758 case OPTION_ARCH_ATTR
:
2759 riscv_opts
.arch_attr
= TRUE
;
2762 case OPTION_NO_ARCH_ATTR
:
2763 riscv_opts
.arch_attr
= FALSE
;
2766 case OPTION_CSR_CHECK
:
2767 riscv_opts
.csr_check
= TRUE
;
2770 case OPTION_NO_CSR_CHECK
:
2771 riscv_opts
.csr_check
= FALSE
;
2774 case OPTION_MISA_SPEC
:
2775 return riscv_set_default_isa_spec (arg
);
2777 case OPTION_MPRIV_SPEC
:
2778 return riscv_set_default_priv_spec (arg
);
2788 riscv_after_parse_args (void)
2790 /* The --with-arch is optional for now, so we have to set the xlen
2791 according to the default_arch, which is set by the --targte, first.
2792 Then, we use the xlen to set the default_arch_with_ext if the
2793 -march and --with-arch are not set. */
2796 if (strcmp (default_arch
, "riscv32") == 0)
2798 else if (strcmp (default_arch
, "riscv64") == 0)
2801 as_bad ("unknown default architecture `%s'", default_arch
);
2803 if (default_arch_with_ext
== NULL
)
2804 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2806 /* Initialize the hash table for extensions with default version. */
2807 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2809 /* If the -misa-spec isn't set, then we set the default ISA spec according
2810 to DEFAULT_RISCV_ISA_SPEC. */
2811 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2812 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2814 /* Set the architecture according to -march or or --with-arch. */
2815 riscv_set_arch (default_arch_with_ext
);
2817 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2818 riscv_set_rvc (FALSE
);
2819 if (riscv_subset_supports ("c"))
2820 riscv_set_rvc (TRUE
);
2822 /* Enable RVE if specified by the -march option. */
2823 riscv_set_rve (FALSE
);
2824 if (riscv_subset_supports ("e"))
2825 riscv_set_rve (TRUE
);
2827 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2828 according to DEFAULT_PRIV_SPEC. */
2829 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2830 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2832 /* If the CIE to be produced has not been overridden on the command line,
2833 then produce version 3 by default. This allows us to use the full
2834 range of registers in a .cfi_return_column directive. */
2835 if (flag_dwarf_cie_version
== -1)
2836 flag_dwarf_cie_version
= 3;
2840 md_pcrel_from (fixS
*fixP
)
2842 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2845 /* Apply a fixup to the object file. */
2848 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2850 unsigned int subtype
;
2851 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2852 bfd_boolean relaxable
= FALSE
;
2856 /* Remember value for tc_gen_reloc. */
2857 fixP
->fx_addnumber
= *valP
;
2859 switch (fixP
->fx_r_type
)
2861 case BFD_RELOC_RISCV_HI20
:
2862 case BFD_RELOC_RISCV_LO12_I
:
2863 case BFD_RELOC_RISCV_LO12_S
:
2864 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2865 | bfd_getl32 (buf
), buf
);
2866 if (fixP
->fx_addsy
== NULL
)
2867 fixP
->fx_done
= TRUE
;
2871 case BFD_RELOC_RISCV_GOT_HI20
:
2872 case BFD_RELOC_RISCV_ADD8
:
2873 case BFD_RELOC_RISCV_ADD16
:
2874 case BFD_RELOC_RISCV_ADD32
:
2875 case BFD_RELOC_RISCV_ADD64
:
2876 case BFD_RELOC_RISCV_SUB6
:
2877 case BFD_RELOC_RISCV_SUB8
:
2878 case BFD_RELOC_RISCV_SUB16
:
2879 case BFD_RELOC_RISCV_SUB32
:
2880 case BFD_RELOC_RISCV_SUB64
:
2881 case BFD_RELOC_RISCV_RELAX
:
2884 case BFD_RELOC_RISCV_TPREL_HI20
:
2885 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2886 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2887 case BFD_RELOC_RISCV_TPREL_ADD
:
2891 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2892 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2893 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2894 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2895 if (fixP
->fx_addsy
!= NULL
)
2896 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2899 _("TLS relocation against a constant"));
2903 /* Use pc-relative relocation for FDE initial location.
2904 The symbol address in .eh_frame may be adjusted in
2905 _bfd_elf_discard_section_eh_frame, and the content of
2906 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2907 Therefore, we cannot insert a relocation whose addend symbol is
2908 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2909 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2910 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2911 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2912 && S_GET_VALUE (fixP
->fx_subsy
)
2913 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2915 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2916 fixP
->fx_subsy
= NULL
;
2923 case BFD_RELOC_RISCV_CFA
:
2924 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2926 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2927 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2928 fixP
->fx_next
->fx_subsy
= NULL
;
2929 fixP
->fx_next
->fx_offset
= 0;
2930 fixP
->fx_subsy
= NULL
;
2932 switch (fixP
->fx_r_type
)
2935 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2936 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2940 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2941 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2945 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2946 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2950 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2951 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2954 case BFD_RELOC_RISCV_CFA
:
2955 /* Load the byte to get the subtype. */
2956 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2957 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2960 case DW_CFA_advance_loc1
:
2961 fixP
->fx_where
= loc
+ 1;
2962 fixP
->fx_next
->fx_where
= loc
+ 1;
2963 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2964 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2967 case DW_CFA_advance_loc2
:
2969 fixP
->fx_next
->fx_size
= 2;
2970 fixP
->fx_where
= loc
+ 1;
2971 fixP
->fx_next
->fx_where
= loc
+ 1;
2972 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2973 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2976 case DW_CFA_advance_loc4
:
2978 fixP
->fx_next
->fx_size
= 4;
2979 fixP
->fx_where
= loc
;
2980 fixP
->fx_next
->fx_where
= loc
;
2981 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2982 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2986 if (subtype
< 0x80 && (subtype
& 0x40))
2988 /* DW_CFA_advance_loc */
2989 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2990 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2991 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2992 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2995 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
3001 /* This case is unreachable. */
3008 /* If we are deleting this reloc entry, we must fill in the
3009 value now. This can happen if we have a .word which is not
3010 resolved when it appears but is later defined. */
3011 if (fixP
->fx_addsy
== NULL
)
3013 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3014 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3019 case BFD_RELOC_RISCV_JMP
:
3022 /* Fill in a tentative value to improve objdump readability. */
3023 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3024 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3025 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3029 case BFD_RELOC_12_PCREL
:
3032 /* Fill in a tentative value to improve objdump readability. */
3033 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3034 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3035 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3039 case BFD_RELOC_RISCV_RVC_BRANCH
:
3042 /* Fill in a tentative value to improve objdump readability. */
3043 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3044 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3045 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3049 case BFD_RELOC_RISCV_RVC_JUMP
:
3052 /* Fill in a tentative value to improve objdump readability. */
3053 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3054 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3055 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3059 case BFD_RELOC_RISCV_CALL
:
3060 case BFD_RELOC_RISCV_CALL_PLT
:
3064 case BFD_RELOC_RISCV_PCREL_HI20
:
3065 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3066 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3067 relaxable
= riscv_opts
.relax
;
3070 case BFD_RELOC_RISCV_ALIGN
:
3074 /* We ignore generic BFD relocations we don't know about. */
3075 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3076 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3079 if (fixP
->fx_subsy
!= NULL
)
3080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3081 _("unsupported symbol subtraction"));
3083 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3084 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3086 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3087 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3088 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3089 fixP
->fx_next
->fx_size
= 0;
3093 /* Because the value of .cfi_remember_state may changed after relaxation,
3094 we insert a fix to relocate it again in link-time. */
3097 riscv_pre_output_hook (void)
3099 const frchainS
*frch
;
3102 /* Save the current segment info. */
3104 subsegT subseg
= now_subseg
;
3106 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3107 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3111 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3113 if (frag
->fr_type
== rs_cfa
)
3116 expressionS
*symval
;
3118 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3119 exp
.X_op
= O_subtract
;
3120 exp
.X_add_symbol
= symval
->X_add_symbol
;
3121 exp
.X_add_number
= 0;
3122 exp
.X_op_symbol
= symval
->X_op_symbol
;
3124 /* We must set the segment before creating a frag after all
3125 frag chains have been chained together. */
3126 subseg_set (s
, frch
->frch_subseg
);
3128 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3129 BFD_RELOC_RISCV_CFA
);
3134 /* Restore the original segment info. */
3135 subseg_set (seg
, subseg
);
3139 /* This structure is used to hold a stack of .option values. */
3141 struct riscv_option_stack
3143 struct riscv_option_stack
*next
;
3144 struct riscv_set_options options
;
3147 static struct riscv_option_stack
*riscv_opts_stack
;
3149 /* Handle the .option pseudo-op. */
3152 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3154 char *name
= input_line_pointer
, ch
;
3156 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3157 ++input_line_pointer
;
3158 ch
= *input_line_pointer
;
3159 *input_line_pointer
= '\0';
3161 if (strcmp (name
, "rvc") == 0)
3162 riscv_set_rvc (TRUE
);
3163 else if (strcmp (name
, "norvc") == 0)
3164 riscv_set_rvc (FALSE
);
3165 else if (strcmp (name
, "pic") == 0)
3166 riscv_opts
.pic
= TRUE
;
3167 else if (strcmp (name
, "nopic") == 0)
3168 riscv_opts
.pic
= FALSE
;
3169 else if (strcmp (name
, "relax") == 0)
3170 riscv_opts
.relax
= TRUE
;
3171 else if (strcmp (name
, "norelax") == 0)
3172 riscv_opts
.relax
= FALSE
;
3173 else if (strcmp (name
, "csr-check") == 0)
3174 riscv_opts
.csr_check
= TRUE
;
3175 else if (strcmp (name
, "no-csr-check") == 0)
3176 riscv_opts
.csr_check
= FALSE
;
3177 else if (strcmp (name
, "push") == 0)
3179 struct riscv_option_stack
*s
;
3181 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3182 s
->next
= riscv_opts_stack
;
3183 s
->options
= riscv_opts
;
3184 riscv_opts_stack
= s
;
3186 else if (strcmp (name
, "pop") == 0)
3188 struct riscv_option_stack
*s
;
3190 s
= riscv_opts_stack
;
3192 as_bad (_(".option pop with no .option push"));
3195 riscv_opts
= s
->options
;
3196 riscv_opts_stack
= s
->next
;
3202 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3204 *input_line_pointer
= ch
;
3205 demand_empty_rest_of_line ();
3208 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3209 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3210 use in DWARF debug information. */
3213 s_dtprel (int bytes
)
3220 if (ex
.X_op
!= O_symbol
)
3222 as_bad (_("Unsupported use of %s"), (bytes
== 8
3225 ignore_rest_of_line ();
3228 p
= frag_more (bytes
);
3229 md_number_to_chars (p
, 0, bytes
);
3230 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3232 ? BFD_RELOC_RISCV_TLS_DTPREL64
3233 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3235 demand_empty_rest_of_line ();
3238 /* Handle the .bss pseudo-op. */
3241 s_bss (int ignore ATTRIBUTE_UNUSED
)
3243 subseg_set (bss_section
, 0);
3244 demand_empty_rest_of_line ();
3248 riscv_make_nops (char *buf
, bfd_vma bytes
)
3252 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3253 means we are not within a valid instruction sequence. It is thus safe
3254 to use a zero byte, even though that is not a valid instruction. */
3258 /* Use at most one 2-byte NOP. */
3259 if ((bytes
- i
) % 4 == 2)
3261 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
3265 /* Fill the remainder with 4-byte NOPs. */
3266 for ( ; i
< bytes
; i
+= 4)
3267 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
3270 /* Called from md_do_align. Used to create an alignment frag in a
3271 code section by emitting a worst-case NOP sequence that the linker
3272 will later relax to the correct number of NOPs. We can't compute
3273 the correct alignment now because of other linker relaxations. */
3276 riscv_frag_align_code (int n
)
3278 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3279 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3280 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3284 /* If we are moving to a smaller alignment than the instruction size, then no
3285 alignment is required. */
3286 if (bytes
<= insn_alignment
)
3289 /* When not relaxing, riscv_handle_align handles code alignment. */
3290 if (!riscv_opts
.relax
)
3293 nops
= frag_more (worst_case_bytes
);
3295 ex
.X_op
= O_constant
;
3296 ex
.X_add_number
= worst_case_bytes
;
3298 riscv_make_nops (nops
, worst_case_bytes
);
3300 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3301 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3306 /* Implement HANDLE_ALIGN. */
3309 riscv_handle_align (fragS
*fragP
)
3311 switch (fragP
->fr_type
)
3314 /* When relaxing, riscv_frag_align_code handles code alignment. */
3315 if (!riscv_opts
.relax
)
3317 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3318 - fragP
->fr_address
- fragP
->fr_fix
);
3319 /* We have 4 byte uncompressed nops. */
3320 bfd_signed_vma size
= 4;
3321 bfd_signed_vma excess
= bytes
% size
;
3322 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3327 /* Insert zeros or compressed nops to get 4 byte alignment. */
3330 riscv_make_nops (p
, excess
);
3331 fragP
->fr_fix
+= excess
;
3335 /* Insert variable number of 4 byte uncompressed nops. */
3336 riscv_make_nops (p
, size
);
3337 fragP
->fr_var
= size
;
3347 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3349 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3352 /* Translate internal representation of relocation info to BFD target
3356 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3358 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3360 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3361 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3362 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3363 reloc
->addend
= fixp
->fx_addnumber
;
3365 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3366 if (reloc
->howto
== NULL
)
3368 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3369 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3371 /* We don't have R_RISCV_8/16, but for this special case,
3372 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3376 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3377 _("cannot represent %s relocation in object file"),
3378 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3386 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3388 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3390 offsetT old_var
= fragp
->fr_var
;
3391 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3392 return fragp
->fr_var
- old_var
;
3398 /* Expand far branches to multi-instruction sequences. */
3401 md_convert_frag_branch (fragS
*fragp
)
3409 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3411 exp
.X_op
= O_symbol
;
3412 exp
.X_add_symbol
= fragp
->fr_symbol
;
3413 exp
.X_add_number
= fragp
->fr_offset
;
3415 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3417 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3419 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3423 /* Expand the RVC branch into a RISC-V one. */
3424 insn
= bfd_getl16 (buf
);
3425 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3426 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3428 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3429 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3430 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3431 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3432 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3433 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3436 bfd_putl32 (insn
, buf
);
3440 /* Invert the branch condition. Branch over the jump. */
3441 insn
= bfd_getl16 (buf
);
3442 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3443 insn
|= ENCODE_RVC_B_IMM (6);
3444 bfd_putl16 (insn
, buf
);
3449 /* Just keep the RVC branch. */
3450 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3451 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3452 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3453 2, &exp
, FALSE
, reloc
);
3462 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3465 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3467 /* Invert the branch condition. Branch over the jump. */
3468 insn
= bfd_getl32 (buf
);
3469 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3470 insn
|= ENCODE_SBTYPE_IMM (8);
3471 md_number_to_chars ((char *) buf
, insn
, 4);
3475 /* Jump to the target. */
3476 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3477 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3478 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3483 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3484 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3485 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3486 4, &exp
, FALSE
, reloc
);
3495 fixp
->fx_file
= fragp
->fr_file
;
3496 fixp
->fx_line
= fragp
->fr_line
;
3498 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3499 + fragp
->fr_fix
+ fragp
->fr_var
);
3501 fragp
->fr_fix
+= fragp
->fr_var
;
3504 /* Relax a machine dependent frag. This returns the amount by which
3505 the current size of the frag should change. */
3508 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3511 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3512 md_convert_frag_branch (fragp
);
3516 md_show_usage (FILE *stream
)
3518 fprintf (stream
, _("\
3520 -fpic generate position-independent code\n\
3521 -fno-pic don't generate position-independent code (default)\n\
3522 -march=ISA set the RISC-V architecture\n\
3523 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3524 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3525 -mabi=ABI set the RISC-V ABI\n\
3526 -mrelax enable relax (default)\n\
3527 -mno-relax disable relax\n\
3528 -march-attr generate RISC-V arch attribute\n\
3529 -mno-arch-attr don't generate RISC-V arch attribute\n\
3533 /* Standard calling conventions leave the CFA at SP on entry. */
3535 riscv_cfi_frame_initial_instructions (void)
3537 cfi_add_CFA_def_cfa_register (X_SP
);
3541 tc_riscv_regname_to_dw2regnum (char *regname
)
3545 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3548 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3551 /* CSRs are numbered 4096 -> 8191. */
3552 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3555 as_bad (_("unknown register `%s'"), regname
);
3560 riscv_elf_final_processing (void)
3562 riscv_set_abi_by_arch ();
3563 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3566 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3567 since these directives break relaxation when used with symbol deltas. */
3570 s_riscv_leb128 (int sign
)
3573 char *save_in
= input_line_pointer
;
3576 if (exp
.X_op
!= O_constant
)
3577 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3578 demand_empty_rest_of_line ();
3580 input_line_pointer
= save_in
;
3581 return s_leb128 (sign
);
3584 /* Parse the .insn directive. */
3587 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3589 char *str
= input_line_pointer
;
3590 struct riscv_cl_insn insn
;
3591 expressionS imm_expr
;
3592 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3595 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3596 ++input_line_pointer
;
3598 save_c
= *input_line_pointer
;
3599 *input_line_pointer
= '\0';
3601 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3602 &imm_reloc
, insn_type_hash
);
3606 as_bad ("%s `%s'", error
, str
);
3610 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3611 append_insn (&insn
, &imm_expr
, imm_reloc
);
3614 *input_line_pointer
= save_c
;
3615 demand_empty_rest_of_line ();
3618 /* Update arch and priv attributes. If we don't set the corresponding ELF
3619 attributes, then try to output the default ones. */
3622 riscv_write_out_attrs (void)
3624 const char *arch_str
, *priv_str
, *p
;
3625 /* versions[0] is major, versions[1] is minor,
3626 and versions[3] is revision. */
3627 unsigned versions
[3] = {0}, number
= 0;
3630 /* Re-write arch attribute to normalize the arch string. */
3631 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3632 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3633 xfree ((void *)arch_str
);
3635 /* For the file without any instruction, we don't set the default_priv_spec
3636 according to the priv attributes since the md_assemble isn't called.
3637 Call riscv_set_default_priv_spec here for the above case, although
3638 it seems strange. */
3640 && !riscv_set_default_priv_spec (NULL
))
3643 /* If we already have set elf priv attributes, then no need to do anything,
3644 assembler will generate them according to what you set. Otherwise, don't
3645 generate or update them when no CSR and priv instructions are used.
3646 Generate the priv attributes according to default_priv_spec, which can be
3647 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3648 priv attribute sets. */
3649 if (!explicit_priv_attr
)
3652 /* Re-write priv attributes by default_priv_spec. */
3653 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3655 for (i
= 0; *p
; ++p
)
3657 if (*p
== '.' && i
< 3)
3659 versions
[i
++] = number
;
3662 else if (ISDIGIT (*p
))
3663 number
= (number
* 10) + (*p
- '0');
3666 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3670 versions
[i
] = number
;
3672 /* Set the priv attributes. */
3673 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3674 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3675 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3678 /* Add the default contents for the .riscv.attributes section. If any
3679 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3680 to update the arch and priv attributes. */
3683 riscv_set_public_attributes (void)
3685 if (riscv_opts
.arch_attr
|| explicit_attr
)
3686 riscv_write_out_attrs ();
3689 /* Called after all assembly has been done. */
3694 riscv_set_public_attributes ();
3697 /* Given a symbolic attribute NAME, return the proper integer value.
3698 Returns -1 if the attribute is not known. */
3701 riscv_convert_symbolic_attribute (const char *name
)
3710 /* When you modify this table you should
3711 also modify the list in doc/c-riscv.texi. */
3712 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3716 T(priv_spec_revision
),
3717 T(unaligned_access
),
3727 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3728 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3729 return attribute_table
[i
].tag
;
3734 /* Parse a .attribute directive. */
3737 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3739 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3741 obj_attribute
*attr
;
3743 explicit_attr
= TRUE
;
3746 case Tag_RISCV_arch
:
3748 attr
= elf_known_obj_attributes_proc (stdoutput
);
3749 if (!start_assemble
)
3750 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3752 as_fatal (_(".attribute arch must set before any instructions"));
3754 if (old_xlen
!= xlen
)
3756 /* We must re-init bfd again if xlen is changed. */
3757 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3758 bfd_find_target (riscv_target_format (), stdoutput
);
3760 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3761 as_warn (_("Could not set architecture and machine"));
3765 case Tag_RISCV_priv_spec
:
3766 case Tag_RISCV_priv_spec_minor
:
3767 case Tag_RISCV_priv_spec_revision
:
3769 as_fatal (_(".attribute priv spec must set before any instructions"));
3777 /* Pseudo-op table. */
3779 static const pseudo_typeS riscv_pseudo_table
[] =
3781 /* RISC-V-specific pseudo-ops. */
3782 {"option", s_riscv_option
, 0},
3786 {"dtprelword", s_dtprel
, 4},
3787 {"dtpreldword", s_dtprel
, 8},
3789 {"uleb128", s_riscv_leb128
, 0},
3790 {"sleb128", s_riscv_leb128
, 1},
3791 {"insn", s_riscv_insn
, 0},
3792 {"attribute", s_riscv_attribute
, 0},
3798 riscv_pop_insert (void)
3800 extern void pop_insert (const pseudo_typeS
*);
3802 pop_insert (riscv_pseudo_table
);