1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2022 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits
46 (first bits enough to extract instruction length on a long opcode). */
49 /* The long encoded instruction bits ([0] is non-zero on a long opcode). */
50 char insn_long_opcode
[RISCV_MAX_INSN_LEN
];
52 /* The frag that contains the instruction. */
55 /* The offset into FRAG of the first instruction byte. */
58 /* The relocs associated with the instruction, if any. */
62 /* All RISC-V CSR belong to one of these classes. */
68 CSR_CLASS_I_32
, /* rv32 only */
69 CSR_CLASS_F
, /* f-ext only */
70 CSR_CLASS_ZKR
, /* zkr only */
71 CSR_CLASS_V
, /* rvv only */
72 CSR_CLASS_DEBUG
, /* debug CSR */
73 CSR_CLASS_H
, /* hypervisor */
74 CSR_CLASS_H_32
, /* hypervisor, rv32 only */
75 CSR_CLASS_SMAIA
, /* Smaia */
76 CSR_CLASS_SMAIA_32
, /* Smaia, rv32 only */
77 CSR_CLASS_SMSTATEEN
, /* Smstateen only */
78 CSR_CLASS_SMSTATEEN_32
, /* Smstateen RV32 only */
79 CSR_CLASS_SSAIA
, /* Ssaia */
80 CSR_CLASS_SSAIA_AND_H
, /* Ssaia with H */
81 CSR_CLASS_SSAIA_32
, /* Ssaia, rv32 only */
82 CSR_CLASS_SSAIA_AND_H_32
, /* Ssaia with H, rv32 only */
83 CSR_CLASS_SSSTATEEN
, /* S[ms]stateen only */
84 CSR_CLASS_SSSTATEEN_AND_H
, /* S[ms]stateen only (with H) */
85 CSR_CLASS_SSSTATEEN_AND_H_32
, /* S[ms]stateen RV32 only (with H) */
86 CSR_CLASS_SSCOFPMF
, /* Sscofpmf only */
87 CSR_CLASS_SSCOFPMF_32
, /* Sscofpmf RV32 only */
88 CSR_CLASS_SSTC
, /* Sstc only */
89 CSR_CLASS_SSTC_AND_H
, /* Sstc only (with H) */
90 CSR_CLASS_SSTC_32
, /* Sstc RV32 only */
91 CSR_CLASS_SSTC_AND_H_32
, /* Sstc RV32 only (with H) */
94 /* This structure holds all restricted conditions for a CSR. */
95 struct riscv_csr_extra
97 /* Class to which this CSR belongs. Used to decide whether or
98 not this CSR is legal in the current -march context. */
99 enum riscv_csr_class csr_class
;
101 /* CSR may have differnet numbers in the previous priv spec. */
104 /* Record the CSR is defined/valid in which versions. */
105 enum riscv_spec_class define_version
;
107 /* Record the CSR is aborted/invalid from which versions. If it isn't
108 aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */
109 enum riscv_spec_class abort_version
;
111 /* The CSR may have more than one setting. */
112 struct riscv_csr_extra
*next
;
115 /* This structure contains information about errors that occur within the
117 struct riscv_ip_error
119 /* General error message */
122 /* Statement that caused the error */
125 /* Missing extension that needs to be enabled */
126 const char* missing_ext
;
130 #define DEFAULT_ARCH "riscv64"
133 #ifndef DEFAULT_RISCV_ATTR
134 #define DEFAULT_RISCV_ATTR 0
137 /* Let riscv_after_parse_args set the default value according to xlen. */
138 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
139 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
142 /* Need to sync the version with RISC-V compiler. */
143 #ifndef DEFAULT_RISCV_ISA_SPEC
144 #define DEFAULT_RISCV_ISA_SPEC "20191213"
147 #ifndef DEFAULT_RISCV_PRIV_SPEC
148 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
151 static const char default_arch
[] = DEFAULT_ARCH
;
152 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
153 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
154 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
156 static unsigned xlen
= 0; /* The width of an x-register. */
157 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
158 static bool rve_abi
= false;
161 FLOAT_ABI_DEFAULT
= -1,
167 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
169 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
170 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
172 static unsigned elf_flags
= 0;
174 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
175 Otherwise, return 1. */
178 riscv_set_default_isa_spec (const char *s
)
180 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
181 RISCV_GET_ISA_SPEC_CLASS (s
, class);
182 if (class == ISA_SPEC_CLASS_NONE
)
184 as_bad ("unknown default ISA spec `%s' set by "
185 "-misa-spec or --with-isa-spec", s
);
189 default_isa_spec
= class;
193 /* Set the default_priv_spec. Find the privileged elf attributes when
194 the input string is NULL. Return 0 if the spec isn't supported.
195 Otherwise, return 1. */
198 riscv_set_default_priv_spec (const char *s
)
200 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
201 unsigned major
, minor
, revision
;
204 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
205 if (class != PRIV_SPEC_CLASS_NONE
)
207 default_priv_spec
= class;
213 as_bad (_("unknown default privileged spec `%s' set by "
214 "-mpriv-spec or --with-priv-spec"), s
);
218 /* Set the default_priv_spec by the privileged elf attributes. */
219 attr
= elf_known_obj_attributes_proc (stdoutput
);
220 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
221 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
222 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
223 /* Version 0.0.0 is the default value and meningless. */
224 if (major
== 0 && minor
== 0 && revision
== 0)
227 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
228 if (class != PRIV_SPEC_CLASS_NONE
)
230 default_priv_spec
= class;
234 /* Still can not find the privileged spec class. */
235 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
236 "privileged elf attributes"), major
, minor
, revision
);
240 /* This is the set of options which the .option pseudo-op may modify. */
241 struct riscv_set_options
243 int pic
; /* Generate position-independent code. */
244 int rvc
; /* Generate RVC code. */
245 int relax
; /* Emit relocs the linker is allowed to relax. */
246 int arch_attr
; /* Emit architecture and privileged elf attributes. */
247 int csr_check
; /* Enable the CSR checking. */
250 static struct riscv_set_options riscv_opts
=
255 DEFAULT_RISCV_ATTR
, /* arch_attr */
259 /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag
260 for elf_flags once we have enabled c extension. */
263 riscv_set_rvc (bool rvc_value
)
266 elf_flags
|= EF_RISCV_RVC
;
268 riscv_opts
.rvc
= rvc_value
;
271 /* Turn on the tso flag for elf_flags once we have enabled ztso extension. */
276 elf_flags
|= EF_RISCV_TSO
;
279 /* The linked list hanging off of .subsets_list records all enabled extensions,
280 which are parsed from the architecture string. The architecture string can
281 be set by the -march option, the elf architecture attributes, and the
282 --with-arch configure option. */
283 static riscv_parse_subset_t riscv_rps_as
=
285 NULL
, /* subset_list, we will set it later once
286 riscv_opts_stack is created or updated. */
287 as_bad
, /* error_handler. */
289 &default_isa_spec
, /* isa_spec. */
290 true, /* check_unknown_prefixed_ext. */
293 /* Update the architecture string in the subset_list. */
296 riscv_reset_subsets_list_arch_str (void)
298 riscv_subset_list_t
*subsets
= riscv_rps_as
.subset_list
;
299 if (subsets
->arch_str
!= NULL
)
300 free ((void *) subsets
->arch_str
);
301 subsets
->arch_str
= riscv_arch_str (xlen
, subsets
);
304 /* This structure is used to hold a stack of .option values. */
305 struct riscv_option_stack
307 struct riscv_option_stack
*next
;
308 struct riscv_set_options options
;
309 riscv_subset_list_t
*subset_list
;
312 static struct riscv_option_stack
*riscv_opts_stack
= NULL
;
314 /* Set which ISA and extensions are available. */
317 riscv_set_arch (const char *s
)
319 if (s
!= NULL
&& strcmp (s
, "") == 0)
321 as_bad (_("the architecture string of -march and elf architecture "
322 "attributes cannot be empty"));
326 if (riscv_rps_as
.subset_list
== NULL
)
328 riscv_rps_as
.subset_list
= XNEW (riscv_subset_list_t
);
329 riscv_rps_as
.subset_list
->head
= NULL
;
330 riscv_rps_as
.subset_list
->tail
= NULL
;
331 riscv_rps_as
.subset_list
->arch_str
= NULL
;
333 riscv_release_subset_list (riscv_rps_as
.subset_list
);
334 riscv_parse_subset (&riscv_rps_as
, s
);
335 riscv_reset_subsets_list_arch_str ();
337 riscv_set_rvc (false);
338 if (riscv_subset_supports (&riscv_rps_as
, "c"))
339 riscv_set_rvc (true);
341 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
345 /* Indicate -mabi option is explictly set. */
346 static bool explicit_mabi
= false;
348 /* Set the abi information. */
351 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
354 float_abi
= new_float_abi
;
358 /* If the -mabi option isn't set, then set the abi according to the
359 ISA string. Otherwise, check if there is any conflict. */
362 riscv_set_abi_by_arch (void)
366 if (riscv_subset_supports (&riscv_rps_as
, "q"))
367 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
368 else if (riscv_subset_supports (&riscv_rps_as
, "d"))
369 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
370 else if (riscv_subset_supports (&riscv_rps_as
, "e"))
371 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, true);
373 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
377 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
379 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
380 else if (abi_xlen
< xlen
)
381 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
383 if (riscv_subset_supports (&riscv_rps_as
, "e") && !rve_abi
)
384 as_bad ("only the ilp32e ABI is supported for e extension");
386 if (float_abi
== FLOAT_ABI_SINGLE
387 && !riscv_subset_supports (&riscv_rps_as
, "f"))
388 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
390 else if (float_abi
== FLOAT_ABI_DOUBLE
391 && !riscv_subset_supports (&riscv_rps_as
, "d"))
392 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
394 else if (float_abi
== FLOAT_ABI_QUAD
395 && !riscv_subset_supports (&riscv_rps_as
, "q"))
396 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
400 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
401 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
402 elf_flags
|= float_abi
<< 1;
405 elf_flags
|= EF_RISCV_RVE
;
408 /* Handle of the OPCODE hash table. */
409 static htab_t op_hash
= NULL
;
411 /* Handle of the type of .insn hash table. */
412 static htab_t insn_type_hash
= NULL
;
414 /* This array holds the chars that always start a comment. If the
415 pre-processor is disabled, these aren't very useful. */
416 const char comment_chars
[] = "#";
418 /* This array holds the chars that only start a comment at the beginning of
419 a line. If the line seems to have the form '# 123 filename'
420 .line and .file directives will appear in the pre-processed output
422 Note that input_file.c hand checks for '#' at the beginning of the
423 first line of the input file. This is because the compiler outputs
424 #NO_APP at the beginning of its output.
426 Also note that C style comments are always supported. */
427 const char line_comment_chars
[] = "#";
429 /* This array holds machine specific line separator characters. */
430 const char line_separator_chars
[] = ";";
432 /* Chars that can be used to separate mant from exp in floating point nums. */
433 const char EXP_CHARS
[] = "eE";
435 /* Chars that mean this number is a floating point constant.
436 As in 0f12.456 or 0d1.2345e12. */
437 const char FLT_CHARS
[] = "rRsSfFdDxXpPhH";
439 /* Indicate we are already assemble any instructions or not. */
440 static bool start_assemble
= false;
442 /* Indicate ELF attributes are explicitly set. */
443 static bool explicit_attr
= false;
445 /* Indicate CSR or priv instructions are explicitly used. */
446 static bool explicit_priv_attr
= false;
448 static char *expr_end
;
450 /* Macros for encoding relaxation state for RVC branches and far jumps. */
451 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
454 | ((uncond) ? 1 : 0) \
457 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
458 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
459 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
460 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
462 /* Is the given value a sign-extended 32-bit value? */
463 #define IS_SEXT_32BIT_NUM(x) \
464 (((x) &~ (offsetT) 0x7fffffff) == 0 \
465 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
467 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
468 #define IS_ZEXT_32BIT_NUM(x) \
469 (((x) &~ (offsetT) 0xffffffff) == 0 \
470 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
472 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
473 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
474 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
475 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
477 #define INSERT_IMM(n, s, INSN, VALUE) \
478 INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s)
480 /* Determine if an instruction matches an opcode. */
481 #define OPCODE_MATCHES(OPCODE, OP) \
482 (((OPCODE) & MASK_##OP) == MATCH_##OP)
484 /* Create a new mapping symbol for the transition to STATE. */
487 make_mapping_symbol (enum riscv_seg_mstate state
,
490 const char *arch_str
,
491 bool odd_data_padding
)
501 if (arch_str
!= NULL
)
503 size_t size
= strlen (arch_str
) + 3; /* "$x" + '\0' */
504 buff
= xmalloc (size
);
505 snprintf (buff
, size
, "$x%s", arch_str
);
515 symbolS
*symbol
= symbol_new (name
, now_seg
, frag
, value
);
516 symbol_get_bfdsym (symbol
)->flags
|= (BSF_NO_FLAGS
| BSF_LOCAL
);
517 if (arch_str
!= NULL
)
519 /* Store current $x+arch into tc_segment_info. */
520 seg_info (now_seg
)->tc_segment_info_data
.arch_map_symbol
= symbol
;
521 xfree ((void *) buff
);
524 /* If .fill or other data filling directive generates zero sized data,
525 then mapping symbol for the following code will have the same value.
527 Please see gas/testsuite/gas/riscv/mapping.s: .text.zero.fill.first
528 and .text.zero.fill.last. */
529 symbolS
*first
= frag
->tc_frag_data
.first_map_symbol
;
530 symbolS
*last
= frag
->tc_frag_data
.last_map_symbol
;
531 symbolS
*removed
= NULL
;
536 know (S_GET_VALUE (first
) == S_GET_VALUE (symbol
)
538 /* Remove the old one. */
541 frag
->tc_frag_data
.first_map_symbol
= symbol
;
543 else if (last
!= NULL
)
545 /* The mapping symbols should be added in offset order. */
546 know (S_GET_VALUE (last
) <= S_GET_VALUE (symbol
));
547 /* Remove the old one. */
548 if (S_GET_VALUE (last
) == S_GET_VALUE (symbol
))
551 frag
->tc_frag_data
.last_map_symbol
= symbol
;
556 if (odd_data_padding
)
558 /* If the removed mapping symbol is $x+arch, then add it back to
560 const char *str
= strncmp (S_GET_NAME (removed
), "$xrv", 4) == 0
561 ? S_GET_NAME (removed
) + 2 : NULL
;
562 make_mapping_symbol (MAP_INSN
, frag
->fr_fix
+ 1, frag
, str
,
563 false/* odd_data_padding */);
565 symbol_remove (removed
, &symbol_rootP
, &symbol_lastP
);
568 /* Set the mapping state for frag_now. */
571 riscv_mapping_state (enum riscv_seg_mstate to_state
,
575 enum riscv_seg_mstate from_state
=
576 seg_info (now_seg
)->tc_segment_info_data
.map_state
;
577 bool reset_seg_arch_str
= false;
579 if (!SEG_NORMAL (now_seg
)
580 /* For now we only add the mapping symbols to text sections.
581 Therefore, the dis-assembler only show the actual contents
582 distribution for text. Other sections will be shown as
583 data without the details. */
584 || !subseg_text_p (now_seg
))
587 /* The mapping symbol should be emitted if not in the right
589 symbolS
*seg_arch_symbol
=
590 seg_info (now_seg
)->tc_segment_info_data
.arch_map_symbol
;
591 if (to_state
== MAP_INSN
&& seg_arch_symbol
== 0)
593 /* Always add $x+arch at the first instruction of section. */
594 reset_seg_arch_str
= true;
596 else if (seg_arch_symbol
!= 0
597 && to_state
== MAP_INSN
599 && strcmp (riscv_rps_as
.subset_list
->arch_str
,
600 S_GET_NAME (seg_arch_symbol
) + 2) != 0)
602 reset_seg_arch_str
= true;
604 else if (from_state
== to_state
)
607 valueT value
= (valueT
) (frag_now_fix () - max_chars
);
608 seg_info (now_seg
)->tc_segment_info_data
.map_state
= to_state
;
609 const char *arch_str
= reset_seg_arch_str
610 ? riscv_rps_as
.subset_list
->arch_str
: NULL
;
611 make_mapping_symbol (to_state
, value
, frag_now
, arch_str
,
612 false/* odd_data_padding */);
615 /* Add the odd bytes of paddings for riscv_handle_align. */
618 riscv_add_odd_padding_symbol (fragS
*frag
)
620 /* If there was already a mapping symbol, it should be
621 removed in the make_mapping_symbol.
623 Please see gas/testsuite/gas/riscv/mapping.s: .text.odd.align.*. */
624 make_mapping_symbol (MAP_DATA
, frag
->fr_fix
, frag
,
625 NULL
/* arch_str */, true/* odd_data_padding */);
628 /* Remove any excess mapping symbols generated for alignment frags in
629 SEC. We may have created a mapping symbol before a zero byte
630 alignment; remove it if there's a mapping symbol after the
634 riscv_check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
,
636 void *dummy ATTRIBUTE_UNUSED
)
638 segment_info_type
*seginfo
= seg_info (sec
);
641 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
644 for (fragp
= seginfo
->frchainP
->frch_root
;
646 fragp
= fragp
->fr_next
)
648 symbolS
*last
= fragp
->tc_frag_data
.last_map_symbol
;
649 fragS
*next
= fragp
->fr_next
;
651 if (last
== NULL
|| next
== NULL
)
654 /* Check the last mapping symbol if it is at the boundary of
656 if (S_GET_VALUE (last
) < next
->fr_address
)
658 know (S_GET_VALUE (last
) == next
->fr_address
);
662 symbolS
*next_first
= next
->tc_frag_data
.first_map_symbol
;
663 if (next_first
!= NULL
)
665 /* The last mapping symbol overlaps with another one
666 which at the start of the next frag.
668 Please see the gas/testsuite/gas/riscv/mapping.s:
669 .text.zero.fill.align.A and .text.zero.fill.align.B. */
670 know (S_GET_VALUE (last
) == S_GET_VALUE (next_first
));
671 symbolS
*removed
= last
;
672 if (strncmp (S_GET_NAME (last
), "$xrv", 4) == 0
673 && strcmp (S_GET_NAME (next_first
), "$x") == 0)
674 removed
= next_first
;
675 symbol_remove (removed
, &symbol_rootP
, &symbol_lastP
);
679 if (next
->fr_next
== NULL
)
681 /* The last mapping symbol is at the end of the section.
683 Please see the gas/testsuite/gas/riscv/mapping.s:
684 .text.last.section. */
685 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
686 symbol_remove (last
, &symbol_rootP
, &symbol_lastP
);
690 /* Since we may have empty frags without any mapping symbols,
691 keep looking until the non-empty frag. */
692 if (next
->fr_address
!= next
->fr_next
->fr_address
)
695 next
= next
->fr_next
;
697 while (next
!= NULL
);
701 /* The default target format to use. */
704 riscv_target_format (void)
706 if (target_big_endian
)
707 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
709 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
712 /* Return the length of instruction INSN. */
714 static inline unsigned int
715 insn_length (const struct riscv_cl_insn
*insn
)
717 return riscv_insn_length (insn
->insn_opcode
);
720 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
723 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
726 insn
->insn_opcode
= mo
->match
;
727 insn
->insn_long_opcode
[0] = 0;
733 /* Install INSN at the location specified by its "frag" and "where" fields. */
736 install_insn (const struct riscv_cl_insn
*insn
)
738 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
739 if (insn
->insn_long_opcode
[0] != 0)
740 memcpy (f
, insn
->insn_long_opcode
, insn_length (insn
));
742 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
745 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
746 and install the opcode in the new location. */
749 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
753 if (insn
->fixp
!= NULL
)
755 insn
->fixp
->fx_frag
= frag
;
756 insn
->fixp
->fx_where
= where
;
761 /* Add INSN to the end of the output. */
764 add_fixed_insn (struct riscv_cl_insn
*insn
)
766 char *f
= frag_more (insn_length (insn
));
767 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
771 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
772 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
774 frag_grow (max_chars
);
775 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
776 frag_var (rs_machine_dependent
, max_chars
, var
,
777 subtype
, symbol
, offset
, NULL
);
780 /* Compute the length of a branch sequence, and adjust the stored length
781 accordingly. If FRAGP is NULL, the worst-case length is returned. */
784 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
786 int jump
, rvc
, length
= 8;
791 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
792 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
793 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
795 /* Assume jumps are in range; the linker will catch any that aren't. */
796 length
= jump
? 4 : 8;
798 if (fragp
->fr_symbol
!= NULL
799 && S_IS_DEFINED (fragp
->fr_symbol
)
800 && !S_IS_WEAK (fragp
->fr_symbol
)
801 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
803 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
804 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
805 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
807 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
809 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
811 else if (!jump
&& rvc
)
816 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
821 /* Information about an opcode name, mnemonics and its value. */
828 /* List for all supported opcode name. */
829 static const struct opcode_name_t opcode_name_list
[] =
874 /* Hash table for lookup opcode name. */
875 static htab_t opcode_names_hash
= NULL
;
877 /* Initialization for hash table of opcode name. */
880 init_opcode_names_hash (void)
882 const struct opcode_name_t
*opcode
;
884 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
885 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
886 as_fatal (_("internal: duplicate %s"), opcode
->name
);
889 /* Find `s` is a valid opcode name or not, return the opcode name info
892 static const struct opcode_name_t
*
893 opcode_name_lookup (char **s
)
897 struct opcode_name_t
*o
;
899 /* Find end of name. */
901 if (is_name_beginner (*e
))
903 while (is_part_of_name (*e
))
906 /* Terminate name. */
910 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
912 /* Advance to next token if one was recognized. */
922 /* All RISC-V registers belong to one of these classes. */
934 static htab_t reg_names_hash
= NULL
;
935 static htab_t csr_extra_hash
= NULL
;
937 #define ENCODE_REG_HASH(cls, n) \
938 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
939 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
940 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
943 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
945 void *hash
= ENCODE_REG_HASH (class, n
);
946 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
947 as_fatal (_("internal: duplicate %s"), name
);
951 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
955 for (i
= 0; i
< n
; i
++)
956 hash_reg_name (class, names
[i
], i
);
959 /* Init hash table csr_extra_hash to handle CSR. */
962 riscv_init_csr_hash (const char *name
,
964 enum riscv_csr_class
class,
965 enum riscv_spec_class define_version
,
966 enum riscv_spec_class abort_version
)
968 struct riscv_csr_extra
*entry
, *pre_entry
;
969 bool need_enrty
= true;
972 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
973 while (need_enrty
&& entry
!= NULL
)
975 if (entry
->csr_class
== class
976 && entry
->address
== address
977 && entry
->define_version
== define_version
978 && entry
->abort_version
== abort_version
)
988 entry
= notes_alloc (sizeof (*entry
));
989 entry
->csr_class
= class;
990 entry
->address
= address
;
991 entry
->define_version
= define_version
;
992 entry
->abort_version
= abort_version
;
995 if (pre_entry
== NULL
)
996 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
998 pre_entry
->next
= entry
;
1001 /* Return the CSR address after checking the ISA dependency and
1002 the privileged spec version.
1004 There are one warning and two errors for CSR,
1006 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
1007 or the privileged spec, report warning only if -mcsr-check is set.
1008 Unknown CSR: the CSR has never been defined, report error.
1009 Improper CSR: the CSR number over the range (> 0xfff), report error. */
1012 riscv_csr_address (const char *csr_name
,
1013 struct riscv_csr_extra
*entry
)
1015 struct riscv_csr_extra
*saved_entry
= entry
;
1016 enum riscv_csr_class csr_class
= entry
->csr_class
;
1017 bool need_check_version
= false;
1018 bool is_rv32_only
= false;
1019 bool is_h_required
= false;
1020 const char* extension
= NULL
;
1024 case CSR_CLASS_I_32
:
1025 is_rv32_only
= true;
1028 need_check_version
= true;
1031 case CSR_CLASS_H_32
:
1032 is_rv32_only
= true;
1044 extension
= "zve32x";
1046 case CSR_CLASS_SMAIA_32
:
1047 is_rv32_only
= true;
1049 case CSR_CLASS_SMAIA
:
1050 extension
= "smaia";
1052 case CSR_CLASS_SMSTATEEN_32
:
1053 is_rv32_only
= true;
1055 case CSR_CLASS_SMSTATEEN
:
1056 extension
= "smstateen";
1058 case CSR_CLASS_SSAIA
:
1059 case CSR_CLASS_SSAIA_AND_H
:
1060 case CSR_CLASS_SSAIA_32
:
1061 case CSR_CLASS_SSAIA_AND_H_32
:
1062 is_rv32_only
= (csr_class
== CSR_CLASS_SSAIA_32
1063 || csr_class
== CSR_CLASS_SSAIA_AND_H_32
);
1064 is_h_required
= (csr_class
== CSR_CLASS_SSAIA_AND_H
1065 || csr_class
== CSR_CLASS_SSAIA_AND_H_32
);
1066 extension
= "ssaia";
1068 case CSR_CLASS_SSSTATEEN_AND_H_32
:
1069 is_rv32_only
= true;
1071 case CSR_CLASS_SSSTATEEN_AND_H
:
1072 is_h_required
= true;
1074 case CSR_CLASS_SSSTATEEN
:
1075 extension
= "ssstateen";
1077 case CSR_CLASS_SSCOFPMF_32
:
1078 is_rv32_only
= true;
1080 case CSR_CLASS_SSCOFPMF
:
1081 extension
= "sscofpmf";
1083 case CSR_CLASS_SSTC
:
1084 case CSR_CLASS_SSTC_AND_H
:
1085 case CSR_CLASS_SSTC_32
:
1086 case CSR_CLASS_SSTC_AND_H_32
:
1087 is_rv32_only
= (csr_class
== CSR_CLASS_SSTC_32
1088 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
1089 is_h_required
= (csr_class
== CSR_CLASS_SSTC_AND_H
1090 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
1093 case CSR_CLASS_DEBUG
:
1096 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
1099 if (riscv_opts
.csr_check
)
1101 if (is_rv32_only
&& xlen
!= 32)
1102 as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name
);
1103 if (is_h_required
&& !riscv_subset_supports (&riscv_rps_as
, "h"))
1104 as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name
);
1106 if (extension
!= NULL
1107 && !riscv_subset_supports (&riscv_rps_as
, extension
))
1108 as_warn (_("invalid CSR `%s', needs `%s' extension"),
1109 csr_name
, extension
);
1112 while (entry
!= NULL
)
1114 if (!need_check_version
1115 || (default_priv_spec
>= entry
->define_version
1116 && default_priv_spec
< entry
->abort_version
))
1118 /* Find the CSR according to the specific version. */
1119 return entry
->address
;
1121 entry
= entry
->next
;
1124 /* Can not find the CSR address from the chosen privileged version,
1125 so use the newly defined value. */
1126 if (riscv_opts
.csr_check
)
1128 const char *priv_name
= NULL
;
1129 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
1130 if (priv_name
!= NULL
)
1131 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
1132 csr_name
, priv_name
);
1135 return saved_entry
->address
;
1138 /* Return -1 if the CSR has never been defined. Otherwise, return
1142 reg_csr_lookup_internal (const char *s
)
1144 struct riscv_csr_extra
*r
=
1145 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
1150 return riscv_csr_address (s
, r
);
1154 reg_lookup_internal (const char *s
, enum reg_class
class)
1158 if (class == RCLASS_CSR
)
1159 return reg_csr_lookup_internal (s
);
1161 r
= str_hash_find (reg_names_hash
, s
);
1162 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
1165 if (riscv_subset_supports (&riscv_rps_as
, "e")
1166 && class == RCLASS_GPR
1167 && DECODE_REG_NUM (r
) > 15)
1170 return DECODE_REG_NUM (r
);
1174 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
1180 /* Find end of name. */
1182 if (is_name_beginner (*e
))
1184 while (is_part_of_name (*e
))
1187 /* Terminate name. */
1191 /* Look for the register. Advance to next token if one was recognized. */
1192 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
1202 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
1204 const char *p
= strchr (*s
, ',');
1205 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
1210 for (i
= 0; i
< size
; i
++)
1211 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0
1212 && array
[i
][len
] == '\0')
1222 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1223 #define USE_IMM(n, s) \
1224 (used_bits |= ((insn_t)((1ull<<n)-1) << (s)))
1226 /* For consistency checking, verify that all bits are specified either
1227 by the match/mask part of the instruction definition, or by the
1228 operand list. The `length` could be the actual instruction length or
1229 0 for auto-detection. */
1232 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
1234 const char *oparg
, *opargStart
;
1235 insn_t used_bits
= opc
->mask
;
1237 insn_t required_bits
;
1240 length
= riscv_insn_length (opc
->match
);
1241 /* We don't support instructions longer than 64-bits yet. */
1244 insn_width
= 8 * length
;
1246 required_bits
= ((insn_t
)~0ULL) >> (64 - insn_width
);
1248 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1250 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1251 opc
->name
, opc
->args
);
1255 for (oparg
= opc
->args
; *oparg
; ++oparg
)
1263 case 'U': break; /* CRS1, constrained to equal RD. */
1264 case 'c': break; /* CRS1, constrained to equal sp. */
1265 case 'T': /* CRS2, floating point. */
1266 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1267 case 'S': /* CRS1S, floating point. */
1268 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1269 case 'w': break; /* CRS1S, constrained to equal RD. */
1270 case 'D': /* CRS2S, floating point. */
1271 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1272 case 'x': break; /* CRS2S, constrained to equal RD. */
1273 case 'z': break; /* CRS2S, constrained to be x0. */
1274 case '>': /* CITYPE immediate, compressed shift. */
1275 case 'u': /* CITYPE immediate, compressed lui. */
1276 case 'v': /* CITYPE immediate, li to compressed lui. */
1277 case 'o': /* CITYPE immediate, allow zero. */
1278 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1279 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1280 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1281 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1282 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1283 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1284 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1285 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1286 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1287 /* CLTYPE and CSTYPE have the same immediate encoding. */
1288 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1289 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1290 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1291 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1292 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1293 case 'F': /* Compressed funct for .insn directive. */
1296 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1297 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1298 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1299 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1301 goto unknown_validate_operand
;
1305 goto unknown_validate_operand
;
1307 break; /* end RVC */
1312 case 'f': USE_BITS (OP_MASK_VD
, OP_SH_VD
); break;
1313 case 'e': USE_BITS (OP_MASK_VWD
, OP_SH_VWD
); break;
1314 case 's': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
); break;
1315 case 't': USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1316 case 'u': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1317 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1318 case 'v': USE_BITS (OP_MASK_VD
, OP_SH_VD
);
1319 USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1320 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1322 case 'b': used_bits
|= ENCODE_RVV_VB_IMM (-1U); break;
1323 case 'c': used_bits
|= ENCODE_RVV_VC_IMM (-1U); break;
1326 case 'k': USE_BITS (OP_MASK_VIMM
, OP_SH_VIMM
); break;
1327 case 'm': USE_BITS (OP_MASK_VMASK
, OP_SH_VMASK
); break;
1328 case 'M': break; /* Macro operand, must be a mask register. */
1329 case 'T': break; /* Macro operand, must be a vector register. */
1331 goto unknown_validate_operand
;
1333 break; /* end RVV */
1337 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1338 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1339 case 'A': break; /* Macro operand, must be symbol. */
1340 case 'B': break; /* Macro operand, must be symbol or constant. */
1341 case 'c': break; /* Macro operand, must be symbol or constant. */
1342 case 'I': break; /* Macro operand, must be constant. */
1343 case 'D': /* RD, floating point. */
1344 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1345 case 'y': USE_BITS (OP_MASK_BS
, OP_SH_BS
); break;
1346 case 'Y': USE_BITS (OP_MASK_RNUM
, OP_SH_RNUM
); break;
1347 case 'Z': /* RS1, CSR number. */
1348 case 'S': /* RS1, floating point. */
1349 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1350 case 'U': /* RS1 and RS2 are the same, floating point. */
1351 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1353 case 'T': /* RS2, floating point. */
1354 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1355 case 'R': /* RS3, floating point. */
1356 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1357 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1358 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1359 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1360 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1361 case 'o': /* ITYPE immediate, load displacement. */
1362 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1363 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1364 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1365 case 'f': /* Fall through. */
1366 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1367 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1368 case 'z': break; /* Zero immediate. */
1369 case '[': break; /* Unused operand. */
1370 case ']': break; /* Unused operand. */
1371 case '0': break; /* AMO displacement, must to zero. */
1372 case '1': break; /* Relaxation operand. */
1373 case 'F': /* Funct for .insn directive. */
1376 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1377 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1378 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1380 goto unknown_validate_operand
;
1383 case 'O': /* Opcode for .insn directive. */
1386 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1387 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1389 goto unknown_validate_operand
;
1392 case 'X': /* Integer immediate. */
1399 case 'l': /* Literal. */
1400 oparg
+= strcspn(oparg
, ",") - 1;
1402 case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
1404 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
1407 n
= strtol (oparg
+ 1, (char **)&oparg
, 10);
1409 goto unknown_validate_operand
;
1410 s
= strtol (oparg
+ 1, (char **)&oparg
, 10);
1416 goto unknown_validate_operand
;
1421 unknown_validate_operand
:
1422 as_bad (_("internal: bad RISC-V opcode "
1423 "(unknown operand type `%s'): %s %s"),
1424 opargStart
, opc
->name
, opc
->args
);
1429 if (used_bits
!= required_bits
)
1431 as_bad (_("internal: bad RISC-V opcode "
1432 "(bits %#llx undefined or invalid): %s %s"),
1433 (unsigned long long)(used_bits
^ required_bits
),
1434 opc
->name
, opc
->args
);
1442 struct percent_op_match
1445 bfd_reloc_code_real_type reloc
;
1448 /* Common hash table initialization function for instruction and .insn
1452 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1453 bool insn_directive_p
)
1457 htab_t hash
= str_htab_create ();
1458 while (opcodes
[i
].name
)
1460 const char *name
= opcodes
[i
].name
;
1461 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1462 as_fatal (_("internal: duplicate %s"), name
);
1466 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1468 if (insn_directive_p
)
1469 length
= ((name
[0] == 'c') ? 2 : 4);
1471 length
= 0; /* Let assembler determine the length. */
1472 if (!validate_riscv_insn (&opcodes
[i
], length
))
1473 as_fatal (_("internal: broken assembler. "
1474 "No assembly attempted"));
1477 gas_assert (!insn_directive_p
);
1480 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1486 /* This function is called once, at assembler startup time. It should set up
1487 all the tables, etc. that the MD part of the assembler will need. */
1492 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1494 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1495 as_warn (_("could not set architecture and machine"));
1497 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1498 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1500 reg_names_hash
= str_htab_create ();
1501 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1502 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1503 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1504 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1505 hash_reg_names (RCLASS_VECR
, riscv_vecr_names_numeric
, NVECR
);
1506 hash_reg_names (RCLASS_VECM
, riscv_vecm_names_numeric
, NVECM
);
1507 /* Add "fp" as an alias for "s0". */
1508 hash_reg_name (RCLASS_GPR
, "fp", 8);
1510 /* Create and insert CSR hash tables. */
1511 csr_extra_hash
= str_htab_create ();
1512 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1513 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1514 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1515 DECLARE_CSR(name, num, class, define_version, abort_version);
1516 #include "opcode/riscv-opc.h"
1519 opcode_names_hash
= str_htab_create ();
1520 init_opcode_names_hash ();
1522 /* Set the default alignment for the text section. */
1523 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1527 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1534 case BFD_RELOC_RISCV_HI20
:
1535 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1537 case BFD_RELOC_RISCV_LO12_S
:
1538 return ENCODE_STYPE_IMM (value
);
1540 case BFD_RELOC_RISCV_LO12_I
:
1541 return ENCODE_ITYPE_IMM (value
);
1548 /* Output an instruction. IP is the instruction information.
1549 ADDRESS_EXPR is an operand of the instruction to be used with
1553 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1554 bfd_reloc_code_real_type reloc_type
)
1556 dwarf2_emit_insn (0);
1558 if (reloc_type
!= BFD_RELOC_UNUSED
)
1560 reloc_howto_type
*howto
;
1562 gas_assert (address_expr
);
1563 if (reloc_type
== BFD_RELOC_12_PCREL
1564 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1566 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1567 int best_case
= insn_length (ip
);
1568 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1570 if (now_seg
== absolute_section
)
1572 as_bad (_("relaxable branches not supported in absolute section"));
1576 add_relaxed_insn (ip
, worst_case
, best_case
,
1577 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1578 address_expr
->X_add_symbol
,
1579 address_expr
->X_add_number
);
1584 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1586 as_bad (_("internal: unsupported RISC-V relocation number %d"),
1589 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1590 bfd_get_reloc_size (howto
),
1591 address_expr
, false, reloc_type
);
1593 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1597 add_fixed_insn (ip
);
1599 /* We need to start a new frag after any instruction that can be
1600 optimized away or compressed by the linker during relaxation, to prevent
1601 the assembler from computing static offsets across such an instruction.
1602 This is necessary to get correct EH info. */
1603 if (reloc_type
== BFD_RELOC_RISCV_HI20
1604 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1605 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1606 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1608 frag_wane (frag_now
);
1613 /* Build an instruction created by a macro expansion. This is passed
1614 a pointer to the count of instructions created so far, an expression,
1615 the name of the instruction to build, an operand format string, and
1616 corresponding arguments. */
1619 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1621 const struct riscv_opcode
*mo
;
1622 struct riscv_cl_insn insn
;
1623 bfd_reloc_code_real_type r
;
1625 const char *fmtStart
;
1627 va_start (args
, fmt
);
1629 r
= BFD_RELOC_UNUSED
;
1630 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1633 /* Find a non-RVC variant of the instruction. append_insn will compress
1635 while (riscv_insn_length (mo
->match
) < 4)
1637 gas_assert (strcmp (name
, mo
->name
) == 0);
1639 create_insn (&insn
, mo
);
1649 INSERT_OPERAND (VD
, insn
, va_arg (args
, int));
1652 INSERT_OPERAND (VS1
, insn
, va_arg (args
, int));
1655 INSERT_OPERAND (VS2
, insn
, va_arg (args
, int));
1659 int reg
= va_arg (args
, int);
1662 INSERT_OPERAND (VMASK
, insn
, 1);
1667 INSERT_OPERAND (VMASK
, insn
, 0);
1671 goto unknown_macro_argument
;
1674 goto unknown_macro_argument
;
1679 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1682 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1685 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1691 gas_assert (ep
!= NULL
);
1692 r
= va_arg (args
, int);
1700 unknown_macro_argument
:
1701 as_fatal (_("internal: invalid macro argument `%s'"), fmtStart
);
1706 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1708 append_insn (&insn
, ep
, r
);
1711 /* Build an instruction created by a macro expansion. Like md_assemble but
1712 accept a printf-style format string and arguments. */
1715 md_assemblef (const char *format
, ...)
1721 va_start (ap
, format
);
1723 r
= vasprintf (&buf
, format
, ap
);
1726 as_fatal (_("internal: vasprintf failed"));
1734 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1738 normalize_constant_expr (expressionS
*ex
)
1742 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1743 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1744 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1748 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1749 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1752 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1755 if (ex
->X_op
== O_big
)
1756 as_bad (_("unsupported large constant"));
1757 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1758 as_bad (_("unknown CSR `%s'"),
1759 S_GET_NAME (ex
->X_add_symbol
));
1760 else if (ex
->X_op
!= O_constant
)
1761 as_bad (_("instruction %s requires absolute expression"),
1763 normalize_constant_expr (ex
);
1767 make_internal_label (void)
1769 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1773 /* Load an entry from the GOT. */
1776 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1777 const char *lo_insn
, const char *lo_pattern
,
1778 bfd_reloc_code_real_type hi_reloc
,
1779 bfd_reloc_code_real_type lo_reloc
)
1782 ep2
.X_op
= O_symbol
;
1783 ep2
.X_add_symbol
= make_internal_label ();
1784 ep2
.X_add_number
= 0;
1786 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1787 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1791 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1792 bfd_reloc_code_real_type hi_reloc
,
1793 bfd_reloc_code_real_type lo_reloc
)
1795 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1799 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1800 bfd_reloc_code_real_type hi_reloc
,
1801 bfd_reloc_code_real_type lo_reloc
)
1803 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1806 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1809 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1810 bfd_reloc_code_real_type reloc
)
1812 /* Ensure the jalr is emitted to the same frag as the auipc. */
1814 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1815 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1816 /* See comment at end of append_insn. */
1817 frag_wane (frag_now
);
1821 /* Load an integer constant into a register. */
1824 load_const (int reg
, expressionS
*ep
)
1826 int shift
= RISCV_IMM_BITS
;
1827 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1828 expressionS upper
= *ep
, lower
= *ep
;
1829 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1830 upper
.X_add_number
-= lower
.X_add_number
;
1832 if (ep
->X_op
!= O_constant
)
1834 as_bad (_("unsupported large constant"));
1838 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1840 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1841 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1844 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1845 load_const (reg
, &upper
);
1847 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1848 if (lower
.X_add_number
!= 0)
1849 md_assemblef ("addi x%d, x%d, %" PRId64
, reg
, reg
,
1850 (int64_t) lower
.X_add_number
);
1854 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1857 if (upper
.X_add_number
!= 0)
1859 /* Discard low part and zero-extend upper immediate. */
1860 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1862 md_assemblef ("lui x%d, 0x%" PRIx64
, reg
, (uint64_t) upper_imm
);
1866 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1867 md_assemblef ("%s x%d, x%d, %" PRId64
, ADD32_INSN
, reg
, hi_reg
,
1868 (int64_t) lower
.X_add_number
);
1872 /* Zero extend and sign extend byte/half-word/word. */
1875 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1879 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1880 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1884 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1885 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1889 /* Expand RISC-V Vector macros into one or more instructions. */
1892 vector_macro (struct riscv_cl_insn
*ip
)
1894 int vd
= (ip
->insn_opcode
>> OP_SH_VD
) & OP_MASK_VD
;
1895 int vs1
= (ip
->insn_opcode
>> OP_SH_VS1
) & OP_MASK_VS1
;
1896 int vs2
= (ip
->insn_opcode
>> OP_SH_VS2
) & OP_MASK_VS2
;
1897 int vm
= (ip
->insn_opcode
>> OP_SH_VMASK
) & OP_MASK_VMASK
;
1898 int vtemp
= (ip
->insn_opcode
>> OP_SH_VFUNCT6
) & OP_MASK_VFUNCT6
;
1899 int mask
= ip
->insn_mo
->mask
;
1907 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1908 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1913 /* Masked. Have vtemp to avoid overlap constraints. */
1916 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1917 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1921 /* Preserve the value of vd if not updating by vm. */
1922 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1923 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1924 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1925 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1930 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1931 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1932 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1935 as_bad (_("must provide temp if destination overlaps mask"));
1942 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1943 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1948 /* Masked. Have vtemp to avoid overlap constraints. */
1951 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1952 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1956 /* Preserve the value of vd if not updating by vm. */
1957 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1958 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1959 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1960 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1965 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1966 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1967 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1970 as_bad (_("must provide temp if destination overlaps mask"));
1978 /* Expand RISC-V assembly macros into one or more instructions. */
1981 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1982 bfd_reloc_code_real_type
*imm_reloc
)
1984 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1985 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1986 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1987 int mask
= ip
->insn_mo
->mask
;
1992 load_const (rd
, imm_expr
);
1997 /* Load the address of a symbol into a register. */
1998 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1999 as_bad (_("offset too large"));
2001 if (imm_expr
->X_op
== O_constant
)
2002 load_const (rd
, imm_expr
);
2003 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
2004 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
2005 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2006 else /* Local PIC symbol, or any non-PIC symbol. */
2007 pcrel_load (rd
, rd
, imm_expr
, "addi",
2008 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2012 pcrel_load (rd
, rd
, imm_expr
, "addi",
2013 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2017 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
2018 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2022 pcrel_load (rd
, rd
, imm_expr
, "lb",
2023 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2027 pcrel_load (rd
, rd
, imm_expr
, "lbu",
2028 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2032 pcrel_load (rd
, rd
, imm_expr
, "lh",
2033 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2037 pcrel_load (rd
, rd
, imm_expr
, "lhu",
2038 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2042 pcrel_load (rd
, rd
, imm_expr
, "lw",
2043 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2047 pcrel_load (rd
, rd
, imm_expr
, "lwu",
2048 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2052 pcrel_load (rd
, rd
, imm_expr
, "ld",
2053 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2057 pcrel_load (rd
, rs1
, imm_expr
, "flw",
2058 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2062 pcrel_load (rd
, rs1
, imm_expr
, "fld",
2063 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2067 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
2068 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2072 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
2073 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2077 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
2078 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2082 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
2083 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2087 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
2088 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2092 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
2093 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2097 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
2101 riscv_ext (rd
, rs1
, xlen
- 16, false);
2105 riscv_ext (rd
, rs1
, xlen
- 32, false);
2109 riscv_ext (rd
, rs1
, xlen
- 8, true);
2113 riscv_ext (rd
, rs1
, xlen
- 16, true);
2122 pcrel_load (rd
, rs1
, imm_expr
, "flh",
2123 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2126 pcrel_store (rs2
, rs1
, imm_expr
, "fsh",
2127 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2131 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
2136 static const struct percent_op_match percent_op_utype
[] =
2138 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
2139 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
2140 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
2141 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
2142 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
2143 {"%hi", BFD_RELOC_RISCV_HI20
},
2147 static const struct percent_op_match percent_op_itype
[] =
2149 {"%lo", BFD_RELOC_RISCV_LO12_I
},
2150 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
2151 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
2155 static const struct percent_op_match percent_op_stype
[] =
2157 {"%lo", BFD_RELOC_RISCV_LO12_S
},
2158 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
2159 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
2163 static const struct percent_op_match percent_op_rtype
[] =
2165 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
2169 static const struct percent_op_match percent_op_null
[] =
2174 /* Return true if *STR points to a relocation operator. When returning true,
2175 move *STR over the operator and store its relocation code in *RELOC.
2176 Leave both *STR and *RELOC alone when returning false. */
2179 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
2180 const struct percent_op_match
*percent_op
)
2182 for ( ; percent_op
->str
; percent_op
++)
2183 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
2185 int len
= strlen (percent_op
->str
);
2187 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
2190 *str
+= strlen (percent_op
->str
);
2191 *reloc
= percent_op
->reloc
;
2193 /* Check whether the output BFD supports this relocation.
2194 If not, issue an error and fall back on something safe. */
2195 if (*reloc
!= BFD_RELOC_UNUSED
2196 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
2198 as_bad ("internal: relocation %s isn't supported by the "
2199 "current ABI", percent_op
->str
);
2200 *reloc
= BFD_RELOC_UNUSED
;
2208 my_getExpression (expressionS
*ep
, char *str
)
2212 save_in
= input_line_pointer
;
2213 input_line_pointer
= str
;
2215 expr_end
= input_line_pointer
;
2216 input_line_pointer
= save_in
;
2219 /* Parse string STR as a 16-bit relocatable operand. Store the
2220 expression in *EP and the relocation, if any, in RELOC.
2221 Return the number of relocation operators used (0 or 1).
2223 On exit, EXPR_END points to the first character after the expression. */
2226 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2227 char *str
, const struct percent_op_match
*percent_op
)
2230 unsigned crux_depth
, str_depth
, regno
;
2233 /* First, check for integer registers. No callers can accept a reg, but
2234 we need to avoid accidentally creating a useless undefined symbol below,
2235 if this is an instruction pattern that can't match. A glibc build fails
2236 if this is removed. */
2237 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
2239 ep
->X_op
= O_register
;
2240 ep
->X_add_number
= regno
;
2245 /* Search for the start of the main expression.
2247 End the loop with CRUX pointing to the start of the main expression and
2248 with CRUX_DEPTH containing the number of open brackets at that point. */
2255 crux_depth
= str_depth
;
2257 /* Skip over whitespace and brackets, keeping count of the number
2259 while (*str
== ' ' || *str
== '\t' || *str
== '(')
2265 && parse_relocation (&str
, reloc
, percent_op
));
2267 my_getExpression (ep
, crux
);
2270 /* Match every open bracket. */
2271 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
2276 as_bad ("unclosed '('");
2283 /* Parse opcode name, could be an mnemonics or number. */
2286 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2287 char *str
, const struct percent_op_match
*percent_op
)
2289 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
2293 ep
->X_op
= O_constant
;
2294 ep
->X_add_number
= o
->val
;
2298 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
2301 /* Parse string STR as a vsetvli operand. Store the expression in *EP.
2302 On exit, EXPR_END points to the first character after the expression. */
2305 my_getVsetvliExpression (expressionS
*ep
, char *str
)
2307 unsigned int vsew_value
= 0, vlmul_value
= 0;
2308 unsigned int vta_value
= 0, vma_value
= 0;
2309 bfd_boolean vsew_found
= FALSE
, vlmul_found
= FALSE
;
2310 bfd_boolean vta_found
= FALSE
, vma_found
= FALSE
;
2312 if (arg_lookup (&str
, riscv_vsew
, ARRAY_SIZE (riscv_vsew
), &vsew_value
))
2317 as_bad (_("multiple vsew constants"));
2320 if (arg_lookup (&str
, riscv_vlmul
, ARRAY_SIZE (riscv_vlmul
), &vlmul_value
))
2325 as_bad (_("multiple vlmul constants"));
2328 if (arg_lookup (&str
, riscv_vta
, ARRAY_SIZE (riscv_vta
), &vta_value
))
2333 as_bad (_("multiple vta constants"));
2336 if (arg_lookup (&str
, riscv_vma
, ARRAY_SIZE (riscv_vma
), &vma_value
))
2341 as_bad (_("multiple vma constants"));
2345 if (vsew_found
|| vlmul_found
|| vta_found
|| vma_found
)
2347 ep
->X_op
= O_constant
;
2348 ep
->X_add_number
= (vlmul_value
<< OP_SH_VLMUL
)
2349 | (vsew_value
<< OP_SH_VSEW
)
2350 | (vta_value
<< OP_SH_VTA
)
2351 | (vma_value
<< OP_SH_VMA
);
2356 my_getExpression (ep
, str
);
2361 /* Detect and handle implicitly zero load-store offsets. For example,
2362 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such
2363 an implicit offset was detected. */
2366 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
2368 /* Check whether there is only a single bracketed expression left.
2369 If so, it must be the base register and the constant must be zero. */
2370 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
2372 ep
->X_op
= O_constant
;
2373 ep
->X_add_number
= 0;
2380 /* All RISC-V CSR instructions belong to one of these classes. */
2389 /* Return which CSR instruction is checking. */
2391 static enum csr_insn_type
2392 riscv_csr_insn_type (insn_t insn
)
2394 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
2395 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
2397 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
2398 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
2400 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
2401 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
2404 return INSN_NOT_CSR
;
2407 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
2408 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
2409 CSR address is 0x3. */
2412 riscv_csr_read_only_check (insn_t insn
)
2414 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
2415 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
2416 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
2417 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
2420 && (((csr_insn
== INSN_CSRRS
2421 || csr_insn
== INSN_CSRRC
)
2423 || csr_insn
== INSN_CSRRW
))
2429 /* Return true if it is a privileged instruction. Otherwise, return false.
2431 uret is actually a N-ext instruction. So it is better to regard it as
2432 an user instruction rather than the priv instruction.
2434 hret is used to return from traps in H-mode. H-mode is removed since
2435 the v1.10 priv spec, but probably be added in the new hypervisor spec.
2436 Therefore, hret should be controlled by the hypervisor spec rather than
2437 priv spec in the future.
2439 dret is defined in the debug spec, so it should be checked in the future,
2443 riscv_is_priv_insn (insn_t insn
)
2445 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
2446 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
2447 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
2448 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
2449 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
2450 check it here to keep the compatible. */
2451 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
2454 /* This routine assembles an instruction into its binary format. As a
2455 side effect, it sets the global variable imm_reloc to the type of
2456 relocation to do if one of the operands is an address expression. */
2458 static struct riscv_ip_error
2459 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
2460 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
2462 /* The operand string defined in the riscv_opcodes. */
2463 const char *oparg
, *opargStart
;
2464 /* The parsed operands from assembly. */
2465 char *asarg
, *asargStart
;
2467 struct riscv_opcode
*insn
;
2469 const struct percent_op_match
*p
;
2470 struct riscv_ip_error error
;
2471 error
.msg
= "unrecognized opcode";
2472 error
.statement
= str
;
2473 error
.missing_ext
= NULL
;
2474 /* Indicate we are assembling instruction with CSR. */
2475 bool insn_with_csr
= false;
2477 /* Parse the name of the instruction. Terminate the string if whitespace
2478 is found so that str_hash_find only sees the name part of the string. */
2479 for (asarg
= str
; *asarg
!= '\0'; ++asarg
)
2480 if (ISSPACE (*asarg
))
2487 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
2490 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
2492 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
2495 if (!riscv_multi_subset_supports (&riscv_rps_as
, insn
->insn_class
))
2497 error
.missing_ext
= riscv_multi_subset_supports_ext (&riscv_rps_as
,
2502 /* Reset error message of the previous round. */
2503 error
.msg
= _("illegal operands");
2504 error
.missing_ext
= NULL
;
2505 create_insn (ip
, insn
);
2507 imm_expr
->X_op
= O_absent
;
2508 *imm_reloc
= BFD_RELOC_UNUSED
;
2509 p
= percent_op_itype
;
2511 for (oparg
= insn
->args
;; ++oparg
)
2514 asarg
+= strspn (asarg
, " \t");
2517 case '\0': /* End of args. */
2518 if (insn
->pinfo
!= INSN_MACRO
)
2520 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2523 /* For .insn, insn->match and insn->mask are 0. */
2524 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2530 if (riscv_is_priv_insn (ip
->insn_opcode
))
2531 explicit_priv_attr
= true;
2533 /* Check if we write a read-only CSR by the CSR
2536 && riscv_opts
.csr_check
2537 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2539 /* Restore the character in advance, since we want to
2540 report the detailed warning message here. */
2542 *(asargStart
- 1) = save_c
;
2543 as_warn (_("read-only CSR is written `%s'"), str
);
2544 insn_with_csr
= false;
2547 /* The (segmant) load and store with EEW 64 cannot be used
2548 when zve32x is enabled. */
2549 if (ip
->insn_mo
->pinfo
& INSN_V_EEW64
2550 && riscv_subset_supports (&riscv_rps_as
, "zve32x")
2551 && !riscv_subset_supports (&riscv_rps_as
, "zve64x"))
2553 error
.msg
= _("illegal opcode for zve32x");
2559 /* Successful assembly. */
2561 insn_with_csr
= false;
2567 case 's': /* RS1 x8-x15. */
2568 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2569 || !(regno
>= 8 && regno
<= 15))
2571 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2573 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2574 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2575 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2578 case 't': /* RS2 x8-x15. */
2579 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2580 || !(regno
>= 8 && regno
<= 15))
2582 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2584 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2585 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2586 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2589 case 'U': /* RS1, constrained to equal RD. */
2590 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2591 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2595 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
2597 INSERT_OPERAND (CRS2
, *ip
, regno
);
2599 case 'c': /* RS1, constrained to equal sp. */
2600 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2604 case 'z': /* RS2, constrained to equal x0. */
2605 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2609 case '>': /* Shift amount, 0 - (XLEN-1). */
2610 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2611 || imm_expr
->X_op
!= O_constant
2612 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2614 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2617 imm_expr
->X_op
= O_absent
;
2620 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2621 || imm_expr
->X_op
!= O_constant
2622 || imm_expr
->X_add_number
< 0
2623 || imm_expr
->X_add_number
>= 32
2624 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2626 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2629 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2630 || imm_expr
->X_op
!= O_constant
2631 || imm_expr
->X_add_number
< 0
2632 || imm_expr
->X_add_number
>= 64
2633 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2635 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2638 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2639 || imm_expr
->X_op
!= O_constant
2640 || imm_expr
->X_add_number
< 0
2641 || imm_expr
->X_add_number
>= 256
2642 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2644 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2647 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2648 || imm_expr
->X_op
!= O_constant
2649 || imm_expr
->X_add_number
== 0
2650 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2652 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2655 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2657 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2658 || imm_expr
->X_op
!= O_constant
2659 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2661 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2664 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2666 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2667 || imm_expr
->X_op
!= O_constant
2668 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2670 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2673 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2675 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2676 || imm_expr
->X_op
!= O_constant
2677 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2680 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2683 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2685 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2686 || imm_expr
->X_op
!= O_constant
2687 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2690 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2693 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2694 || imm_expr
->X_op
!= O_constant
2695 /* C.addiw, c.li, and c.andi allow zero immediate.
2696 C.addi allows zero immediate as hint. Otherwise this
2698 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2700 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2703 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2704 || imm_expr
->X_op
!= O_constant
2705 || imm_expr
->X_add_number
== 0
2706 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2709 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2712 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2713 || imm_expr
->X_op
!= O_constant
2714 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2717 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2720 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2722 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2723 || imm_expr
->X_op
!= O_constant
2724 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2727 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2730 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2732 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2733 || imm_expr
->X_op
!= O_constant
2734 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2737 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2740 p
= percent_op_utype
;
2741 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
2744 if (imm_expr
->X_op
!= O_constant
2745 || imm_expr
->X_add_number
<= 0
2746 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2747 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2748 && (imm_expr
->X_add_number
<
2749 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2751 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2754 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2755 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2756 || ((int32_t)imm_expr
->X_add_number
2757 != imm_expr
->X_add_number
))
2759 imm_expr
->X_add_number
=
2760 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2766 case 'S': /* Floating-point RS1 x8-x15. */
2767 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2768 || !(regno
>= 8 && regno
<= 15))
2770 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2772 case 'D': /* Floating-point RS2 x8-x15. */
2773 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2774 || !(regno
>= 8 && regno
<= 15))
2776 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2778 case 'T': /* Floating-point RS2. */
2779 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
))
2781 INSERT_OPERAND (CRS2
, *ip
, regno
);
2787 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2788 || imm_expr
->X_op
!= O_constant
2789 || imm_expr
->X_add_number
< 0
2790 || imm_expr
->X_add_number
>= 64)
2792 as_bad (_("bad value for compressed funct6 "
2793 "field, value must be 0...63"));
2796 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2797 imm_expr
->X_op
= O_absent
;
2802 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2803 || imm_expr
->X_op
!= O_constant
2804 || imm_expr
->X_add_number
< 0
2805 || imm_expr
->X_add_number
>= 16)
2807 as_bad (_("bad value for compressed funct4 "
2808 "field, value must be 0...15"));
2811 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2812 imm_expr
->X_op
= O_absent
;
2817 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2818 || imm_expr
->X_op
!= O_constant
2819 || imm_expr
->X_add_number
< 0
2820 || imm_expr
->X_add_number
>= 8)
2822 as_bad (_("bad value for compressed funct3 "
2823 "field, value must be 0...7"));
2826 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2827 imm_expr
->X_op
= O_absent
;
2832 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2833 || imm_expr
->X_op
!= O_constant
2834 || imm_expr
->X_add_number
< 0
2835 || imm_expr
->X_add_number
>= 4)
2837 as_bad (_("bad value for compressed funct2 "
2838 "field, value must be 0...3"));
2841 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2842 imm_expr
->X_op
= O_absent
;
2847 goto unknown_riscv_ip_operand
;
2852 goto unknown_riscv_ip_operand
;
2854 break; /* end RVC */
2860 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2862 INSERT_OPERAND (VD
, *ip
, regno
);
2865 case 'e': /* AMO VD */
2866 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
) && regno
== 0)
2867 INSERT_OPERAND (VWD
, *ip
, 0);
2868 else if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2870 INSERT_OPERAND (VWD
, *ip
, 1);
2871 INSERT_OPERAND (VD
, *ip
, regno
);
2877 case 'f': /* AMO VS3 */
2878 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2880 if (!EXTRACT_OPERAND (VWD
, ip
->insn_opcode
))
2881 INSERT_OPERAND (VD
, *ip
, regno
);
2884 /* VS3 must match VD. */
2885 if (EXTRACT_OPERAND (VD
, ip
->insn_opcode
) != regno
)
2891 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2893 INSERT_OPERAND (VS1
, *ip
, regno
);
2897 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2899 INSERT_OPERAND (VS2
, *ip
, regno
);
2902 case 'u': /* VS1 == VS2 */
2903 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2905 INSERT_OPERAND (VS1
, *ip
, regno
);
2906 INSERT_OPERAND (VS2
, *ip
, regno
);
2909 case 'v': /* VD == VS1 == VS2 */
2910 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2912 INSERT_OPERAND (VD
, *ip
, regno
);
2913 INSERT_OPERAND (VS1
, *ip
, regno
);
2914 INSERT_OPERAND (VS2
, *ip
, regno
);
2917 /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
2918 and is used to choose vs1/rs1/frs1/imm or vs2 for
2919 v[f]merge. It use the same encoding as the vector mask
2922 if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
) && regno
== 0)
2926 case 'b': /* vtypei for vsetivli */
2927 my_getVsetvliExpression (imm_expr
, asarg
);
2928 check_absolute_expr (ip
, imm_expr
, FALSE
);
2929 if (!VALID_RVV_VB_IMM (imm_expr
->X_add_number
))
2930 as_bad (_("bad value for vsetivli immediate field, "
2931 "value must be 0..1023"));
2933 |= ENCODE_RVV_VB_IMM (imm_expr
->X_add_number
);
2934 imm_expr
->X_op
= O_absent
;
2938 case 'c': /* vtypei for vsetvli */
2939 my_getVsetvliExpression (imm_expr
, asarg
);
2940 check_absolute_expr (ip
, imm_expr
, FALSE
);
2941 if (!VALID_RVV_VC_IMM (imm_expr
->X_add_number
))
2942 as_bad (_("bad value for vsetvli immediate field, "
2943 "value must be 0..2047"));
2945 |= ENCODE_RVV_VC_IMM (imm_expr
->X_add_number
);
2946 imm_expr
->X_op
= O_absent
;
2950 case 'i': /* vector arith signed immediate */
2951 my_getExpression (imm_expr
, asarg
);
2952 check_absolute_expr (ip
, imm_expr
, FALSE
);
2953 if (imm_expr
->X_add_number
> 15
2954 || imm_expr
->X_add_number
< -16)
2955 as_bad (_("bad value for vector immediate field, "
2956 "value must be -16...15"));
2957 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
2958 imm_expr
->X_op
= O_absent
;
2962 case 'j': /* vector arith unsigned immediate */
2963 my_getExpression (imm_expr
, asarg
);
2964 check_absolute_expr (ip
, imm_expr
, FALSE
);
2965 if (imm_expr
->X_add_number
< 0
2966 || imm_expr
->X_add_number
>= 32)
2967 as_bad (_("bad value for vector immediate field, "
2968 "value must be 0...31"));
2969 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
2970 imm_expr
->X_op
= O_absent
;
2974 case 'k': /* vector arith signed immediate, minus 1 */
2975 my_getExpression (imm_expr
, asarg
);
2976 check_absolute_expr (ip
, imm_expr
, FALSE
);
2977 if (imm_expr
->X_add_number
> 16
2978 || imm_expr
->X_add_number
< -15)
2979 as_bad (_("bad value for vector immediate field, "
2980 "value must be -15...16"));
2981 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
- 1);
2982 imm_expr
->X_op
= O_absent
;
2986 case 'm': /* optional vector mask */
2989 INSERT_OPERAND (VMASK
, *ip
, 1);
2992 else if (*asarg
== ',' && asarg
++
2993 && reg_lookup (&asarg
, RCLASS_VECM
, ®no
)
2996 INSERT_OPERAND (VMASK
, *ip
, 0);
3001 case 'M': /* required vector mask */
3002 if (reg_lookup (&asarg
, RCLASS_VECM
, ®no
) && regno
== 0)
3004 INSERT_OPERAND (VMASK
, *ip
, 0);
3009 case 'T': /* vector macro temporary register */
3010 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
) || regno
== 0)
3012 /* Store it in the FUNCT6 field as we don't have anyplace
3013 else to store it. */
3014 INSERT_OPERAND (VFUNCT6
, *ip
, regno
);
3018 goto unknown_riscv_ip_operand
;
3020 break; /* end RVV */
3023 if (*asarg
++ == *oparg
)
3032 if (*asarg
++ == *oparg
)
3036 case '<': /* Shift amount, 0 - 31. */
3037 my_getExpression (imm_expr
, asarg
);
3038 check_absolute_expr (ip
, imm_expr
, false);
3039 if ((unsigned long) imm_expr
->X_add_number
> 31)
3040 as_bad (_("improper shift amount (%"PRIu64
")"),
3041 imm_expr
->X_add_number
);
3042 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
3043 imm_expr
->X_op
= O_absent
;
3047 case '>': /* Shift amount, 0 - (XLEN-1). */
3048 my_getExpression (imm_expr
, asarg
);
3049 check_absolute_expr (ip
, imm_expr
, false);
3050 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
3051 as_bad (_("improper shift amount (%"PRIu64
")"),
3052 imm_expr
->X_add_number
);
3053 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
3054 imm_expr
->X_op
= O_absent
;
3058 case 'Z': /* CSRRxI immediate. */
3059 my_getExpression (imm_expr
, asarg
);
3060 check_absolute_expr (ip
, imm_expr
, false);
3061 if ((unsigned long) imm_expr
->X_add_number
> 31)
3062 as_bad (_("improper CSRxI immediate (%"PRIu64
")"),
3063 imm_expr
->X_add_number
);
3064 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
3065 imm_expr
->X_op
= O_absent
;
3069 case 'E': /* Control register. */
3070 insn_with_csr
= true;
3071 explicit_priv_attr
= true;
3072 if (reg_lookup (&asarg
, RCLASS_CSR
, ®no
))
3073 INSERT_OPERAND (CSR
, *ip
, regno
);
3076 my_getExpression (imm_expr
, asarg
);
3077 check_absolute_expr (ip
, imm_expr
, true);
3078 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
3079 as_bad (_("improper CSR address (%"PRIu64
")"),
3080 imm_expr
->X_add_number
);
3081 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
3082 imm_expr
->X_op
= O_absent
;
3087 case 'm': /* Rounding mode. */
3088 if (arg_lookup (&asarg
, riscv_rm
,
3089 ARRAY_SIZE (riscv_rm
), ®no
))
3091 INSERT_OPERAND (RM
, *ip
, regno
);
3097 case 'Q': /* Fence predecessor/successor. */
3098 if (arg_lookup (&asarg
, riscv_pred_succ
,
3099 ARRAY_SIZE (riscv_pred_succ
), ®no
))
3102 INSERT_OPERAND (PRED
, *ip
, regno
);
3104 INSERT_OPERAND (SUCC
, *ip
, regno
);
3109 case 'd': /* Destination register. */
3110 case 's': /* Source register. */
3111 case 't': /* Target register. */
3113 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
3119 /* Now that we have assembled one operand, we use the args
3120 string to figure out where it goes in the instruction. */
3124 INSERT_OPERAND (RS1
, *ip
, regno
);
3127 INSERT_OPERAND (RD
, *ip
, regno
);
3130 INSERT_OPERAND (RS2
, *ip
, regno
);
3133 INSERT_OPERAND (RS3
, *ip
, regno
);
3140 case 'D': /* Floating point RD. */
3141 case 'S': /* Floating point RS1. */
3142 case 'T': /* Floating point RS2. */
3143 case 'U': /* Floating point RS1 and RS2. */
3144 case 'R': /* Floating point RS3. */
3145 if (reg_lookup (&asarg
,
3146 (riscv_subset_supports (&riscv_rps_as
, "zfinx")
3147 ? RCLASS_GPR
: RCLASS_FPR
), ®no
))
3155 INSERT_OPERAND (RD
, *ip
, regno
);
3158 INSERT_OPERAND (RS1
, *ip
, regno
);
3161 INSERT_OPERAND (RS1
, *ip
, regno
);
3164 INSERT_OPERAND (RS2
, *ip
, regno
);
3167 INSERT_OPERAND (RS3
, *ip
, regno
);
3175 my_getExpression (imm_expr
, asarg
);
3176 if (imm_expr
->X_op
!= O_big
3177 && imm_expr
->X_op
!= O_constant
)
3179 normalize_constant_expr (imm_expr
);
3184 my_getExpression (imm_expr
, asarg
);
3185 normalize_constant_expr (imm_expr
);
3186 /* The 'A' format specifier must be a symbol. */
3187 if (imm_expr
->X_op
!= O_symbol
)
3189 *imm_reloc
= BFD_RELOC_32
;
3194 my_getExpression (imm_expr
, asarg
);
3195 normalize_constant_expr (imm_expr
);
3196 /* The 'B' format specifier must be a symbol or a constant. */
3197 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
3199 if (imm_expr
->X_op
== O_symbol
)
3200 *imm_reloc
= BFD_RELOC_32
;
3204 case 'j': /* Sign-extended immediate. */
3205 p
= percent_op_itype
;
3206 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3208 case 'q': /* Store displacement. */
3209 p
= percent_op_stype
;
3210 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
3212 case 'o': /* Load displacement. */
3213 p
= percent_op_itype
;
3214 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3217 /* This is used for TLS, where the fourth operand is
3218 %tprel_add, to get a relocation applied to an add
3219 instruction, for relaxation to use. */
3220 p
= percent_op_rtype
;
3222 case '0': /* AMO displacement, which must be zero. */
3223 p
= percent_op_null
;
3225 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3228 /* If this value won't fit into a 16 bit offset, then go
3229 find a macro that will generate the 32 bit offset
3231 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3233 normalize_constant_expr (imm_expr
);
3234 if (imm_expr
->X_op
!= O_constant
3235 || (*oparg
== '0' && imm_expr
->X_add_number
!= 0)
3237 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
3238 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
3244 case 'p': /* PC-relative offset. */
3246 *imm_reloc
= BFD_RELOC_12_PCREL
;
3247 my_getExpression (imm_expr
, asarg
);
3251 case 'u': /* Upper 20 bits. */
3252 p
= percent_op_utype
;
3253 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3255 if (imm_expr
->X_op
!= O_constant
)
3258 if (imm_expr
->X_add_number
< 0
3259 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
3260 as_bad (_("lui expression not in range 0..1048575"));
3262 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
3263 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
3268 case 'a': /* 20-bit PC-relative offset. */
3270 my_getExpression (imm_expr
, asarg
);
3272 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
3276 my_getExpression (imm_expr
, asarg
);
3278 if (strcmp (asarg
, "@plt") == 0)
3280 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
3287 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
, p
)
3288 || imm_expr
->X_op
!= O_constant
3289 || imm_expr
->X_add_number
< 0
3290 || imm_expr
->X_add_number
>= 128
3291 || (imm_expr
->X_add_number
& 0x3) != 3)
3293 as_bad (_("bad value for opcode field, "
3294 "value must be 0...127 and "
3295 "lower 2 bits must be 0x3"));
3298 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
3299 imm_expr
->X_op
= O_absent
;
3304 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
, p
)
3305 || imm_expr
->X_op
!= O_constant
3306 || imm_expr
->X_add_number
< 0
3307 || imm_expr
->X_add_number
>= 3)
3309 as_bad (_("bad value for opcode field, "
3310 "value must be 0...2"));
3313 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
3314 imm_expr
->X_op
= O_absent
;
3319 goto unknown_riscv_ip_operand
;
3327 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3328 || imm_expr
->X_op
!= O_constant
3329 || imm_expr
->X_add_number
< 0
3330 || imm_expr
->X_add_number
>= 128)
3332 as_bad (_("bad value for funct7 field, "
3333 "value must be 0...127"));
3336 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
3337 imm_expr
->X_op
= O_absent
;
3342 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3343 || imm_expr
->X_op
!= O_constant
3344 || imm_expr
->X_add_number
< 0
3345 || imm_expr
->X_add_number
>= 8)
3347 as_bad (_("bad value for funct3 field, "
3348 "value must be 0...7"));
3351 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
3352 imm_expr
->X_op
= O_absent
;
3357 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3358 || imm_expr
->X_op
!= O_constant
3359 || imm_expr
->X_add_number
< 0
3360 || imm_expr
->X_add_number
>= 4)
3362 as_bad (_("bad value for funct2 field, "
3363 "value must be 0...3"));
3366 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
3367 imm_expr
->X_op
= O_absent
;
3372 goto unknown_riscv_ip_operand
;
3376 case 'y': /* bs immediate */
3377 my_getExpression (imm_expr
, asarg
);
3378 check_absolute_expr (ip
, imm_expr
, FALSE
);
3379 if ((unsigned long)imm_expr
->X_add_number
> 3)
3380 as_bad(_("Improper bs immediate (%lu)"),
3381 (unsigned long)imm_expr
->X_add_number
);
3382 INSERT_OPERAND(BS
, *ip
, imm_expr
->X_add_number
);
3383 imm_expr
->X_op
= O_absent
;
3387 case 'Y': /* rnum immediate */
3388 my_getExpression (imm_expr
, asarg
);
3389 check_absolute_expr (ip
, imm_expr
, FALSE
);
3390 if ((unsigned long)imm_expr
->X_add_number
> 10)
3391 as_bad(_("Improper rnum immediate (%lu)"),
3392 (unsigned long)imm_expr
->X_add_number
);
3393 INSERT_OPERAND(RNUM
, *ip
, imm_expr
->X_add_number
);
3394 imm_expr
->X_op
= O_absent
;
3399 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3400 || imm_expr
->X_op
!= O_constant
3401 || imm_expr
->X_add_number
!= 0)
3404 imm_expr
->X_op
= O_absent
;
3407 case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
3408 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3410 my_getExpression (imm_expr
, asarg
);
3411 check_absolute_expr (ip
, imm_expr
, false);
3412 if (((unsigned) (imm_expr
->X_add_number
) & 0x1fU
)
3413 || imm_expr
->X_add_number
>= (signed) RISCV_IMM_REACH
/ 2
3414 || imm_expr
->X_add_number
< -(signed) RISCV_IMM_REACH
/ 2)
3415 as_bad (_("improper prefetch offset (%ld)"),
3416 (long) imm_expr
->X_add_number
);
3418 ENCODE_STYPE_IMM ((unsigned) (imm_expr
->X_add_number
) &
3420 imm_expr
->X_op
= O_absent
;
3424 case 'X': /* Integer immediate. */
3432 case 'l': /* Literal. */
3433 n
= strcspn (++oparg
, ",");
3434 if (strncmp (oparg
, asarg
, n
))
3435 as_bad (_("unexpected literal (%s)"), asarg
);
3439 case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
3442 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
3446 n
= strtol (oparg
+ 1, (char **)&oparg
, 10);
3448 goto unknown_riscv_ip_operand
;
3449 s
= strtol (oparg
+ 1, (char **)&oparg
, 10);
3452 my_getExpression (imm_expr
, asarg
);
3453 check_absolute_expr (ip
, imm_expr
, false);
3456 if (!VALIDATE_U_IMM (imm_expr
->X_add_number
, n
))
3457 as_bad (_("improper immediate value (%"PRIu64
")"),
3458 imm_expr
->X_add_number
);
3462 if (!VALIDATE_S_IMM (imm_expr
->X_add_number
, n
))
3463 as_bad (_("improper immediate value (%"PRIi64
")"),
3464 imm_expr
->X_add_number
);
3466 INSERT_IMM (n
, s
, *ip
, imm_expr
->X_add_number
);
3467 imm_expr
->X_op
= O_absent
;
3471 goto unknown_riscv_ip_operand
;
3476 unknown_riscv_ip_operand
:
3477 as_fatal (_("internal: unknown argument type `%s'"),
3483 insn_with_csr
= false;
3487 /* Restore the character we might have clobbered above. */
3489 *(asargStart
- 1) = save_c
;
3494 /* Similar to riscv_ip, but assembles an instruction according to the
3495 hardcode values of .insn directive. */
3498 riscv_ip_hardcode (char *str
,
3499 struct riscv_cl_insn
*ip
,
3500 expressionS
*imm_expr
,
3503 struct riscv_opcode
*insn
;
3504 insn_t values
[2] = {0, 0};
3505 unsigned int num
= 0;
3507 input_line_pointer
= str
;
3510 expression (imm_expr
);
3511 switch (imm_expr
->X_op
)
3514 values
[num
++] = (insn_t
) imm_expr
->X_add_number
;
3517 /* Extract lower 32-bits of a big number.
3518 Assume that generic_bignum_to_int32 work on such number. */
3519 values
[num
++] = (insn_t
) generic_bignum_to_int32 ();
3522 /* The first value isn't constant, so it should be
3523 .insn <type> <operands>. We have been parsed it
3527 return _("values must be constant");
3530 while (*input_line_pointer
++ == ',' && num
< 2 && imm_expr
->X_op
!= O_big
);
3532 input_line_pointer
--;
3533 if (*input_line_pointer
!= '\0')
3534 return _("unrecognized values");
3536 insn
= XNEW (struct riscv_opcode
);
3537 insn
->match
= values
[num
- 1];
3538 create_insn (ip
, insn
);
3539 unsigned int bytes
= riscv_insn_length (insn
->match
);
3541 if (num
== 2 && values
[0] != bytes
)
3542 return _("value conflicts with instruction length");
3544 if (imm_expr
->X_op
== O_big
)
3546 unsigned int llen
= 0;
3547 for (LITTLENUM_TYPE lval
= generic_bignum
[imm_expr
->X_add_number
- 1];
3549 lval
>>= BITS_PER_CHAR
;
3550 unsigned int repr_bytes
3551 = (imm_expr
->X_add_number
- 1) * CHARS_PER_LITTLENUM
+ llen
;
3552 if (bytes
< repr_bytes
)
3553 return _("value conflicts with instruction length");
3554 for (num
= 0; num
< imm_expr
->X_add_number
- 1; ++num
)
3555 number_to_chars_littleendian (
3556 ip
->insn_long_opcode
+ num
* CHARS_PER_LITTLENUM
,
3557 generic_bignum
[num
],
3558 CHARS_PER_LITTLENUM
);
3560 number_to_chars_littleendian (
3561 ip
->insn_long_opcode
+ num
* CHARS_PER_LITTLENUM
,
3562 generic_bignum
[num
],
3564 memset(ip
->insn_long_opcode
+ repr_bytes
, 0, bytes
- repr_bytes
);
3568 if (bytes
< sizeof(values
[0]) && values
[num
- 1] >> (8 * bytes
) != 0)
3569 return _("value conflicts with instruction length");
3575 md_assemble (char *str
)
3577 struct riscv_cl_insn insn
;
3578 expressionS imm_expr
;
3579 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3581 /* The architecture and privileged elf attributes should be set
3582 before assembling. */
3583 if (!start_assemble
)
3585 start_assemble
= true;
3587 riscv_set_abi_by_arch ();
3588 if (!riscv_set_default_priv_spec (NULL
))
3592 riscv_mapping_state (MAP_INSN
, 0, false/* fr_align_code */);
3594 const struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
3595 &imm_reloc
, op_hash
);
3599 if (error
.missing_ext
)
3600 as_bad ("%s `%s', extension `%s' required", error
.msg
,
3601 error
.statement
, error
.missing_ext
);
3603 as_bad ("%s `%s'", error
.msg
, error
.statement
);
3607 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3608 macro (&insn
, &imm_expr
, &imm_reloc
);
3610 append_insn (&insn
, &imm_expr
, imm_reloc
);
3614 md_atof (int type
, char *litP
, int *sizeP
)
3616 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
3620 md_number_to_chars (char *buf
, valueT val
, int n
)
3622 if (target_big_endian
)
3623 number_to_chars_bigendian (buf
, val
, n
);
3625 number_to_chars_littleendian (buf
, val
, n
);
3628 const char *md_shortopts
= "O::g::G:";
3632 OPTION_MARCH
= OPTION_MD_BASE
,
3639 OPTION_NO_ARCH_ATTR
,
3641 OPTION_NO_CSR_CHECK
,
3645 OPTION_LITTLE_ENDIAN
,
3649 struct option md_longopts
[] =
3651 {"march", required_argument
, NULL
, OPTION_MARCH
},
3652 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
3653 {"fpic", no_argument
, NULL
, OPTION_PIC
},
3654 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
3655 {"mabi", required_argument
, NULL
, OPTION_MABI
},
3656 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
3657 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
3658 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
3659 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
3660 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
3661 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
3662 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
3663 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
3664 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
3665 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
3667 {NULL
, no_argument
, NULL
, 0}
3669 size_t md_longopts_size
= sizeof (md_longopts
);
3672 md_parse_option (int c
, const char *arg
)
3677 default_arch_with_ext
= arg
;
3681 riscv_opts
.pic
= false;
3685 riscv_opts
.pic
= true;
3689 if (strcmp (arg
, "ilp32") == 0)
3690 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
3691 else if (strcmp (arg
, "ilp32e") == 0)
3692 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
3693 else if (strcmp (arg
, "ilp32f") == 0)
3694 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
3695 else if (strcmp (arg
, "ilp32d") == 0)
3696 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
3697 else if (strcmp (arg
, "ilp32q") == 0)
3698 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
3699 else if (strcmp (arg
, "lp64") == 0)
3700 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
3701 else if (strcmp (arg
, "lp64f") == 0)
3702 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
3703 else if (strcmp (arg
, "lp64d") == 0)
3704 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
3705 else if (strcmp (arg
, "lp64q") == 0)
3706 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
3709 explicit_mabi
= true;
3713 riscv_opts
.relax
= true;
3716 case OPTION_NO_RELAX
:
3717 riscv_opts
.relax
= false;
3720 case OPTION_ARCH_ATTR
:
3721 riscv_opts
.arch_attr
= true;
3724 case OPTION_NO_ARCH_ATTR
:
3725 riscv_opts
.arch_attr
= false;
3728 case OPTION_CSR_CHECK
:
3729 riscv_opts
.csr_check
= true;
3732 case OPTION_NO_CSR_CHECK
:
3733 riscv_opts
.csr_check
= false;
3736 case OPTION_MISA_SPEC
:
3737 return riscv_set_default_isa_spec (arg
);
3739 case OPTION_MPRIV_SPEC
:
3740 return riscv_set_default_priv_spec (arg
);
3742 case OPTION_BIG_ENDIAN
:
3743 target_big_endian
= 1;
3746 case OPTION_LITTLE_ENDIAN
:
3747 target_big_endian
= 0;
3758 riscv_after_parse_args (void)
3760 /* The --with-arch is optional for now, so we still need to set the xlen
3761 according to the default_arch, which is set by the --target. */
3764 if (strcmp (default_arch
, "riscv32") == 0)
3766 else if (strcmp (default_arch
, "riscv64") == 0)
3769 as_bad ("unknown default architecture `%s'", default_arch
);
3772 /* Set default specs. */
3773 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
3774 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
3775 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
3776 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
3778 riscv_set_arch (default_arch_with_ext
);
3780 /* If the CIE to be produced has not been overridden on the command line,
3781 then produce version 3 by default. This allows us to use the full
3782 range of registers in a .cfi_return_column directive. */
3783 if (flag_dwarf_cie_version
== -1)
3784 flag_dwarf_cie_version
= 3;
3788 md_pcrel_from (fixS
*fixP
)
3790 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3793 /* Apply a fixup to the object file. */
3796 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
3798 unsigned int subtype
;
3799 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
3800 bool relaxable
= false;
3804 /* Remember value for tc_gen_reloc. */
3805 fixP
->fx_addnumber
= *valP
;
3807 switch (fixP
->fx_r_type
)
3809 case BFD_RELOC_RISCV_HI20
:
3810 case BFD_RELOC_RISCV_LO12_I
:
3811 case BFD_RELOC_RISCV_LO12_S
:
3812 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
3813 | bfd_getl32 (buf
), buf
);
3814 if (fixP
->fx_addsy
== NULL
)
3815 fixP
->fx_done
= true;
3819 case BFD_RELOC_RISCV_GOT_HI20
:
3820 case BFD_RELOC_RISCV_ADD8
:
3821 case BFD_RELOC_RISCV_ADD16
:
3822 case BFD_RELOC_RISCV_ADD32
:
3823 case BFD_RELOC_RISCV_ADD64
:
3824 case BFD_RELOC_RISCV_SUB6
:
3825 case BFD_RELOC_RISCV_SUB8
:
3826 case BFD_RELOC_RISCV_SUB16
:
3827 case BFD_RELOC_RISCV_SUB32
:
3828 case BFD_RELOC_RISCV_SUB64
:
3829 case BFD_RELOC_RISCV_RELAX
:
3832 case BFD_RELOC_RISCV_TPREL_HI20
:
3833 case BFD_RELOC_RISCV_TPREL_LO12_I
:
3834 case BFD_RELOC_RISCV_TPREL_LO12_S
:
3835 case BFD_RELOC_RISCV_TPREL_ADD
:
3839 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
3840 case BFD_RELOC_RISCV_TLS_GD_HI20
:
3841 case BFD_RELOC_RISCV_TLS_DTPREL32
:
3842 case BFD_RELOC_RISCV_TLS_DTPREL64
:
3843 if (fixP
->fx_addsy
!= NULL
)
3844 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3847 _("TLS relocation against a constant"));
3851 /* Use pc-relative relocation for FDE initial location.
3852 The symbol address in .eh_frame may be adjusted in
3853 _bfd_elf_discard_section_eh_frame, and the content of
3854 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3855 Therefore, we cannot insert a relocation whose addend symbol is
3856 in .eh_frame. Othrewise, the value may be adjusted twice. */
3857 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3858 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3859 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3860 && S_GET_VALUE (fixP
->fx_subsy
)
3861 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3863 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3864 fixP
->fx_subsy
= NULL
;
3871 case BFD_RELOC_RISCV_CFA
:
3872 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3874 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3875 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3876 fixP
->fx_next
->fx_subsy
= NULL
;
3877 fixP
->fx_next
->fx_offset
= 0;
3878 fixP
->fx_subsy
= NULL
;
3880 switch (fixP
->fx_r_type
)
3883 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3884 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3888 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3889 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3893 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3894 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3898 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3899 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3902 case BFD_RELOC_RISCV_CFA
:
3903 /* Load the byte to get the subtype. */
3904 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3905 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3908 case DW_CFA_advance_loc1
:
3909 fixP
->fx_where
= loc
+ 1;
3910 fixP
->fx_next
->fx_where
= loc
+ 1;
3911 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3912 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3915 case DW_CFA_advance_loc2
:
3917 fixP
->fx_next
->fx_size
= 2;
3918 fixP
->fx_where
= loc
+ 1;
3919 fixP
->fx_next
->fx_where
= loc
+ 1;
3920 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3921 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3924 case DW_CFA_advance_loc4
:
3926 fixP
->fx_next
->fx_size
= 4;
3927 fixP
->fx_where
= loc
;
3928 fixP
->fx_next
->fx_where
= loc
;
3929 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3930 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3934 if (subtype
< 0x80 && (subtype
& 0x40))
3936 /* DW_CFA_advance_loc */
3937 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3938 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3939 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3940 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3943 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3949 /* This case is unreachable. */
3956 /* If we are deleting this reloc entry, we must fill in the
3957 value now. This can happen if we have a .word which is not
3958 resolved when it appears but is later defined. */
3959 if (fixP
->fx_addsy
== NULL
)
3961 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3962 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3967 case BFD_RELOC_RISCV_JMP
:
3970 /* Fill in a tentative value to improve objdump readability. */
3971 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3972 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3973 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
3977 case BFD_RELOC_12_PCREL
:
3980 /* Fill in a tentative value to improve objdump readability. */
3981 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3982 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3983 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
3987 case BFD_RELOC_RISCV_RVC_BRANCH
:
3990 /* Fill in a tentative value to improve objdump readability. */
3991 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3992 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3993 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
3997 case BFD_RELOC_RISCV_RVC_JUMP
:
4000 /* Fill in a tentative value to improve objdump readability. */
4001 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4002 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4003 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
4007 case BFD_RELOC_RISCV_CALL
:
4008 case BFD_RELOC_RISCV_CALL_PLT
:
4012 case BFD_RELOC_RISCV_PCREL_HI20
:
4013 case BFD_RELOC_RISCV_PCREL_LO12_S
:
4014 case BFD_RELOC_RISCV_PCREL_LO12_I
:
4015 relaxable
= riscv_opts
.relax
;
4018 case BFD_RELOC_RISCV_ALIGN
:
4022 /* We ignore generic BFD relocations we don't know about. */
4023 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
4024 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
4027 if (fixP
->fx_subsy
!= NULL
)
4028 as_bad_subtract (fixP
);
4030 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
4031 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
4033 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
4034 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
4035 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
4036 fixP
->fx_next
->fx_size
= 0;
4040 /* Because the value of .cfi_remember_state may changed after relaxation,
4041 we insert a fix to relocate it again in link-time. */
4044 riscv_pre_output_hook (void)
4046 const frchainS
*frch
;
4049 /* Save the current segment info. */
4051 subsegT subseg
= now_subseg
;
4053 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
4054 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
4058 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
4060 if (frag
->fr_type
== rs_cfa
)
4063 expressionS
*symval
;
4065 symval
= symbol_get_value_expression (frag
->fr_symbol
);
4066 exp
.X_op
= O_subtract
;
4067 exp
.X_add_symbol
= symval
->X_add_symbol
;
4068 exp
.X_add_number
= 0;
4069 exp
.X_op_symbol
= symval
->X_op_symbol
;
4071 /* We must set the segment before creating a frag after all
4072 frag chains have been chained together. */
4073 subseg_set (s
, frch
->frch_subseg
);
4075 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
4076 BFD_RELOC_RISCV_CFA
);
4081 /* Restore the original segment info. */
4082 subseg_set (seg
, subseg
);
4085 /* Handle the .option pseudo-op. */
4088 s_riscv_option (int x ATTRIBUTE_UNUSED
)
4090 char *name
= input_line_pointer
, ch
;
4092 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4093 ++input_line_pointer
;
4094 ch
= *input_line_pointer
;
4095 *input_line_pointer
= '\0';
4097 if (strcmp (name
, "rvc") == 0)
4099 riscv_update_subset (&riscv_rps_as
, "+c");
4100 riscv_reset_subsets_list_arch_str ();
4101 riscv_set_rvc (true);
4103 else if (strcmp (name
, "norvc") == 0)
4105 riscv_update_subset (&riscv_rps_as
, "-c");
4106 riscv_reset_subsets_list_arch_str ();
4107 riscv_set_rvc (false);
4109 else if (strcmp (name
, "pic") == 0)
4110 riscv_opts
.pic
= true;
4111 else if (strcmp (name
, "nopic") == 0)
4112 riscv_opts
.pic
= false;
4113 else if (strcmp (name
, "relax") == 0)
4114 riscv_opts
.relax
= true;
4115 else if (strcmp (name
, "norelax") == 0)
4116 riscv_opts
.relax
= false;
4117 else if (strcmp (name
, "csr-check") == 0)
4118 riscv_opts
.csr_check
= true;
4119 else if (strcmp (name
, "no-csr-check") == 0)
4120 riscv_opts
.csr_check
= false;
4121 else if (strncmp (name
, "arch,", 5) == 0)
4124 if (ISSPACE (*name
) && *name
!= '\0')
4126 riscv_update_subset (&riscv_rps_as
, name
);
4127 riscv_reset_subsets_list_arch_str ();
4129 riscv_set_rvc (false);
4130 if (riscv_subset_supports (&riscv_rps_as
, "c"))
4131 riscv_set_rvc (true);
4133 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
4136 else if (strcmp (name
, "push") == 0)
4138 struct riscv_option_stack
*s
;
4140 s
= XNEW (struct riscv_option_stack
);
4141 s
->next
= riscv_opts_stack
;
4142 s
->options
= riscv_opts
;
4143 s
->subset_list
= riscv_rps_as
.subset_list
;
4144 riscv_opts_stack
= s
;
4145 riscv_rps_as
.subset_list
= riscv_copy_subset_list (s
->subset_list
);
4147 else if (strcmp (name
, "pop") == 0)
4149 struct riscv_option_stack
*s
;
4151 s
= riscv_opts_stack
;
4153 as_bad (_(".option pop with no .option push"));
4156 riscv_subset_list_t
*release_subsets
= riscv_rps_as
.subset_list
;
4157 riscv_opts_stack
= s
->next
;
4158 riscv_opts
= s
->options
;
4159 riscv_rps_as
.subset_list
= s
->subset_list
;
4160 riscv_release_subset_list (release_subsets
);
4166 as_warn (_("unrecognized .option directive: %s\n"), name
);
4168 *input_line_pointer
= ch
;
4169 demand_empty_rest_of_line ();
4172 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
4173 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
4174 use in DWARF debug information. */
4177 s_dtprel (int bytes
)
4184 if (ex
.X_op
!= O_symbol
)
4186 as_bad (_("unsupported use of %s"), (bytes
== 8
4189 ignore_rest_of_line ();
4192 p
= frag_more (bytes
);
4193 md_number_to_chars (p
, 0, bytes
);
4194 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
4196 ? BFD_RELOC_RISCV_TLS_DTPREL64
4197 : BFD_RELOC_RISCV_TLS_DTPREL32
));
4199 demand_empty_rest_of_line ();
4202 /* Handle the .bss pseudo-op. */
4205 s_bss (int ignore ATTRIBUTE_UNUSED
)
4207 subseg_set (bss_section
, 0);
4208 demand_empty_rest_of_line ();
4212 riscv_make_nops (char *buf
, bfd_vma bytes
)
4216 /* RISC-V instructions cannot begin or end on odd addresses, so this case
4217 means we are not within a valid instruction sequence. It is thus safe
4218 to use a zero byte, even though that is not a valid instruction. */
4222 /* Use at most one 2-byte NOP. */
4223 if ((bytes
- i
) % 4 == 2)
4225 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
4229 /* Fill the remainder with 4-byte NOPs. */
4230 for ( ; i
< bytes
; i
+= 4)
4231 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
4234 /* Called from md_do_align. Used to create an alignment frag in a
4235 code section by emitting a worst-case NOP sequence that the linker
4236 will later relax to the correct number of NOPs. We can't compute
4237 the correct alignment now because of other linker relaxations. */
4240 riscv_frag_align_code (int n
)
4242 bfd_vma bytes
= (bfd_vma
) 1 << n
;
4243 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
4244 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
4248 /* If we are moving to a smaller alignment than the instruction size, then no
4249 alignment is required. */
4250 if (bytes
<= insn_alignment
)
4253 /* When not relaxing, riscv_handle_align handles code alignment. */
4254 if (!riscv_opts
.relax
)
4257 /* Maybe we should use frag_var to create a new rs_align_code fragment,
4258 rather than just use frag_more to handle an alignment here? So that we
4259 don't need to call riscv_mapping_state again later, and then only need
4260 to check frag->fr_type to see if it is frag_align_code. */
4261 nops
= frag_more (worst_case_bytes
);
4263 ex
.X_op
= O_constant
;
4264 ex
.X_add_number
= worst_case_bytes
;
4266 riscv_make_nops (nops
, worst_case_bytes
);
4268 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
4269 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
4271 riscv_mapping_state (MAP_INSN
, worst_case_bytes
, true/* fr_align_code */);
4273 /* We need to start a new frag after the alignment which may be removed by
4274 the linker, to prevent the assembler from computing static offsets.
4275 This is necessary to get correct EH info. */
4276 frag_wane (frag_now
);
4282 /* Implement HANDLE_ALIGN. */
4285 riscv_handle_align (fragS
*fragP
)
4287 switch (fragP
->fr_type
)
4290 /* When relaxing, riscv_frag_align_code handles code alignment. */
4291 if (!riscv_opts
.relax
)
4293 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
4294 - fragP
->fr_address
- fragP
->fr_fix
);
4295 /* We have 4 byte uncompressed nops. */
4296 bfd_signed_vma size
= 4;
4297 bfd_signed_vma excess
= bytes
% size
;
4298 bfd_boolean odd_padding
= (excess
% 2 == 1);
4299 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
4304 /* Insert zeros or compressed nops to get 4 byte alignment. */
4308 riscv_add_odd_padding_symbol (fragP
);
4309 riscv_make_nops (p
, excess
);
4310 fragP
->fr_fix
+= excess
;
4314 /* The frag will be changed to `rs_fill` later. The function
4315 `write_contents` will try to fill the remaining spaces
4316 according to the patterns we give. In this case, we give
4317 a 4 byte uncompressed nop as the pattern, and set the size
4318 of the pattern into `fr_var`. The nop will be output to the
4319 file `fr_offset` times. However, `fr_offset` could be zero
4320 if we don't need to pad the boundary finally. */
4321 riscv_make_nops (p
, size
);
4322 fragP
->fr_var
= size
;
4331 /* This usually called from frag_var. */
4334 riscv_init_frag (fragS
* fragP
, int max_chars
)
4336 /* Do not add mapping symbol to debug sections. */
4337 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
4340 switch (fragP
->fr_type
)
4345 riscv_mapping_state (MAP_DATA
, max_chars
, false/* fr_align_code */);
4348 riscv_mapping_state (MAP_INSN
, max_chars
, true/* fr_align_code */);
4356 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
4358 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
4361 /* Translate internal representation of relocation info to BFD target
4365 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
4367 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4369 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4370 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4371 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4372 reloc
->addend
= fixp
->fx_addnumber
;
4374 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4375 if (reloc
->howto
== NULL
)
4377 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
4378 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
4380 /* We don't have R_RISCV_8/16, but for this special case,
4381 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
4385 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4386 _("cannot represent %s relocation in object file"),
4387 bfd_get_reloc_code_name (fixp
->fx_r_type
));
4395 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
4397 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
4399 offsetT old_var
= fragp
->fr_var
;
4400 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
4401 return fragp
->fr_var
- old_var
;
4407 /* Expand far branches to multi-instruction sequences. */
4410 md_convert_frag_branch (fragS
*fragp
)
4418 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
4420 exp
.X_op
= O_symbol
;
4421 exp
.X_add_symbol
= fragp
->fr_symbol
;
4422 exp
.X_add_number
= fragp
->fr_offset
;
4424 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
4426 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
4428 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4432 /* Expand the RVC branch into a RISC-V one. */
4433 insn
= bfd_getl16 (buf
);
4434 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
4435 if ((insn
& MASK_C_J
) == MATCH_C_J
)
4437 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
4438 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
4439 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
4440 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
4441 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
4442 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
4445 bfd_putl32 (insn
, buf
);
4449 /* Invert the branch condition. Branch over the jump. */
4450 insn
= bfd_getl16 (buf
);
4451 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
4452 insn
|= ENCODE_CBTYPE_IMM (6);
4453 bfd_putl16 (insn
, buf
);
4458 /* Just keep the RVC branch. */
4459 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4460 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
4461 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4462 2, &exp
, false, reloc
);
4471 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4474 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
4476 /* Invert the branch condition. Branch over the jump. */
4477 insn
= bfd_getl32 (buf
);
4478 insn
^= MATCH_BEQ
^ MATCH_BNE
;
4479 insn
|= ENCODE_BTYPE_IMM (8);
4480 bfd_putl32 (insn
, buf
);
4484 /* Jump to the target. */
4485 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4486 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
4487 bfd_putl32 (MATCH_JAL
, buf
);
4492 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4493 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
4494 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4495 4, &exp
, false, reloc
);
4504 fixp
->fx_file
= fragp
->fr_file
;
4505 fixp
->fx_line
= fragp
->fr_line
;
4507 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
4508 + fragp
->fr_fix
+ fragp
->fr_var
);
4510 fragp
->fr_fix
+= fragp
->fr_var
;
4513 /* Relax a machine dependent frag. This returns the amount by which
4514 the current size of the frag should change. */
4517 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
4520 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
4521 md_convert_frag_branch (fragp
);
4525 md_show_usage (FILE *stream
)
4527 fprintf (stream
, _("\
4529 -fpic or -fPIC generate position-independent code\n\
4530 -fno-pic don't generate position-independent code (default)\n\
4531 -march=ISA set the RISC-V architecture\n\
4532 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
4533 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\
4534 -mabi=ABI set the RISC-V ABI\n\
4535 -mrelax enable relax (default)\n\
4536 -mno-relax disable relax\n\
4537 -march-attr generate RISC-V arch attribute\n\
4538 -mno-arch-attr don't generate RISC-V arch attribute\n\
4539 -mcsr-check enable the csr ISA and privilege spec version checks\n\
4540 -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\
4541 -mbig-endian assemble for big-endian\n\
4542 -mlittle-endian assemble for little-endian\n\
4546 /* Standard calling conventions leave the CFA at SP on entry. */
4549 riscv_cfi_frame_initial_instructions (void)
4551 cfi_add_CFA_def_cfa_register (X_SP
);
4555 tc_riscv_regname_to_dw2regnum (char *regname
)
4559 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
4562 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
4565 if ((reg
= reg_lookup_internal (regname
, RCLASS_VECR
)) >= 0)
4568 /* CSRs are numbered 4096 -> 8191. */
4569 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
4572 as_bad (_("unknown register `%s'"), regname
);
4577 riscv_elf_final_processing (void)
4579 riscv_set_abi_by_arch ();
4580 riscv_release_subset_list (riscv_rps_as
.subset_list
);
4581 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4584 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
4585 since these directives break relaxation when used with symbol deltas. */
4588 s_riscv_leb128 (int sign
)
4591 char *save_in
= input_line_pointer
;
4594 if (exp
.X_op
!= O_constant
)
4595 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
4596 demand_empty_rest_of_line ();
4598 input_line_pointer
= save_in
;
4599 return s_leb128 (sign
);
4602 /* Parse the .insn directive. There are three formats,
4603 Format 1: .insn <type> <operand1>, <operand2>, ...
4604 Format 2: .insn <length>, <value>
4605 Format 3: .insn <value>. */
4608 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
4610 char *str
= input_line_pointer
;
4611 struct riscv_cl_insn insn
;
4612 expressionS imm_expr
;
4613 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
4616 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4617 ++input_line_pointer
;
4619 save_c
= *input_line_pointer
;
4620 *input_line_pointer
= '\0';
4622 riscv_mapping_state (MAP_INSN
, 0, false/* fr_align_code */);
4624 struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
4625 &imm_reloc
, insn_type_hash
);
4628 char *save_in
= input_line_pointer
;
4629 error
.msg
= riscv_ip_hardcode (str
, &insn
, &imm_expr
, error
.msg
);
4630 input_line_pointer
= save_in
;
4635 if (error
.missing_ext
)
4636 as_bad ("%s `%s', extension `%s' required", error
.msg
, error
.statement
,
4639 as_bad ("%s `%s'", error
.msg
, error
.statement
);
4643 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
4644 append_insn (&insn
, &imm_expr
, imm_reloc
);
4647 *input_line_pointer
= save_c
;
4648 demand_empty_rest_of_line ();
4651 /* Update architecture and privileged elf attributes. If we don't set
4652 them, then try to output the default ones. */
4655 riscv_write_out_attrs (void)
4657 const char *arch_str
, *priv_str
, *p
;
4658 /* versions[0]: major version.
4659 versions[1]: minor version.
4660 versions[2]: revision version. */
4661 unsigned versions
[3] = {0}, number
= 0;
4664 /* Re-write architecture elf attribute. */
4665 arch_str
= riscv_rps_as
.subset_list
->arch_str
;
4666 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
4668 /* For the file without any instruction, we don't set the default_priv_spec
4669 according to the privileged elf attributes since the md_assemble isn't
4672 && !riscv_set_default_priv_spec (NULL
))
4675 /* If we already have set privileged elf attributes, then no need to do
4676 anything. Otherwise, don't generate or update them when no CSR and
4677 privileged instructions are used. */
4678 if (!explicit_priv_attr
)
4681 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
4683 for (i
= 0; *p
; ++p
)
4685 if (*p
== '.' && i
< 3)
4687 versions
[i
++] = number
;
4690 else if (ISDIGIT (*p
))
4691 number
= (number
* 10) + (*p
- '0');
4694 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
4698 versions
[i
] = number
;
4700 /* Re-write privileged elf attributes. */
4701 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
4702 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
4703 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
4706 /* Add the default contents for the .riscv.attributes section. */
4709 riscv_set_public_attributes (void)
4711 if (riscv_opts
.arch_attr
|| explicit_attr
)
4712 riscv_write_out_attrs ();
4715 /* Called after all assembly has been done. */
4718 riscv_md_finish (void)
4720 riscv_set_public_attributes ();
4723 /* Adjust the symbol table. */
4726 riscv_adjust_symtab (void)
4728 bfd_map_over_sections (stdoutput
, riscv_check_mapping_symbols
, (char *) 0);
4729 elf_adjust_symtab ();
4732 /* Given a symbolic attribute NAME, return the proper integer value.
4733 Returns -1 if the attribute is not known. */
4736 riscv_convert_symbolic_attribute (const char *name
)
4745 /* When you modify this table you should
4746 also modify the list in doc/c-riscv.texi. */
4747 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
4751 T(priv_spec_revision
),
4752 T(unaligned_access
),
4761 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
4762 if (strcmp (name
, attribute_table
[i
].name
) == 0)
4763 return attribute_table
[i
].tag
;
4768 /* Parse a .attribute directive. */
4771 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
4773 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4775 obj_attribute
*attr
;
4777 explicit_attr
= true;
4780 case Tag_RISCV_arch
:
4782 attr
= elf_known_obj_attributes_proc (stdoutput
);
4783 if (!start_assemble
)
4784 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
4786 as_fatal (_("architecture elf attributes must set before "
4787 "any instructions"));
4789 if (old_xlen
!= xlen
)
4791 /* We must re-init bfd again if xlen is changed. */
4792 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
4793 bfd_find_target (riscv_target_format (), stdoutput
);
4795 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
4796 as_warn (_("could not set architecture and machine"));
4800 case Tag_RISCV_priv_spec
:
4801 case Tag_RISCV_priv_spec_minor
:
4802 case Tag_RISCV_priv_spec_revision
:
4804 as_fatal (_("privileged elf attributes must set before "
4805 "any instructions"));
4813 /* Mark symbol that it follows a variant CC convention. */
4816 s_variant_cc (int ignored ATTRIBUTE_UNUSED
)
4822 elf_symbol_type
*elfsym
;
4824 c
= get_symbol_name (&name
);
4826 as_bad (_("missing symbol name for .variant_cc directive"));
4827 sym
= symbol_find_or_make (name
);
4828 restore_line_pointer (c
);
4829 demand_empty_rest_of_line ();
4831 bfdsym
= symbol_get_bfdsym (sym
);
4832 elfsym
= elf_symbol_from (bfdsym
);
4833 gas_assert (elfsym
);
4834 elfsym
->internal_elf_sym
.st_other
|= STO_RISCV_VARIANT_CC
;
4837 /* Same as elf_copy_symbol_attributes, but without copying st_other.
4838 This is needed so RISC-V specific st_other values can be independently
4839 specified for an IFUNC resolver (that is called by the dynamic linker)
4840 and the symbol it resolves (aliased to the resolver). In particular,
4841 if a function symbol has special st_other value set via directives,
4842 then attaching an IFUNC resolver to that symbol should not override
4843 the st_other setting. Requiring the directive on the IFUNC resolver
4844 symbol would be unexpected and problematic in C code, where the two
4845 symbols appear as two independent function declarations. */
4848 riscv_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
4850 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
4851 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
4852 /* If size is unset, copy size from src. Because we don't track whether
4853 .size has been used, we can't differentiate .size dest, 0 from the case
4854 where dest's size is unset. */
4855 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
4859 destelf
->size
= XNEW (expressionS
);
4860 *destelf
->size
= *srcelf
->size
;
4862 S_SET_SIZE (dest
, S_GET_SIZE (src
));
4866 /* RISC-V pseudo-ops table. */
4867 static const pseudo_typeS riscv_pseudo_table
[] =
4869 {"option", s_riscv_option
, 0},
4873 {"dtprelword", s_dtprel
, 4},
4874 {"dtpreldword", s_dtprel
, 8},
4876 {"uleb128", s_riscv_leb128
, 0},
4877 {"sleb128", s_riscv_leb128
, 1},
4878 {"insn", s_riscv_insn
, 0},
4879 {"attribute", s_riscv_attribute
, 0},
4880 {"variant_cc", s_variant_cc
, 0},
4881 {"float16", float_cons
, 'h'},
4887 riscv_pop_insert (void)
4889 extern void pop_insert (const pseudo_typeS
*);
4891 pop_insert (riscv_pseudo_table
);