1 @c Copyright (C) 1996-2021 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
152 @code{cortex-m0plus},
156 @code{marvell-whitney},
162 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
163 @code{i80200} (Intel XScale processor)
164 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
167 The special name @code{all} may be used to allow the
168 assembler to accept instructions valid for any ARM processor.
170 In addition to the basic instruction set, the assembler can be told to
171 accept various extension mnemonics that extend the processor using the
172 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
173 is equivalent to specifying @code{-mcpu=ep9312}.
175 Multiple extensions may be specified, separated by a @code{+}. The
176 extensions should be specified in ascending alphabetical order.
178 Some extensions may be restricted to particular architectures; this is
179 documented in the list of extensions below.
181 Extension mnemonics may also be removed from those the assembler accepts.
182 This is done be prepending @code{no} to the option that adds the extension.
183 Extensions that are removed should be listed after all extensions which have
184 been added, again in ascending alphabetical order. For example,
185 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
188 The following extensions are currently supported:
189 @code{bf16} (BFloat16 extensions for v8.6-A architecture),
190 @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
192 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
193 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
194 @code{fp} (Floating Point Extensions for v8-A architecture),
195 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
196 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
197 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
202 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
204 @code{os} (Operating System for v6M architecture),
205 @code{predres} (Execution and Data Prediction Restriction Instruction for
206 v8-A architectures, added by default from v8.5-A),
207 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
208 default from v8.5-A),
209 @code{sec} (Security Extensions for v6K and v7-A architectures),
210 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
211 @code{virt} (Virtualization Extensions for v7-A architecture, implies
213 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
214 @code{ras} (Reliability, Availability and Serviceability extensions
215 for v8-A architecture),
216 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
221 @cindex @code{-march=} command-line option, ARM
222 @item -march=@var{architecture}[+@var{extension}@dots{}]
223 This option specifies the target architecture. The assembler will issue
224 an error message if an attempt is made to assemble an instruction which
225 will not execute on the target architecture. The following architecture
226 names are recognized:
264 @code{armv8.1-m.main},
270 If both @code{-mcpu} and
271 @code{-march} are specified, the assembler will use
272 the setting for @code{-mcpu}.
274 The architecture option can be extended with a set extension options. These
275 extensions are context sensitive, i.e. the same extension may mean different
276 things when used with different architectures. When used together with a
277 @code{-mfpu} option, the union of both feature enablement is taken.
278 See their availability and meaning below:
280 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
282 @code{+fp}: Enables VFPv2 instructions.
283 @code{+nofp}: Disables all FPU instrunctions.
287 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
288 @code{+nofp}: Disables all FPU instructions.
292 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
293 @code{+vfpv3-d16}: Alias for @code{+fp}.
294 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
295 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
296 conversion instructions and 16 double-word registers.
297 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
298 instructions and 32 double-word registers.
299 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
300 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
301 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
303 @code{+neon}: Alias for @code{+simd}.
304 @code{+neon-vfpv3}: Alias for @code{+simd}.
305 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
306 NEONv1 instructions with 32 double-word registers.
307 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
308 double-word registers.
309 @code{+mp}: Enables Multiprocessing Extensions.
310 @code{+sec}: Enables Security Extensions.
311 @code{+nofp}: Disables all FPU and NEON instructions.
312 @code{+nosimd}: Disables all NEON instructions.
316 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
317 @code{+vfpv4-d16}: Alias for @code{+fp}.
318 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
319 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
320 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
321 conversion instructions and 16 double-word registers.
322 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
323 instructions and 32 double-word registers.
324 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
325 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
326 double-word registers.
327 @code{+neon-vfpv4}: Alias for @code{+simd}.
328 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
330 @code{+neon-vfpv3}: Alias for @code{+neon}.
331 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
332 NEONv1 instructions with 32 double-word registers.
333 double-word registers.
334 @code{+nofp}: Disables all FPU and NEON instructions.
335 @code{+nosimd}: Disables all NEON instructions.
339 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
340 double-word registers.
341 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
342 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
343 @code{+vfpv3-d16}: Alias for @code{+fp}.
344 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
345 floating-point conversion instructions with 16 double-word registers.
346 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
347 conversion instructions with 16 double-word registers.
348 @code{+idiv}: Enables integer division instructions in ARM mode.
349 @code{+nofp}: Disables all FPU instructions.
353 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
354 double-word registers.
355 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
356 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
357 double-word registers.
358 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
359 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
360 @code{+nofp}: Disables all FPU instructions.
362 For @code{armv8-m.main}:
364 @code{+dsp}: Enables DSP Extension.
365 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
366 double-word registers.
367 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
368 @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
369 @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
370 @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
371 @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
372 @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
373 @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
374 @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
375 @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
376 @code{+nofp}: Disables all FPU instructions.
377 @code{+nodsp}: Disables DSP Extension.
379 For @code{armv8.1-m.main}:
381 @code{+dsp}: Enables DSP Extension.
382 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
383 for Armv8.1-M Mainline with 16 double-word registers.
384 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
385 Armv8.1-M Mainline, implies @code{+fp}.
386 @code{+mve}: Enables integer only M-profile Vector Extension for
387 Armv8.1-M Mainline, implies @code{+dsp}.
388 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
389 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
390 @code{+nofp}: Disables all FPU instructions.
391 @code{+nodsp}: Disables DSP Extension.
392 @code{+nomve}: Disables all M-profile Vector Extensions.
396 @code{+crc}: Enables CRC32 Extension.
397 @code{+simd}: Enables VFP and NEON for Armv8-A.
398 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
400 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
401 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
403 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
404 @code{+nocrypto}: Disables Cryptography Extensions.
406 For @code{armv8.1-a}:
408 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
409 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
411 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
412 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
414 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
415 @code{+nocrypto}: Disables Cryptography Extensions.
417 For @code{armv8.2-a} and @code{armv8.3-a}:
419 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
420 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
421 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
422 for Armv8.2-A, implies @code{+fp16}.
423 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
425 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
427 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
428 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
430 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
431 @code{+nocrypto}: Disables Cryptography Extensions.
433 For @code{armv8.4-a}:
435 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
437 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
438 Variant Extensions for Armv8.2-A, implies @code{+simd}.
439 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
441 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
442 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
444 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
445 @code{+nocryptp}: Disables Cryptography Extensions.
447 For @code{armv8.5-a}:
449 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
451 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
452 Variant Extensions for Armv8.2-A, implies @code{+simd}.
453 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
455 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
456 @code{+nocryptp}: Disables Cryptography Extensions.
459 @cindex @code{-mfpu=} command-line option, ARM
460 @item -mfpu=@var{floating-point-format}
462 This option specifies the floating point format to assemble for. The
463 assembler will issue an error message if an attempt is made to assemble
464 an instruction which will not execute on the target floating point unit.
465 The following format options are recognized:
485 @code{vfpv3-d16-fp16},
502 @code{neon-fp-armv8},
503 @code{crypto-neon-fp-armv8},
504 @code{neon-fp-armv8.1}
506 @code{crypto-neon-fp-armv8.1}.
508 In addition to determining which instructions are assembled, this option
509 also affects the way in which the @code{.double} assembler directive behaves
510 when assembling little-endian code.
512 The default is dependent on the processor selected. For Architecture 5 or
513 later, the default is to assemble for VFP instructions; for earlier
514 architectures the default is to assemble for FPA instructions.
516 @cindex @code{-mfp16-format=} command-line option
517 @item -mfp16-format=@var{format}
518 This option specifies the half-precision floating point format to use
519 when assembling floating point numbers emitted by the @code{.float16}
521 The following format options are recognized:
524 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
525 point format is used, if @code{alternative} is specified then the Arm
526 alternative half-precision format is used. If this option is set on the
527 command line then the format is fixed and cannot be changed with
528 the @code{float16_format} directive. If this value is not set then
529 the IEEE 754-2008 format is used until the format is explicitly set with
530 the @code{float16_format} directive.
532 @cindex @code{-mthumb} command-line option, ARM
534 This option specifies that the assembler should start assembling Thumb
535 instructions; that is, it should behave as though the file starts with a
536 @code{.code 16} directive.
538 @cindex @code{-mthumb-interwork} command-line option, ARM
539 @item -mthumb-interwork
540 This option specifies that the output generated by the assembler should
541 be marked as supporting interworking. It also affects the behaviour
542 of the @code{ADR} and @code{ADRL} pseudo opcodes.
544 @cindex @code{-mimplicit-it} command-line option, ARM
545 @item -mimplicit-it=never
546 @itemx -mimplicit-it=always
547 @itemx -mimplicit-it=arm
548 @itemx -mimplicit-it=thumb
549 The @code{-mimplicit-it} option controls the behavior of the assembler when
550 conditional instructions are not enclosed in IT blocks.
551 There are four possible behaviors.
552 If @code{never} is specified, such constructs cause a warning in ARM
553 code and an error in Thumb-2 code.
554 If @code{always} is specified, such constructs are accepted in both
555 ARM and Thumb-2 code, where the IT instruction is added implicitly.
556 If @code{arm} is specified, such constructs are accepted in ARM code
557 and cause an error in Thumb-2 code.
558 If @code{thumb} is specified, such constructs cause a warning in ARM
559 code and are accepted in Thumb-2 code. If you omit this option, the
560 behavior is equivalent to @code{-mimplicit-it=arm}.
562 @cindex @code{-mapcs-26} command-line option, ARM
563 @cindex @code{-mapcs-32} command-line option, ARM
566 These options specify that the output generated by the assembler should
567 be marked as supporting the indicated version of the Arm Procedure.
570 @cindex @code{-matpcs} command-line option, ARM
572 This option specifies that the output generated by the assembler should
573 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
574 enabled this option will cause the assembler to create an empty
575 debugging section in the object file called .arm.atpcs. Debuggers can
576 use this to determine the ABI being used by.
578 @cindex @code{-mapcs-float} command-line option, ARM
580 This indicates the floating point variant of the APCS should be
581 used. In this variant floating point arguments are passed in FP
582 registers rather than integer registers.
584 @cindex @code{-mapcs-reentrant} command-line option, ARM
585 @item -mapcs-reentrant
586 This indicates that the reentrant variant of the APCS should be used.
587 This variant supports position independent code.
589 @cindex @code{-mfloat-abi=} command-line option, ARM
590 @item -mfloat-abi=@var{abi}
591 This option specifies that the output generated by the assembler should be
592 marked as using specified floating point ABI.
593 The following values are recognized:
599 @cindex @code{-eabi=} command-line option, ARM
600 @item -meabi=@var{ver}
601 This option specifies which EABI version the produced object files should
603 The following values are recognized:
609 @cindex @code{-EB} command-line option, ARM
611 This option specifies that the output generated by the assembler should
612 be marked as being encoded for a big-endian processor.
614 Note: If a program is being built for a system with big-endian data
615 and little-endian instructions then it should be assembled with the
616 @option{-EB} option, (all of it, code and data) and then linked with
617 the @option{--be8} option. This will reverse the endianness of the
618 instructions back to little-endian, but leave the data as big-endian.
620 @cindex @code{-EL} command-line option, ARM
622 This option specifies that the output generated by the assembler should
623 be marked as being encoded for a little-endian processor.
625 @cindex @code{-k} command-line option, ARM
626 @cindex PIC code generation for ARM
628 This option specifies that the output of the assembler should be marked
629 as position-independent code (PIC).
631 @cindex @code{--fix-v4bx} command-line option, ARM
633 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
634 the linker option of the same name.
636 @cindex @code{-mwarn-deprecated} command-line option, ARM
637 @item -mwarn-deprecated
638 @itemx -mno-warn-deprecated
639 Enable or disable warnings about using deprecated options or
640 features. The default is to warn.
642 @cindex @code{-mccs} command-line option, ARM
644 Turns on CodeComposer Studio assembly syntax compatibility mode.
646 @cindex @code{-mwarn-syms} command-line option, ARM
648 @itemx -mno-warn-syms
649 Enable or disable warnings about symbols that match the names of ARM
650 instructions. The default is to warn.
658 * ARM-Instruction-Set:: Instruction Set
659 * ARM-Chars:: Special Characters
660 * ARM-Regs:: Register Names
661 * ARM-Relocations:: Relocations
662 * ARM-Neon-Alignment:: NEON Alignment Specifiers
665 @node ARM-Instruction-Set
666 @subsection Instruction Set Syntax
667 Two slightly different syntaxes are support for ARM and THUMB
668 instructions. The default, @code{divided}, uses the old style where
669 ARM and THUMB instructions had their own, separate syntaxes. The new,
670 @code{unified} syntax, which can be selected via the @code{.syntax}
671 directive, and has the following main features:
675 Immediate operands do not require a @code{#} prefix.
678 The @code{IT} instruction may appear, and if it does it is validated
679 against subsequent conditional affixes. In ARM mode it does not
680 generate machine code, in THUMB mode it does.
683 For ARM instructions the conditional affixes always appear at the end
684 of the instruction. For THUMB instructions conditional affixes can be
685 used, but only inside the scope of an @code{IT} instruction.
688 All of the instructions new to the V6T2 architecture (and later) are
689 available. (Only a few such instructions can be written in the
690 @code{divided} syntax).
693 The @code{.N} and @code{.W} suffixes are recognized and honored.
696 All instructions set the flags if and only if they have an @code{s}
701 @subsection Special Characters
703 @cindex line comment character, ARM
704 @cindex ARM line comment character
705 The presence of a @samp{@@} anywhere on a line indicates the start of
706 a comment that extends to the end of that line.
708 If a @samp{#} appears as the first character of a line then the whole
709 line is treated as a comment, but in this case the line could also be
710 a logical line number directive (@pxref{Comments}) or a preprocessor
711 control command (@pxref{Preprocessing}).
713 @cindex line separator, ARM
714 @cindex statement separator, ARM
715 @cindex ARM line separator
716 The @samp{;} character can be used instead of a newline to separate
719 @cindex immediate character, ARM
720 @cindex ARM immediate character
721 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
723 @cindex identifiers, ARM
724 @cindex ARM identifiers
725 *TODO* Explain about /data modifier on symbols.
728 @subsection Register Names
730 @cindex ARM register names
731 @cindex register names, ARM
732 *TODO* Explain about ARM register naming, and the predefined names.
734 @node ARM-Relocations
735 @subsection ARM relocation generation
737 @cindex data relocations, ARM
738 @cindex ARM data relocations
739 Specific data relocations can be generated by putting the relocation name
740 in parentheses after the symbol name. For example:
746 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
748 The following relocations are supported:
764 For compatibility with older toolchains the assembler also accepts
765 @code{(PLT)} after branch targets. On legacy targets this will
766 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
767 targets it will encode either the @samp{R_ARM_CALL} or
768 @samp{R_ARM_JUMP24} relocation, as appropriate.
770 @cindex MOVW and MOVT relocations, ARM
771 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
772 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
773 respectively. For example to load the 32-bit address of foo into r0:
776 MOVW r0, #:lower16:foo
777 MOVT r0, #:upper16:foo
780 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
781 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
782 generated by prefixing the value with @samp{#:lower0_7:#},
783 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
784 respectively. For example to load the 32-bit address of foo into r0:
787 MOVS r0, #:upper8_15:#foo
789 ADDS r0, #:upper0_7:#foo
791 ADDS r0, #:lower8_15:#foo
793 ADDS r0, #:lower0_7:#foo
796 @node ARM-Neon-Alignment
797 @subsection NEON Alignment Specifiers
799 @cindex alignment for NEON instructions
800 Some NEON load/store instructions allow an optional address
802 The ARM documentation specifies that this is indicated by
803 @samp{@@ @var{align}}. However GAS already interprets
804 the @samp{@@} character as a "line comment" start,
805 so @samp{: @var{align}} is used instead. For example:
808 vld1.8 @{q0@}, [r0, :128]
811 @node ARM Floating Point
812 @section Floating Point
814 @cindex floating point, ARM (@sc{ieee})
815 @cindex ARM floating point (@sc{ieee})
816 The ARM family uses @sc{ieee} floating-point numbers.
819 @section ARM Machine Directives
821 @cindex machine directives, ARM
822 @cindex ARM machine directives
825 @c AAAAAAAAAAAAAAAAAAAAAAAAA
828 @cindex @code{.2byte} directive, ARM
829 @cindex @code{.4byte} directive, ARM
830 @cindex @code{.8byte} directive, ARM
831 @item .2byte @var{expression} [, @var{expression}]*
832 @itemx .4byte @var{expression} [, @var{expression}]*
833 @itemx .8byte @var{expression} [, @var{expression}]*
834 These directives write 2, 4 or 8 byte values to the output section.
837 @cindex @code{.align} directive, ARM
838 @item .align @var{expression} [, @var{expression}]
839 This is the generic @var{.align} directive. For the ARM however if the
840 first argument is zero (ie no alignment is needed) the assembler will
841 behave as if the argument had been 2 (ie pad to the next four byte
842 boundary). This is for compatibility with ARM's own assembler.
844 @cindex @code{.arch} directive, ARM
845 @item .arch @var{name}
846 Select the target architecture. Valid values for @var{name} are the same as
847 for the @option{-march} command-line option without the instruction set
850 Specifying @code{.arch} clears any previously selected architecture
853 @cindex @code{.arch_extension} directive, ARM
854 @item .arch_extension @var{name}
855 Add or remove an architecture extension to the target architecture. Valid
856 values for @var{name} are the same as those accepted as architectural
857 extensions by the @option{-mcpu} and @option{-march} command-line options.
859 @code{.arch_extension} may be used multiple times to add or remove extensions
860 incrementally to the architecture being compiled for.
862 @cindex @code{.arm} directive, ARM
864 This performs the same action as @var{.code 32}.
866 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
868 @cindex @code{.bss} directive, ARM
870 This directive switches to the @code{.bss} section.
872 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
874 @cindex @code{.cantunwind} directive, ARM
876 Prevents unwinding through the current function. No personality routine
877 or exception table data is required or permitted.
879 @cindex @code{.code} directive, ARM
880 @item .code @code{[16|32]}
881 This directive selects the instruction set being generated. The value 16
882 selects Thumb, with the value 32 selecting ARM.
884 @cindex @code{.cpu} directive, ARM
885 @item .cpu @var{name}
886 Select the target processor. Valid values for @var{name} are the same as
887 for the @option{-mcpu} command-line option without the instruction set
890 Specifying @code{.cpu} clears any previously selected architecture
893 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
895 @cindex @code{.dn} and @code{.qn} directives, ARM
896 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
897 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
899 The @code{dn} and @code{qn} directives are used to create typed
900 and/or indexed register aliases for use in Advanced SIMD Extension
901 (Neon) instructions. The former should be used to create aliases
902 of double-precision registers, and the latter to create aliases of
903 quad-precision registers.
905 If these directives are used to create typed aliases, those aliases can
906 be used in Neon instructions instead of writing types after the mnemonic
907 or after each operand. For example:
916 This is equivalent to writing the following:
922 Aliases created using @code{dn} or @code{qn} can be destroyed using
925 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
927 @cindex @code{.eabi_attribute} directive, ARM
928 @item .eabi_attribute @var{tag}, @var{value}
929 Set the EABI object attribute @var{tag} to @var{value}.
931 The @var{tag} is either an attribute number, or one of the following:
932 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
933 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
934 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
935 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
936 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
937 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
938 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
939 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
940 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
941 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
942 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
943 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
944 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
945 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
946 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
947 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
948 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
949 @code{Tag_conformance}, @code{Tag_T2EE_use},
950 @code{Tag_Virtualization_use}
952 The @var{value} is either a @code{number}, @code{"string"}, or
953 @code{number, "string"} depending on the tag.
955 Note - the following legacy values are also accepted by @var{tag}:
956 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
957 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
959 @cindex @code{.even} directive, ARM
961 This directive aligns to an even-numbered address.
963 @cindex @code{.extend} directive, ARM
964 @cindex @code{.ldouble} directive, ARM
965 @item .extend @var{expression} [, @var{expression}]*
966 @itemx .ldouble @var{expression} [, @var{expression}]*
967 These directives write 12byte long double floating-point values to the
968 output section. These are not compatible with current ARM processors
971 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
973 @cindex @code{.float16} directive, ARM
974 @item .float16 @var{value [,...,value_n]}
975 Place the half precision floating point representation of one or more
976 floating-point values into the current section. The exact format of the
977 encoding is specified by @code{.float16_format}. If the format has not
978 been explicitly set yet (either via the @code{.float16_format} directive or
979 the command line option) then the IEEE 754-2008 format is used.
981 @cindex @code{.float16_format} directive, ARM
982 @item .float16_format @var{format}
983 Set the format to use when encoding float16 values emitted by
984 the @code{.float16} directive.
985 Once the format has been set it cannot be changed.
986 @code{format} should be one of the following: @code{ieee} (encode in
987 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
988 the Arm alternative half precision format).
991 @cindex @code{.fnend} directive, ARM
993 Marks the end of a function with an unwind table entry. The unwind index
994 table entry is created when this directive is processed.
996 If no personality routine has been specified then standard personality
997 routine 0 or 1 will be used, depending on the number of unwind opcodes
1000 @anchor{arm_fnstart}
1001 @cindex @code{.fnstart} directive, ARM
1003 Marks the start of a function with an unwind table entry.
1005 @cindex @code{.force_thumb} directive, ARM
1007 This directive forces the selection of Thumb instructions, even if the
1008 target processor does not support those instructions
1010 @cindex @code{.fpu} directive, ARM
1011 @item .fpu @var{name}
1012 Select the floating-point unit to assemble for. Valid values for @var{name}
1013 are the same as for the @option{-mfpu} command-line option.
1015 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
1016 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
1018 @cindex @code{.handlerdata} directive, ARM
1020 Marks the end of the current function, and the start of the exception table
1021 entry for that function. Anything between this directive and the
1022 @code{.fnend} directive will be added to the exception table entry.
1024 Must be preceded by a @code{.personality} or @code{.personalityindex}
1027 @c IIIIIIIIIIIIIIIIIIIIIIIIII
1029 @cindex @code{.inst} directive, ARM
1030 @item .inst @var{opcode} [ , @dots{} ]
1031 @itemx .inst.n @var{opcode} [ , @dots{} ]
1032 @itemx .inst.w @var{opcode} [ , @dots{} ]
1033 Generates the instruction corresponding to the numerical value @var{opcode}.
1034 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1035 specified explicitly, overriding the normal encoding rules.
1037 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
1038 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
1039 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
1041 @item .ldouble @var{expression} [, @var{expression}]*
1044 @cindex @code{.ltorg} directive, ARM
1046 This directive causes the current contents of the literal pool to be
1047 dumped into the current section (which is assumed to be the .text
1048 section) at the current location (aligned to a word boundary).
1049 @code{GAS} maintains a separate literal pool for each section and each
1050 sub-section. The @code{.ltorg} directive will only affect the literal
1051 pool of the current section and sub-section. At the end of assembly
1052 all remaining, un-empty literal pools will automatically be dumped.
1054 Note - older versions of @code{GAS} would dump the current literal
1055 pool any time a section change occurred. This is no longer done, since
1056 it prevents accurate control of the placement of literal pools.
1058 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1060 @cindex @code{.movsp} directive, ARM
1061 @item .movsp @var{reg} [, #@var{offset}]
1062 Tell the unwinder that @var{reg} contains an offset from the current
1063 stack pointer. If @var{offset} is not specified then it is assumed to be
1066 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1067 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1069 @cindex @code{.object_arch} directive, ARM
1070 @item .object_arch @var{name}
1071 Override the architecture recorded in the EABI object attribute section.
1072 Valid values for @var{name} are the same as for the @code{.arch} directive.
1073 Typically this is useful when code uses runtime detection of CPU features.
1075 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1077 @cindex @code{.packed} directive, ARM
1078 @item .packed @var{expression} [, @var{expression}]*
1079 This directive writes 12-byte packed floating-point values to the
1080 output section. These are not compatible with current ARM processors
1084 @cindex @code{.pad} directive, ARM
1085 @item .pad #@var{count}
1086 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1087 A positive value indicates the function prologue allocated stack space by
1088 decrementing the stack pointer.
1090 @cindex @code{.personality} directive, ARM
1091 @item .personality @var{name}
1092 Sets the personality routine for the current function to @var{name}.
1094 @cindex @code{.personalityindex} directive, ARM
1095 @item .personalityindex @var{index}
1096 Sets the personality routine for the current function to the EABI standard
1097 routine number @var{index}
1099 @cindex @code{.pool} directive, ARM
1101 This is a synonym for .ltorg.
1103 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1104 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1106 @cindex @code{.req} directive, ARM
1107 @item @var{name} .req @var{register name}
1108 This creates an alias for @var{register name} called @var{name}. For
1115 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1118 @cindex @code{.save} directive, ARM
1119 @item .save @var{reglist}
1120 Generate unwinder annotations to restore the registers in @var{reglist}.
1121 The format of @var{reglist} is the same as the corresponding store-multiple
1125 @exdent @emph{core registers}
1126 .save @{r4, r5, r6, lr@}
1127 stmfd sp!, @{r4, r5, r6, lr@}
1128 @exdent @emph{FPA registers}
1131 @exdent @emph{VFP registers}
1132 .save @{d8, d9, d10@}
1133 fstmdx sp!, @{d8, d9, d10@}
1134 @exdent @emph{iWMMXt registers}
1135 .save @{wr10, wr11@}
1136 wstrd wr11, [sp, #-8]!
1137 wstrd wr10, [sp, #-8]!
1140 wstrd wr11, [sp, #-8]!
1142 wstrd wr10, [sp, #-8]!
1146 @cindex @code{.setfp} directive, ARM
1147 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1148 Make all unwinder annotations relative to a frame pointer. Without this
1149 the unwinder will use offsets from the stack pointer.
1151 The syntax of this directive is the same as the @code{add} or @code{mov}
1152 instruction used to set the frame pointer. @var{spreg} must be either
1153 @code{sp} or mentioned in a previous @code{.movsp} directive.
1163 @cindex @code{.secrel32} directive, ARM
1164 @item .secrel32 @var{expression} [, @var{expression}]*
1165 This directive emits relocations that evaluate to the section-relative
1166 offset of each expression's symbol. This directive is only supported
1169 @cindex @code{.syntax} directive, ARM
1170 @item .syntax [@code{unified} | @code{divided}]
1171 This directive sets the Instruction Set Syntax as described in the
1172 @ref{ARM-Instruction-Set} section.
1174 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1176 @cindex @code{.thumb} directive, ARM
1178 This performs the same action as @var{.code 16}.
1180 @cindex @code{.thumb_func} directive, ARM
1182 This directive specifies that the following symbol is the name of a
1183 Thumb encoded function. This information is necessary in order to allow
1184 the assembler and linker to generate correct code for interworking
1185 between Arm and Thumb instructions and should be used even if
1186 interworking is not going to be performed. The presence of this
1187 directive also implies @code{.thumb}
1189 This directive is not necessary when generating EABI objects. On these
1190 targets the encoding is implicit when generating Thumb code.
1192 @cindex @code{.thumb_set} directive, ARM
1194 This performs the equivalent of a @code{.set} directive in that it
1195 creates a symbol which is an alias for another symbol (possibly not yet
1196 defined). This directive also has the added property in that it marks
1197 the aliased symbol as being a thumb function entry point, in the same
1198 way that the @code{.thumb_func} directive does.
1200 @cindex @code{.tlsdescseq} directive, ARM
1201 @item .tlsdescseq @var{tls-variable}
1202 This directive is used to annotate parts of an inlined TLS descriptor
1203 trampoline. Normally the trampoline is provided by the linker, and
1204 this directive is not needed.
1206 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1208 @cindex @code{.unreq} directive, ARM
1209 @item .unreq @var{alias-name}
1210 This undefines a register alias which was previously defined using the
1211 @code{req}, @code{dn} or @code{qn} directives. For example:
1218 An error occurs if the name is undefined. Note - this pseudo op can
1219 be used to delete builtin in register name aliases (eg 'r0'). This
1220 should only be done if it is really necessary.
1222 @cindex @code{.unwind_raw} directive, ARM
1223 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1224 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1225 the stack pointer by @var{offset} bytes.
1227 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1230 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1232 @cindex @code{.vsave} directive, ARM
1233 @item .vsave @var{vfp-reglist}
1234 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1235 using FLDMD. Also works for VFPv3 registers
1236 that are to be restored using VLDM.
1237 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1241 @exdent @emph{VFP registers}
1242 .vsave @{d8, d9, d10@}
1243 fstmdd sp!, @{d8, d9, d10@}
1244 @exdent @emph{VFPv3 registers}
1245 .vsave @{d15, d16, d17@}
1246 vstm sp!, @{d15, d16, d17@}
1249 Since FLDMX and FSTMX are now deprecated, this directive should be
1250 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1252 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1253 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1254 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1255 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1263 @cindex opcodes for ARM
1264 @code{@value{AS}} implements all the standard ARM opcodes. It also
1265 implements several pseudo opcodes, including several synthetic load
1270 @cindex @code{NOP} pseudo op, ARM
1276 This pseudo op will always evaluate to a legal ARM instruction that does
1277 nothing. Currently it will evaluate to MOV r0, r0.
1279 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1282 ldr <register> , = <expression>
1285 If expression evaluates to a numeric constant then a MOV or MVN
1286 instruction will be used in place of the LDR instruction, if the
1287 constant can be generated by either of these instructions. Otherwise
1288 the constant will be placed into the nearest literal pool (if it not
1289 already there) and a PC relative LDR instruction will be generated.
1291 @cindex @code{ADR reg,<label>} pseudo op, ARM
1294 adr <register> <label>
1297 This instruction will load the address of @var{label} into the indicated
1298 register. The instruction will evaluate to a PC relative ADD or SUB
1299 instruction depending upon where the label is located. If the label is
1300 out of range, or if it is not defined in the same file (and section) as
1301 the ADR instruction, then an error will be generated. This instruction
1302 will not make use of the literal pool.
1304 If @var{label} is a thumb function symbol, and thumb interworking has
1305 been enabled via the @option{-mthumb-interwork} option then the bottom
1306 bit of the value stored into @var{register} will be set. This allows
1307 the following sequence to work as expected:
1310 adr r0, thumb_function
1314 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1317 adrl <register> <label>
1320 This instruction will load the address of @var{label} into the indicated
1321 register. The instruction will evaluate to one or two PC relative ADD
1322 or SUB instructions depending upon where the label is located. If a
1323 second instruction is not needed a NOP instruction will be generated in
1324 its place, so that this instruction is always 8 bytes long.
1326 If the label is out of range, or if it is not defined in the same file
1327 (and section) as the ADRL instruction, then an error will be generated.
1328 This instruction will not make use of the literal pool.
1330 If @var{label} is a thumb function symbol, and thumb interworking has
1331 been enabled via the @option{-mthumb-interwork} option then the bottom
1332 bit of the value stored into @var{register} will be set.
1336 For information on the ARM or Thumb instruction sets, see @cite{ARM
1337 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1340 @node ARM Mapping Symbols
1341 @section Mapping Symbols
1343 The ARM ELF specification requires that special symbols be inserted
1344 into object files to mark certain features:
1350 At the start of a region of code containing ARM instructions.
1354 At the start of a region of code containing THUMB instructions.
1358 At the start of a region of data.
1362 The assembler will automatically insert these symbols for you - there
1363 is no need to code them yourself. Support for tagging symbols ($b,
1364 $f, $p and $m) which is also mentioned in the current ARM ELF
1365 specification is not implemented. This is because they have been
1366 dropped from the new EABI and so tools cannot rely upon their
1369 @node ARM Unwinding Tutorial
1372 The ABI for the ARM Architecture specifies a standard format for
1373 exception unwind information. This information is used when an
1374 exception is thrown to determine where control should be transferred.
1375 In particular, the unwind information is used to determine which
1376 function called the function that threw the exception, and which
1377 function called that one, and so forth. This information is also used
1378 to restore the values of callee-saved registers in the function
1379 catching the exception.
1381 If you are writing functions in assembly code, and those functions
1382 call other functions that throw exceptions, you must use assembly
1383 pseudo ops to ensure that appropriate exception unwind information is
1384 generated. Otherwise, if one of the functions called by your assembly
1385 code throws an exception, the run-time library will be unable to
1386 unwind the stack through your assembly code and your program will not
1389 To illustrate the use of these pseudo ops, we will examine the code
1390 that G++ generates for the following C++ input:
1393 void callee (int *);
1404 This example does not show how to throw or catch an exception from
1405 assembly code. That is a much more complex operation and should
1406 always be done in a high-level language, such as C++, that directly
1407 supports exceptions.
1409 The code generated by one particular version of G++ when compiling the
1416 @ Function supports interworking.
1417 @ args = 0, pretend = 0, frame = 8
1418 @ frame_needed = 1, uses_anonymous_args = 0
1440 Of course, the sequence of instructions varies based on the options
1441 you pass to GCC and on the version of GCC in use. The exact
1442 instructions are not important since we are focusing on the pseudo ops
1443 that are used to generate unwind information.
1445 An important assumption made by the unwinder is that the stack frame
1446 does not change during the body of the function. In particular, since
1447 we assume that the assembly code does not itself throw an exception,
1448 the only point where an exception can be thrown is from a call, such
1449 as the @code{bl} instruction above. At each call site, the same saved
1450 registers (including @code{lr}, which indicates the return address)
1451 must be located in the same locations relative to the frame pointer.
1453 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1454 op appears immediately before the first instruction of the function
1455 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1456 op appears immediately after the last instruction of the function.
1457 These pseudo ops specify the range of the function.
1459 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1460 @code{.pad}) matters; their exact locations are irrelevant. In the
1461 example above, the compiler emits the pseudo ops with particular
1462 instructions. That makes it easier to understand the code, but it is
1463 not required for correctness. It would work just as well to emit all
1464 of the pseudo ops other than @code{.fnend} in the same order, but
1465 immediately after @code{.fnstart}.
1467 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1468 indicates registers that have been saved to the stack so that they can
1469 be restored before the function returns. The argument to the
1470 @code{.save} pseudo op is a list of registers to save. If a register
1471 is ``callee-saved'' (as specified by the ABI) and is modified by the
1472 function you are writing, then your code must save the value before it
1473 is modified and restore the original value before the function
1474 returns. If an exception is thrown, the run-time library restores the
1475 values of these registers from their locations on the stack before
1476 returning control to the exception handler. (Of course, if an
1477 exception is not thrown, the function that contains the @code{.save}
1478 pseudo op restores these registers in the function epilogue, as is
1479 done with the @code{ldmfd} instruction above.)
1481 You do not have to save callee-saved registers at the very beginning
1482 of the function and you do not need to use the @code{.save} pseudo op
1483 immediately following the point at which the registers are saved.
1484 However, if you modify a callee-saved register, you must save it on
1485 the stack before modifying it and before calling any functions which
1486 might throw an exception. And, you must use the @code{.save} pseudo
1487 op to indicate that you have done so.
1489 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1490 modification of the stack pointer that does not save any registers.
1491 The argument is the number of bytes (in decimal) that are subtracted
1492 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1493 subtracting from the stack pointer increases the size of the stack.)
1495 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1496 indicates the register that contains the frame pointer. The first
1497 argument is the register that is set, which is typically @code{fp}.
1498 The second argument indicates the register from which the frame
1499 pointer takes its value. The third argument, if present, is the value
1500 (in decimal) added to the register specified by the second argument to
1501 compute the value of the frame pointer. You should not modify the
1502 frame pointer in the body of the function.
1504 If you do not use a frame pointer, then you should not use the
1505 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1506 should avoid modifying the stack pointer outside of the function
1507 prologue. Otherwise, the run-time library will be unable to find
1508 saved registers when it is unwinding the stack.
1510 The pseudo ops described above are sufficient for writing assembly
1511 code that calls functions which may throw exceptions. If you need to
1512 know more about the object-file format used to represent unwind
1513 information, you may consult the @cite{Exception Handling ABI for the
1514 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / thirdparty / binutils-gdb.git / blob