gas/doc/c-bfin.texi

   1 @c Copyright 2005, 2006, 2009, 2010
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node Blackfin-Dependent
  10 @chapter Blackfin Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter Blackfin Dependent Features
  16 @end ifclear
  17
  18 @cindex Blackfin support
  19 @menu
  20 * Blackfin Options::            Blackfin Options
  21 * Blackfin Syntax::             Blackfin Syntax
  22 * Blackfin Directives::         Blackfin Directives
  23 @end menu
  24
  25 @node Blackfin Options
  26 @section Options
  27 @cindex Blackfin options (none)
  28 @cindex options for Blackfin (none)
  29
  30 @c man begin OPTIONS
  31 @table @gcctabopt
  32
  33 @cindex @code{-mcpu=} command line option, Blackfin
  34 @item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]}
  35 This option specifies the target processor.  The optional @var{sirevision}
  36 is not used in assembler.  It's here such that GCC can easily pass down its
  37 @code{-mcpu=} option.  The assembler will issue an
  38 error message if an attempt is made to assemble an instruction which
  39 will not execute on the target processor.  The following processor names are
  40 recognized:
  41 @code{bf504},
  42 @code{bf506},
  43 @code{bf512},
  44 @code{bf514},
  45 @code{bf516},
  46 @code{bf518},
  47 @code{bf522},
  48 @code{bf523},
  49 @code{bf524},
  50 @code{bf525},
  51 @code{bf526},
  52 @code{bf527},
  53 @code{bf531},
  54 @code{bf532},
  55 @code{bf533},
  56 @code{bf534},
  57 @code{bf535} (not implemented yet),
  58 @code{bf536},
  59 @code{bf537},
  60 @code{bf538},
  61 @code{bf539},
  62 @code{bf542},
  63 @code{bf542m},
  64 @code{bf544},
  65 @code{bf544m},
  66 @code{bf547},
  67 @code{bf547m},
  68 @code{bf548},
  69 @code{bf548m},
  70 @code{bf549},
  71 @code{bf549m},
  72 @code{bf561},
  73 and
  74 @code{bf592}.
  75
  76 @cindex @code{-mfdpic} command line option, Blackfin
  77 @item -mfdpic
  78 Assemble for the FDPIC ABI.
  79
  80 @cindex @code{-mno-fdpic} command line option, Blackfin
  81 @cindex @code{-mnopic} command line option, Blackfin
  82 @item -mno-fdpic
  83 @itemx -mnopic
  84 Disable -mfdpic.
  85 @end table
  86 @c man end
  87
  88 @node Blackfin Syntax
  89 @section Syntax
  90 @cindex Blackfin syntax
  91 @cindex syntax, Blackfin
  92
  93 @table @code
  94 @item Special Characters
  95 Assembler input is free format and may appear anywhere on the line.
  96 One instruction may extend across multiple lines or more than one
  97 instruction may appear on the same line.  White space (space, tab,
  98 comments or newline) may appear anywhere between tokens.  A token must
  99 not have embedded spaces.  Tokens include numbers, register names,
 100 keywords, user identifiers, and also some multicharacter special
 101 symbols like "+=", "/*" or "||".
 102
 103 @item Instruction Delimiting
 104 A semicolon must terminate every instruction.  Sometimes a complete
 105 instruction will consist of more than one operation.  There are two
 106 cases where this occurs.  The first is when two general operations
 107 are combined.  Normally a comma separates the different parts, as in
 108
 109 @smallexample
 110 a0= r3.h * r2.l, a1 = r3.l * r2.h ;
 111 @end smallexample
 112
 113 The second case occurs when a general instruction is combined with one
 114 or two memory references for joint issue.  The latter portions are
 115 set off by a "||" token.
 116
 117 @smallexample
 118 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
 119 @end smallexample
 120
 121 @item Register Names
 122
 123 The assembler treats register names and instruction keywords in a case
 124 insensitive manner.  User identifiers are case sensitive.  Thus, R3.l,
 125 R3.L, r3.l and r3.L are all equivalent input to the assembler.
 126
 127 Register names are reserved and may not be used as program identifiers.
 128
 129 Some operations (such as "Move Register") require a register pair.
 130 Register pairs are always data registers and are denoted using a colon,
 131 eg., R3:2.  The larger number must be written firsts.  Note that the
 132 hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
 133
 134 Some instructions (such as --SP (Push Multiple)) require a group of
 135 adjacent registers.  Adjacent registers are denoted in the syntax by
 136 the range enclosed in parentheses and separated by a colon, eg., (R7:3).
 137 Again, the larger number appears first.
 138
 139 Portions of a particular register may be individually specified.  This
 140 is written with a dot (".") following the register name and then a
 141 letter denoting the desired portion.  For 32-bit registers, ".H"
 142 denotes the most significant ("High") portion.  ".L" denotes the
 143 least-significant portion.  The subdivisions of the 40-bit registers
 144 are described later.
 145
 146 @item Accumulators
 147 The set of 40-bit registers A1 and A0 that normally contain data that
 148 is being manipulated.  Each accumulator can be accessed in four ways.
 149
 150 @table @code
 151 @item one 40-bit register
 152 The register will be referred to as A1 or A0.
 153 @item one 32-bit register
 154 The registers are designated as A1.W or A0.W.
 155 @item two 16-bit registers
 156 The registers are designated as A1.H, A1.L, A0.H or A0.L.
 157 @item one 8-bit register
 158 The registers are designated as A1.X or A0.X for the bits that
 159 extend beyond bit 31.
 160 @end table
 161
 162 @item Data Registers
 163 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
 164 normally contain data for manipulation.  These are abbreviated as
 165 D-register or Dreg.  Data registers can be accessed as 32-bit registers
 166 or as two independent 16-bit registers.  The least significant 16 bits
 167 of each register is called the "low" half and is designated with ".L"
 168 following the register name.  The most significant 16 bits are called
 169 the "high" half and is designated with ".H" following the name.
 170
 171 @smallexample
 172    R7.L, r2.h, r4.L, R0.H
 173 @end smallexample
 174
 175 @item Pointer Registers
 176 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
 177 normally contain byte addresses of data structures.  These are
 178 abbreviated as P-register or Preg.
 179
 180 @smallexample
 181 p2, p5, fp, sp
 182 @end smallexample
 183
 184 @item Stack Pointer SP
 185 The stack pointer contains the 32-bit address of the last occupied
 186 byte location in the stack.  The stack grows by decrementing the
 187 stack pointer.
 188
 189 @item Frame Pointer FP
 190 The frame pointer contains the 32-bit address of the previous frame
 191 pointer in the stack.  It is located at the top of a frame.
 192
 193 @item Loop Top
 194 LT0 and LT1.  These registers contain the 32-bit address of the top of
 195 a zero overhead loop.
 196
 197 @item Loop Count
 198 LC0 and LC1.  These registers contain the 32-bit counter of the zero
 199 overhead loop executions.
 200
 201 @item Loop Bottom
 202 LB0 and LB1.  These registers contain the 32-bit address of the bottom
 203 of a zero overhead loop.
 204
 205 @item Index Registers
 206 The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
 207 addresses of data structures.  Abbreviated I-register or Ireg.
 208
 209 @item Modify Registers
 210 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
 211 offset values that are added and subracted to one of the index
 212 registers.  Abbreviated as Mreg.
 213
 214 @item Length Registers
 215 The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
 216 length in bytes of the circular buffer.  Abbreviated as Lreg.  Clear
 217 the Lreg to disable circular addressing for the corresponding Ireg.
 218
 219 @item Base Registers
 220 The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
 221 base address in bytes of the circular buffer.  Abbreviated as Breg.
 222
 223 @item Floating Point
 224 The Blackfin family has no hardware floating point but the .float
 225 directive generates ieee floating point numbers for use with software
 226 floating point libraries.
 227
 228 @item Blackfin Opcodes
 229 For detailed information on the Blackfin machine instruction set, see
 230 the Blackfin(r) Processor Instruction Set Reference.
 231
 232 @end table
 233
 234 @node Blackfin Directives
 235 @section Directives
 236 @cindex Blackfin directives
 237 @cindex directives, Blackfin
 238
 239 The following directives are provided for compatibility with the VDSP assembler.
 240
 241 @table @code
 242 @item .byte2
 243 Initializes a four byte data object.
 244 @item .byte4
 245 Initializes a two byte data object.
 246 @item .db
 247 TBD
 248 @item .dd
 249 TBD
 250 @item .dw
 251 TBD
 252 @item .var
 253 Define and initialize a 32 bit data object.
 254 @end table