gas/doc/c-bfin.texi

   1 @c Copyright 2005, 2006, 2009
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @ifset GENERIC
   6 @page
   7 @node Blackfin-Dependent
   8 @chapter Blackfin Dependent Features
   9 @end ifset
  10 @ifclear GENERIC
  11 @node Machine Dependencies
  12 @chapter Blackfin Dependent Features
  13 @end ifclear
  14
  15 @cindex Blackfin support
  16 @menu
  17 * Blackfin Options::            Blackfin Options
  18 * Blackfin Syntax::             Blackfin Syntax
  19 * Blackfin Directives::         Blackfin Directives
  20 @end menu
  21
  22 @node Blackfin Options
  23 @section Options
  24 @cindex Blackfin options (none)
  25 @cindex options for Blackfin (none)
  26
  27 @table @code
  28
  29 @cindex @code{-mcpu=} command line option, Blackfin
  30 @item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]}
  31 This option specifies the target processor.  The optional @var{sirevision}
  32 is not used in assembler.  It's here such that GCC can easily pass down its
  33 @code{-mcpu=} option.  The assembler will issue an
  34 error message if an attempt is made to assemble an instruction which
  35 will not execute on the target processor.  The following processor names are
  36 recognized:
  37 @code{bf512},
  38 @code{bf514},
  39 @code{bf516},
  40 @code{bf518},
  41 @code{bf522},
  42 @code{bf523},
  43 @code{bf524},
  44 @code{bf525},
  45 @code{bf526},
  46 @code{bf527},
  47 @code{bf531},
  48 @code{bf532},
  49 @code{bf533},
  50 @code{bf534},
  51 @code{bf535} (not implemented yet),
  52 @code{bf536},
  53 @code{bf537},
  54 @code{bf538},
  55 @code{bf539},
  56 @code{bf542},
  57 @code{bf542m},
  58 @code{bf544},
  59 @code{bf544m},
  60 @code{bf547},
  61 @code{bf547m},
  62 @code{bf548},
  63 @code{bf548m},
  64 @code{bf549},
  65 @code{bf549m},
  66 and
  67 @code{bf561}.
  68
  69 @cindex @code{-mfdpic} command line option, Blackfin
  70 @item -mfdpic
  71 Assemble for the FDPIC ABI.
  72
  73 @cindex @code{-mno-fdpic} command line option, Blackfin
  74 @cindex @code{-mnopic} command line option, Blackfin
  75 @item -mno-fdpic/-mnopic
  76 Disable -mfdpic.
  77 @end table
  78
  79 @node Blackfin Syntax
  80 @section Syntax
  81 @cindex Blackfin syntax
  82 @cindex syntax, Blackfin
  83
  84 @table @code
  85 @item Special Characters
  86 Assembler input is free format and may appear anywhere on the line.
  87 One instruction may extend across multiple lines or more than one
  88 instruction may appear on the same line.  White space (space, tab,
  89 comments or newline) may appear anywhere between tokens.  A token must
  90 not have embedded spaces.  Tokens include numbers, register names,
  91 keywords, user identifiers, and also some multicharacter special
  92 symbols like "+=", "/*" or "||".
  93
  94 @item Instruction Delimiting
  95 A semicolon must terminate every instruction.  Sometimes a complete
  96 instruction will consist of more than one operation.  There are two
  97 cases where this occurs.  The first is when two general operations
  98 are combined.  Normally a comma separates the different parts, as in
  99
 100 @smallexample
 101 a0= r3.h * r2.l, a1 = r3.l * r2.h ;
 102 @end smallexample
 103
 104 The second case occurs when a general instruction is combined with one
 105 or two memory references for joint issue.  The latter portions are
 106 set off by a "||" token.
 107
 108 @smallexample
 109 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
 110 @end smallexample
 111
 112 @item Register Names
 113
 114 The assembler treats register names and instruction keywords in a case
 115 insensitive manner.  User identifiers are case sensitive.  Thus, R3.l,
 116 R3.L, r3.l and r3.L are all equivalent input to the assembler.
 117
 118 Register names are reserved and may not be used as program identifiers.
 119
 120 Some operations (such as "Move Register") require a register pair.
 121 Register pairs are always data registers and are denoted using a colon,
 122 eg., R3:2.  The larger number must be written firsts.  Note that the
 123 hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
 124
 125 Some instructions (such as --SP (Push Multiple)) require a group of
 126 adjacent registers.  Adjacent registers are denoted in the syntax by
 127 the range enclosed in parentheses and separated by a colon, eg., (R7:3).
 128 Again, the larger number appears first.
 129
 130 Portions of a particular register may be individually specified.  This
 131 is written with a dot (".") following the register name and then a
 132 letter denoting the desired portion.  For 32-bit registers, ".H"
 133 denotes the most significant ("High") portion.  ".L" denotes the
 134 least-significant portion.  The subdivisions of the 40-bit registers
 135 are described later.
 136
 137 @item Accumulators
 138 The set of 40-bit registers A1 and A0 that normally contain data that
 139 is being manipulated.  Each accumulator can be accessed in four ways.
 140
 141 @table @code
 142 @item one 40-bit register
 143 The register will be referred to as A1 or A0.
 144 @item one 32-bit register
 145 The registers are designated as A1.W or A0.W.
 146 @item two 16-bit registers
 147 The registers are designated as A1.H, A1.L, A0.H or A0.L.
 148 @item one 8-bit register
 149 The registers are designated as A1.X or A0.X for the bits that
 150 extend beyond bit 31.
 151 @end table
 152
 153 @item Data Registers
 154 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
 155 normally contain data for manipulation.  These are abbreviated as
 156 D-register or Dreg.  Data registers can be accessed as 32-bit registers
 157 or as two independent 16-bit registers.  The least significant 16 bits
 158 of each register is called the "low" half and is designated with ".L"
 159 following the register name.  The most significant 16 bits are called
 160 the "high" half and is designated with ".H" following the name.
 161
 162 @smallexample
 163    R7.L, r2.h, r4.L, R0.H
 164 @end smallexample
 165
 166 @item Pointer Registers
 167 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
 168 normally contain byte addresses of data structures.  These are
 169 abbreviated as P-register or Preg.
 170
 171 @smallexample
 172 p2, p5, fp, sp
 173 @end smallexample
 174
 175 @item Stack Pointer SP
 176 The stack pointer contains the 32-bit address of the last occupied
 177 byte location in the stack.  The stack grows by decrementing the
 178 stack pointer.
 179
 180 @item Frame Pointer FP
 181 The frame pointer contains the 32-bit address of the previous frame
 182 pointer in the stack.  It is located at the top of a frame.
 183
 184 @item Loop Top
 185 LT0 and LT1.  These registers contain the 32-bit address of the top of
 186 a zero overhead loop.
 187
 188 @item Loop Count
 189 LC0 and LC1.  These registers contain the 32-bit counter of the zero
 190 overhead loop executions.
 191
 192 @item Loop Bottom
 193 LB0 and LB1.  These registers contain the 32-bit address of the bottom
 194 of a zero overhead loop.
 195
 196 @item Index Registers
 197 The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
 198 addresses of data structures.  Abbreviated I-register or Ireg.
 199
 200 @item Modify Registers
 201 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
 202 offset values that are added and subracted to one of the index
 203 registers.  Abbreviated as Mreg.
 204
 205 @item Length Registers
 206 The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
 207 length in bytes of the circular buffer.  Abbreviated as Lreg.  Clear
 208 the Lreg to disable circular addressing for the corresponding Ireg.
 209
 210 @item Base Registers
 211 The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
 212 base address in bytes of the circular buffer.  Abbreviated as Breg.
 213
 214 @item Floating Point
 215 The Blackfin family has no hardware floating point but the .float
 216 directive generates ieee floating point numbers for use with software
 217 floating point libraries.
 218
 219 @item Blackfin Opcodes
 220 For detailed information on the Blackfin machine instruction set, see
 221 the Blackfin(r) Processor Instruction Set Reference.
 222
 223 @end table
 224
 225 @node Blackfin Directives
 226 @section Directives
 227 @cindex Blackfin directives
 228 @cindex directives, Blackfin
 229
 230 The following directives are provided for compatibility with the VDSP assembler.
 231
 232 @table @code
 233 @item .byte2
 234 Initializes a four byte data object.
 235 @item .byte4
 236 Initializes a two byte data object.
 237 @item .db
 238 TBD
 239 @item .dd
 240 TBD
 241 @item .dw
 242 TBD
 243 @item .var
 244 Define and initialize a 32 bit data object.
 245 @end table