1 @c Copyright (C) 2019-2023 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter BPF Dependent Features
12 @node Machine Dependencies
13 @chapter BPF Dependent Features
18 * BPF Options:: BPF specific command-line options.
19 * BPF Special Characters:: Comments and statements.
20 * BPF Registers:: Register names.
21 * BPF Directives:: Machine directives.
22 * BPF Instructions:: Machine instructions.
27 @cindex BPF options (none)
28 @cindex options for BPF (none)
33 @cindex @option{-EB} command-line option, BPF
35 This option specifies that the assembler should emit big-endian eBPF.
37 @cindex @option{-EL} command-line option, BPF
39 This option specifies that the assembler should emit little-endian
42 @cindex @option{-mdialect} command-line options, BPF
43 @item -mdialect=@var{dialect}
44 This option specifies the assembly language dialect to recognize while
45 assembling. The assembler supports @option{normal} and
48 @cindex @option{-misa-spec} command-line options, BPF
49 @item -misa-spec=@var{spec}
50 This option specifies the version of the BPF instruction set to use
51 when assembling. The BPF ISA versions supported are @option{v1} @option{v2}, @option{v3} and @option{v4}.
53 The value @option{xbpf} can be specified to recognize extra
54 instructions that are used by GCC for testing purposes. But beware
55 this is not valid BPF.
58 Note that if no endianness option is specified in the command line,
59 the host endianness is used.
62 @node BPF Special Characters
63 @section BPF Special Characters
65 @cindex line comment character, BPF
66 @cindex BPF line comment character
67 The presence of a @samp{;} on a line indicates the start of a comment
68 that extends to the end of the current line. If a @samp{#} appears as
69 the first character of a line, the whole line is treated as a comment.
71 @cindex statement separator, BPF
72 Statements and assembly directives are separated by newlines.
75 @section BPF Registers
77 @cindex BPF register names
78 @cindex register names, BPF
79 The eBPF processor provides ten general-purpose 64-bit registers,
80 which are read-write, and a read-only frame pointer register:
87 General-purpose registers.
90 Read-only frame pointer register.
93 All BPF registers are 64-bit long. However, in the Pseudo-C syntax
94 registers can be referred using different names, which actually
95 reflect the kind of instruction they appear on:
102 General-purpose register in an instruction that operates on its value
103 as if it was a 64-bit value.
105 General-purpose register in an instruction that operates on its value
106 as if it was a 32-bit value.
108 Read-only frame pointer register.
112 Note that in the Pseudo-C syntax register names are not preceded by
116 @section BPF Directives
118 @cindex machine directives, BPF
120 The BPF version of @code{@value{AS}} supports the following additional
124 @cindex @code{half} directive, BPF
126 The @code{.half} directive produces a 16 bit value.
128 @cindex @code{word} directive, BPF
130 The @code{.word} directive produces a 32 bit value.
132 @cindex @code{dword} directive, BPF
134 The @code{.dword} directive produces a 64 bit value.
137 @node BPF Instructions
138 @section BPF Instructions
141 @cindex opcodes for BPF
142 In the instruction descriptions below the following field descriptors
147 Destination general-purpose register whose role is to be the
148 destination of an operation.
150 Source general-purpose register whose role is to be the source of an
153 16-bit signed PC-relative offset, measured in number of 64-bit words,
156 32-bit signed PC-relative offset, measured in number of 64-bit words,
159 Signed 16-bit immediate representing an offset in bytes.
161 Signed 16-bit immediate representing a displacement to a target,
162 measured in number of 64-bit words @emph{minus one}.
164 Signed 32-bit immediate.
166 Signed 64-bit immediate.
169 @subsection Arithmetic instructions
171 The destination register in these instructions act like an
174 Note that in pseudoc syntax these instructions should use @code{r}
182 64-bit arithmetic addition.
188 64-bit arithmetic subtraction.
194 64-bit arithmetic multiplication.
200 64-bit arithmetic integer division.
206 64-bit integer remainder.
212 64-bit bit-wise ``and'' operation.
218 64-bit bit-wise ``or'' operation.
224 64-bit bit-wise exclusive-or operation.
230 64-bit left shift, by @code{rs} or @code{imm32} bits.
236 64-bit right logical shift, by @code{rs} or @code{imm32} bits.
239 @itemx arsh rd, imm32
242 64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
248 64-bit arithmetic negation.
250 Note that in the @code{rd = - imm32} syntax there must be at least
251 one white space between @code{-} and @code{imm32}. Otherwise the
252 instruction is parsed as a @code{mov rd, imm32} instruction with a
253 negative 32-bit immediate. This is a consequence of a syntactic
254 ambiguity in the pseudoc syntax.
260 Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32}
264 @subsection 32-bit arithmetic instructions
266 The destination register in these instructions act as an accumulator.
268 Note that in pseudoc syntax these instructions should use @code{w}
269 registers. It is not allowed to mix @code{w} and @code{r} registers
270 in the same instruction.
274 @itemx add32 rd, imm32
277 32-bit arithmetic addition.
280 @itemx sub32 rd, imm32
283 32-bit arithmetic subtraction.
286 @itemx mul32 rd, imm32
289 32-bit arithmetic multiplication.
292 @itemx div32 rd, imm32
295 32-bit arithmetic integer division.
298 @itemx mod32 rd, imm32
301 32-bit integer remainder.
304 @itemx and32 rd, imm32
307 32-bit bit-wise ``and'' operation.
310 @itemx or32 rd, imm32
313 32-bit bit-wise ``or'' operation.
316 @itemx xor32 rd, imm32
319 32-bit bit-wise exclusive-or operation.
322 @itemx lsh32 rd, imm32
325 32-bit left shift, by @code{rs} or @code{imm32} bits.
328 @itemx rsh32 rd, imm32
331 32-bit right logical shift, by @code{rs} or @code{imm32} bits.
334 @itemx arsh32 rd, imm32
337 32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
340 @itemx neg32 rd, imm32
343 32-bit arithmetic negation.
345 Note that in the @code{rd = - imm32} syntax there must be at least
346 one white space between @code{-} and @code{imm32}. Otherwise the
347 instruction is parsed as a @code{mov32 rd, imm32} instruction with a
348 negative 32-bit immediate. This is a consequence of a syntactic
349 ambiguity in the pseudoc syntax.
352 @itemx mov32 rd, imm32
355 Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32}
359 @subsection Endianness conversion instructions
368 Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to
369 little-endian and store it back in @code{rd}.
376 Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian
377 and store it back in @code{rd}.
380 @subsection 64-bit load and pseudo maps
385 Load the given signed 64-bit immediate to the destination register
389 @subsection Load instructions for socket filters
391 The following instructions are intended to be used in socket filters,
392 and are therefore not general-purpose: they make assumptions on the
393 contents of several registers. See the file
394 @file{Documentation/networking/filter.txt} in the Linux kernel source
395 tree for more information.
401 @itemx r0 = *(u64 *) skb[imm32]
402 Absolute 64-bit load.
405 @itemx r0 = *(u32 *) skb[imm32]
406 Absolute 32-bit load.
409 @itemx r0 = *(u16 *) skb[imm32]
410 Absolute 16-bit load.
413 @itemx r0 = *(u8 *) skb[imm32]
420 @item ldinddw rs, imm32
421 @itemx r0 = *(u64 *) skb[rs + imm32]
422 Indirect 64-bit load.
424 @item ldindw rs, imm32
425 @itemx r0 = *(u32 *) skb[rs + imm32]
426 Indirect 32-bit load.
428 @item ldindh rs, imm32
429 @itemx r0 = *(u16 *) skb[rs + imm32]
430 Indirect 16-bit load.
432 @item ldindb %s, imm32
433 @itemx r0 = *(u8 *) skb[rs + imm32]
437 @subsection Generic load/store instructions
439 General-purpose load and store instructions are provided for several
442 Load to register instructions:
445 @item ldxdw rd, [rs + offset16]
446 @itemx rd = *(u64 *) (rs + offset16)
449 @item ldxw rd, [rs + offset16]
450 @itemx rd = *(u32 *) (rs + offset16)
453 @item ldxh rd, [rs + offset16]
454 @itemx rd = *(u16 *) (rs + offset16)
457 @item ldxb rd, [rs + offset16]
458 @itemx rd = *(u8 *) (rs + offset16)
462 Store from register instructions:
465 @item stxdw [rd + offset16], %s
466 @itemx *(u64 *) (rd + offset16)
467 Generic 64-bit store.
469 @item stxw [rd + offset16], %s
470 @itemx *(u32 *) (rd + offset16)
471 Generic 32-bit store.
473 @item stxh [rd + offset16], %s
474 @itemx *(u16 *) (rd + offset16)
475 Generic 16-bit store.
477 @item stxb [rd + offset16], %s
478 @itemx *(u8 *) (rd + offset16)
482 Store from immediates instructions:
485 @item stdw [rd + offset16], imm32
486 @itemx *(u64 *) (rd + offset16) = imm32
487 Store immediate as 64-bit.
489 @item stw [rd + offset16], imm32
490 @itemx *(u32 *) (rd + offset16) = imm32
491 Store immediate as 32-bit.
493 @item sth [rd + offset16], imm32
494 @itemx *(u16 *) (rd + offset16) = imm32
495 Store immediate as 16-bit.
497 @item stb [rd + offset16], imm32
498 @itemx *(u8 *) (rd + offset16) = imm32
499 Store immediate as 8-bit.
502 @subsection Jump instructions
504 eBPF provides the following compare-and-jump instructions, which
505 compare the values of the two given registers, or the values of a
506 register and an immediate, and perform a branch in case the comparison
514 @item jeq rd, rs, disp16
515 @itemx jeq rd, imm32, disp16
516 @itemx if rd == rs goto disp16
517 @itemx if rd == imm32 goto disp16
518 Jump if equal, unsigned.
520 @item jgt rd, rs, disp16
521 @itemx jgt rd, imm32, disp16
522 @itemx if rd > rs goto disp16
523 @itemx if rd > imm32 goto disp16
524 Jump if greater, unsigned.
526 @item jge rd, rs, disp16
527 @itemx jge rd, imm32, disp16
528 @itemx if rd >= rs goto disp16
529 @itemx if rd >= imm32 goto disp16
530 Jump if greater or equal.
532 @item jlt rd, rs, disp16
533 @itemx jlt rd, imm32, disp16
534 @itemx if rd < rs goto disp16
535 @itemx if rd < imm32 goto disp16
538 @item jle rd , rs, disp16
539 @itemx jle rd, imm32, disp16
540 @itemx if rd <= rs goto disp16
541 @itemx if rd <= imm32 goto disp16
542 Jump if lesser or equal.
544 @item jset rd, rs, disp16
545 @itemx jset rd, imm32, disp16
546 @itemx if rd & rs goto disp16
547 @itemx if rd & imm32 goto disp16
548 Jump if signed equal.
550 @item jne rd, rs, disp16
551 @itemx jne rd, imm32, disp16
552 @itemx if rd != rs goto disp16
553 @itemx if rd != imm32 goto disp16
556 @item jsgt rd, rs, disp16
557 @itemx jsgt rd, imm32, disp16
558 @itemx if rd s> rs goto disp16
559 @itemx if rd s> imm32 goto disp16
560 Jump if signed greater.
562 @item jsge rd, rs, disp16
563 @itemx jsge rd, imm32, disp16
564 @itemx if rd s>= rd goto disp16
565 @itemx if rd s>= imm32 goto disp16
566 Jump if signed greater or equal.
568 @item jslt rd, rs, disp16
569 @itemx jslt rd, imm32, disp16
570 @itemx if rd s< rs goto disp16
571 @itemx if rd s< imm32 goto disp16
572 Jump if signed lesser.
574 @item jsle rd, rs, disp16
575 @itemx jsle rd, imm32, disp16
576 @itemx if rd s<= rs goto disp16
577 @itemx if rd s<= imm32 goto disp16
578 Jump if signed lesser or equal.
581 A call instruction is provided in order to perform calls to other eBPF
582 functions, or to external kernel helpers:
587 Jump and link to the offset @emph{disp32}, or to the kernel helper
588 function identified by @emph{imm32}.
595 Terminate the eBPF program.
598 @subsection 32-bit jump instructions
600 eBPF provides the following compare-and-jump instructions, which
601 compare the 32-bit values of the two given registers, or the values of
602 a register and an immediate, and perform a branch in case the
603 comparison holds true.
605 These instructions are only available in BPF v3 or later.
608 @item jeq32 rd, rs, disp16
609 @itemx jeq32 rd, imm32, disp16
610 @itemx if rd == rs goto disp16
611 @itemx if rd == imm32 goto disp16
612 Jump if equal, unsigned.
614 @item jgt32 rd, rs, disp16
615 @itemx jgt32 rd, imm32, disp16
616 @itemx if rd > rs goto disp16
617 @itemx if rd > imm32 goto disp16
618 Jump if greater, unsigned.
620 @item jge32 rd, rs, disp16
621 @itemx jge32 rd, imm32, disp16
622 @itemx if rd >= rs goto disp16
623 @itemx if rd >= imm32 goto disp16
624 Jump if greater or equal.
626 @item jlt32 rd, rs, disp16
627 @itemx jlt32 rd, imm32, disp16
628 @itemx if rd < rs goto disp16
629 @itemx if rd < imm32 goto disp16
632 @item jle32 rd , rs, disp16
633 @itemx jle32 rd, imm32, disp16
634 @itemx if rd <= rs goto disp16
635 @itemx if rd <= imm32 goto disp16
636 Jump if lesser or equal.
638 @item jset32 rd, rs, disp16
639 @itemx jset32 rd, imm32, disp16
640 @itemx if rd & rs goto disp16
641 @itemx if rd & imm32 goto disp16
642 Jump if signed equal.
644 @item jne32 rd, rs, disp16
645 @itemx jne32 rd, imm32, disp16
646 @itemx if rd != rs goto disp16
647 @itemx if rd != imm32 goto disp16
650 @item jsgt32 rd, rs, disp16
651 @itemx jsgt32 rd, imm32, disp16
652 @itemx if rd s> rs goto disp16
653 @itemx if rd s> imm32 goto disp16
654 Jump if signed greater.
656 @item jsge32 rd, rs, disp16
657 @itemx jsge32 rd, imm32, disp16
658 @itemx if rd s>= rd goto disp16
659 @itemx if rd s>= imm32 goto disp16
660 Jump if signed greater or equal.
662 @item jslt32 rd, rs, disp16
663 @itemx jslt32 rd, imm32, disp16
664 @itemx if rd s< rs goto disp16
665 @itemx if rd s< imm32 goto disp16
666 Jump if signed lesser.
668 @item jsle32 rd, rs, disp16
669 @itemx jsle32 rd, imm32, disp16
670 @itemx if rd s<= rs goto disp16
671 @itemx if rd s<= imm32 goto disp16
672 Jump if signed lesser or equal.
675 @subsection Atomic instructions
677 Atomic exchange-and-add instructions are provided in two flavors: one
678 for swapping 64-bit quantities and another for 32-bit quantities.
681 @item aadd [rd + offset16], rs
682 @itemx *(u64 *)(rd + offset16) = rs
683 Atomic add instruction.
685 @item aor [rd + offset16], rs
686 @itemx *(u64 *) (rd + offset16) |= rs
687 Atomic or instruction.
689 @item aand [rd + offset16], rs
690 @itemx *(u64 *) (rd + offset16) &= rs
691 Atomic and instruction.
693 @item axor [rd + offset16], rs
694 @itemx *(u64 *) (rd + offset16) ^= rs
695 Atomic xor instruction
696 @item xaddw [%d+offset16],%s
697 Exchange-and-add a 32-bit value at the specified location.
701 The following variants perform fetching before the atomic operation.
704 @item afadd [dr + offset16], rs
706 Atomic fetch-and-add instruction.
708 @item afor [dr + offset16], rs
710 Atomic fetch-and-or instruction.
712 @item afand [dr + offset16], rs
714 Atomic fetch-and-and instruction.
716 @item afxor [dr + offset16], rs
718 Atomic fetch-and-or instruction
721 The above instructions were introduced in the V3 of the BPF
722 instruction set. The following instruction is supported for backwards
726 @item xadddw [rd + offset16], rs
727 Alias to @code{aadd}.
730 @subsection 32-bit atomic instructions
732 Atomic exchange-and-add instructions are provided in two flavors: one
733 for swapping 32-bit quantities and another for 32-bit quantities.
736 @item aadd32 [rd + offset16], rs
737 @itemx *(u32 *)(rd + offset16) = rs
738 Atomic add instruction.
740 @item aor32 [rd + offset16], rs
741 @itemx *(u32 *) (rd + offset16) |= rs
742 Atomic or instruction.
744 @item aand32 [rd + offset16], rs
745 @itemx *(u32 *) (rd + offset16) &= rs
746 Atomic and instruction.
748 @item axor32 [rd + offset16], rs
749 @itemx *(u32 *) (rd + offset16) ^= rs
750 Atomic xor instruction
754 The following variants perform fetching before the atomic operation.
757 @item afadd32 [dr + offset16], rs
759 Atomic fetch-and-add instruction.
761 @item afor32 [dr + offset16], rs
763 Atomic fetch-and-or instruction.
765 @item afand32 [dr + offset16], rs
767 Atomic fetch-and-and instruction.
769 @item afxor32 [dr + offset16], rs
771 Atomic fetch-and-or instruction
774 The above instructions were introduced in the V3 of the BPF
775 instruction set. The following instruction is supported for backwards
779 @item xaddw [rd + offset16], rs
780 Alias to @code{aadd32}.