1 # Test new instructions
135 # Test explicitly parallel and implicitly parallel instructions
136 # Including apparent instruction sequence reordering.
147 bcl bcl || addi fp, #77
154 bl bcl || addv fp, fp
161 bnc bcl || addx fp, fp
168 bncl bcl || and fp, fp
175 bra bcl || cmp fp, fp
182 jl fp || cmpeq fp, fp
189 jmp fp || cmpu fp, fp
196 ld fp, @fp || cmpz r1
203 ld fp, @r1+ || ldi r2, #77
210 ldb fp, @fp || mv r2, fp
217 ldh fp, @fp || neg r2, fp
231 lduh fp, @fp || not r2, fp
238 lock fp, @fp || or r2, fp
245 mvfc fp, cr1 || sub r2, fp
252 mvtc fp, cr2 || subv r2, fp
266 sll fp, r1 || xor r2, fp
273 slli fp, #22 || machi r2, fp
280 sra fp, fp || maclh1 r2, fp
287 srai fp, #22 || maclo r2, fp
294 srl fp, fp || macwhi r2, fp
301 srli fp, #22 || macwlo r2, fp
308 st fp, @fp || macwu1 r2, fp
315 st fp, @+fp || msblo r2, fp
322 st fp, @-fp || mul r2, fp
329 stb fp, @fp || mulhi r2, fp
336 sth fp, @fp || mullo r2, fp
343 trap #2 || mulwhi r2, fp
348 .global unlock__mulwlo
350 unlock fp, @fp || mulwlo r2, fp
357 add fp, fp || mulwu1 r2, fp
362 .global addi__mvfachi
364 addi fp, #77 || mvfachi r2, a0
369 .global addv__mvfaclo
371 addv fp, fp || mvfaclo r2, a1
376 .global addx__mvfacmi
378 addx fp, fp || mvfacmi r2, a0
385 and fp, fp || mvtachi r2, a0
392 cmp fp, fp || mvtaclo r2, a0
399 cmpeq fp, fp || rac a1
406 cmpu fp, fp || rach a0, a1
419 # Test private instructions
458 # Test parallel versions of the private instructions
470 jnc fp || ldi fp, #77
488 # Test automatic and explicit parallelisation of instructions
502 .global sadd__nop_reverse
513 .global add__not__dest_clash
519 .global add__not__src_clash
525 .global add__not__no_clash
537 .global mul__sra__reverse_src_clash
538 mul__sra__reverse_src_clash:
555 .global bc__add__forced_parallel
556 bc__add__forced_parallel:
557 bc label || add r5, r6
560 .global add__bc__forced_parallel
561 add__bc__forced_parallel:
562 add r7, r8 || bc label
566 ; Additional testcases.
567 ; These insns were added to the chip later.